lab Manual soen 228

SOEN 228/298 Lab Manual

Author:

Rick   Fenster

Last Revision: June 1, 2015

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Contents 1 Introduction

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1.1 Representing Binary . . . . . . . . 1.2 Commonly Use Used Parts in the Lab . 1.2.1 Breadboard . . . . . . . . . 1.2.2 Switches . . . . . . . . . . . 1.2.3 Resistors . . . . . . . . . . 1.2.4 Capacitors . . . . . . . . . 1.2.5 LEDs . . . . . . . . . . . . 1.2.6 Integrated Circuits . . . . . 1.2.7 Power Supply . . . . . . . . 1.2.8 Tools . . . . . . . . . . . . 1.3 Basic Logic Functions . . . . . . . 1.3.1 NOT Function . . . . . . . 1.3.2 OR Function . . . . . . . . 1.3.3 AND Function . . . . . . .

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2 Lab Experime Experiment nt 0: Introd Introduct uction ion to the Breadboar Breadboard d and ElecElectronic Circuits 10

2.1 2.2 2.3 2.4 2.4 2.5 2.6 2.6 2.7 2.7

Introdu oduction ion to Lab Exper perime iment 0 . . . . . . Using the Power Supply . . . . . . . . . . . . Wiring Switches for Inputs . . . . . . . . . . The The 7404 7404,, 7408 7408 and and 7432 7432 Inte Integr grat ated ed Circ Circui uits ts Step 0: Wi Wiring the Breadboa board . . . . . . . . Ste Step 1: 1: Con Controll rollin ingg an LED LED By a Swi Swittch . . . Ste Step 2: 2: Tes Testting ing the the 7404 7404,, 74 7408 and and 7432 7432 . . .

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3 Lab Exp eriment 1: The Half Adder

3.1 3.2 3.3 3.4

Introduction . . . . . . . . . . . The Half Adder . . . . . . . . . Step 0: Sim Simplif lify the Function . Step 1: Imp Implement the Circuit .

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4 Lab Exp eriment 2: Latches and Flip-Flops

4.1 4.2 4.3 4.4 4.5 4.6

Introduction . . . . . . . . . . . . . . . . . . The S-R Latch . . . . . . . . . . . . . . . . The D Flip-Flop . . . . . . . . . . . . . . . Step 0: Ass Assemble the S-R Latch . . . . . . . Step 1: Ass Assemble the D Flip lip-Flop lop . . . . . . *Ste *Step p 2: 2: Build Build A Posi Positi tive ve-E -Edg dgee Tri Trigg gger ered ed D

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5 Proj Proje ect Exper xperiiment ent 0: Th The e Timi Timing ng Signa ignall Gene enerato rator r

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Duty Cycle and Frequency . . . . . . . . . . . . . . . . . . . . . . 5.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . .

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5.4 5.5 5.6 5.7 5.7 5.8 5.8 5.9

A Review iew on Orders of Magnitu itude . . . . . The 555 Timer . . . . . . . . . . . . . . . . The 74LS164 SIPO Shift ift Regist ister . . . . . . Feedb eedbac ack k For the the Timi Timing ng Sign Signal al Gene Genera rato torr Asse Assem mblin blingg the the Timi Timing ng Sign Signal al Gene Genera rato torr . . Some Pro je ject Tips . . . . . . . . . . . . . .

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6 Project Experime Experiment nt 1: The Bus, Bus, Arithmeti Arithmetic c Unit and and Program Program Counter 23

6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Program Counter . . . . . . . . . . . . . . . . . . . . . . . . The Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . 74LS283 4-Bit Adder . . . . . . . . . . . . . . . . . . . . . . . . . 74LS395 4-Bit Shift ift Regist ister . . . . . . . . . . . . . . . . . . . . A Brief Over Overview view on the the Program Program Counte Counterr and Increm Increment enter er System System Assembling the Circuit . . . . . . . . . . . . . . . . . . . . . . . .

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7 Project Project Experime Experiment nt 2: Data Data Register Registerss and the Memory Memory Address Register 30

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Putting It All Together . . . . . . . . . . . . . . . . . . . . . . . 8 Pro ject Experiment 3: Program Memory

8.1 8.2 8.3 8.4 8.5 8.5 8.6 8.7 8.8

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Introduction . . . . . . . . . . . . . . . . . . . . . A Brief Overview on Memory . . . . . . . . . . . Decoders . . . . . . . . . . . . . . . . . . . . . . . SCM21C14E-4 1K x 4 RAM . . . . . . . . . . . . 7442 7442 Bina Binary ry Code Coded d Deci Decima mall to Deci Decima mall Dec Decod oder er 74LS157 Quad Multiplexer . . . . . . . . . . . . 74LS12 74L S1266 TriTri-Sta State te Bu Buff er . . . . . . . . . . . . . . The Experiment . . . . . . . . . . . . . . . . . . 8.8.1 Building the Circuit . . . . . . . . . . . . 8.8.2 Programming the RAM . . . . . . . . . . 8.8. 8.8.33 Disp Displa lay ying ing the the Con Conten tents of the the RAM RAM . . . 8.8.4 Demonstrating Your Work . . . . . . . . .

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9 Proje oject Exper periment 4: The Control Signal General

9.1 9.2 9.3 9.4 9.5 9.5

The IncB Instruction . . . . . . . . The MovAB Instruction . . . . . . The MovBA Instruction . . . . . . The IncA Instruction . . . . . . . . Impl Implem emen enti ting ng the the Sign ignal Gene Generrato ator

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10 A Note on Circuit Schematics

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10.1 B lo lock Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Ele Electrica ical Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Using the the Right Right Symbo Symboll and Show Showing ing Supply Supply Connec Connections tions 10.2.2 10. 2.2 Part Part Nam Names es and Refere Reference nces: s: Why Do They They Matt Matter? er? . . . 11 Usin Using g the the 74LS 74LS17 173 3 As a Repl Replac acem emen entt for for the the 74LS 74LS39 395 5

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List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Breadboard . . . . . . . . . . . . . . . . . . . . . . . . . . Switch Schematic Symbol . . . . . . . . . . . . . . . . . . DIP Switch Pack . . . . . . . . . . . . . . . . . . . . . . . Resistor Schematic Symbols . . . . . . . . . . . . . . . . . Resistor Pack Equivalent Circuit . . . . . . . . . . . . . . Buss Bussed ed Resi Resist stor or Pack ack and and Indiv ndivid idua uall Resi Resist stor or . . . . . . . Capacitor Schematic Symbol bols . . . . . . . . . . . . . . . . Ceramic and Electrolyt lytic Capacito itors . . . . . . . . . . . . LED Schematic Symbol . . . . . . . . . . . . . . . . . . . LED Pack and Single LED . . . . . . . . . . . . . . . . . Anode side of LED Pack . . . . . . . . . . . . . . . . . . . Typical Integrated Circuit . . . . . . . . . . . . . . . . . . Power Supply Schematic Symbols bols . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . Lab Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . NOT Gate Symbol . . . . . . . . . . . . . . . . . . . . . . OR Gate Symbol . . . . . . . . . . . . . . . . . . . . . . . AND Gate Symbol . . . . . . . . . . . . . . . . . . . . . . Switch with a Pull Down Resistor . . . . . . . . . . . . . . 7404 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . 7408 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . 7432 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . Sch Schem emat atic ic for a Swit witch Con Controll rolled ed LED LED . . . . . . . . . . NAND S-R Latch . . . . . . . . . . . . . . . . . . . . . . . D Flip-Flop Block Diagrams . . . . . . . . . . . . . . . . . Lev Level-T el-Tri rigg gger ered ed D Flip Flip-F -Flo lop p Imp Imple leme men ntati tation on . . . . . . . . Implementation ion of a NAND Gate . . . . . . . . . . . . . . Implem Implemen entat tation ion of a Posit Positiv ive-E e-Edge dge Trigger riggered ed D Flip-Fl Flip-Flop op Sample Timing Diagram . . . . . . . . . . . . . . . . . . . 555 Timer Pin-Out Diagram . . . . . . . . . . . . . . . . . 555 Timer Astable Circuit . . . . . . . . . . . . . . . . . . Shift Register Behavior . . . . . . . . . . . . . . . . . . . 74LS164 Pin-Out Diagram . . . . . . . . . . . . . . . . . . 7420 Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . 4 Bit Bus Example . . . . . . . . . . . . . . . . . . . . . .

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36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

74LS283 Pin-Out Diagram . . . . . . . . . . 74LS395 Pin-Out Diagram . . . . . . . . . . Prog Progra ram m Coun Countter Regi Regist ster er Sch Schem emat atic ic . . . . 4-Bit Adder Schematic . . . . . . . . . . . . Sum Register Schematic . . . . . . . . . . . Mirror Register Schematic . . . . . . . . . . Data Register Schematic . . . . . . . . . . . Mem Me mory ory Addr Addres esss Regi Regist steer Schema hemati ticc . . . . SCM21C14E-4 Pin-Out Out Diag iagram . . . . . . 7442 Pin-Out Diagram . . . . . . . . . . . . 74LS157 Pin-Out Diagram . . . . . . . . . . 74LS126 Pin-Out Diagram . . . . . . . . . . RAM Circuit Diagram . . . . . . . . . . . . Control Sign ignal Generator Logic . . . . . . . Typical Block ock Diagram . . . . . . . . . . . . Typical Elec lectrica ical Schematic . . . . . . . . . Sch Schem emat atic ic With ith Multi ultipl plee Ref Refere erences nces . . . . 74LS 74LS17 1733 Circ Circui uitt for for Repl Replac acin ingg The The 74 74LS LS39 395 5

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Truth Table for the NOT Function . . . . . . . . . . . . . . Truth Table for the OR Function . . . . . . . . . . . . . . . Truth Table for the AND Function . . . . . . . . . . . . . . Truth Table for the Half Adder . . . . . . . . . . . . . . . . Truth Table for the S-R Latch . . . . . . . . . . . . . . . . Truth Table for the D Flip-Flop . . . . . . . . . . . . . . . . Orders of Magnitude . . . . . . . . . . . . . . . . . . . . . . Sample Layout of a 32 X 1B Memory . . . . . . . . . . . . . Truth ruth Table able for for 2 bit bit Act Activ ivee Hig High h and and Acti Active ve Low Low Dec Decode oders rs Behavior of SCM21C14E-4 . . . . . . . . . . . . . . . . . . Truth Table for 7442 Decode oder . . . . . . . . . . . . . . . . .

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List of Tables 1 2 3 4 5 6 7 8 9 10 11

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1

Intr Introd oduc ucti tion on

The purpose of this laboratory is to introduce students to digital logic and comput com puter er archit architect ecture ure at a physi physical cal level. level. Studen Students ts will prototy prototype pe and test test circuits that will form a basic, toy computer capable of executing a few selected instruction instructionss by using TTL integrat integrated ed circuits. In particular, particular, this lab mak makes es use of the 7400 logic family. The first set of lab experiments serve to provide some familiarization and exploration with digital logic. Once a comfortable working knowledge of digital logic has been established, a simple computer is built through 5 experiments. This This com comput puter er contain containss the majority majority of the basics basics needed needed for a com comput puter: er: a program counter, memory, registers, a data bus and a control signal generator. This lab experiment experiment computer computer has the following following specifications: specifications: a clock of  approximately 3.25 Hz, two 4-bit general purpose data registers, an incrementer, 16 X 4 bit instruction memory and three instructions.

1.1

Repre Represen sentin ting g Binary Binary

Binary Binary systems systems have have two two values alues of concer concern: n: Log Logic ic 0 and Logic Logic 1. Since Since this laboratory uses TTL technologies, a Logic 0 is considered to be  0 Volts (Ground  or GND) and GND)  and a Logic 1 is considered to be  5 Volts .

1.2 1.2.1 1.2.1

Common Commonly ly Used Used Parts Parts in the the Lab Lab Breadbo Breadboard ard

The breadboard breadboard is a tool used to prototype prototype and assemble assemble digital circuits. circuits. It is designed to intentionally slot integrated circuits with ease. Please see Figure 1 below. In the center, the gap is used to isolate the columns. For every column, there there is a metal metal plate running running down. down. These These metal metal plates plates stop stop at the gap in the breadboard. breadboard. Because Because of this, each connector connector in a particular column column forms a parallel connection. The only exceptions to this are the two sets of rows on the top and bottom of a breadboard. breadboard. Each Each one of these rows rows has all of its sockets sockets connected together and called  rails . This characteri characteristic stic makes makes these two two rows ideal for +5 Volts and Ground.

Figure 1: Breadboard 1

1.2.2 1.2.2

Switc Switches hes

The switches used in these labs are single-pole, single throw switches (SPST). When the switch is closed  is  closed , it forms a connection and when  open , the connection is broken. broken. In the lab, switches switches come come in packs packs of 8, 10 or 12 and are placed placed in the gaps of the breadboards. breadboards. A 12 pack pack switch is shown in Figure 3. The circuit symbol for a SPST is shown in Figure 2.

Figure 2: Switch Schematic Symbol

Figure 3: DIP Switch Pack

1.2.3 1.2.3

Resis Resistor torss

A resist resistor or is a basic basic com compone ponent nt for any any electr electrica icall circui circuit. t. It simply resists resists electr electrica icall curren current. t. The resista resistance nce of a resist resistor or is measu measured red in Ohms Ohms ( Ω ). In these experim experimen ents, ts, a resist resistor or is used used for two two purpose purposes. s. The first is to act as a pull-down resistor for inputs and data lines, meaning that the resistor is connected connected to Ground. The other reason is to limit the flow of current current for LEDs so that the LEDs do not burn out. Two common resistor symbols are shown in Figure 4. There are two packages available for use in the SOEN 228/289 labs. The first type is an individual resistor, used primarily in the Timing Signal Generator. The other type is a resistor pack, which contains multiple resistors in one unit. The resistor packs used in the lab are all tied to a common pin which makes these 2

Figure 4: Resistor Schematic Symbols resistors ideal for use with switch or LED packs since only one wire is necessary to tie them to V CC   or Ground Ground.. Common Common pins are usually usually an outerm outermost ost pin denoted by a strip or a dot on one end of the resistor pack to show which side the pin is on. A typical resistor resistor pack of 4 resistors resistors is equivalen equivalentt to the circuit shown shown in Figure Figure 5. Actual Actual resist resistors ors are shown shown in Figure Figure 6. A bussed bussed resistor resistor pack is shown on the left with its common pin emphasized and a single resistor is shown on the right.

Figure 5: Resistor Pack Equivalent Circuit

Figure Figure 6: Bussed Bussed Resistor Resistor Pack and Individual Individual Resistor

1.2.4 1.2.4

Capaci Capacitor torss

A capacitor capacitor is a device that stores stores electrical charges charges then discharges discharges them. In this lab, capacitors are only used during the Timing Signal Generator experiment. ment. There are two types of capacitors capacitors presented presented to students. students. The first type is a ceramic capacitor which is a capacitor that can be placed in any direction. On the other hand, electrolytic capacitors are polarized and must be plugged in with the longer leg being a positive positive side. Its unit is the Farad Farad (F). Figure 7 shows the circuit schematic symbol for the capacitor. In Figure 8, a ceramic capacitor is shown on the left and an electrolytic capacitor on the right.  Take note of the longer leg on the electrolytic capacitor. 3

This is due to the fact that it is polarized and must be connected to the positive  side.

Figure 7: Capacitor Schematic Symbols

Figure Figure 8: Ceramic Ceramic and Electrolytic Electrolytic Capacitors Capacitors

1.2. 1.2.5 5

LEDs LEDs

A light emitting diode is a a device that emits light when a current is passed through. The brightness of the device is proportional to the amount of current. Because of this, an LED must be wired in series with a resistor to ensure that the LED will not burn out. The position in which the LED is plugged in does matter matter.. The positiv positivee end, also also known known as the  the   anode   anode   must be connected to a greater voltage than the negative part called a  cathode . In Figure 9, the circuit schematic schematic symbol symbol for an LED is shown. Pin 1 designates designates the anode, while pin 2 designates designates the cathode. cathode.

Figure 9: LED Schematic Symbol

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In this lab, two types of LEDs are availabl available. e. The first type is a LED pack which has multiple LEDs in one package that is designed to conveniently fit the breadboa breadboard. rd. The other other is a standa standard rd hole-thr hole-throug ough h pack package age.. The anode is marked marked on the LED pack pack by havin having g text (see Figure Figure 11, while the holeholethrough LED has its anode designated by the longer leg. Typically, the package type is used in the lab experiments due to convenience. The cathode is usually connected connected to a resistor resistor and then to ground. Figure Figure 10 presents presents the two types of  LEDs available. An LED pack is on the left side and individual LED is on the right.

Figure 10: LED Pack and Single LED

Figure 11: Anode side of LED Pack

1.2.6 1.2.6

Integ Integrat rated ed Circ Circuit uitss

An integrated circuit (IC or informally, chip) is a device that provides some functi functiona onalit lity y. These These devices devices come in many many shapes and forms. forms. In these these lab experiments, the dual inline package (DIP) format is used since these devices conven convenient iently ly fit onto onto the breadboard. breadboard. Every Every IC must must have have its supply pins connected nected to power power the device. In these labs, V CC  (5 Volts) and Ground must be connected connected to the device at the designated designated pins. A typical 14 pin IC is presente presented d in Figure 12. There is usually a plastic indent to visualize the alignment of the integrat integrated ed circuit circuit and should should be reference referenced d when placing the integrated integrated circuit circuit onto the breadboard.

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Figure 12: Typical Integrated Circuit 1.2.7 1.2.7

Powe Power r Supply Supply

A pow p ower er supply provides provides the p ower ower needed for the circuit. The red connector connector denotes VCC  (5 Volts) and Ground (0 Volts) is denoted by the black connector. This colour scheme is a typical method of colour-coding wires and is suggested for use during the labs. The power supplies supplies availabl availablee in the lab are shown in Figure Figure 14. In this case, the dedica dedicated ted 5 Volt and Ground Ground chann channel el on the far right right is used. The symbols symbols for V CC  and Ground are shown in Figure 13.   Note  that there are di  ff erent erent symbols for showing V CC  CC .

Figure 13: Power Supply Schematic Symbols

Figure 14: Power Supply

1.2. 1.2.8 8

Tools ools

In the lab, there are two tools that will be used. The first is a wire cutter and stripper. It is used to cut wire and strip the plastic insulation around the wire to expose the metal for inserting inserting into the breadboard. breadboard. The other tool is an IC

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Puller, which is used for the extraction and removal of integrated circuits when placed on the breadboard. These tools are shown in Figure 15.

Figure 15: Lab Tools

1.3

Basic Basic Logic Logic Fun unct ction ionss

In a digital system, any digital logic function can be expressed by using three fundam fundamen ental tal function functions. s. These These functi functions ons are AND, AND, NOT and OR and correcorrespond with their equivalen equivalentt functions functions in a discrete discrete mathematics mathematics course. Each Each of these functions have have multiple inputs but only one output. Their behaviours behaviours are described in truth in  truth tables  which tables  which contain every possible combination of inputs and their their respect respectiv ivee output outputs. s. If a log logic ic function function has n inputs inputs,, it will have have 2 possible combinations. n

1.3.1 1.3.1

NOT Functio unction n

The NOT function is the simplest basic logic function. function. It has a single input and simply inverts it. This function can be described by the following equation: F  =  X 

The behaviour of the function is shown in Table 1. In the SOEN 228/298 labs, the 7404 the  7404  IC is used to provide inverters that perform this function. The symbol for the NOT Gate is shown shown in Figure Figure 16. The wire cutter cutter/st /strip ripper per is on the right and the IC puller is on the left.

Figure 16: NOT Gate Symbol

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X

F

0 1

1 0

Table 1: Truth Table for the NOT Function 1.3.2 1.3.2

OR Functio unction n

The OR function can be described as if any of the inputs are equal to a Logic 1, the output will also be a Logic 1. It can be written as the equation F  =  A + B

The OR function is provided by the 7432  the  7432  IC.  IC. The truth table for the OR function is shown in Table 2. The symbol for the OR gate is shown in Figure 17. A

B

F

0 0 1 1

0 1 0 1

0 1 1 1

Table 2: Truth Table for the OR Function

Figure 17: OR Gate Symbol

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1.3.3 1.3.3

AND Functio unction n

The AND function behaves in such a way that the output is equal to a Logic 1 if and only if, all the inputs are equal to a Logic 1. The OR function can be described as if any of the inputs are equal to a Logic 1, the output will also be a Logic 1. It can be written as the equations F  =  A B or  F  =  AB The AND gate symbol is shown in Figure 18 and the truth table for the AND function is shown in Table 3. In the SOEN 228/298 lab experiments, the AND function is provided by the 7408  the  7408  integrated  integrated circuit. •

A

B

F

0 0 1 1

0 1 0 1

0 0 0 1

Table 3: Truth Table for the AND Function

Figure 18: AND Gate Symbol

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2 2.1

Lab Experime Experiment nt 0: Introdu Introducti ction on to the BreadBreadboard and Electronic Circuits Introd Introduc uctio tion n to Lab Lab Experim Experimen entt 0

The goal of this lab experiment is to become familiar with using the breadboard, integrated circuits, LEDs, power supplies, resistors and switches.

2.2

Using Using the Powe Powerr Supp Supply ly

To supply power to the breadboard, use the dedicated 5V channel and Ground on the far right of the power supply.   When modifying a circuit, it is important  to not perform modifications on your circuit while the power supply is on ! on  !

2.3

Wiring Wiring Switc Switche hess for for Input Inputss

To safely provide proper inputs, we must ensure that the input pin of a device gets gets a steady steady Logic Logic 0 or Logic 1. This This is done by wiring wiring a switc switch h in a manner manner that that uses uses a pull pull down down resistor resistor.. A pull pull down down resistor resistor serve servess as a method method to contro controll the curren currentt flowin flowingg throug through h a device device.. This This is the reason reason why LEDs LEDs requir requiree resist resistors ors in series series.. If the switch switch is open, the input input pin has a resist resistor or and Ground Ground connecte connected d which which leads leads to 0 Volts. olts. When When the switch switch is closed closed,, a connection to V CC  is formed so that the input pin can receive 5 Volts without a short circuit. The implementation of this is shown in Figure 19.

Figure 19: Switch with a Pull Down Resistor

2.4

The Th e 7404, 7404, 7408 and and 7432 Integ Integra rated ted Circu Circuits its

In this lab experiment, the student must verify the truth tables of the three basic digital digital logic functions. functions. These logic functions functions are performed by gates containe contained d 10

on integrated integrated circuits. circuits. The 7404 is an integrated integrated circuit circuit that provides provides 6 NOT gates, 4 AND gates are provided on the 7408 and lastly, 4 OR gates are built into into the 7432. Each Each integ integrat rated ed circui circuitt has its own own layo layout ut of what pins pins serve serve what what function function.. To know what each each pin does, does, a   pin-out diagram   diagram   provides the layout of the integrated circuit in question. The pin-out diagrams for the 7404, 7408 and 7432 are shown in Figures 20, 21 and 22.

Figure 20: 7404 Pin-Out Diagram

Figure 21: 7408 Pin-Out Diagram

Figure 22: 7432 Pin-Out Diagram

2.5

Step Step 0 0:: Wiring Wiring the the Brea Breadbo dboard ard

Before any circuit can be constructed, the breadboard must first be wired properly to ensure that all the rails are powered. powered. Wire each each red rail to V CC  and each blue rail to Ground. 11

2.6

Step Step 1: Contro Controlli lling ng an an LED LED By a Swit Switc ch

The first portion of the lab experiment is to wire an LED controlled by a switch. When the switch is closed, the LED should be powered. The circuit is provided in Figure 23. Take special special notice notice of how the LED is wired wired in the schematic. schematic. Make sure the anode is wired to V CC  CC  and the needed resistor is placed in the  circuit.

Figure 23: Schematic for a Switch Controlled LED

2.7

Step Step 2: Testin esting g the 7404 7404,, 7408 7408 and 7432 7432

In this portion of the lab experiment, the truth tables for NOT, AND and OR functions are to be checked. Outputs are to be driven by LEDs so that when the output output is a Logic 1, the LED is on and off  when the output output is a Logic 0. RememRemember to wire V CC   and Ground correctly! correctly! Ask your lab demonstrator demonstrator to verify before powering on the circuit. Note: For more information information on drawing drawing logic  logic  diagrams and schematics, please see the section A Note on Circuit Schematics.

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3 3.1

Lab Lab Exper Experim imen entt 1: 1: Th The e Half Half Add Adder er Introd Introduc uctio tion n

In this lab experiment, a simple combinational circuit is to be designed and assembled assembled from the basic three gates. A  combinational circuit  is circuit  is a circuit that has an output a ff ected ected by inputs. If a combinational circuit has n inputs, then it has up to 2 possible scenarios scenarios to provide provide outputs. There is no memory in these circuits to use when producing the output. n

3.2 3.2

The Th e Half Half Adde Adderr

The circuit in question is a half a  half adder , a simple circuit that can add up to two. It has two inputs, inputs, A and B, and two two output outputs, s, sum and carry carry out. out. The truth truth table for a half adder is shown in Table 4. A

B

Carry Out

Sum

0 0 1 1

0 1 0 1

0 0 0 1

0 1 1 0

Table 4: Truth Table for the Half Adder

3.3

Step Step 0: Simplif Simplify y the the Fun Functi ction on

The first step of this experiment is to simplify the circuit in such a manner that it can b e implemented implemented by using only the 7404, 7408 and 7432 7432.. This circuit only requires one IC of each type.

3.4

Step Step 1: Impleme Implement nt the Circu Circuit it

This This portion portion of the lab experimen experimentt is to build the actual actual circuit circuit.. Show Show your your lab demonstrator demonstrator your your functioning functioning circuit. The inputs must be controlle controlled d by switches and outputs must drive LEDs.

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4 4.1

Lab Lab Experi Experime men nt 2: Latc Latches hes and and Flip Flip-F -Flo lops ps Introd Introduc uctio tion n

This This lab experimen experimentt is about about sequen sequentia tiall circui circuits. ts. A sequen sequentia tiall circui circuitt diff ers ers from a com combinat binational ional circuit since it has memory. memory. The two primitive primitive types of  memory memo ry elements elements are to be built: a latch and a flip-fop. A latch immediatel immediately y responds to its inputs, while a flip-flop requires an enable of sorts.

4.2 4.2

The Th e S-R S-R Latc Latch h

The S-R Latch Latch is the most basic form form of memory element element possible. possible. It can be built multiple ways but in this lab, the NAND implementation is chosen and shown shown in Figure Figure 24. The output output Q   Q   is the data data output output of the memory memory.. The behavior of this S-R Latch is shown in Table 5. When  S  and  R  are both equal to a Logic 0, the latch enters an undesirable, indeterminate state.

Figure 24: NAND S-R Latch

S

R

Q

0 0 1 1

0 1 0 1

Invalid lid State 1 0 0 1 No Change

Q

Table 5: Truth Table for the S-R Latch

4.3 4.3

The Th e D Flip Flip-F -Flo lop p

The S-R Latch can be improved improved upon. By adding a few components, components, a D Flip Flop Flop can be formed formed.. The advan advantag tages es of the D Flip-Fl Flip-Flop op is that that it is easier easier to handle with only one data input and it does not allow for the flip-flop to enter the indeterminate indeterminate state. Additionally Additionally,, an enable input is also placed onto the flip-flop. The behaviour is detailed in Table 6. There are two two ways a Flip-flop can respond to the enable input. The first way way is called level level triggered. triggered. When the enable signal is asserted, the data can 14

D

E

Q

X 0 1

0 1 1

No Change 0 1 1 0

Q

Table 6: Truth Table Table for the D Flip-Flop Flip-Flop be changed. The other method is called edge triggered and is when the flip-flop responds responds to the change change in the enable signal. When the flip-flop is triggered triggered by the enable going high to low, the flip-flop is said to be negative-edge triggered. If  the flip-flop is triggered by the enable signal going high, it is called positive-edge triggered. triggered. An edge-triggere edge-triggered d flip-flop is far more desirable due to the change in data being nearly instantaneous, while the level-triggered flip-flop provides an opportunity opportunity to have have data modified. A block diagram of the level triggered triggered D Flip-Flops Flip-Flops is shown shown in Figure 25. On the left is an edge-trigge edge-triggered red flip-flop and on the right right is a level-trigger level-triggered ed flip-flop. Figure 26 details the implementatio implementation n of the level-triggered D Flip-Flop.

Figure 25: D Flip-Flop Block Diagrams

Figure 26: Level-Triggered D Flip-Flop Implementation

4.4

Step Step 0: Assemb Assemble le the the S-R Latch Latch

The first step in this lab experiment is to assemble the S-R latch. Since NAND gates are not available, an equivalent circuit can be made by using an AND

15

gate with a NOT gate connected to its output. An example of this is shown in Figure 27. Show your lab demonstrator the functioning circuit.

Figure 27: Implementation of a NAND Gate

4.5

Step Step 1: Assemb Assemble le the the D Flip Flip-Fl -Flop op

Once the S-R latch has been built and verified, verified, it is time to build the D flip-flop. The variant implemented is a level-triggered flip-flop as seen in Figure 26. When done, show your lab demonstrator the functioning circuit.

4.6

*Step *Step 2: Build Build A Posit Positiv ive-Ed e-Edge ge Trigg Triggered ered D Flip-Flo Flip-Flop p

If there is time remaining in the lab period, a positive-edge triggered D flip-flop can be built from two level-triggered D flip-flops. A block diagram is shown in Figure Figure 28. If the invert inverter er was mo move ved d so that the enable enable was was inve inverte rted d on the leftmost leftmost D flip-flop, flip-flop, it would would act as a negative-edge negative-edge triggered triggered D flip-flop. flip-flop. This method is called the master-slave  the  master-slave  implementation.  implementation.

Figure 28: Implementation of a Positive-Edge Triggered D Flip-Flop

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5 5.1

Project Project Experime Experiment nt 0: The Timing Timing Signal Signal GenGenerator Introd Introduc uctio tion n

In this project experiment, experiment, the timing timing signal generator generator is built. This is essenessential for the project since the timing signal generator produces the clock signal, important enable signals and will dictate how fast the computer will function. Before demonstrating the circuit, a few definitions and devices must be reviewed.

5.2

Duty Du ty Cycle Cycle and and Freq Frequen uency cy

The first term that is of interest interest is frequency frequency.. Frequency requency is how fast something something may alternate or repeat. It is measured in Hz and is defined as f   = s

1 T 

s

Ts  is the period (in seconds) of how long the signal lasts until it is repeated. To calculate the duty cycle, use the following equation where t is the amount of  time that the signal is set to a logic 1: DC  =

t T 

s

5.3 5.3

Timi Timing ng Diag Diagra rams ms

A timing diagram is a useful tool to determine how a system may operate when signal signalss are bound bound to change. change. It is simply simply composed composed of a time time axis axis and all the signals of concern. Figure 29 demonstrates how the duty cycle and period may look on a timing timing diagram diagram.. In this example example,, the frequen frequency cy is 50 MHz (whic (which h gives a timescale in nanoseconds). The period is found to be 20 ns. If we were to use the frequency equation, it can easily be seen that the frequency is in fact 50 MHz.

Figure 29: Sample Timing Diagram

5.4

A Revie Review w on Ord Orders ers of of Magni Magnitud tude e

Before proceeding further, a review on orders of magnitude is necessary. Table 7 displays the orders of magnitude to be mindful of. 17

Orde Orderr of Ma Magn gnit itud udee

Prefi Prefix x

109 106 103 10−3 10−6 10−9

Giga (G) Mega (M) Kilo (K) Milli (m) Micro (µ) Nano (n)

Table 7: Orders of Magnitude

5.5 5.5

The Th e 555 555 Time Timerr

At the core of the Timing Signal Generator circuit, a versatile integrated circuit called called the 555 555 Timer is used. used. The 555 diff ers ers from all the integrated circuits used used at this this point since since it is an 8 pin device device.. This This device has many many modes of  operation but in this lab, it is only used in  astable  mode  astable  mode so that it can provide a signal that alternates between a logic 0 and logic 1 as seen in Figure 29. The pin-out diagram for the 555 timer is shown in Figure 30.

Figure 30: 555 Timer Pin-Out Diagram Like any integrated circuit used in this lab, the V CC  and GND pins must be connected connected for the device to operate. Another Another thing worth noting noting is that the 4th  R ST  must be a logic 0 so to prevent pin is a reset pin. To reset the 555 timer,  RST  the device from constantly resetting, it is wired directly to V CC. The clock pulse is generated by using an RC (resistor and capacitor) circuit and measuring its voltage. This RC circuit constantly charges and discharges. Inside the 555 timer is a flip flop which switches value when the voltage in the RC circuit reaches 1 VCC or 23 VCC . The value value at the output of the timer timer is the value value of the flip 3 flop. To build a clock signal generator, generator, the frequency frequency and the duty cycle must be known. Two equations are used for determining these values. To determine

18

the frequency, the following equation is used: f   = s

1 T 

=

s

1.44 (R1  + 2 R2 )C 2

To determine the duty cycle, the following equation can be used: D  =

R2 R1  + 2 R2

Figure below shows shows a typical typical astable circuit circuit with the output of the timer called CLK (Clock). (Clock). Note Note how pin 4, the reset reset pin, is wired wired to V CC . The capac capacito itorr C1 is optional optional but desirable to have have because it can reduce reduce noise. Even Even though pin 1 and 8 are not shown, they are wired to their respective V CC  and Ground rails.

Figure 31: 555 Timer Astable Circuit

5.6

The Th e 74LS1 74LS164 64 SIPO SIPO Shif Shiftt Regis Register ter

The other integrated circuit of interest in this lab experiment is the 74LS164 SIPO (Serial (Serial In, Parallel Parallel Out) Shift Register. Register. This device takes takes an input and shifts shifts all the contents contents by one output every clock cycle. It has 8 outputs which can all be accessed at any time but only one input. A shift register moves values from one internal internal flip flop to the next. The 74LS164 moves moves values values from Q A to QH . A graph graph showing showing this behavio behaviorr for a 4 bit SIPO shift shift regist register er is seen seen in Figure 32. The pin-out diagram for the 74LS164 is shown in Figure 33.

Figure 32: Shift Register Register Behavior Behavior To wire the 74LS164 correctly, pin 14 must be wired to V CC  and pin 7 to Ground. Ground. The outputs outputs are the pins that correspond to Q A to QH  where QA is the first output stage.   It should also be noted that the values from these pins  19

Figure 33: 74LS164 Pin-Out Diagram are denoted by T 0  0  to T 7  7 . Pin 9 is used to clear the register. It is triggered when the input is a logic 0 in a similar manner as the 555 timer reset pin and must be wired to VCC  to not reset continuo continuously usly.. The input to the register register is A B . With this in mind, if A = 1 and B = 0, the next value taken into the register will be a 0. When When the device device is powere powered d on, all intern internal al flip-flops flip-flops are set to 0 and when the CLR pin is triggered, the device is returned to this state. •

5.7

Feedbac eedback k For For the Timing Timing Signal Signal Genera Generator tor

The last thing necessary necessary for the timing signal signal generator is feedback. feedback. The 555 timer provides a clock which is fed into the shift register but now the inputs to the shift register need to be determined. determined. Feedback eedback is taken from the shift register and fed to a 4 input NAND gate (7420 IC). The output of this NAND gate gate is supplied supplied to pins 1 and 2 of the 74LS164. 74LS164. By doing so, the input to the shift register will in fact be the output of the NAND gate  Y  =  Y  Y . The inputs of the NAND gate are taken from Q B , QD , QF  and QG . Figure 34 provides the pin-out diagram for the 7420 Quad Input NAND Gate. •

Figure 34: 7420 Pin-Out Diagram When the timing signal generator is powered on, all outputs are set to 0. Due to the feedback provided by the 7420, this will place a logic 1 at the shift regist register er input for the next clock clock cycle. cycle. After After several several clock clock cycles cycles,, the shift

20

regi regist ster er’s ’s output outputss will will all all be set set to logic logic 1. At this this point point,, the the inpu inputt to the register will become a 0. A pulse of two logic 0 values will circulate through the shift register’s register’s outputs outputs from this point onward. onward. Since all the registers registers used on the computer use an  active low Enable  signal, Enable  signal, this pulse will trigger the enable  the  enable  inputs or outputs on these registers.

5.8

Assemb Assembling ling the Timing Timing S Signa ignall Genera Generator tor

The first portion in assembling the timing signal generator is to build the circuit in Figure 31. Your lab instructor instructor will provide the values values of the resistors resistors and capacitors capacitors used for the timing timing circuit. Wire an LED to pin 3 of the 555 timer IC. This will provide a visual representation of the clock signal generated by your circuit. It is suggested that you do not remove this LED for the remainder of the project. •

  Build the circuit in Figure 3. Your lab instructor instructor will provide you with the values used for the capacitor and resistors. Connect an LED to pin 3 of the 555 timer. This will provide provide you with a visualizatio visualization n of the clock signal signal.. It is sugges suggested ted that you keep keep this this LED for the remain remainder der of the project to help with troubleshoot troubleshooting. ing.

•

 Assemble the shift register and feedback circuit.

•

 Wire up the 74LS164 and 7420 ICs by connecting V CC  and GND

•

 Take the outputs Q B , QD , QF  and QG  of the 74LS164 and connect them to the inputs of a NAND gate provided by the 7420

•

 Connect the output of the NAND gate to the inputs of the 74LS164

•

 Connect the clock generated by the 555 timer to the 74LS164

•

 Wire the outputs of the 74LS164 to LEDs

5.9 5.9 •

•

•

Some Some Proje Project ct Tips Tips  Use a colour scheme : scheme : Red wires should be used for V CC , black wires for GND. Any other colours used is up to the students to decide. Remaining consistent with colour choices will make the project easier to troubleshoot.   Use short wires : wires : Longer Longer wires wires ma may y make things things more di fficult to troubleshoo bleshoot. t. Longer Longer wires can get in the way during during troubl troublesh eshooti ooting ng and become harder to trace.   Maximize your space : space : Maximizing Maximizing your your space will go a long way. way. If you decide to spread things out, you may run out of space on your breadboard and have to redo your work to create space for other parts of the project.

21

•

•

 Beware of exposed wire : wire : When stripping wire, sometimes too much metal can be exposed. If you use a wire with a substantial amount of metal exposed, be careful that the metal does not make contact with other exposed wires. If this happens, your circuit may not function as desired despite it being wired correctly. Additionally, later on in the project, too much exposed wire can lead to unusual behaviour in your circuit due to magnetic fields. fields. Remove Remove just enough of the coating to get a good connection connection into into the breadboard.   LEDs can be used to troubleshoot : troubleshoot : An LED can be a useful tool to troubleshoot a circuit that may not function properly. By using an LED and a long wire, a student can determine the logic value at any point in a circuit if the LED turns on.

22

6 6.1

Proje Project ct Exper Experim imen entt 1: Th The e Bus, Bus, Arit Arithm hmet etic ic Unit and Program Counter Introd Introduc uctio tion n

This lab focuses around building the bus of the computer and implementing several crucial components of the computer, namely the arithmetic unit and program program counter. counter. Four integrated integrated circuits are used for this experiment, experiment, three 74LS395 74LS395 4-bit shift registers registers and a 74LS283 74LS283 4-bit adder. Before Before continuing continuing any further, let us focus on what a bus is and why it is of concern.

6.2 6.2

The Th e Data Data Bus Bus

A bus is a series of wires that numerous numerous devices devices are connected connected to. Instead Instead of  patching numerous cables on a breadboard or traces on a circuit board, a set of  wires is used for multiple multiple devices to pass data through. If multiple multiple devices are connected onto a bus, a major concern is how can the devices be controlled so that they do not process the data when needed? needed? In the case of the SOEN228 lab, this is handled by the timing signal generator built in the previous lab. As an example, assume that a 4 bit bus is needed for a project on a breadboard. To implement it, each row can be lengthened beyond the gaps on a breadboard by running running one wire and connecting connecting it to the next row. By doing this, long rows can be linked with the same logic value and can be used to connect di ff erent erent devices. This can be visualized in Figure 35. For this experiment, the bus lanes are B3 to B0 , going from left to right. An advantage of using a bus is that devices have a centralized point in which they can communicate without patching numerous cables in many directions. The two two com compone ponent ntss being being built built in this this lab use the bus to com commu munic nicate ate.. In this lab experiment, a four bit bus similar to what is shown in Figure 35 is constructe constructed. d. The program counter counter and arithmetic arithmetic unit are connected connected to this bus and comm communica unicate te through it. These devices devices are controlle controlled d by the timing signal generator generator built previously. previously. The first four pulses of the instruction instruction cycle are used: T0 , T1 , T2  and T3 . When dealing with numerous devices on a bus, some method is needed so that the devices on the bus that output data do not interfere with each other. The shift registers used in this lab experiment have tri-state outputs. This means that they can output a logic 0, logic 1 or a  high-impedance value   value   (also known as a High-Z). High-Z). When these devices are outputting outputting a High-Z, High-Z, they e ff ectively ectively have no output output on the bus. This This is used so that that device devicess can share share the bus without without having multiple devices try and output their data at the same time.

6.3

The Th e Progra Program m Coun Counter

The Program Counter of a computer is an essential register. It holds the location of the instruc instructio tion n to be execut executed. ed. During During the execut execution ion cycle, cycle, the program program counter is incremented through the bus so that the next instruction can be read 23

Figure 35: 4 Bit Bus Example when needed. needed. It can be envisioned envisioned as a bo okma okmark rk used to keep the place in a rather rather large book. It is implemented implemented by using a 74LS395 shift shift register. register. Since the 74LS395 is a four bit shift register, the computer will have a total of 16 available instructions before it rolls over back to 0000.

6.4

The Th e Arithm Arithmeti etic c Un Unit it

The arithmetic arithmetic unit provides provides the ability ability to incremen incrementt the program counter. counter. Without this, the computer would just execute a single instruction and would not be of much much use. use. The arithme arithmetic tic unit is create created d by using using a 74L 74LS39 S3955 shift shift register and a 74LS283 4-bit adder. The inputs of the adder are taken from the bus, the output is fed to the inputs of the 74LS395 belonging to the arithmetic unit. The outputs of the 74LS395 are fed to the bus as well. Since the 74LS395 has the ability to control the state of its outputs, the Timing Signal Generator is used to ensure that only one shift register is outputting data at a time. Ultimately, this allows the program counter to increment itself and allow the computer computer to run any program provided provided.. Additionally Additionally,, the arithmetic arithmetic unit is used as the incremente incrementerr when the IncB instructio instruction n is executed executed (more on that in a later project experiment experiment). ).

6.5

74LS2 74LS283 83 4-Bit 4-Bit Adde Adderr

The 74LS283 is a 4-bit adder in a 16 pin package. The pin-out diagram is shown in Figure 36. Pin 16 must be wired to V CC  and Pin 8 must be wired to GND.

24

The pins labeled S0 , S1 , S2  and S3  are the sum outputs, X0 to X3 are one set of  inputs and Y0 to Y3 are the other input. For this lab, the inputs Y 0 to Y3 are grounded while pin 7, the carry in is wired to V CC . Inpu Inputs ts X0 to X3  is taken from the bus. By doing this, the sum will always be  P C  =  =  P C  +  + 1.

Figure 36: 74LS283 Pin-Out Diagram

6.6

74LS3 74LS395 95 4-Bi 4-Bitt Shift Shift Regis Register ter

The 74LS395 is a 4-Bit Shift Register. In this case, it will be used as a regular register register with its shifting ability ability disabled. The pin out diagram can be seen in Figure Figure 37. 37. Each Each Pn  pin can be seen as an input for a D flip-flop, while each Qn  pin can be seen as the output for the flip-flop. The master reset pin is tied to VCC  to prevent prevent the register register from resetting. resetting. Pin 7 serves serves as a control control mode for parallel loading or shifting and is set to V CC  as well so that the register will do parallel loads.  In case there are no 74LS395s left, consult the section called  “Using the 74LS173 As A Replacement for the 74LS395”

Figure 37: 74LS395 Pin-Out Diagram Once again, pin 16 must be wired to V CC  and pin 8 to ground ground.. The clock clock for this register to update is negative edged which works with the timing signal generator generator built built in the previous lab. Pin 7 is wired to V CC  so that the register 25

will simply simply load all the data at once. once. Becaus Becausee of this, this, pin 2 is wired wired to GND in this this lab. Pin Pin 1 is also also wired wired to VCC  except for the case where the register needs needs to be reset. reset. At that that point, point, the wire attac attached hed to pin 1 can be bridged bridged to GND mome momenta ntarily rily.. Additionally Additionally,, the output is controlle controlled d by an active active low input. When pin 9 is set to logic 1, the outputs are high impedance.

6.7

A Brief Brief Overvi Overview ew on the the Program Program Counter Counter and and IncreIncrementer System

Each of the shift registers use one the first four clock pulses generated by the 74LS164: 74LS164: T0 , T1 , T2  and T3 . When When T0   becomes active, the program counter register outputs (the address of the current instruction) its contents onto the bus. bus. The value value flows into the 74L 74LS28 S2833 4-bit 4-bit adder and is increm incremen ented ted by 1. T1  becomes active and the SUM register stores the data. Afterwards, when T 2 becomes active, the output of the SUM register becomes available on the bus. The last step in the cycle is when T 3  becomes active and causes the PC register to write the incremente incremented d value. value. The end result of this cycle can b e expressed expressed as X = X + 1. Once Once the register register reach reaches es 1111, 1111, it will roll over over to 0000 and repeat repeat the cycle. cycle. A third third register register is placed placed on the bus to be used used as a tool to mirror any register. It must use the same timing signal of the register intended to be mirror mirrored ed for it to work. work. The outputs outputs are wired to LEDs and the inputs inputs are taken from the bus.

6.8

Assem Assembli bling ng the Circui Circuitt

This portion of the computer computer makes use of the Timing Signal Generator Generator and its first four pulses, T 0 to T3 . The wiring wiring is presen presented ted on the follow following ing pages pages in Figures 38, 39, 40 and 41.   It is up to the student to determine what reference  each register and part is.  The first signal, T 0 , triggers the output of the program counter. It will be wired to the connection called PC out . T1  triggers the inputs of the SUM register so it will be connected to SUM in  respectfully. T2  triggers the output of the SUM register, so it will be wired to SUM out  and lastly, T3  triggers the input of the program register so it will be wired to PC in . Additionally, the output enable on the mirror register is tied to Ground so that it will always output the contents to a set of LEDs, making it useful for a debugging tool.

26

Figure 38: Program Counter Register Schematic

27

Figure 39: 4-Bit Adder Schematic

Figure 40: Sum Register Schematic

28

Figure 41: Mirror Register Schematic

29

7 7.1

Project Project Experime Experiment nt 2: Data Data Registe Registers rs and the Memory Address Register Introd Introduc uctio tion n

In this lab experiment, the data registers for the processor and the memory address register are placed into the circuit.   It is necessary that the bus and  timing signal generator have been produced at this point since these registers are  dependent on the timing signal generator and bus.   Before continuing onward, let us define what purpose the data registers and memory address register serve.

7.2 7.2

Data Data Regi Regist ster erss

A data register is a memory storage device that holds data. For the purpose of  the lab, these registers serve as storage devices for the processor. Data registers are necessary because generally manipulating contents of memory is slow or the computer is not able to do so. The ability to do so is referred to as DMA, direct memory access.

7.3

Puttin Putting g It All All Toge Togeth ther er

In this lab experiment, the 74LS395 shift register is used for the three registers needed in this experiment. This is essential because the three registers discussed do need to use the bus. The 74LS395 74LS395 has tri-sta tri-state te outputs outputs which which mak makee it desira desirable ble for use with with a bus. bus. When When the output output enable enable of the 74L 74LS39 S3955 (pin (pin 9, see Figure 37) is a logic 1, the outputs are disconnected from the bus by using the high-impedance high-impedance mode (Hi-Z). (Hi-Z). Three registers registers are needed needed for this portion of  the project: data registers A, B and the memory address register. The data registers at this point in time are wired to have both their inputs and outputs wired to the bus but their output enable and clock pins are to be tied to VCC   to disable the inputs inputs and outputs. outputs. The MAR is wired diff erently. erently. A memory address register’s purpose is to constantly provide the address of  the RAM used used for the instru instructi ction. on. Becaus Becausee of this, this, the registe registerr must must obtain obtain its contents from the bus when the Program Counter register outputs its value. The output enable pin is wired to ground to ensure that it will always output. For now, the outputs are wired to LEDs to demonstrate that the register works. In the forthcoming parts of the project, the outputs of this register will be wired to the address address line inputs inputs of the memory memory.. The clock clock for the MAR should should be wired to T1 . This is done so that the MAR has the address of the memory for the complete duration of the instruction execution. Many of these connections are temporary and will be modified in the future. The enables on the data registers will eventually be wired so that they can function with the Control Signal Generator seen in Project Experiment 4. The MAR is wired to LEDs to display its contents and verify that it does in fact work. In the next experiment, the outputs of the MAR are wired so that it can provide the address necessary for the RAM. 30

The functionality of these registers must be shown to the lab demonstrator. The timing signals produced by the Timing Signal Generator are to be used to demonstrat demonstratee that they are wired correctly correctly.. Whichev Whichever er timing signals signals used to show the functionalit functionality y is up to the student student to determine determine.. Because Because of this, it is critical critical that the previous previous lab experiment experimentss have have been completed completed with successful successful results. results. A sample of how the data registers are intended intended to be wired is shown in Figure 42, while the wiring for the MAR is shown in Figure 43.

Figure Figure 42: Data Register Register Schematic Schematic

Figure 43: Memory Address Register Schematic

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8 8.1

Projec Projectt Exper Experim imen entt 3: Prog Progra ram m Memo Memory ry Introd Introduc uctio tion n

In this experiment, the program memory and its supporting circuit is wired up and tested. tested. Before Before delving into the details of how the computer computer makes makes use of these hardware components, a brief review of memory, tri-state bu ff ers ers and decoders decoders will b e presente presented. d.

8.2

A Brie Brieff Ove Overvi rview ew on on M Memo emory ry

Memory is a storage device conceive Memory conceived d for the storing of multiple multiple bits. While the diff erent erent types of memories will not be discussed here, the basics of how a mem memory ory is struct structure ured d will will be mentio mentioned ned.. For the experim experimen ents ts in this this lab, lab, Random Random Access Memory (RAM) is used. This implies that the memory is not accessed in a sequential manner like traversing addresses (starting from address 0 to address 1 to address 2 and so on until the desired location has been reached) but rather, the contents of a cell can be read or written by provided an address. This behaviour behaviour is similar similar to an array when programming programming.. In this lab, the two properties of memory to be concerned with are the number of cells and the size of data they can hold. To read or write a cell’s contents, contents, the address address must be provided. provided. The number number of addresses addresses available available are 2 where n is the number of  address lines available. As an example, if a memory has 5 address lines then it has 25 or 32 addresses. Now, let us assume this memory holds a total of 8 bits (1 byte) byte) in each each cell. cell. We can then then say that this is a 32x1B memory memory or a 32B memory. An example of this memory and its contents is shown in Table 8. Note  that b denotes bits, while B denotes bytes. A 4Mb memory memory means  4 × 220 bits, while a 4MB memory means  4 means  4 × 220 bytes. n

Address

D7

D6

D5

D4

D3

D2

D1

D0

00000 (0x00) 00001 (0x01) 00010 (0x02) 00011 (0x03) 00100 (0x04) ... 11111 (0x1F)

0 1 1 0 1

1 0 1 0 1

1 1 1 1 1

1 0 0 0 1

0 0 0 1 0

0 1 1 1 1

0 0 0 0 0

0 1 1 1 1

1

1

0

1

.. . 0

0

1

1

Table 8: Sample Layout of a 32 X 1B Memory

8.3 8.3

Deco Decode ders rs

A decoder is a combinational circuit that takes m inputs and sets the one output that corresponds corresponds with the numerica numericall value in binary as active. active. It produces an output output in the form form of one-hot one-hot.. This This implie impliess that that if a 3 bit decoder decoder is active active 32

high, a valid output would be 0b00100000 or 0b1101111 if it is active low. The complete truth table for a 2 bit decoder is shown in Table 9. Inpu Inputt 00 01 10 11

Acti Activ ve High High

Acti Activ ve Lo Low w

1 0 0 0

0 1 1 1

0 1 0 0

0 0 1 0

0 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Table 9: Truth Table for 2 bit Active High and Active Low Decoders

8.4 8.4

SCM2 SCM21C 1C14 14EE-4 4 1K 1K x 4 RAM RAM

The SCM21C SCM21C14E 14E-4 -4 is the memory memory used in the SOEN22 SOEN228 8 Lab. It is a 1K X 4 RAM. This implies that it holds a total of 4096 bits with 4 bits per cell. It has 10 address lines and therefore therefore also has a total of 1024 addresses. addresses. A total of 18 pins pins are found found on the SCM21C SCM21C14E 14E-4. -4. Pin 18 is VCC   and pin 9 is GND, and both must be connected. To read from and write to the device, pins 11 to 14 are I/O pins which serve the purpose of both reading and writing memory. memory. There are two two control control pins on the SCM21C14ESCM21C14E-4. 4. The first pin is the  chip select  on pin 8. It is an active low input. When Pin 8 is set to logic 1, the I/O pins are set to a high impedance (High-Z) mode. When pin 8 is set to logic 0, the chip is enabled enabled and the I/O pins pins are no longer longer in the high impedan impedance ce state. state. The device’s behaviour is dictated by pin by  pin 10  when 10  when enabled. Pin 10 is known as the write enable . It is also active active low and control controlss the I/O pins pins if pin 8 is log logic ic 0 as well. When pin 10 is given a logic 1 value, the I/O pins output output the data at the location provided by the address pins. If pin 10 is given a logic 0, the data on the I/O pins is writte written n to the addres addresss provid provided ed by the address address pins. This This is summarized summarized in Table 10. The pin layout layout is shown shown in Figure 44.   Note: This  RAM is volatile, it does not store its contents when powered down.

Figure Figure 44: SCM21C14ESCM21C14E-44 Pin-Out Pin-Out Diagram Diagram

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CE

WE  

I/O Pin Behavior Behavior

0 0 1

0 1 X

Write Contents to Address Output Contents at Add Address High Impedance Mode

Table 10: Behavior of SCM21C14E-4

8.5

7442 7442 Binary Binary Coded Coded Deci Decimal mal to Decim Decimal al Decode Decoderr

The 7442 decoder decoder is a 4 input, input, 10 output output active active low decoder. decoder. For any input greater than 9 or 0b1001 the value across all outputs will be a logic 1 since there are no outputs corresponding corresponding with any inputs greater greater than 9. The truth table for the 7442 is shown below in Table 11. I 3

I 2

I 1

I 0

Y 0

Y 1

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

Y 8

Y 9

0 0 0 0 0 0 0 0 1 1

0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1

0 1 1 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1 1 1

1 1 0 1 1 1 1 1 1 1

1 1 1 0 1 1 1 1 1 1

1 1 1 1 0 1 1 1 1 1

1 1 1 1 1 0 1 1 1 1

1 1 1 1 1 1 0 1 1 1

1 1 1 1 1 1 1 0 1 1

1 1 1 1 1 1 1 1 0 1

1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 1

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

1 1 1 1 1 1

Table 11: Truth Table for 7442 Decoder The 7442 comes in a 16 pin dual inline package. package. This implies implies that pin 8 is ground and pin 16 in V CC . Both Both pins pins must must be connec connected ted to their their respectiv respectivee supplies supplies to allow allow proper functionalit functionality y. The pin layout layout for the 7442 is shown shown in Figure 45.

8.6

74LS1 74LS157 57 Quad Quad M Mult ultipl iplex exer er

The 74LS157 Quad Multiplexer is an integrated circuit that contains four multiplexers plexers controlled controlled by a single select select signal. signal. A multiplexe multiplexerr functions as a switch. In this case, case, there there are 8 input input pins, 4 output output pins and one select select pin. If the

34

Figure 45: 7442 Pin-Out Diagram select pin is set to logic 0, the multiplexers will output the data on the A input. On the other hand, if the select pin is set to logic 1, the multiplexe multiplexers rs will output output the data on the B input. The 74LS157 also has an enable pin (pin 15) which is active active low. If the enable pin is set to an active active high, the outputs outputs of the 74LS157 74LS157 are in high impedance mode. The pin-out diagram is shown in Figure 46.

Figure 46: 74LS157 Pin-Out Diagram

8.7

74LS1 74LS126 26 Tri-Sta ri-State te Buff er er

The 74LS126 74LS126 tri-state tri-state bu ff er er provides 4 bu ff ers ers that are controlled by independent enable signals for each bu ff er. er. A buff er er simply outputs the value it is given as an input. input. The tri-state tri-state feature makes makes using this integrate integrated d circuit circuit ideal for busses. When the enable signal is logic high, the output is enabled. If the enable signal is a logic low, the output is a high-impedance mode which acts as if the outputs outputs were disconnected. disconnected. The pin layout layout is presente presented d in Figure Figure 47.

8.8 8.8

The Th e Exper Experim imen entt

The experiment is split into three components: the first component is to assemble the circuit needed to program the RAM, while the second task is to program the RAM. Lastly, students are to demonstrate to their lab demonstrator what they have programmed.

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Figure 47: 74LS126 Pin-Out Diagram 8.8.1 8.8.1

Buildi Building ng the the Circui Circuitt

The circuit circuit is built built by using using the schema schematic tic shown shown in Figure Figure 48. Pull-d Pull-dow own n resistors resistors are necessary necessary and cannot cannot be omitted. omitted. The address lines A 4 to A9 are grounded so that the RAM will not use more than four bits to address since the memory memo ry address register register and program counter counter only provide up to 4 bits. This implies that the computer is able to execute a program of 16 instructions. The write enable pin is tied to a switch so that the memory can be easily switched between read or write modes. Anothe Anotherr bus is used to input the data. data. This This is done done so that that the data can be input then read without needing to switch wires around while the circuit is operati operationa onal. l. The data being inputt inputted ed is fed into into a 74L 74LS12 S1266 quad quad tri-st tri-state ate buff er. er. The control pins of these bu ff ers ers are tied to a switch called PROGRAM. When the switch provides a logic 1, the bu ff ers ers output their contents. When set to 0, the bu ff ers ers are in high-impeda high-impedance nce mode. Another Another set of tri-state tri-state bu ff ers ers are placed to output to the 7442 used to generate the instruction signals. This extra set of bu ff ers ers use the inversion of PROGRAM to enable the outputs. This is done so that the computer does not attempt to execute unwanted instructions while transitioning transitioning from reading and writing writing memo memory ry.. The switches switches D3 to D0 are used for data inputting. The address lines A 3 to A0  are tied to switches and fed through a 74LS157 multiplexe multiplexer. r. This is necessary necessary since the MARs outputs will also be wired into into these address lines. The multiplexer’s select is controlled by the ADDRSELECT switch. 8.8.2 8.8.2

Progra Programmi mming ng the RAM

Below are the steps to program the RAM. Please follow these instructions carefully or else the programming will fail. 1. Turn on the circuit. Do not power down down the circuit at all or else any saved saved data will be lost and the process must be restarted. 2. Set the CE switch switch to high. high. By doing this, this, the RAM is in high impedance impedance mode.

36

3. Set the WE switch to low. This sets the RAM into write mode when the CE switch goes low. 4. Set the PROGRAM switch to high. This enables the bu ff ers ers needed and disables the ones not. 5. Set the ADDRSELECT ADDRSELECT switch to low. This selects selects the address switches switches to the RAM. 6. Set the address address switches switches accordingly accordingly.. Start at 0000. At this moment moment as well, set the data switches to reflect the desired instruction. 7. Set the CE switch to low. This will cause the RAM to write the instruction defined by the data switches at the address provided by the address switches. 8. Repeat from Step Step 2 until until all 16 instructions instructions have have been stored in the RAM. 8.8.3 8.8.3

Displa Displayin ying g the Conten Contents ts of the RAM RAM

At this point, the circuit should still be powered. If you do shut down the circuit at any point in time, you must reprogram your RAM. Set the CE switch to high so that the RAM is una ff ected ected by any work being done. The write enable pin is now to be set to a logic high so that the RAM enters read mode. Additionally, the PROGRAM PROGRAM switch switch should be set to low as well. The output of the RAM is fed into the decoder which will then produce the appropriate control signal for the computer to execute. execute. The decoder’s outputs outputs are the instruction instruction signals ISIG0  to ISIG5 . Please refer to the schematic is shown in Figure 48. To set the RAM for outputting data: 1. Keep the circuit circuit powered. powered. 2. Set the CE switch to high to set I/O pins to high impedance mode. 3. Set PROGRAM PROGRAM switch to low to enable tri-state tri-state bu ff ers ers for the decoder and disable the input buff ers. ers. 4. Set WE switch to high to enter enter read mode. 5. Set the ADDRSELECT ADDRSELECT switch switch to high. 6. Set the CE switch to low to re-enable re-enable the RAM. 7. Reset Program Program Counter Counter if needed. needed.

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8.8.4 8.8.4

Demonstra Demonstrating ting Your Work

For this experiment, the students are expected to fill all 16 addresses in memory and be able able to show show their conten contents ts to the lab demonst demonstrat rator. or. It is best for debugging to make a table of the values you input, the expected result and what result is actually obtained. obtained. The content contentss of each each address is to be determined determined by the students. students. The outputs outputs of the 7442 decoder are intended intended to b e wired to LEDs to visualize the results. Remember that anything above 0101 is a NULL instruction!

38

Figure 48: RAM Circuit Diagram 39

9

Proje Project ct Exper Experim imen entt 4: Th The e Con Contro trol Sig Signal nal General

The control signal generator is the portion of the project that renders the computer puter able to execute execute function functions. s. Up to this point, point, a progra program m count counter, er, timtiming/clock system and memory have been implemented. This experiment builds the combinational logic needed to facilitate the instructions decoded from memory. The decoded values are then fed into the control signal generator to produce the necessary signals to execute instructions. The timing of this computer is subdivided into 8 pulses, T 0 to T7 . Only Only T0 to T3  have been used and have been used solely to increment the program counter. counter. The remaining remaining four pulses are used for instructio instruction n execution. execution. While the design built has support for up to six instructions, only three will be implemente plemented. d. There is no definition for which instruction instruction signal corresponds corresponds with a particular value stored in the memory.  It is up to the student to decide what  each instruction signal from the decoder should trigger.

9.1

The Th e IncB IncB Instru Instructi ction on

The IncB instruction is an instruction that increments the value of B by 1. This instruction makes use of the bus, the 74LS283 4-bit adder and SUM register that have have been b een used only for incremen incrementing ting the program counter counter so far. In previous experiments, the 74LS283 was wired to increment values by 1 and this does not change. change. This behaviour behaviour is in fact identical identical to how the program counter counter works but with diff erent erent timing signals. The IncB instruction is executed by doing the order of tasks: 1. Data Register Register B outputs outputs its contents contents onto the bus 2. SUM Register Register writes the incremen incremented ted value value of B = B + 1 3. SUM Register outputs value of B = B + 1 onto the bus 4. Data Register Register B writes the contents contents of the bus

9.2

The Th e MovA MovAB B Inst Instruc ructio tion n

The MovAB instruction simply copies the values of Data Register A to Data Register Register B by using the bus. This is achieved achieved by doing the following tasks tasks in order: 1. Data Register Register A outputs outputs its contents contents onto the bus 2. Data Register Register B writes the contents contents of the bus

40

9.3

The Th e MovBA MovBA Instru Instructi ction on

The MovBA instruction operates and behaves the same way as the MovAB instruction but the contents of B is copied to A. It is achieved by: 1. Data Register Register B outputting outputting its content contentss onto the bus 2. Data Register Register A writing the content contentss of the bus

9.4

The Th e IncA IncA Instru Instructi ction on

Similarly, the IncA instruction behaves the same way as the IncB instruction behave behavess and incremen increments ts the value value of A by 1. The instruct instruction ion is omi omitte tted d but can be implemented as an exercise by the students. It is executed by doing the following: 1. Data Register Register A outputs outputs its contents contents onto the bus 2. SUM Register Register writes the incremen incremented ted value value of A = A + 1 3. SUM Register outputs value of A = A + 1 onto the bus 4. Data Register Register A writes the contents contents of the bus

9.5

Implemen Implementing ting the Signal Signal Gene Generato ratorr

To implement the Control Signal Generator for three 3 instructions, two 7432 ICs and one 7408 IC are needed. To implement implement the additional additional IncA instrucinstruction, additional additional logic is needed and it is up to the student student produce it. Before Before proceeding onward, the signal IncB is an output of the 7442 decoder used in the previous experiment designated by the student to increment the data register B. Similarly, MovBA and MovAB are also output signals chosen by the students students.. There are two control control signals for the Data Register Register B, B in  which controls the input and Bout which controls the output. Similarly, two signals exist for the Data Register A, A in   and Aout . The input input signal signal goes to the clock clock of  the register, while the output enables of the registers is fed the output signals. Additionally, the SUMin  and SUMout  signals for the SUM register are modified as well. The supporti supporting ng logic is shown shown below, below, in Figure 49.   Each instruction  should should be implemented implemented and tested tested at a time. This will make it easier easier to diagnose  diagnose  and debug should any issue arise.

41

Figure Figure 49: Control Control Signal Generator Generator Logic

42

10

A Note Note on on Cir Circu cuit it Sc Schemat hematic icss

This section aims to clarify some questions and misunderstandings about how a logic block diagram diff ers ers from an electrical schematic.

10.1 10.1

Block Block Diagra Diagrams ms

A block diagram is a quick way of visualizing how a logic system may function. Symbols are used to denote di ff erent erent components or gates within the system. It is a suitable tool for prototyping a logic function. As an example, let us consider the function  F  = (A B ) + C . A logic block diagram of this function is shown in Figure 50. •

Figure 50: Typical Block Diagram This diagram easily shows how the function is built from logic but it does not provide provide details about how it is physically physically implement implemented. ed. How the user interacts interacts with the inputs A and B is completely left unknown along with how the outputs are handled. handled. These details details are suited for an electrical electrical schemat schematic. ic.   In a block  diagram, there should be no reference to switches, LEDs, part names, ground, V CC  CC  and so on...

10.2

Electri Electrical cal Sc Schema hematics tics

An electrical schematic is a comprehensive diagram, showing how devices are intercon interconnecte nected. d. In an electrical electrical schematic, schematic, the whole system system is displayed displayed.. This includes includes every detail detail such as labelled switches switches for inputs, resistors, resistors, LEDs. If  somebody were to recreate a system, an electrical schematic would be a suitable tool tool to do so rather rather than a bloc block k diag diagra ram. m. Using Using the same same func functi tion on F  = (A B ) + C , an electrical electrical schematic schematic is produced produced in Figure 51. In the schematic schematic,, there are switches, switches, power power supply supply connection connections, s, grounds, grounds, LEDs, resistors, resistors, part names, names, reference referencess and pin numbers. numbers. This system can be easily replicated replicated with no questions asked. •

10.2.1 10.2.1

Using Using the Right Right Symbol Symbol and Showing Showing Supply Connect Connections ions

When making schematics, it is common practice to not show supply pins such as connections to V CC  and GND. This is due to the fact that it is assumed that the person who would read the schematic knows that having these supply pins

43

Figure 51: Typical Electrical Schematic wired is a necessity. As an example, the schematic for the 555 Timer (Figure 31) do not show the connections to V CC  and GND (pins 1 and 8). In an electrical schematic, it is common convention to use the logic symbols for the basic logic functions functions such as AND, NAND, NOR, NOT, OR, XNOR and XOR. These symbols do not have pins for supply voltages like V CC   or GND. This is due to the fact that a schematic can be presented in a clearer manner. That being said, the symbols symbols are still annotated annotated with their part their part name, reference  and pin numbers . Depending on the schematic software used, a logic component may come as a whole IC for a part. 10.2.2 10.2.2

Part Part Names Names and Refere Reference nces: s: Why Why Do They Matter? Matter?

Using the appropriate part in schematics can be confusing at times. To use the appropriat appropriatee name, knowledg knowledgee of the circuit is required beforehand. beforehand. Consider Consider the example of an AND gate IC. There are multiple AND gates with di ff erent erent technolo technologies. gies. Not all of them use the same logic level values, values, some may treat a logi logicc 1 as 3.3 Volt Voltss inste instead ad of 5 Volts olts.. Some Some AND gates gates may be able able to operate operate faster than others. others. Because Because of this, it is critical to use the proper part in a schem schemati atic. c. A 74LS08 74LS08 AND gate gate is not the same same as a 4081 even even if they they may perform perform the same logic function. function. Additionally Additionally,, using the right right part in a schematic is also beneficial since it is representative of what is performed in the labs. Note: While the 7400 logic family is used, the variants variants used in the lab are the 74LS and 74HC families. families. The pin-outs pin-outs are the same but internally internally,, these integrated circuits di ff er. er. They are equivalen equivalentt in specification specification and can be used interch interchangea angeably bly.. It would be incorrect incorrect to say a 74A 74ACT08 CT08 was used as opposed opposed to a 7408 or 74LS08. For the basic AND, NOT and OR gates, it is common to not refer to the family unless necessary necessary.. Saying Saying that a 7404 was used is correct, correct, as well as saying that a 74LS04 was used. In many cases, an integrated circuit may have multiple gates or units of  44

the same same functi function. on. This This is a com common mon occurre occurrence nce as seen in the 7404, 7404, 740 74088 and 7432. 7432. It would would not be resour resourcef ceful ul or efficient to take three 7432 devices if three OR gates gates were were needed. Since the 7432 provides four readily available available OR gates, one integrated circuit is su fficient. cient. Each part used in a schematic schematic is given a  a   reference . Generally Generally,, for resistors, resistors, the scheme scheme is R then the number number of  the resistor. resistor. For capacitors, capacitors, it is similar with C then a number following following the letter. letter. For integrated integrated circuits, circuits, however, however, the letter U is used to designate designate an integrat integrated ed circuit then followed followed by a number. number. As seen in Figure 51, each each part is labeled appropriately appropriately and then a letter is designated. designated. This letter indicates indicates the unit  the  unit  used.  used. The first unit was used for the 7408 and it is the first integrated circuit placed, therefore the reference is U1A. Now, the function F  =  A B C   calls for two two AND gates. Only one 7408 is needed since there are four AND gates onboard. In Figure 51, the schematic is shown. The two AND gates come from the same integrated integrated circuit and are denoted by U1. Each gate is an individual unit which explains why there is an AND gate designated by U1A and another designated by U1B. Also, take note of how the pins di ff er er for each unit. •

•

Figure 52: Schematic With Multiple References

45

11

Using Using the the 74LS 74LS173 173 As a Replac Replacemen ementt for for the the 74LS395

The 741LS73 4 Bit Register can be used as a replacement for the 74LS395 Register. There are a few notable di ff erences erences between the two integrated circuits however and the goal of this Appendix is to detail what is needed so that the 74LS173 can be used. The most important di ff erence erence is that the 74LS173 Register is a positiveedge clocked device. The register writes data when the clock signal transitions from low to high. Throughout the project, negative-edged triggered devices are used. To mak makee the 74LS173 compatible compatible with the project, project, an inverter inverter is needed needed on the clock. Because of this, the 74LS173 requires at least one 7404 for proper use. Additionally Additionally,, the master master reset (pin 15) is active active high as well. To prevent prevent the device from constantly resetting, pin 15 must be wired to ground. Additionally, the data input enable pins (pins 9 and 10) are wired to ground. This is to ensure that the data will be written every every clock pulse. The output enable pins are active active low so inverte inverters rs are needed. Stored Stored data will b e output when both pins 1 and 2 are active low and should be wired to the TSG. As expected, pin 8 is wired to ground and pin 16 is wired to V CC . Pins 3 to 6 are outputs and Pins 11 to 14 are inputs. The typical use of the 74LS173 as a replacement for the 74LS395 is shown in Figure 53.

Figure 53: 74LS173 Circuit for Replacing The 74LS395

46