L9929-STMicroelectronics.pdf
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L9929 SPI CONTROLLED H-BRIDGE PRELIMINARY DATA
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Features
Figure 1. Package
OPERATING SUPPLY VOLTAGE 5V TO 28V TYPICAL RDSon = 150 m Ω FOR EACH OUTPUT TRANSISTOR (AT 25°C) CONTINOUS DC LOAD CURRENT 5A (Tcase < 100 °C) OUTPUT CURRENT LIMITATION AT TYP. 8.6A SHORT CIRCUIT SHUT DOWN FOR OUTPUT CURRENTS OVER TYP. 10.6A LOGIC- INPUTS TTL/CMOS-COMPATIBLE OPERATING-FREQUENCY UP TO 30 kHz OVER TEMPERATURE PROTECTION SHORT CIRCUIT PROTECTION UNDERVOLTAGE DISABLE FUNCTION DIAGNOSTIC BY SPI OR STATUS-FLAG (CONFIGURABLE) ENABLE AND DISABLE INPUT SO20 POWER PACKAGE
Description
The L9929 is an SPI controlled H-Bridge, designed for the control of DC and stepper motors in safety critical applications and under extreme environmental conditions.
PowerSO20
PowerSSO24
Table 1. Order Codes Part Number
Package
L9929
PowerSO20
L9929XP
PowerSSO24
The H-Bridge is protected against over temperature and short circuits and has an under voltage lockout for all the supply voltages "V S" (Main DC power supply). All malfunctions cause the output stages to go tristate. The H-Bridge contains integrated free-wheel diodes. In case of free-wheeling condition, the low side transistor is switched on in parallel of its diode to reduce the current injected into the substrate. Switching in parallel is only allowed, if the voltage level of the according output-stage is below the ground-level. In this case it must be ensured, that the upper transistor is switched off.
Figure 2. Block Diagram VS UNDERVOLTAGE VS
INTERNAL 5V SUPPLY
IN1 IN2
GATE CONTROL 1
OVERCURRENT HIGH-SIDE
DI
OUT1 GATE CONTROL 2
EN LOGIC
OUT2
DMS SF/SCK
OVER TEMPERATURE
OVERCURRENT LOW-SIDE
SS SI SO
MAXIMUM CURRENT LIMITATION GND
D01AT470A
May 2005 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 2 1/23
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L9929 Table 2. Pin Function PowerS020 N°
NAME
Description
1
GND
2
SCK/SF
3
IN1
Input 1
4
VS
Supply voltage
5
VS
Supply voltage
6
OU 1
Output 1
7
OU 1
Output 1
8
SO
serial out
9
SI
serial in
10
GND
Ground
11
GND
Ground
12
DMS
Diag Diagno nost stic ic-Mo -Mode de sele selecti ction on (+ Supp Supply ly Volta oltage ge for for SPI-I SPI-Int nter erfface) ace)
13
EN
14
OU2
Output 2
15
OU2
Output 2
16
VS
Supply voltage
17
SS
Slave select
18
DI
Disable
19
IN2
Input 2
20
GND
Ground
Ground SPI-Clock/Status-flag
Enable
Figure 3. Pin Connection (Top view)
GND
1
20
GND
SCK
2
19
IN2
IN1
3
18
DI
VS
4
17
SS
VS
5
16
VS
OU1
6
15
OU2
OU1
7
14
OU2
SO
8
13
EN
SI
9
12
DMS
10
11
GND
GND
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L9929 Table 3. Pin Function PowerSS024 N°
NAME
Description
1
GND
2
SCK/SF
3
IN1
Input 1
4
N.C.
Not Connected
5
VS
Supply voltage
6
VS
Supply voltage
7
OUT1
Output 1
8
OUT1
Output 1
9
SO
Serial Out
10
SI
Serial In
11
GND
Ground
12
GND
Ground
13
GND
Ground
14
GND
Ground
15
DMS
Diag Diagno nost stic ic-Mo -Mode de sele selecti ction on (+ Supp Supply ly Volta oltage ge for for SPI-I SPI-Int nter erfface) ace)
16
EN
17
OUT2
Output 2
18
OUT2
Output 2
19
VS
Supply voltage
20
SS
Slave select
21
DI
Disable
22
IN2
Input 2
23
N.C.
Not Connected
24
GND
Ground
Ground SPI-Clock
Enable
Figure 4. Pin Connection (Top view)
GND
1
24
GND
SCK
2
23
NC
INPUT 1
3
22
INPUT 2
N.C.
4
21
DISABLE
VS
5
20
SS
VS
6
19
VS
OUT 1
7
18
OUT 2
OUT 1
8
17
OUT 2
SO
9
16
ENABLE
SI
10
15
DMS
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L9929 Table 4. Absolute Maximum Ratings The integrated circuit must not be destroyed by use at the limit values. Each limit value can be used, as long as no other limit is violated. Volt Voltag age e ref refer eren ence ce poin point: t: All All val value ues s are are,, ifif not not othe otherwi rwise se stat stated ed,, rel relat ativ ive e to to gro groun und. d. Dire Direct ctio ion n of curr curren entt flow flow:: Curr Curren entt flow flow into into a pin pin is posi positi tive ve.. Rise-, Rise-, fall fall-- and dela delayti ytime mes: s: If not not otherw otherwise ise stat stated, ed, all all rise rise times times are are betwee between n 10% 10% and 90% 90%,, fall time times s between 90% and 10% and delay times at 50% of the relevant steps. Symbol
VS
Parameter
Supply voltage
Test Condition
Min.
Typ.
Max.
Unit
static destruction proof
-1
40
V
dynamic destruction proof t 5 V
150
250
mΩ
Switch on Resistance HS
R OUT-GND, VS > 5 V
150
250
mΩ
Switch-off Current (*)
-40 °C < T j < 165 °C T j < 175 °C
7 .8
8.6 2.5
10.5(tbd)
A A
ta
Switch-off time
12
17
22
µs
tb
Blanking time
8
11.5
15
µs
Tracking
1 .3
1.5
1 .7
|IOUK|
Shor t circuit detection current (*)
8 .9
10.6
-
A
∆|IOUK|
Shor t Circuit Current Trecking (*)
1 .3
2.0
-
A
200
µs
ta /tb
t
Reactivation titime af after in interna rnal shut down
Overcurrent- or overtemperature shut down to reactivation of the output stage
IL
Leakage Current
Output stage switched off
1
mA
VFD
FreeFree-whe wheel el diode diode forwa forward rd volta voltage ge
I O = 3A, V S = 0V
2
V
ISF
Output„high“ (SF not set)
VSF = 5V
20
µA
ISF
Output„low“ (SF set)
VSF = 0.5V
350
µA
VSF = 0.8V
400
µA
VSF = 1V
400
µA
Timing
f
Maximum PWM Frequency
min. operating time 10 µs Device can not be controlled with higher frequency (specify in max ratings?)
2
30
kH z
fS
Switching Frequency during current limitation
f = 1/(t a+tb)
20
50
kH z
tdon
Output ON-delay
IN1 --> OUT1 or IN2 --> OUT2
3
7 .5
µs
tdoff
Output OFF-delay
3
5
µs
tr tf
Output rise time
OUT1H--> OUT1L, OUT2H--> OUT2L,
1
5
µs
Outout fall time
IOUT = 3 A
1
3
µs
OUT1L--> OUT1H, OUT2L--> OUT2H
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L9929 Figure 5. Output delay time INn
50%
50%
tdon
tdoff 90%
OUTn
10%
D01AT472
Figure 6. Disable delay time DIn
50%
tddis OUTn
Z
10%
D01AT473
Figure 7. Output switching time 90 %
90 %
OUTn
10% tf
tr
D01AT474
Figure 8. Current values to be inserted after characterization LOAD CURRENT
Reaching Switch-off current, limitation phase is started by triggering tb OVERCURRENT
> typ.10.6 A
typ. 8.6A A CURRENT LIMITATION PHASE
CONTROL SIGNAL
STATUS FLAG
DETAIL A
OVERCURRENT DETECTION ta
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L9929 Figure 9. Temperature-depending current-limitation Maximum rating for junction temperature Over temperature switch-off Switch-off current in case of current limitation For typical 165°C < Tj < 175°C the maximum current decreases
for < 1s 175°C > typ. 175°C typ. 8.6A Tj < typ. 165°C
Imax
Tolerance range of temperature dependent current reduction
typ. 8.6A Range of Overtemperature switch-off
typ. 2.5A
165°C
175°C
Tj
Table 5. Electrical Characteristics (continued) Characteristics (continued) Spi Interface The timing of L9929 is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is taken over on the falling edge of the SCK signal. - SS = active without without any clocks at at SCK is not allowed - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active. Figure 10. 10
9
SS 11
SCK
2
1
3
8
12
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L9929 Table 5. Electrical Characteristcs Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1
V
Input SCK (SPI clock input)
VSCKL
Low Level
VSCKH
High Level
2
∆VSCK
Hysteresis
0 .1
CSCK
Input Capacity
-ISCK
Input Current
Pull up current source connected to VS
V
20
0 .4
V
10
pF
50
µA
1
V
Input SS (Slave select signal)
VSSL
Low Level
L9929 is selected
VSSH
High Level
2
∆VSS
Hysteresis
0 .1
CSS
Input Capacity
-ISS
Input Current
Pull up current source connected to VS
V
20
0 .4
V
10
pF
50
µA
1
V
Input SI (SPI data input)
VSIL
Low Level
VSIH
High Level
2
∆VSI
Hysteresis
0 .1
CSI
Input Capacity
Guaranteed by design
-ISI
Input Current
Pull up current source connected to VS
V
20
0 .4
V
10
pF
50
µA
1
V
(Tristate output of the L9929 (SPI output); On active reset (DI) output SO is in tristate.) tris tate.) Output SO (Tristate VSOL
Low Level
I SO = 2mA
VSOH
High Level
I SO = -2mA
CSO
Capacity
Capacity of the pin in tristate
-ISO
Leakage Current
In tristate
2
-1 0
V 10
pF
10
µA
0.8
V V
10
mA
Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode)
Vi Ic Timing
Input Voltage Input Current
SPI-Mode Status-Flag-Mode SPI-Mode
4.5
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L9929 Table 5. Electrical Characteristcs (continued) Symbol
tdt
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Transfer Delay (8) (referred to master)
150
ns
tSCKH
Serial clock high time (9) (referred to master)
50
ns
tSCKL
Access time (10) (referred to master)
8.35
µs
Clock inactive before chipselect becomes valid (11)
200
ns
Clock inactive after chipselect becomes valid (12)
200
ns
20
ns
trs
Rise-, fall time
Load on SO 50pF
TIMING Diagnostic Threshold (Open Load Detection DMS > 3.1V, 3.1V, EN < 18V and/or DI > 2V)
VOUT1 VOUT2
Load is available
0 .8 0.8
VOUT1 VOUT2
Load is missing
1
IOUT2 IOUT1 tD
3
Diagnostic Current
DMS > 3.1V, EN EN < 0.8V EN < 18V and/or DI > 2V
Tracking Diagnostic Current Delay Time
V V VS 0.8
V V µA µA
700 1000
1000 1500
1350 2000
I OUT1 / IOUT2
1 .4
1.5
1 .6
* After disabling the device, the load has to be demagnetized during tD ,to avoid erroneous OL detection
30
100
ms
Truth Table
Table 7. Truth Table Pos.
SF 3)
DI
EN
IN1
IN2
O UT 1
OU T 2
1. Forward
L
H
H
L
H
L
H
2. Reverse
L
H
L
H
L
H
H
3. Free-wheeling low
L
H
L
L
L
L
H
4. Free-wheeling high
L
H
H
H
H
H
H
5 Disable
H
X
X
X
Z
Z
L
SPI 4) DIA_REG
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L9929 1.) 2.)
In case case of under undervolta voltage ge tristate tristate and status-fla status-flag g are are reset reset automatica automatically. lly. Whenever Whenever overcu overcurrent rrent or overt overtempe emperatur rature e is detected detected,, the fault fault is stored stored (i.e. statu status-fla s-flag g remains remains low). low). The tristate conditions and the status-flag 3) are reset via DI or EN. L = Low H = High X = High or Low Z = High impedance (all output stage transistors transistors are switched off in static state. For more more inform. see next page page ) Overcurrent: IOUT1,2 >10.6 A Overtemperature:
T j
>175°C
Un U ndervoltage:
VVs-GND
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