[J. Bhasker] a Verilog HDL Primer
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A
HDL
VERILOGf
Primer
Second Edition
J. Bhasker
A
HDL
Verilog\302\256
Second
Edition
Primer
Other booksby the
author:
same
Verilog HDL Synthesis, A ISBN 0-9650391-5-3.
Practical
A VHDL Primer, Third Edition, ISBN 0-13-096575-8.
Prentice Hall, Englewood Cliffs,
VHDL Primer, Synthesis ISBN 0-9650391-9-6.
Second Edition, Star
VHDL Primer, Synthesis ISBN 0-9650391-0-2.
Star Galaxy
A
A
HDL Primer, Verilog ISBN 0-9656277-4-8.
A
Primer: Revised Edition, VHDL ISBN 0-13-181447-8. Guide to VHDL Syntax, ISBN 0-13-324351-6.
A
VHDL Featuresand Applications: A
VHDL
Primer,
In Japanese:
In German: Verlag
GmbH,
Prentice
Galaxy Press,AUentown,
Prentice HaU, EnglewoodCliffs, Study
IEEE,
Guide,
HaU, Englewood
PA,
A Guide
ISBN
1998,
1997,
1995,
1995,
Cliffs, NJ, 1992,ISBN
Die VHDL-Syntax(Translation of ISBN 3-8272-9528-9.
NJ,
1995, Order
A VHDL Primer, CQ Publishing, Japan, 1996,
NJ,
PA,
1996,
PA,
Prentice Hall, EnglewoodCliffs,
1998,
1999,
NJ,
Galaxy Publishing,AUentown,
Publishing, AUentown,
First Edition, Star
A
Publishing, AUentown, PA
Star Galaxy
Primer,
No. HL5712. 0-13-952987-X.
4-7898-3286-4.
to VHDL
Syntax), Prentice Hall
A
HDL
Verilog
Second Edition
Primer
J. Bhasker Bell
Star
Lucent
Laboratories,
Galaxy
Technologies
Publishing
1058TreelineDrive,
Allentown,
PA
18103
Copyright
1999
\302\251 1997,
Lucent
Technologies.
All rights reserved.
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writing from
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Galaxy
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book
the
may
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publisher.
WARNING
- DISCLAIMER
The author and examples contained
error-freeor
publisher have used their best efforts in preparing this book and the in it. They make no representation, however, that the examplesare are suitable for every application to which a reader may attempt to apply
of any kind, expressedor the publisher make no warranty or theory contained in this book, these examples,documentation all of which is provided \"as is\". The author and the publisher shall not be liable for any direct or indirect damages arising from any use, direct or indirect, of the examples
them. The
author
and
regard to
implied,
with
provided
in this
book.
trademark of Cadence Design Systems, Inc. Inc. registered trademark of VeriBest, Material in Appendix A is reprinted from IEEE Std 1364-1995 \"IEEE Standard Hardware Based on Hardware the 1995 Description Description Language Verilog Language\", Copyright \302\251 from the placement by the IEEE, Inc.The IEEE disclaims any responsibility or liability resulting is reprinted with the permission and use in the described manner. Information of the IEEE.
Verilog is a registered VeriBest\302\256
Printed
is a
in
the
United
States
of America
10987654
Library of CongressCatalogCardNumber: ISBN
0-9650391-7-X
98-61678
To my
wife, Geetha
Contents
deface JHAPTER
xv
1
Introduction
1.1.
What
is
1
HDL?,
Verilog
2
1.2.
History,
1.3.
Major Capabilities, 2
1.4.
Exercises, 5
Zhafter 2 A
Tutorial
2.1.
A
6
Module,
2.2.
Delays,
2.3.
Describing in Dataflow
2.4.
Describing
2.5.
Describing
2.6.
Describing
2.7.
8
in
Simulating
Style,
in Structural in
Style, 9
Behavioral
Style, 14 Style,
Mixed-design
a Design,
2.8. Exercises,22
11
17
16
Contents
Chapter 3
Language
24
Elements
24
3.1.
Identifiers,
3.2.
Comments, 25
3.3.
Format,
26
Functions, 26
Tasks and
3.4.
System
3.5.
Compiler
27
Directives,
define and yifdef, *else
3.5.7. 3.5.2.
27
yundef,
and
3.5.3.
*default_nettype,
3.5.4.
^include, 28
28
yendif,
28
3.5.5. >esetall,29
3.6.
3.5.6.
^timescale,
3.5.7.
yunconnected_drive
3.5.8.
ycelldefine
Value Set,
29
and
andynounconnected_drive, 31
yendcelldefine,
32
3.6.1. Integers,32 Decimal
Simple
3.7.
3.6.2.
Base Format 34 Reals,
3.6.3.
Strings, 35
Data
3.7.1.
Form,
33 33
Notation,
36
Types,
Net Types,
37
Tri Nets,
and
Wire
36
Wor and Trior Nets, 38 Triand
and
Wand
Nets,
39
TriregNet, 39 Nets, 40 SupplyO and Supply 1 Nets, Tril
and
TriO
3.7.2. UndeclaredNets, 3.7.3.
Vectored
and Scalared
3.7.4. Register
Types,
Reg
Register,
40
40
Nets, 41
41
41
Memories, 42 Integer
Register,
Time Register,
3.8.
viii
Real and Parameters, 47
Realtime
45
46 Register,
46
31
3.9.
Exercises,48
Zhafter 4
Expressions
4.1.
50
Operands,
51
4.1.1.
Constant,
4.1.2.
Parameter, 52
4.1.3.
Net,
4.1.4.
Register,
4.1.5.
Bit-select, 53
52
52
4.1.6. Part-select,53 A2.
4.1.7.
Memory
4.1.8.
Function
54
Element,
Call, 54
Operators, 55
4.2.1.
Arithmetic
57
Operators,
Result Size,
57
Unsignedand 4.2.2.
Relational
4.2.3.
Equality
4.2.4.
Logical
4.2.5.
Bit-wise
4.2.6.
Reduction
58
Signed,
60
Operators, 61
Operators,
Operators,
62 63
Operators,
Operators,
4.2.7.
Shift
4.2.8.
Conditional
65
66
Operators,
Operator,
67
and Replication, 4.2.9. Concatenation of Expressions,
4.3.
Kinds
4.4.
Exercises,69
68
Zhapter 5
Gate-levelModeling
5.1. 5.2.
5.3.
The
Built-in
Primitive
Gates,
Multiple-input Gates, 71 Gates,
Multiple-output
Gates, 75
5.4.
Tristate
5.5.
Pull Gates,77
5.6.
MOS
Switches,
77
74
70
67
Contents
5.7.
Bidirectional
5.8.
Gate
80
Switches,
80
Delays,
5.8.1. Min.typ.maxDelay
5.9.
Array
5.10.
Implicit Nets, 83
5.11.
A
5.12. A 2-to-4
5.13.
A
84
Example,
Simple
82
Form,
83
of Instances,
Decoder Example, 85
Master-slave
5.14. A Parity Circuit, 5.15.Exercises, 88
86
Example,
Flip-flop
87
Chapter 6
User-Defined
90
Primitives
a UDP,
6.1.
Defining
6.2.
Combinational
6.3.
Sequential
90 91
UDP,
UDP, 93
6.3.1. Initializingthe 6.3.2.
6.3.3. 6.3.4.
UDP, 93 UDP,
Sequential
Edge-triggered
93
Register,
94
Mixing Edge-triggered and Level-sensitiveBehavior,
95
96
6.4.
Another
6.5.
Summary of Table Entries, 96
6.6. Chapter
State
Level-sensitive Sequential
Example, 97
Exercises,
7
Dataflow
98
Modeling
7.1.
Continuous
7.2.
An Example,
7.3.
Net
7.4.
Delays, 101
7.5.
Net
Delays,
104
7.6.
Examples,
105
98
Assignment,
100
Declaration
Assignment,
101
7.6.7. Master-slaveFlip-flop, 105
7.6.2. 1.1.
Magnitude
Exercises,
106
Comparator,
106
Contents
:hapter
8
107
Behavioral Modeling
8.1.
8.2.
8.3.
8.4.
Procedural
107
Constructs,
8.1.1.
Initial Statement,
8.1.2.
Always
108 110
Statement,
One Module, 112
8.1.3.
In
Timing
Controls,
8.2.1.
Delay Control,
114
8.2.2.
Event
116
114
Control,
Edge-triggered
Event Control,
116
Level-sensitive
Event
118
8.3.1.
Sequential
8.3.2.
Parallel
119
Block,
Block, 121
Procedural
123
Assignments,
Intra-statement
8.4.1.
Control,
119
Block Statement,
125
Delay,
8.4.2. BlockingProceduralAssignment, 8.4.3.
Non-blocking
8.5.
8.6.
Case
Assignment,
130
in Case,
Don't-cares
136
Loop Statement, 136
8.7.1.
Repeat-loop
8.7.3.
While-loop
Statement, 137 138
Statement,
Statement, 139
For-loop
Procedural
Continuous
8.8.1.
137
Statement,
Forever-loop
8.7.2.
8.7.4.
8.8.
vs Procedural
133
Statement,
8.6.1.
8.7.
Assignment, 128
Procedural
8.4.4. Continuous Assignment ConditionalStatement, 131
126
Assignment,
Assign - deassign,
8.8.2. Force-
release,
8.9.
A Handshake
8.10.
Exercises,145
Example,
139
140
141
143
:hapter9
Structural Modeling 9.1.
Module,
147
147
xi
Contents
9.2.
Ports,
9.3.
Module
Instantiation,
9.3.1.
Unconnected Ports, 151
9.3.2.
Different
9.3.3.
Module Parameter
148
148
Port
151
Lengths,
152
Statement,
Defparam
9.4.
Module InstanceParameter External Ports, 155
9.5.
Examples, 158
9.6.
152
Values,
Value
Assignment,
Exercises,160
Chapter 10
161
Other Topics 10.1.
Tasks,
161
10.1.1.
Task Definition,
10.1.2. Task 10.2.
10.2.2.
Calling,
Function
167
Call,
Display Tasks, 168 Displayand Write Tasks, Strobe Tasks, 170 File I/O
Tasks, 172 and
Readingfrom
174
a File,
175
Control
Simulation
Time
Simulation
Conversion Functions, Distribution
10.4.
Disable
10.5.
Named Events,
10.6.
Mixing
Statement, Structure
180
Functions,
10.3.8.Probabilistic
xii
176
Tasks,
Timing Check Tasks, 177
10.3.6. 10.3.7.
File, 173
Timescale Tasks,
10.3.4.
172
Files,
Closing to a
out
Writing
10.3.3.
168
171
Tasks,
Opening
10.3.5.
168
Functions,
Monitor
10.3.2.
166
Definition,
SystemTasks and 10.3.1.
161
163
165
Functions,
10.2.1. Function 10.3.
153
181 Functions,
183
184 with
Behavior,
187
181
Contents
10.8.
Hierarchical Path Name, 188 Sharing Tasks and Functions, 191
10.9.
Value
10.7.
10.10. 10.11.
File,
(VCD)
Dump
Change
70.9.7.
An
10.9.2.
Format
of VCD File, 196
Specify
Block,
198
193
195
Example,
201
Strengths,
10.11.1.Drive Strength, 201
10.11.2.Charge
202
Strength,
10.12.
Race
203
Condition,
10.13. Exercises, 205 IHAFTER
11
207
Verification
11.1. 11.2.
Writing
a Test
207
Bench,
Waveform Generation, 208
11.2.1. A
11.2.2. Repetitive Patterns,
11.3.
Testbench
77.3.7.
11.4.
11.5. 11.6.
Examples,
11.7.
Zhafter
216 217
Flip-flop,
Vectors from a Text File, 219 to a Text File, 222
Reading Writing
210
216
A Decoder,
11.3.2. A
208
of Values,
Sequence
Vectors
223 SomeMoreExamples, 77.6.7.
A
Clock
11.6.2.
A
Factorial
Design,
11.6.3.
A
Sequence
Detector,
Divider,
223 225 229
Exercises, 231
12
233
Modeling Examples
12.1.
12.2.
12.3.
Modeling
Simple
Modeling
Delays,
Transport
12.4.
Elements,
233
Different Styles of Modeling, 238 240
Delays, 243
ModelingConditionalOperations, 244
xiii
Contents
12.5.
245
Shift Register, 249
12.6.
A Generic
12.7.
State
12.8.
Interacting State Machines, 253
12.9.
Modeling
12.10.
A
12.12.
Machine
250
Modeling,
a Moore
257
FSM,
Modeling a MealyFSM, 259
12.11. Appendix
Logic,
Synchronous
Modeling
Simplified
Blackjack
Program,
261
Exercises, 264
A
Syntax
A.l.
A.2. A.3.
266
Reference
Keywords, 266 Syntax
Conventions,
The Syntax,
268
268
Bibliography
285
Index
287
\342\226\241
xiv
Preface
Here is a neat and
book that explains the basics of the Verilog The description language. Verilog hardware descriptionlanguage, and referred to as Verilog HDL, can be used henceforth to model at levels the switch-level of from abstraction,ranging multiple designs
hardware commonly
digital to the
concise
algorithmic-level. The logic
including
gates
languageoffers
and user-defined
a powerful set of primitives, primitives, and a widerangeof constructs
but of hardware only the concurrentbehavior is nature and its structural The also composition. language interface (PLI). Verilog HDLis a extensible via a programming language levels to use but strong enough to model multiple of abstraction. simple language The Verilog HDL languagewas standardized IEEE in called the the 1995, by IEEE Std 1364-1995; this bookis basedon this standard. that
can
be
used
to model not
also its sequential
hardware of this book is to introducethe Verilog and basic constructs its by explaining important It a Each is primer. is described aspectof the language examples. so that it is easy to understand and not intimidating concise English
The purpose descriptionlanguage
through using
clear,
to
the reader
xv
Preface
for a
beginner. My hope is that
learning
The book provides of examplesfor
A number
model described
The
hardware.
detail.
in
described
the
using
each
provide
the very
first
step
in
sometimes
of
although
in an
is provided
Thebookis of
semantics
of the formal entire
interface,
this book.
and
construct
language
basics of the in modeling.
its usage
is provided;
in
addition,
not
styles supported by
modeling
help explain the construct.The language
of the
understanding
point of view
Verilog HDL are The book explains how stimulus and control can also be same Verilog language, including response monitoring various
The syntax
verification.
read manner,
the
can
to illustrate how collectivelyconstructscan be used to
are provided
examples
and
a thorough
the features
from
both
language,
Verilog
book
this
Verilog HDL.
of
many
the
are shown in an easy to This is done purposely to of constructs of the Verilog
constructs
not
complete.
complete
syntax
appendix for reference. in nature
theoretical
and introduces
the syntax and
than the technical jargon using common terms, rather No address has beenmadeto attempt language. for example, features such as the programming language, language in switch-level modeling, and stochastic modelingare not described
the
language
of the
definition
The book restrictsitselfto the most useful and
the language
are
that
enough
to model
features
common
of
simple as well as complexdevices.
designers as well as others, and system includingcircuit designers and software tool developers,interestedin be used as to model hardware using Verilog HDL.The bookcan also learning an introductory text in a first university course on computer-aided design, as hardware or synthesis. It is well suited for working modeling, professionals well as for undergraduate and graduate study.Designerscan use this book as a HDL and as a reference for work with way to get to know Verilog Verilog HDL. Students and professorswill find this book useful as a teaching tool for and for hardware description languages. hardware design This
is intended
book
Thebook
assumes
as familiarity
with
language
and
by
reading
simulating
and thorough
xvi
a basic
a high-level
I would
Finally,
alone.
them on
for hardware
knowledge
programming
hardware designas well language such as C.
of digital
to comment that it is impractical to learn a Typing out examples from this book and compiling
like
a Verilog simulator is the best way
understandingof the language.Onceyou
to have
gain
a complete this
mastered
Preface
book, look
at
IEEE
the
complete
Standard
on the
information
Reference Manual
Language
(LRM) for
Verilog HDL standard.
Book Organization Chapter
1 provides
a brief history
2 provides
a quick overview
of the
language,describingits
major
capabilities.
Chapter
the three main
styles
of
a design:
of describing
the
by demonstrating
language,
dataflow, behavioral,and
structural style.
It describes
language. and
the basic elements,that is, the nuts and bolts, of the comments, system tasks, compilerdirectives others. amongst
3 describes
Chapter data
types,
identifiers,
Chapter 4 is devoted also
places in the various
different
many
describes
form
an
using
built-in
time
and
An expression can be usedin to expressions. solely a Verilog description,includingdelays. The chapter that can be used to kinds of operatorsand operands
expression.
5 describes
Chapter
a design gate-level modeling,that is, modeling T he Gate are also delays explained. conceptof gates. is also introduced.
primitive delay
scaling
Verilog HDL provides that
is,
Chapter6. Combinational with
of creating user-defined primitives, capability to the built-in primitives. This is the topic of user-defined primitives are described sequential
the
in addition
primitives
and
examples.
The assignments
in
execution
modeling style is modeled using the continuous Chapter 7 describes this assignmentand
dataflow Verilog
HDL.
semantics.
Two kinds of delay, assignmentdelay
and
explains
net
delay,
its
are
described.
Chapter 8 describesthe behavioral main procedural
constructs:the
modeling statement
initial
The chapter also describes procedural blocksare parallel explainedin detail
assignments
with
examples.
It describes
style.
the two
always statement. Sequential and High-level programming
and
in
the
detail.
xvii
Preface constructssuch as conditionalstatement
and
loop
are described in
statement
this chapter. is elaborated in of modeling The structural style of hierarchy and matching of ports is examinedin this in this chapter is how modulesconnectwith each other
9. The
Chapter
concept included
chapter.
Also
via port
associations.
Advanced topics are presented in Chapter 10.Topicssuch are value change dump file, signal strengths blocks, presented. also includes tasks and functions.
as
This
specify
chapter
talk about 11 and 12 are the most practicalchapterssincethey a number of test bench examples and modeling. Chapter 11 shows a and response monitoring. Chapter 12 shows waveform generation
Chapter
verification that
show
of modeling
number Verilog
language
collective
the
demonstrate
A contains a complete syntax reference is described in Backus-Naur Form grammar
The
language.
are all
constructs
In all
arranged alphabetically for
the Verilog
words, system tasks boldface. In syntax part
that
Appendix
Finally, Verilog
examples
usage
of
constructs.
HDL descriptionsthat
and
system
functions, operators
descriptions,
syntax are in boldface.Optional
of the
easier
of
the
(BNF)and
the
search.
appear
in
this book,
reserved
and compiler directives are in and items
marks punctuation in a grammar rule
that
are
are
braces ({...}) square brackets ([...]). Non-boldcurly more times. Occasionallyellipsis(.. items that are repeated zero or identify to that used in Verilog HDL source to indicate code that is not relevant words are written in Courier font to identify its Verilog discussion. Certain its such as in rather than and meaning meaning English gate. indicated
non-bold
using
by
is
All
examples
Version
Verilog simulator,
book have
in this
been
verified
using
the
.)
VeriBest\302\256
14.0.
Acknowledgments It is individuals
who
manuscript
xviii
my
to
pleasure
offered
their
despite their
very
the assistance of the following drafts time and energy to review of
acknowledge
valuable busy
schedule.
this
Preface
1. Brett Graves,GabeMoretti
2. StephanieAlter, Takla,
and
Sriram
at VeriBest,
Smith
Doug
Johnson,
Danny
Tiao
Jenjen
and
Sanjana
Nair, Carlos
Tyagarajan at Bell
Inc. Roman, Mourad
Labs, Lucent
Inc. Technologies,
3.
Mannan
Maqsoodul
at National
This bookowesa lotto their am gratefully
I would
like
to thank
support and for providing a
Last,
sons who
but
not
me
gave
least,
lots
Thank you very
Jean Dussault stimulating
I would like of emotional
much!
and Hao Nham
work
criticism. I
and constructive
comments
detailed
to them.
indebted
Semiconductor Corp.
atmosphere
to thank wife, my without support,
for
their
and my two never
Geetha, which
continuous
Labs.
at Bell
I would
have succeeded.
J. Bhasker PA
Allentown,
February
Preface
to Second
1997
Edition
This improved
for each and every edition includes exercises chapter; course. New makes the more useful in an book hopefully university sections on tasks and functions, MOS switches,bidirectionalswitches, sharing have been and named have been added. The page format and fonts events, to to read. make the book more easier redesigned this
you have any questions, feel free to contact me through
If
please
comments or suggestionsabout my
the
book,
publisher.
J. Bhasker
January, 1999
\342\226\241
xix
1
Chapter
Introduction
This
of the Verilog HDL languageand
it's
capabilities.
major
1.1
the history
describes
chapter
is Verilog HDL?
What
is a
HDL
Verilog
a digital system at to the
level
hardware levels
many
gate-level to the
being modeledcouldvary or
system,
digital
and
hierarchically
The
switch-level. from
that
of a
in between.
anything can
timing
description language that can be of abstraction ranging from the
be explicitly
complexity
used
to model
algorithmic-
of the digital
system
simple gate to a completeelectronic
The digital system modeled
within
can the
be
described
same
description.
The
Verilog of
behavioral nature
composition,
HDL
of response
monitoring
language.
In
includes capabilities to describethe dataflow nature of a design, a design'sstructural waveform generation mechanismincludingaspects and all modeled using one single verification, language provides a programming languageinterface
language
a design, the and a delays
addition,
the
1
CHAPTER
1
Introduction
which the internals of a design can be accessed during control of a simulation run.
through
simulation
the
including
The languagenot only each
for
semantics
simulation
the
defines
language
defines very clear construct. Therefore, models written syntax
but also
in
inherits verified using a Verilogsimulator.Thelanguage language the from C constructs and of its programming operator symbols many HDL an extensive range of modeling capabilities, Verilog provides language. someof which are quite difficult to comprehend initially. However,a core to is quite easy to learn and use. This is sufficient subset of the language has sufficient The modelmost however, complete language, applications. from the most complexchipsto a complete to capture the descriptions capabilities
can be
this
electronic
1.2
system.
History
The Verilog HDL languagewas first developed by Gateway Design simulator Automation1 in 1983 as a hardware modeling languagefor their product.
of their language. Becauseof the popularity a a s usable and HDL practical gained acceptance product, Verilog the popularity of to increase language by a number of designers.In an effort in the public domain in 1990. Open the language, the languagewas placed to promote Verilog. In 1992,OVI was formed (OVI) VerilogInternational This of Verilog HDL as an IEEEstandard. decided to pursue standardization The in 1995. effort was successful and the language became an IEEE standard the Hardware Verilog Description Language complete standard is describedin Reference Manual. The standard is calledIEEEStd 1364-1995.
At
that
time
it was
a proprietary
simulator
1.3
Capabilities
Major
Listed below are the majorcapabilitiesof the Veriloghardware description
language:
1. Gateway
2
Design Automation
has
since been
acquired by
Cadence
Design
Systems.
Major Capabilities \342\200\242 Primitive
and, or
such as
gates,
logic
and
are
nand,
SECTION
1.3
built-in
into
the language. \342\200\242
of
Flexibility primitive
combinational logic
a
or
primitive
primitive.
\342\200\242 Switch-level
primitive
modeling
also built-in
are
be a
either
logic
sequential
primitive (UDP). Such a
a user-defined
creating
could
into the
gates, such
as pmos and
nmos,
language.
are provided for specifyingpin-toand delays, pin path delays timing checks of a design. \342\200\242 A design can be modeled in three different styles or in a mixed - modeled are: These behavioral style. styles style using - modeled procedural dataflow constructs; style using continuous - modeled and structural and module assignments; style \342\200\242
constructs
language
Explicit
using gate
instantiations. \342\200\242 There
data types in Verilog HDL; the net data data type. The net type representsa physical structural while a register type elements
two
are
the register connectionbetween
an abstract
data
\342\200\242 Hierarchical
can be
described, up to
level,
any
can be
design
of
size;
arbitrary
the
language
does not
limit. \342\200\242
is human
and machine
language
exchange
readable. Thus tools
between
impose a
and is an IEEE standard.
is non-proprietary
HDL
Verilog
\342\200\242 It
the
using
instantiation construct.
module \342\200\242 A
represents
element.
storage
designs
and
type
it
can
be
used
as an
and designers.
Verilog HDL languagecan be further by using language interface (PLI) mechanism. PLI is a collection of routines that allow foreign functions to access information within and allows for a Verilog module
\342\200\242 The
capabilities
designer \342\200\242 A
of the
the programming
extended
interaction
design
switch-level,
can be
with
the simulator.
described in a wide range of levels,ranging gate-level,
register-transfer-level
algorithmic-level,includingprocessand can be modeled entirely design built-in switch-level primitives.
\342\200\242 A
at
from
(RTL)
to
using
the
queuing-level. the
switch-level
3
Chapter1
Introduction
\342\200\242 The
same
can be usedto generatestimulus
language
single
specifying test constraints, design values of inputs. and for
\342\200\242
design
under test,
monitored
and
expected
values,
be \342\200\242 At
used to perform
can be
HDL
Verilog
such
that
is,
the
and in
the
for
the
specifying
responsemonitoring
the
of
of a design under test can be with values can also be compared
values
These
displayed.
as
case of a mismatch, a report messagecan
printed. the
behavioral-level,
Verilog
only at the
HDL can
RTL-level, and its algorithmic-level behavior. not
design
\342\200\242 At
the
but
gate and
structural-level,
also
be usedto describea
at the
module
architectural-level
can
instantiations
be
used. \342\200\242
Figure
shows
1-1
HDL, that
in
is,
the mixed-level one
design,
modeling capabilityof Verilog
each module
be
may
modeled
at a
different level.
switch
algorithm
switch gate \\ \\ '
\\ > \342\226\240V
RTL
Figure \342\200\242
Verilog
HDL
and) and \342\200\242
High-level case conditionals,
\342\200\242
Notion
I
also
1-1
gate
Mixed-level modeling.
has built-in
logic functions
such
as &
(bitwise-
(bitwise-or).
programming statements, of concurrency
constructs such as available in the language. and time can be explicitly modeled.
language and loops are
SECTION 1.4
Exercises
\342\200\242 Powerful \342\200\242 The
is
language
a model
example,
write capabilities are provided. non-deterministic under certain situations,that
read and
file
may produce different resultson different the ordering of events on an event queue
is not
is,
for
simulators;
defined
by the standard.
1.4
Exercises
1.
In
2.
What
3.
Can timing
4.
What
which
year
are the
was Verilog
three basic descriptionstyles be described
a design
of
feature
HDL first standardized by the
in the
by Verilog
supported
using Verilog
IEEE?
HDL?
HDL?
parameterized language can be usedto describe
designs?
a test
bench be written
5.
Can
6.
Verilog HDL was first
7.
What
are
8.
What
does
9.
Name two switch-levelmodelingprimitive
10.
Name
the
two main
UDP
stand
using
developed
Verilog by
which
HDL?
company?
data types in Verilog HDL? for?
two logic primitive
gates.
gates.
\342\226\241
5
2
Chapter
Tutorial
A
This
2.1
of the
a quick tutorial
provides
chapter
language.
A Module The
in Verilog
of description
unit
basic
the functionality or which it communicates
is the module.A
structure of a design and externally switch-level
with
also
describes
modules.
other
The
module
describes
the ports
through
structure
of a
and userprimitives, gate-level primitives of a is described dataflow behavior primitives; design using continuousassignments; is described using procedural behavior sequential constructs. A module can also be instantiated insideanother module. design
is
described
using
defined
Hereis
the
module
basic
syntax
module_name
of a
module.
( port_list
Declarations:
reg, wire, parameter,
input, output,inout,
6
)
;
A
. . .
task,
function,
2.1
Section
Module
Statements:
Initial
statement
Always
statement
Module
instantiation
Gate instantiation UDP
instantiation
Continuous
assignment
endmodule
Declarations are usedto define of the
or structure
the various items, such as registers and the Statements are used to define functionality
the module.
within
parameters, used
design. Declarationsand
can
statements
be interspersed
appear before its use. and readability it is best to put all declarations before any statements, convention is followed in all examplesin this book. within
a module;
a declaration must
however,
Here is a simple example of a shown in Figure 2-1.
module HalfAdder input
A,
B,
(A,
modulethat
Sum,
models
the
For
clarity this
and
half-adder
circuit
;
Carry)
B;
Carry;
output
Sum,
assign
#2
assign
#5 Carry
Sum
= A A B;
=
A
& B;
endmodule
A c*
B
B, and
of the
two
output
\" Sum
Al
ti Cany
(\302\273
Figure 2-1 A The name
XI
moduleis HalfAdder. ports
Sum
and
half-adder
It has
circuit.
four
ports; two
Carry. All ports
input
ports
A and
are of size 1-bitsinceno
7
Chapter
2
A Tutorial Also, range has beenspecified.
nodeclaration
been
has
sense
specified.
contains two continuous assignmentstatements are behavior of the half-adder.The statements
i.
Dataflow style
ii.
Behavioral
Hi.
Structural
iv.
mix
in
the
in the
important.
following
and
B.
styles:
style
style of above
sections describethesedesignstyles little explanationabout delays in Verilog HDL.
The following
with
But first,
examples.
a
Delays All
in
delays
Here is
#2
Sum
declaration.
An
example
of such
'timescale Ins / is to
of
time
units.
a delay.
= A A B;
The associationof a time
says
with
assignment
unit
timescale compilerdirective.Such
which
specifiedin terms
HDL model are
to 2 time units.
#2 refers
The
a Verilog
an exampleof a continuous assign
that one
time
unit
with
is
a directive
a directive
using the specified before a module time
physical
is made
is:
lOOps
is to
be treated
be lOOps(the time precisionsays
as Ins and that
the
time
precision
rounded to in the module present containing the above that
directive is 0.1ns). If this compiler continuousassignment,the#2 refersto 2ns.
8
is not
module
describe
that
concurrent
on events occurringon nets A
a designcanbedescribed
a module,
Any
the
within
occurs based
statement
each
of
of appearance
order
their
that
Within
2.2
the net data type since
are of
ports
module
The
the dataflow
Execution
four
these
all
delays
must be
If no such compilerdirective
is
certain time unit; this
to a
default
Dataflow
in
Describing
a Verilog
specified,
default time unit
SECTION 2.3
Style
HDL simulator may by the IEEE
is unspecified
Verilog HDL standard.
Dataflow
in
Describing
Style
The basic mechanism usedto modela design continuousassignment.In a continuous assignment,
net.The
assign Anytime the the
changes,
to the
the
= RHS_expression;
used in the right-hand side operand side expression is evaluated, and the value
right-hand
between to
the
after
delay.
specified
of operand on side. If no delay value
a change
left-hand
style is the is assignedto a
dataflow
a value
an
of
value
the
is:
assignment
] LHS_net
delay
f
left-hand side net
duration assignment
a continuous
of
syntax
in
the is
The delay
and
the default
specified,
assigned
specifies the time
side
right-hand
expression is
the
is zero
delay.
Here modeled
using
is an the
example
of a 2-to-4decodercircuit,shown
dataflow
style.
in
NO
An
-El
>
Abar
2-2,
Z[0]
VO
Nl
>
Bbar
B
Figure
Z[l]
Z[2]
Vt>o-
>
EN
Figure 2-2
A
2-to-4
decoder
Z[3]
circuit.
9
A
Tutorial
/ Ins
Ins
timescale
module Decoder2x4 (A, A, B,
input
[0:3]
output
B,
EN,
Z) ;
EN;
Z;
Abar, Bbar;
wire
assign #1 Abar
= ~A;
assign
#1 Bbar =
assign
#2
assign assign assign
Z[0]
= -
#2 Z[l] = #2 Z[2] = #2 Z[3] =
//
(Abar
Stmt 1
// Stmt 2
~B; &
Bbar
~ (Abar & B & - (A & Bbar & - (A & B & EW)
& EN) ;
EN) ; EN)
;
//
Stmt
//
Stmt 4
// Stmt //
;
Stmt
3
5
6
endmodule
with a backquote, is an example of The first statement, the one that begins timescale sets the time unit in a compilerdirective.The compiler directive to be Ins. For the module for all delays to be Ins and the time precision to values #1 and #2 in the continuous assignmentscorrespond example, the delay values of Ins and 2ns respectively. delay A has three The moduleDecoder2x4 port. input ports and one 4-bit output Bbar wire is one of the net net declaration declares the two wiresAbar and (a six continuous assignment the module contains types). In addition, statements.
at 5ns, statements 3, EN 2-3. When changes because EN is an operand on the right-hand 4, 5, and 6 are to its new side of each of these continuous assignments.Z[0]gets assigned value, which is 0, at time 7ns. When A changes at 15ns, statements 1, 5 and 6 of statements 5 and 6 do not affect the value of Z[0] and execute. Execution to 0 at 5 causes 17ns. Execution Z[2] Z[l]. Executionof statement change to of statement 1 causes Abar to get its new value at time 16ns. Since Abar changes,this in turn causes Z[0] to change value to 1 at time 18ns. Notice that the continuous model dataflow behavior of the assignments See
the
in Figure this is executed;
waveforms
circuit; the structureis implicit, not assignments
execute
concurrently,
explicit.
that is, they
In
addition,
continuous
are order-independent.
Describingin
Behavioral
SECTION 2.4
Style
EN
A
25
15
B
35
20 Z[0]
18
7
Z[l]
38
28
Z[2]
17
23
Z[3]
Figure 2-3 Example of
Behavioral
in
Describing
27
22
0
continuous
assignments.
Style
The behavior of a design is describedusing
constructs.
procedural
These
are:
i. ii.
This statement Always statement: This statement Initial statement:
executes always
only
once.
executes
in a
loop,
that
is executed
statement
repeatedly. Only a registerdata type can be assigned a value in either of these statements. Such a data type retains its value until a new value is assigned. All initial statements and always statements begin executionat time 0 concurrently. Here is an exampleof an always statement used to model the behavior of a is, the
1-bitfull-adder module input output
{A,
FA_Seq A,
in Figure
shown
circuit
B,
B,
Cin,
2-4. Sum, Cout)
Cin;
Sum, Cout;
11
A
Tutorial
Sum
Cout
2-4
Figure
A
1-bit
full-adder.
Sum, Cout;
reg
reg Tl,
T3;
T2,
always @
=
(A
Tl
= A
&
T2 = B T3 = A Cout
Cin) begin
B or
or
(A Sum
A
A
B)
Cin;
Cin;
&
Cin;
&
B;
= {Tl
| T3;
| T2)
end
endmodule
The
has three inputs and two outputs.Sum,Cout, Tl, T2 and to be of type reg (reg is oneof the register data types) because these are assigned values statement. The always statement within the always module
T3 are
FA_Seq
declared
block (begin-end
a sequential
has
expression following on A, B or Cin, the the
occurs
block
sequential
in
statement
A,
B,
pair) associatedwith This
character).
means
that
an
event
whenever
control
for
an
(the
an event
Statements within sequentialblockis executed. execute and the execution suspends after sequentially the sequential block has executed.After the sequential
execution, the always statement again waits
completes
on
@
event
a the
last
block
to occur
or Cin.
The statements
blocking
procedural
appear
within
assignments.
A
that
sequential block are examples of blocking procedural assignment comthe
Describingin pletes execution beforethe next statement may optionally have a delay.
forms: specified in two different Inter-statement delay: Thisis the delay
i.
Intra-statement delay: value of the right-hand
ii.
example of an
is an
example
The
delay is
expression value
to
second
= #3
Sum
by
which
a statement's
side
expression
between
and
the
computing
its assignment
to the
(A
A
delay.
Cin;
of the that the execution specifies time units. That is, after the first statement Hereis and then execute the second assignment.
statement
be delayed by 4 for 4 time units, of intra-statement
to
wait
executes, an
in the
delay
This is the delay
inter-statement
Sum = (A A B) A #4 Tl = A & Cin;
is
assignment
side.
left-hand
The
A procedural
is delayed.
execution
assignment
executes.
SECTION 2.4
Style
can be
Delays
Here
Behavioral
A
B)
delay. Cin;
in this assignment means to be computed wait first,
that
for
value of the right-hand side time 3 units, and then assign the the
Sum.
zero is the assignment, delays are specifiedin a procedural delay More on this and other forms occurs default, is, assignment instantaneously. of statementsthat can be specified in an always statement are discussed in
If no that
Chapter
Here
8.
is an
example of an initial Ins
timescale
statement.
/ Ins
module Test {Pop,Pid);
output reg
Pop,
Pid;
Pop,
Pid;
initial
begin Pop = 0; Pid
=0;
//
Stmt
//
stmt 2
1
13
Chapter 2
A
Tutorial
Pop
= #5
1;
// Stmt
Pid
= #3
1;
// Stmt 4
//
Pop =#6 0;
5
Stmt
// Stmt 6
#2 0;
Pid=
3
end
endmodule This modulegeneratesthe
in Figure 2-5. The initial waveforms shown block which starts executionat time 0ns and after it all statements within the the initial block, executing sequential completes block contains examples of This statement suspends forever. sequential with intra-statement assignments delays specified. Statements blockingprocedural 1 and 2 execute at time 0ns. The executionof the third statement, also at time a value at time 5ns. Statement 4 executesat 5ns, 0, causes Pop to get assigned contains
a sequential
Pid gets
assigned the
statement
and
and Pid statement
gets the
suspends
0
value
forever.
Chapter
the value 0 at 14ns 6 executes,the initial 8 describes initial statement in more detail. at
value
at 16ns.
8ns.
Similarly,
Pop gets
After statement
Pop
14ns
5ns
Pid
16ns
8ns
Figure 2-5
2.5
Describing
in Structural can
Structure
i.
Built-in
gate
Hi. User-defined
14
Module
Test.
Style
in Verilog HDL using: (at the gate-level) primitives
be described
ii. Switch-levelprimitives iv.
of module
Output
(at
the
transistor-level)
primitives (at the gate-level)
instances
(to create
hierarchy)
Describingin Structural are specified by
Interconnections
described in a and based on the logicdiagfam adder circuit
using nets. Hereis an in
shown
module FA_Str (A, B, input A, B, Cin; Sum, Cout; output
example
using built-in Figure 2-4.
fashion
structural
Sum,
Cin,
SECTION
Style
of
2.5
a full-
gate primitives
Cout) ;
wire SI, Tl, T2, T3;
xor A,
XI
{SI,
X2
(Sum,
SI,
and Al (T3,
B) , Cin);
B) ,
A,
A2
(T2,
B, Cin),
A3
(Tl,
A,
Cin);
or
01 (Cout,
Tl, T2, T3);
endmodule
In
this
the module
example,
xor, and, and
built-in gates
SI, Tl, T2,
T3.
and
The
is implied;
sequentially
contains gate The
or.
gate
is,
instances
of
are interconnected by nets can appear in any order since no shown; xor, and and or are being
instances
gate
instantiations
pure structure
that
instantiations,
is
XI, X2, A1, etc. are the instance names.The list of gate primitives; is the output each one signals following gate are its interconnections; the first of the gate and the rest are its inputs. For example,SI is connectedto the xor output of the gate instance XI whileA and B are connected to its inputs. A 4-bit full-adder can be described by instantiating four 1-bit full-adder the logic diagram of which is shown in Figure 2-6. The model of this modules, built-in
4-bit full-adderis shown module parameter
FourBitFA SIZE [SIZE-.l]
input
output
(FA, FB, =
FCin,
FSum,
FCout);
4 ;
FA, FB;
[SIZE-.l] FSum;
input
FCin;
input
FCout;
wire
next.
[l-.SIZE-l]
FTemp;
15
Chapter
A Tutorial
2
FA_Str FAl
FA2
.Cin(FCin),
(.A(FA[1]),
B(FB[1]),
.Sum(FSum[l
), .Cout(FTemp[l])),
(.A(FA[2]),
, .Cin(FTemp[l], .B(FB[2])
.Sum(FSum[2
) ,
)
.Cout(FTemp[2])),
FSum[3], FTemp[3]),
FTemp[2],
FA3
(FA[3]
FS[3],
FA4
(FA[4]
FCout); FS[4], FTemp[3],FSum[4],
endmodule
FB[3]
FA[3]
FB[4]
FA[4]
FB[1]
FA[1]
FB[2]
FAl
FA2r
FA3
FA4
FA[2]
FCin
FCout
FSum[4]
2-6
Figure
example, module
In this
a
module
instantiation,
first two
The
of the
name described
instantiations the form FA3
instances
and
\".
used to model a 4-bit full-adder.In associated by name or by position.
can be and
portjiame
full-adder.
4-bit
use named
FAl
port and the net to which is of
(each
instantiations,
ports FAl
A
are
instantiations
the
FSum[l]
FSum[2]
FSum[3]
is
it
connected
( netjiame)\.")
FA4, associate
ports
associations, that is, to are explicitly The last two
with
The order of the associationsis important instance FA4, the first one FA[4] is connected to port A one FB[4] is connectedto port B of FA_Str, and so on. association.
2.6
is, a
instantiations,
16
using
positional
here,
for
in example, the second
of
FAJStr,
and behavioral constructs can bemixedfreely, structural can contain a mixture of gate instantiations, module and and initial statements, amongst always assignments,
a module,
Within
nets
in Mixed-design Style
Describing that
the
module
continuous
others. Values from
assigneda value
gates or switches, while values drive
only
can
in turn
example
of a
nets)
statements (remember only can drive these statements)
and initial
statements
always
can be
data type
a register
from
within
assignments (can
or continuous
gates
be used to
SECTION 2.7
a Design
Simulating
trigger always
and
statements
initial
statements.
Here is an module
(A, B,
FA_Mix
input
A, B,
Cin;
Sum,
Cout;
output
1-bit full-adder in
reg
Cout;
reg
Tl, T2, T3;
Cin,
a mixed-designstyle.
Cout)
Sum,
;
wire SI;
xoi
XI
instantiation.
II Gate
B) ;
A,
(SI,
always @
//
B or Cin) begin - A & Cin; T2 = B & Cin; T3 = A & S; = (Tl | T2) | T3; Cout (A or
statement.
Always
Tl
end
assign
A
= SI
Sum
II Continuous
Cin;
endmodule
Executionof or
B.
The
always
the
gate
instantiation
occurs
whenever
statement executes whenever there
Cin, and the continuousassignmentexecuteswhenever
assignment.
an event
is an there
event
is an
occurs on A on A, B or event on SI
or Cin.
1.1
Simulating a Design HDL
Verilog
model
provides
control, storing
stimulus,
language. Stimulusand Responses
from
capabilities
the
design
control
under
not only
responses
and
can
be generated
test can
be saved
to describea designbut verification,
all using
also
to
the same
using initial statements. as \"save on change\" or as
17
A
Tutorial
strobed
can be performedby
Finally, verification responses by expected
data.
with comparing
automatically
in an initial
statements
appropriate
writing
statement.
Here is an described
test module 2.3.
of a
example
in Section
earlier
wire
the
tests
module
FA_Seq
Ins/Ins
timescale
module Top;
reg
Top that
list.
an empty port
PCi;
PB,
PA,
may have
module
//A
PCo, PSum;
module under test:
II Instantiate Fl
FA_Seq
PB,
(PA,
II Positional.
PSum, PCo);
PCi,
initial
begin:
ONLY_ONCE
[3:0]
reg
Pal;
II Need 4
bits so that
(Pal = 0; Pal < begin
for
{PA,
PB,
Pal
have
can
Pal
= Pal
PB,
PCi=%b%b%b\",
8;
value
the
8.
+ 1)
= Pal;
PCi)
#5 $display
(\"PA, \"
:::
PCo,
PA, PB,
PSum=%b%b\", PCo,
PCi,
PSum);
end end endmodule The signals in the module instantiation are linked to the ports of the module under test using positional association,that is, PA is connected to port A of module and so on. FA_Seq, PB is connected to port B of moduleFAJSeq, Notice that a for-loop statement has been used in the initial statement to generate a waveform on PA, the for-loop
The target of the first assignment statement a The concatenated bits on represents target. appropriate the right-hand side are assignedto the left-hand side from right to argument left. The initial statement also contains an example of a predefinedsystem task. The in the values Sdisplay system task prints the specified argument to the format specified output. PB
and
PCi.
within
The
delay
control
in the
Sdisplay system task
after play taskis to be executed
5 time
units.
call
This 5
specifies
that the
$dis-
time units basicallyrepre-
SECTION 2.7
a Design
Simulating
sents the settling time for the logic, that is, the delay time between the of a vector and observing the module-under-test'sresponse. application
Thereis the
yet
statement has to block label is not the
be labeled.ONLYjONCE if there
necessary
Figure 2-7 shows the test module.
block.
produced
nuance to this model. Pal is declaredlocally in To do this, the sequentialblock(begin-end)
another
statement.
initial
by
PA, PA,
PB,
PCi
PB,
PCi
the
:
=000 =001
:
PB,
PA,
=100:
Here
produced.
PCo,
PSum
=00
PCo,
PSum
=01
PA PB, PCi =010: PCo, PSum :; PCo, PSum PB, PCi =011 PA PCi
PSum
PCo,
in
case.
this
variables declared locally
are no
waveforms
label
block
the
is
within
the
is the
initial The within
output
=01 =10
=01
PA PB, PCi =101 : PCo, PSum =10 PB,
PA,
PCi
=110::
PA, PB, PCi =111:
PCo,
PSum
=10
PCo,
PSum
=11
PCi
0
5ns
10ns
15ns
20ns
30ns
25ns
35ns
PB
PA
PSum
PCo
Figure 2-7 nand
Waveforms
produced
by executing
Hereis anotherexampleof a testmodulethat in Figure 2-8. gate module RS_FF shown
test bench
exercises
the
Top. cross-coupled
19
Chapter 2
A
Tutorial
Q
Qbar
2-8 Cross-couplednand
Figure
gates.
\"timescale10ns/Ins module
R, S) ;
Qbar,
(Q,
RS_FF
output Q, Qbar;
input
R,
#1
nand
5;
(Q, R, Qbar)-,
nand #1 (Qbar, S, Instance
II
Q)
;
names are
optional
module
under test:
in gate instantiations.
endmodule
module
Test;
reg
TS, TR;
wire TQ, TQb; II
Instantiate
RSJFF NSTA (.Q(TQ) II Using named //
Apply
stimulus:
initial
begin TR
= 0 ;
TS = 0 ;
#5 TS = #5
TS
TR = #5
TS
1;
= 0;
1; = 1;
TR = 0 ;
#5 TS= 0; #5
end
20
TR
= 1;
,
.S(TS)
association.
,
.R(TR)
, .Qbar(TQb));
Simulating a Design
//
Section2.7
output:
Display
initial
$monitor \"
$time,
TQ=%b,
TS=%b,
TR=%b,
\"
%t,
time
(\"At
TQ, TQb)
TS,
TR,
TQb=%b\",
endmodule
Module RS_FF
describesthe structure
in gate instantiations;
for
time unit. This gate delayimpliesthat T+l. Q gets the computed value at time The
the waveform on procedural
task
the test module. The design under test RS_FF is are connected using named association. Therearetwo in this module. The first initial statement simply generates TS and TR. This initial statement contains blocking
its ports
statements
initial
inter-statement
with
assignments
The second initial statement when called causes the
occurs in the specifiedvariables waveforms
the effect
if R
Test is
module and
instantiated
the design. Gate delays are used is 1 delay for the first instantiation or Qbar changes at say time T, then of
the gate
example,
Here
produced.
by the
produced
delays.
specifiedstring the
in
the systemtask
to call
is used
be
to
argument
is the output produced timescale directive
This
Smonitor.
a change
whenever list. Figure 2-9 shows the by the test module. Notice
printed
on the delays.
TR
250 TS
TQ
200
J
\302\261
10ns TQb
150
100
50
x
120
J
0ns Figure
60
2-9
At time At
260ns
W 0
time
At time
Waveforms
210
170
HO
produced
by module
Test.
0, TR=0, TS=0,TQ=x, TQb=x
10,TR=0, TS=0,TQ=l,TQb=l
50,
TR=Q
15=1.
TQ=1.
TQb=l
21
Chapter 2
A
Tutorial
At time
60, TR=0,
At time
100, TR=1. TS=0,TQ=l,TQb=0
110,
time
At
TQ=0, TQb=l
TR=1, TS=0,
120,
At time
150,TR=0,
TQb=l
TQ=0,
TS=l,
160, TR=0, TS=l. TQ=l, TQb=l
time
At
TQ=l,TQb=l
TR=1,TS=0,
At time
TQb=0
TQ=l,
TS=l,
At time
170,
At time
200, TR=0, TS=0,TQ=l.TQb=0
TR=0,
210,
time
At
TR=0,
TQb=0
TQ=l,
TS=l,
TQb=l
TQ=l.
TS=0,
At time
250, TR=1, TS=0,TQ=l,TQb=l
At time
260,
TR=1,
chapters elaborateon thesetopicsand
The following
TQb=l
TQ=0,
TS=0,
more
in greater
detail.
2.8
Exercises
1.
What
statement
2.
What
is the
is used
a design in the dataflow
to describe
style?
purpose of the \"timescalecompilerdirective?
an
Give
example.
3.
What
are the
two kinds of delays that
statement?
assignment
Elaborate
4. Describethe 1-bitfull-adder 5.
What
is the
using shown
can
be
specified
in a
procedural
an example. in Figure
key differencebetween an
2-4 using
the dataflow
statement
initial
and
style.
an always
statement?
6. Generatethe
waveform
following
on a
variable BullsEye using an initial
statement.
0
Figure
22
12
2 3
2-10
A
waveform
22 on variable
24
27
BullsEye.
32
Exercises 7.
a model, in
Write
structural style, for
the
shown
decoder
2-to-4
2.8
SECTION
in
Figure
2-2.
8.
described bench to test the moduleDecoder2x4
a test
Write
in
Section
2.3.
9.
Name two kinds of assignmentstatements
that
you
can have
in
a Verilog
model.
HDL
in 10. When is a label requiredto be specified
the
11. Using following
dataflow
style,
description
logic. Use
exclusive-or
write
block?
a sequential
a Verilog
HDL model for
the
the specifieddelays.
5ns
4ns
ft Ins
5ns
B
Figure 2-11 12.
What
is wrong
assign
with
the
Reset =
#2
following A
Exclusive-or
continuous
logic.
assignment?
WriteBus;
23
3
Chapter
Elements
Language
This
comments,
identifiers,
In
functions.
3.1
elements of Verilog HDL. It introduces numbers, directives, system tasks and system compiler it introduces the two data types in the language. the basic
describes
chapter
addition,
Identifiers An
in Verilog
identifier
the
character,
and
character
must
sensitive.
be
Here
_ (underscore) a letter or
HDL is any
sequence of letters, digits, the $
character, with an underscore.
the
restriction
Count
COUNT
_R2_D2 R56_68
FIVE$
24
that the
In addition, identifiers are some examplesof identifiers.
II
Distinct
from Count.
first
are
case-
Section
Comments
An
ASCII characters
identifier.
an
in
and
character
(backslash)
provides
identifier
escaped
ends
with a
newline).Hereare some
a way of including An escaped identifier
white space (a white of
examples
any
starts
space
the
of
is a
with
3.2
printable a \\
space, tab
or a
identifiers.
escaped
\\7400
\\~Q
The last exampleexplainsthe the
and
escaped identifier, the backslash of the identifier. Thus, identifier space part to identifier OutGate.
is identical
Verilog HDL defines can in
be used
only the language.
in
Note identifier
ALWAYS
3.2
Note
identifiers, called keywords,that A lists all the reservedwords Appendix
of reserved
that
only
lower
the (which
always
is a
are reservedwords. is distinct from the keyword)
case keywords
a keyword).
is not treated the same as the keyword. keyword is a is distinct from the identifier initial (which this convention is different from those of escaped identifiers. escaped
\\initial
identifier
keyword).
in an
that,
contexts.
is not
(which
In addition, an Thus,
list
a
certain
Forexample, identifier
fact
are not
terminating
\\OutGate
OutGate
as
same
is
\\OutGate
that
Comments
There aretwo
forms
in Verilog
of comments
HDL.
/* First form:Can extend
across
many
lines
*/
// Second form: Ends
at
the
end of
this line.
25
Chapter3
3.3
Elements
Language
Format That is, Verilog HDL is case-sensitive. case are distinct.In addition, HDL Verilog
may be tab, and that
across
written
lines,
multiple
space characters)
no
have
differing is free-format, that
or on
special
only in their
identifiers
one line. White
is,
constructs (newline,
space
Here is an
significance.
example
this.
illustrates
initial
Top = 3'bOOl;
begin
#2
Top
= 3'bOll;
end
is same as:
initial
begin Top
= 3'bOOl;
#2 Top
= 3'bOll;
end
3.4
System Tasks and An
or as a
identifier
Functions with
beginning
systemfunction.A
task
a $
character is interpreted a mechanism
provides
as
a system
task
to encapsulate a
from different parts of a design. A task can return zero is like a task except that it can or more values.A function return only one a function executes in zero time, that is, no delays are allowed, value. In addition, behaviorthat
can
whilea task
be invoked
can
have
delays.
(\"Hi, you have reached LT today\") $display /* The $display system task displays the to with a newline character. */ output
;
specified
message
$time
// This
system
Tasksand functions
26
function
are
described
returns
the
in Chapter
current
10.
simulation
time.
CompilerDirectives
\\.5
3.5
SECTION
Directives
Compiler
Certain identifiers that
directives. A
(backquote) character when compiled, remains in effect
directive,
compiler
*
the
with
start
process (which couldspan
entire compilation
compiler directive specifiesotherwise.
Here
is
a different
list of
a complete
the
through
until
files)
multiple
are compiler
standard
compilerdirectives. \342\200\242
\"undef
\"define,
\342\200\242
\"endif
\"else,
\"ifdef,
\342\200\242
\"default_nettype
\342\200\242 \"include \342\200\242 \"resetall \342\200\242 \"timescale \342\200\242
\"nounconnected_drive
\"unconnected_drive,
\342\200\242
\"endcelldefine
\"celldefine,
$.5.1
vdefine
and \"undef
The \"define
C programminglanguage.Hereis an
\"define
Once the the
compilation. many different
the definition
For example the
files with
the
\"define
WORD
wire
\"undef
[
\"WORD
16
:
//
Creates
stays in
effect
usage of MAX_BUS_SIZE
in another
directive
The \"undef directiveremovesthe definition macro. Hereis an example.
\"define
example
much
of this
the
like
directive.
AddReg;
1:0]
is compiled,
directive
\"define
entire
across
-
MAX_BUS_SIZE
[
and is very
32
MAX_BUS_SIZE
\"
reg
for text substitution
is used
directive
#define in the
a macro
of
a previously
through could
be
file. defined
text
for text substitution.
1 ] Bus;
WORD
27
Chapter
3
Language Elements
// The definition // after this 3.5.2
is
WORD
no longer
available
directive.
\"endif
\"else and
\"ifdef,
of \"undef
Thesecompiler
for conditional
used
are
directives
compilation. Here
is an
example.
WINDOWS
\"ifdef
parameter
WORD_SIZE
=16;
WORD_SIZE
= 32;
\"else
parameter \"endif
if the text macroname WINDOWS
During compilation, parameter
is selected,
declaration
otherwise
the second
selected. The
3.5.3
is optional
directive
\"else
the
with
Mfdef
is defined,
the first
parameter declarationis
directive.
\"default_nettype
This directive that is, for nets that
is
to specify not declared.
used are
\"default_nettype
the net
type
for
net
implicit
declarations,
wand
This example specifiesthe default if a net to be a wand net. Therefore, type net is not declared in any module following this directive,the net is assumed
to be a wand
3.5.4
net.
\"include
The \"include compiler directivecan beusedto include file in-line. The file can be specified either with a relative full path name. x
include
28
\"../..
/primitives.v\"
the
path
contents
of any
name or
with
a
Compiler Directives
is replacedwith
this line
compilation,
Upon
of the
contents
the
3.5
SECTION
file \"../../prim-
itives.v\".
\"resetall This compilerdirective
to their default
directives
all compiler
resets
value.
'resetall
For example, this
directive causesthe default
net
type
to be
wire.
'timescale In a Verilog
HDL
model,
The association of time units
compilerdirective.This precision.
actual
with
is used
directive
is of
directive
The
are expressed
all delays
time
is done
to specify
units.
of time
terms
in
using the 'timescale
the time
time
and
unit
the form:
'timescale time_un.it/ time__precision where
the
100 and units
from s, ms,us,ns, ps and
directive
unit of
a time
outside
appears
that follow
it. Hereis an Ins
'timescale
module AndFunc
and
//
and
Ins and a time precisionof lOOps. of a module declaration and affects
\"timescale
The all
delay
values
example.
/ 10Ops (Z,
A,
B) ;
Z;
output
input
1,10,
Ins / 10Ops
'timescale indicates
is made up of values from fs. Here is an example.
and time_precision
timejunit
A,
#(5.22,
Rise
B;
6.17)
and fall
Al (Z,
A,
B)
;
delay specified.
endmodule
29
Elements
Language
specifies all delays to be in ns and delays are rounded to one5.2ns and the 5.22 becomes (lOOps). Therefore, the delay value 6.17 becomes 6.2ns. If instead the following timescale directive the above module,
The directive of
tenth
a ns
delay
value
is used
in
\"timescale 10ns / Ins becomes
5.22
then
52ns,
The \"timescale directive in
directive directive
is
having
place appropriately
What
its
if there
happens
\"timescale
own
all
affects
until another
a compilation
found.
becomes 62ns.
and 6.17
in modules
delays
is morethan
scaled
to this
'timescale
Ins
module AndFunc input
/ lOOps (Z,
B) ;
A,
B;
A,
Al (Z,
6.17)
and #(5.22, endmodule
10ns /
'timescale
A,
B)
Ins
module TB; PutB;
Put A,
reg
wire GetO;
initial
begin PutA
= 0;
PutB
= 0;
#5.21 PutB =
#10.4
PutA
#15 PutB
1;
= 1;
= 0;
end AndFunc
endmodule
AF1
in a
module
In such a case, simulation of precision all the modulesand smallest time precision. Hereis an
Z;
output
one
directive?
smallest time
in the
follow
that
(GetO,
PutA,
this
\"timescale directive or \"resetall
PutB);
;
design each
always all
delays
example.
takes
are
CompilerDirectives
SECTION
3.5
directive. The \"timescale example, each modulehas its own timescale to the delays. Therefore in the first module, directive is first applied 5.22 is in 6.17is a nd is the second 5.21 10.4is 6.2ns, 5.2ns, module, 104ns,and 52ns, If module TB were simulated,the smallesttimeprecision 15 is 150ns. of all in this design is lOOps.Therefore,all delays modules in the delays (especially module TB) will be scaledto a precisionof lOOps. 52ns now becomes Delay and 150ns becomes 520*100ps, 104ns becomes 1040*100ps, 1500*100ps. More importantly, simulation occursusing a time precisionof lOOps. If were simulated, module AndFunc the \"timescale directive of moduleTB has no TB is not a child moduleof moduleAndFunc. effect since module In this
3.5.7
and
\"unconnected_drive
Any
these
unconnected
ports
input
two directives
\"nounconnected_drive in module
instantiations
are either pulledup or pulled
that
appear
between
down.
\"
pulll
uncoxmected_drive
/* All unconnected input are pulled up (connected
ports betweenthese two to 1) . */
directives
*nouncoxmected_drive
\"
pullO
unconnected_drive
unconnected
/* All are
pulled
input ports betweenthese two to 0) . */
directives
down (connected
*nouncoxmected_drive
3.5.8
and
'celldefine
'endcelldefine
These two directivesare used to mark typically encompassa moduledefinition,
a module as
shown
as a in the
cell module. They
following example.
x
celldefine
module
FD1S3AX
{D, CK,
Z)
;
endmodule
*endcelldef
ine
31
Language Elements
Chapter 3
Cellmodulesare
used
3.6
some
by
PLI routines.
Set
Value
the following
has
HDL
Verilog
four basic values,
i. 0 : logic-0orfalse 1:
ii.
logic-1
Hi. x: z:
iv.
or true
unknown
high-impedance
of these four values are built-in Note that the interpretations a 0 always A z in a value always means a high-impedance, and so on.
x.
input
of
same as 0X1Z.A
constant
the
means
language. a logic-0,
an expression is usually interpreted as z are case-insensitive,that is, the value in Verilog HDL is made up of the above
or x and
a gate
the values
Furthermore,
Oxlz is
in
values.
basic
four
at the
z value
A an
into
There are
three types of constants
i*.
Integer
ii.
Real
in
Verilog
HDL.
Hi. String An
underscore
freely;
they
readability;
are the
(_)
character
can be
used in
an
in the number itself. They ignored restriction is that the underscore only
or a real constant can be usedto improve character cannot be the
integer
character.
3.6.1
Integers
An integer
32
number can be written decimal
i*.
Simple
ii.
Base format
in
the
following
two forms,
first
Value
Decimal
Simple An
+
(unary) or a
specified as a sequenceof digits
form is
Here
operator.
(unary)
are some
examples of
an optional
integersin
the
is decimal 32
32
- 15
is
-15
decimal
An integer value in this form represents a in two's complement form. is represented
010000
with
form.
decimal
simple
Form
in this
integer
3.6
SECTION
Set
binary; -15 is 10001in
in 6-bit
signednumber.A negative Thus 32 is 10000in a 5-bit
5-bit
binary,
and is
number
binary,
110001 in a
6-bit
binary.
Notation
Format
Base
of an
The format
[ size
]
in this
integer
'base
form is:
value
in number of bits, base is one specifies the size of the constant or B d b or D (for binary), (for octal), (for decimal),h or H (for and value is a sequence of digits that from the base. The are values hexadecimal) values x and z and the hexadecimalvalues a through f are case-insensitive.
where
the size
of oorO
Here are
some examples.
5'037
5-bit octal
4'D2
4-bit
decimal
4'Blx_01
4-bit
binary
7-bit
x (x z (z
7
'Hx
4-bit
4'hZ
Not
4'd-4 8
'h
3' (2+3)
2A
bOOl
'dlO
legal: Spaces are and
between
Not
legal:
Not
legal;
extended) , that is, xxxxxxx extended) , that is, zzzz value cannot be negative
allowed between size and ' character base and value no space allowed between ' and base b size cannot be an expression
33
3
Elements
Language
(or z)
z) in a hexadecimalvalue represents three bits of x (or z), and x represents
an x (or
that
Note
octal
in
four
(or z), x represents
bits of x
(or z) in binary
one bit of x (or z). in base format notation is always an unsigned number. The size of in this form. If no is is an size specifiedin an specification optional integer of bits specified in the value. the size of the number is the number integer, Here are some examples. A
number
'o721
9-bit octal
'hAF
8-bit
If the
hex
size specifiedis largerthan
number is padded is a x or a z, in
the
to
specified
O's except for or a z respectively
left with a x
case
which
size
the
the
case
is used
for the constant, the where the leftmost bit to pad
to the left. For
example,
10'blO If
size
the
the
0 to
with
Padded
left,
Padded with x to the left,
10'bxOxl
specified
is smaller,
the
then
leftmost
0000000010 xxxxxxxOxl
bits
are appropriately
truncated. For example,
3'bl001_0011
is
5'HOFFF
is same
The ?charactercanbeused be used
to
improve
readability
value (see
don't-care
as
3'bOll
as
same
as 5'HIF for value z in a number. where the value z is interpreted
an alternate
in cases
Chapter 8).
Reals A
real
number
can be
i. Decimalnotation: 2.0
5.678
11572.12
0.1
specified
in
Examples
one
following two forms. in this form are: numbers
of the of
It may as
a
// Not legal: // on either
2.
ii.
notation:
Scientific
side of decimal.
360.0
3.6E2
of numbers
Examples
(e
this
are:
form
as E)
same
is
0.0005
5E-4
Implicit conversionto integeris defined are converted to integersby rounding to the
by
the
to integer
-26.22
gives
Real numbers
language.
nearest integer.
to integer 42.446, 42.45 when converted 92.699 93 when converted 92.5, yield -15.62 to integer gives -16
3
in
23510.0; underscores are ignored
The value
23_5.1e2
3.6
a digit
have
must
SECTION
Set
Value
yields into
42
integer
-26
Strings
a sequenceof characterswithin of split acrosslines.Here are examples
A string is
not be
double
quotes.
A string
may
strings.
ERROR\"
\"INTERNAL
\"REACHED->HERE\"
A character unsigned
is represented by
ASCII
value
which is
treated as an
To Therefore a string is a sequenceof 8-bit ASCIIvalues. \"INTERNAL ERROR\", a variable of size 8*14is needed.
integer.
the string
reg
[
1
Message The
8-bit
an
8*14
:
=
] Message;
\"INTERNAL
character
\\ (backslash)
store
ERROR\";
can be
used to escapecertain
special
characters.
\\n
newline
\\t
tab
\\\\
the
\\
character character
itself
35
Chapter 3
3.7
Language Elements \"
\\\"
the
\\206
character
character
with
octal
value 206
of data
types.
Data types two groups
has
HDL
Verilog
i. Net type: A
net
typo, represents
as a continuous to
connected
ii.
gate
of
value
output.
defaults to a value
of
value is savedfrom one has a default value of x.
and its type
register
z.
element.It is
assignment
are
the
different
kinds of
nets that
belong
to the
net data
\342\200\242
wire
\342\200\242 tri \342\200\242 wor \342\200\242
trior
\342\200\242 wand \342\200\242 triand \342\200\242
trireg
\342\200\242 tril \342\200\242
triO
\342\200\242
supplyO
\342\200\242
1
supply
A simple
syntax for
net_kind
36
driver is
or
an
to the
Net Types Here
[
a net declarationis: msb
: lsb
] net!,
net2 ,
. . .
such
drivers
its
If no
an abstract data storage represents within an always statement only
values
statement,
3.7.1
assignmentor a
the net
type
register
assigned
A
connection betweenstructural from the
type:
Register A
a net,
a physical
is determined
value
Its
elements.
, netN;
type.
initial
next.
Data
is one of the
where net_kind that
expressions
of the
the range
specify
range is specified,a net defaults
if no
wire Rdy, Start; wand [2:0] Addr; The various for a
net,
that
is,
wor
In this
Isb are constant
is optional; net; the rangespecification a size of one bit. Here are some
II
Two
1-bit
//
Addr
is
wire a 3-bit
nets. vector
wand
one exists more than driver nets behave differently when there when there are multiple assignments to a net. Forexample,
assign
i?de = Bit
&
Wyl;
assign
i?de = Kbl
\\
Kip;
Rde has two drivers,onefrom a wor net, the effective value
it is
Since
of the
each
of Rde
continuous
is determined
wor (see following section on wor nets) using the values side (the values of the right-hand expressions).
table
Wire
and
net
used to special
of
the
a
from
drivers
Tri Nets
This is the mostcommontype wire
net.
i?de;
example,
assignments.
to
msb and
3.7
declarations.
net
of
examples
above,
listed
nets
SECTION
Types
and a
tri
are
net
identical
net
of
is used to connectelements. A and semantics; the tri net may be a net, and has no other drive
which
in syntax
describe a net where multiple
drivers
significance.
Reset;
wire
[3:2] Cla,
wire
tri
[MSB-1
:
Pla, Sla;
LSB+1]
Art;
drivers drive a wire is determined by using the following
(or a
If multiple
tri) net, the
value
effective
of the
net
table.
wire (or tri)
0
1
x
z
0
0
x
x
0
37
Elements
Language
wire (or tri)
0
1
x
z
1
x
1
x
1
X
X
X
X
X
z
0
1
x
z
an example.
Here is
assign Cla
Cla =
assign In this
example,
of the determine evaluated
side
an
z index into
and
Wor
A
Sla;
is used
Since Cla is a vector,eachbit
of Cla.
if the
example,
secondright-hand
(the first bits 1 and 1 index into an
first
right-hand
side
is xlx
the tableto give
of the two drivers (the values to index in the above table to
values
The
drivers.
expressions)
of Cla
second
x, the
Pla
For
independently.
the value Olxand the value
& Sla;
value
effective
effective
Pla
Cla has two
right-hand
the
=
expression 0 and 1 index
bits the
table
to give
position
is
has side expression has the value Hz, the
into the table to give a 1, the third bits x and
x).
Trior Nets
This is a wired-ornet, is also a 1. Both
the net
is, if any
that
and
wor
trior
one of the drivers is nets are identical in
a 1,the
value
functionality.
wor
[MSB
trior
: LSB]
If multiple drivers determined
by
using
Art;
: MIN-1]
[MAX-1
drive
the following
wor (or trior) 0
this
Rdx,
Sdx, Bdx;
net,
the effective
value of the net
table.
0
1
0
1x0
x
on
their syntax and
z
is
Data
wor (or trior)
and
Wand
SECTION
Types
0
1
X
z
1
1
1
1
1
X
X
1
X
X
z
0
1
X
z
3.7
Nets
Triand
This net is a wired-and is a 0. Both wand
net,
the net
that
triand
and
the is, if any of the drivers is a nets are identical in their syntax
0,
value
of
and
functionality.
wand
Dbus;
[-7:0]
triand
Clk;
Reset,
If multiple drivers drive determine
the
effective
a wand
following table
is usedto
0
1
X
z
0
0
0
0
0
1
0
1
X
1
X
0
X
X
X
z
0
1
X
z
wand (or triand)
THreg
net, the
value.
Net
This net stores a value
(like
a register)
node.
and is
used to modela capacitive
all drivers When to a trireg net are at high-impedance, that is, have the value z, the trireg net retainsthe last value on the net. In addition, the default value for a trireg net is an x. initial
trireg
[1:8]
Dbus,
Abus;
39
Chapter 3
Elements
Language
Nets
Tril
and
TriO
These nets alsomodelwired-logic nets, characteristicof a triO particular this net, its value is 0 (1 for tril). driving driver. The
The
has
[-3:3]
tril
[0:-5] OtBus, ItBus;
than
(tril)
the effective
value for
a triO
and
(tril)
0
1
X
z
0
0
X
X
0
1
X
1
X
1
X
X
X
X
X
z
0
1
X
0(1)
than
one
no driver
is
or a tril
net
value 0,
and the
that
Nets
Supplyl
The supplyO net is used to modelground,
supplyl net is usedto modela power
3.7.2
more
with
is that if
net
one driver.
triO
SupplyO
shows
table
following
a net
is,
GndBus;
triO
more
that
net,
that is,
that
is,
the
the value
1.
ClkGnd;
supplyO
Gnd,
supplyl
[2:0]
Vcc;
Undeclared Nets In
it is
HDL,
Verilog
possible not to
declarea net.In
such
a case,
the net
defaults to a 1-bitwire net. This
net
implicit
compiler
xdefault_nettype
declaration directive.
can be changed It is of the form:
\"
net_Jcind
de\302\243ault_nettype
For example,
40
with
the
compiler
directive:
by using
the
Data Types \"
wand
default_nettype
net defaults to a
any undeclared
.3
1-bitwand
The keywords,scalared or vectored, vector net. If a net is declaredwith the
part-selectsof this has to be assigned chapter). Here
is an
net
vector
(bit-selects
Bit-select
wor
and part-select
Grb[3:2]
allowed.
[4:0]
Best;
as:
wor [4:0]
Best;
part-select
Best[3:1]
are allowed.
If no such keyword
.4
for a
Grb;
// Bit-select Best[2] and //
be specified
then bit-selects and vectored, keyword allowed; in other words, the entire net and part-selects are describedin the next
Grb[2]
scalared
11 Same //
NOT
optionally
of such a declaration.
example
// are
can
are not
wire vectored [3:1] II
net.
Nets
Scalared
and
Vectored
3.7
SECTION
is
specified,
then the
default is scalared.
Register Types There
five
are
different
kinds of
register types.
\342\200\242
reg
\342\200\242
integer
\342\200\242 time \342\200\242 real \342\200\242 realtime
Reg
Register
The reg kind of registerdata type is the one most commonly used. A which is of the form: declared by using a reg declaration,
reg
is
41
Language Elements
reg
, reg2 ,
] regl
is optional; if no range specification register. Here are someexamples.
[1:32]
reg A an
size.
in a
be of any
can
register
1-bit
A
A
value
a 4-bit
is
Sat
// Kisp, Pisp, Lisp;
The
expressions.
is specified,
range
//
reg [3:0]Sat; reg Cnt;
. . . , regN;
the range and are constant-valued
lsb specify
and
msb
where
: lsb
msb
[
to
defaults
it
a 1-bit
register.
register.
interpretedas
is always
register
number.
unsigned
Comb;
[1:4]
reg
= -2;
Comb
Comb =5;
II
Comb has
//
Comb
two's
14 (1110), the 5
has
of
complement
2.
.
(0101)
Memories A
is an
memory
array of
registers. It is declaredusing
declaration
a reg
of
the form:
reg
[
: lsb
msb
] memoryl memory2
Hereis
example
of a
reg [0:3]
MyMem
an
//
is
MyMem
and
MyMem
Bog
Bog
is
no
such A
memories.
of sixty-four of five
are memories.
Arrays
a memory
equivalent
for the
reg
declaration
single
: lower2
. .
], .
;
[0:63];
an array
an array
not allowed.Noticethat
: lowerl ],
[upper2
declaration.
memory
reg Bog[l:5];
//
[upperl
4-bit registers.
1-bit registers. with
belongs
more
two
than
to the register
dimensions
net data type. can be
used to declareboth
are
data type. Thereis
registers
and
Data
parameter ADDR_SIZE reg [ 1: WORD_SIZE]
RamPar is a memory, bit
an
, DataReg;
8-bit registers, while DataRegis a 8-
of sixteen
array
: 0]
[ADDR_SIZE-1
register.
of caution in but a assignment,
A word in
WORD_SIZE = 8;
=16, RamPar
SECTION 3.7
Types
one
for a memory when it is following assignment,
cannot be
A memory
assignments.
register can. Thereforean
reg [1:5]Dig; //
Dig
is
a 5-bit
assigned a value to be
specified
difference. In the
Let's look at this
assigned.
being
needs
index
register.
Dig = 5'bll011;
is okay,
but
the
following
assignment:
//
[1:5];
reg Bog
Bog
is
a memory
of five
1-bit registers.
Bog=5'bll011;
isnot.
One
memory
way
to assign For
individually.
reg
[0:3]
to a
memory is to assign a value
to
each
word
of a
example,
[1:4];
Xrom
= 4'hA;
Xrom[l]
Xrom[2] = 4'h8;
Xrom[3]
=
Xrom[4]
= 4'h2;
4'hF;
to assign values
An alternate way
tasks:
These
i.
$readmemb
ii.
$readmemh
system
The text
tasks
file must
(loads
read contain
hexadecimal. Hereis
an
binary
to
a memory
is by using
values)
(loads hexadecimalvalues) and load data from a specifiedtext file the
appropriate
the system
form
of numbers,
into
a memory.
either binary or
example.
43
Elements
Language
reg [1:4]
RomB is a may
may be in
RomB);
(\"ram.patt\", file
The
memory.
must contain binary values. The file of what and comments.Hereis an example
\"ram.patt\"
white spaces
contain
also
[7:1];
RomB
$readmenb
the file.
1101
1100
1000
0111 0000
1001
0011
The
system
index
7, the
from task $readmemb causesthe values to be read in starting a part of the memory is to be word index of RomB.If only can be explicitly range specified in the $readmemb task, such as:
leftmost
loaded,
the
RomB,
(\"ram.patt\",
$readmemb
5,
3);
case only RomB[5],RomB[4],and RomB[3] words at the The and values readare 1100 1101, beginning top.
in which file
file may
The
also contain explicitaddressesof the
When index
bound
@5
11001
11010
case the values are read into only
//
value is
a start
of the
$readmemb
form:
example:
@2
in which
from the
1000.
value
@hex_address
such as in this
are read
memory
specified
of the
addresses
specified, readcontinuesuntil
the
RomB,
from address
6
6); and
continues
until
memory.
right-hand
is reached. For example,
(\"rom.patt\",
Starts
the
1.
Section 3.7
Data Types
// Reads
An
an
4.
Register
Integer
for modeling
typically
of the
declaration
integer
can be usedas a general behavior. It is declaredusing high-level
integer values. It
contains
register
integer register,
purpose
4);
6 through
addresses
from
6,
RomB,
(\"rom.patt\",
$readmemb
form:
integer integerl , integer2,. msb and
lsb are constant-valued
..
,
integerNl
msb
: lsb
];
that specify the range of an no bit range is is Notice that integer array; optional. array range specification a minimum of 32 bits; however, an implementation allowed. An integer holds of integer declarations. may provide more. Here are some examples expressions
the
C;
A, B,
integer
II Three integer
integerHist[3:6]; //
An provide
An
of
signed quantities results.
registers.
four
integers.
and arithmetic
operations
arithmetic
complement integer
array
the be accessed as a bit-vector.For example, given are not allowed. One way for integer B, B[6] and B[20:10] is to assign it to a reg register and then bit-value of an integer from the reg register. Here is an example.
cannot
declaration
above
to extract a select
holds
register
integer
two's
An
the
bits
Br eg;
[31:0]
reg
Bint;
integer
// Bint[6]
Bint[20:10]
and
Breg = Bint;
/*
At
this
point,
the
give
Breg[6]
corresponding
are
not allowed.
and Breg[20:10] are from the
allowed
and
bit-values
integer Bint */ This
example
accomplished
by
shows simply
that
using
converting an integer to a bit-vector can an assignment. Type conversionis automatic.
be No
spe-
45
Language Elements
cial functions are necessary.Converting
also be accomplished by using
to an integer
a bit-vector
from
can
some examples.
Here are
an assignment.
integer J;
reg [3:0]
Beg;
= J;
Beg
has the value 32'b0000.. .00110. the value 4'bOHO.
// J
= 6;
J
//
Beg has
Bcg=4'bOlOl;
J
=
Beg;
III
J
=
-6;
// II
= J;
Beg
Note
that
leftmost
bit;
assignment
any
extra
that
value
32'bOOOO.. .00101.
.11010.
J has the value 32'bllll. . Beg has the value 4'blOlO. takes place
always
bits are
remember
can
you
the
J has
from the rightmost
bit
to the
truncated. It is easy to think of type conversion if are represented as two's complement bit-
integers
vectors.
Time
Register
register is usedto storeand
A time
using a time declarationof the time
time_idl
manipulate
It is
values.
time
declared
form:
, time_i
Slbar
Figure 5-7
the
that the gate is also
cannot
be
.12
A 2-to-4
same
Decoder
Hereis
a
4-to-l
multiplexer.
instance name is alsoZ and the Z. This is not allowedin Verilog module. as a net name within one
Notice
the
A
to the output instance name
net connected HDL.
An
of
Example description
gate-level
of a
2-to-4 decoder
circuitshown
in
Figure
5-8.
DEC2x4 {A, B, A, B, Enable;
module input
output [0:3] wire
not
#
(1,
Z) ;
Z;
Bbar;
Abar,
V0 (Abar,
Enable,
2) A)
,
85
CHAPTER 5
Gate-level Modeling
NO
\\
Z[0]
Nl
\\
Z[l]
\\>4b\302\253r V0/>\302\260
A
i\342\200\224 i
N?\\
i
^^
i\342\200\224
^
B
.
Z[2]
Bbar
Z[3] Enable
5-8
Figure VI
A
2-to-4
decoder
circuit.
{Bbar, B);
nand #(4, 3) NO
(Z[0],
Nl
(Z[l],
N2
(Z[2],
N3
(Z[3]
Abar, Bbar), Abar, B), A, Bbar), A, B) ;
Enable, Enable, Enable, ,
Enable,
endmodule
5.13
A Master-slave Here
is a
Flip-flop Example description
gate-level
of a master-slaveD-type
Figure 5-9.
module
MSDFF
input D,
output
(D,
C,
C;
Q,
Qbar;
not
NT1 (NotD,
D) ,
NT2
C),
(NotC,
NT3 (NotY,
86
Y)
;
Q, Qbar) ;
flip-flop
shown
in
Circuit
A Parity
Figure 5-9 A nand ND1 (Dl,
master-slave
SECTION5.14
flip-flop.
D, C), , Ybar) , Y, D2) , NotD)
C,
ND2
(D2,
ND3
(Y,
ND4
(Ybar,
ND5
(Yl,
Dl,
Y, NotC),
ND6 (Y2,
NotC)
NotY,
(Q,
ND8
(Qbar,
,
Yl) ,
Qbar,
ND7
Q);
Y2,
endmodule
1.14
A Parity A described
Circuit for a
model
gate-level
9-bit parity generator,
shownin Figure5-10,is
next.
module
(D, Even,
Parity_9_Bit
input [0:8]
Odd;
Even,
output
xor #(5,
4)
XEO
(E0,
D[0]
, D[l])
XE1
(El,
D[2],
D[3])
, ,
XE2
(E2,
\302\243>[4] ,
D[5])
,
XE3 (E3,
D[6], D[7]),
XFO
E0,
(F0,
Odd);
D;
El) ,
87
Chapter 5
Gate-level
Modeling
i
DO
XODD
Figure 5-10 XF1
{Fl,
E2, E3),
XHO
{HO,
FO,
XEVEN
parity
generator.
,
Fl) D[8],
{Even,
A
HO) ;
not #2 XODD
Even);
{Odd,
endmodule
5.15
Exercises
1. Modelthe
circuit
bench to test out
shown circuit.
the
in Figure 5-11 using primitive Exercise the circuit with
gates. all
possible
Write
a test
values
of
inputs.
2. Model the circuitofa priority primitive
gates.
Output
Valid
Write a test bench and
88
is 0
verify
in Figure 5-12 using encoder shown it is a 1. when all inputs are 0, otherwise that the model behaves as a priority encoder.
Exercises Section5.15
B[0]\342\200\224-j
A[l]
B[l]
T
3
A[2]
B[2]
A[3]
B[3]3 5-11
Figure
Logic
for A
not
equals
B.
Data[3] Encode[0]
Data[2] -j-\302\243>-
Encode[l] D\302\253te[l]
Valid L\342\200\236 D\302\253fa[0]
Figure
5-12
Priority
encoder.
6
Chapter
Primitives
User-Defined
In
the
HDL. This
by Verilog specifying
user-defined
syntax for
6.1
gates
capability
the
exactly
same
is identical
instantiation
way as
a primitive
to
of
that
gate,
of
that
instantiation.
a gate
using a
is defined
UDP
UDP declarationwhich
has
the
following
syntax.
primitive
UDP_name
( OutputName
Output_declaration
List_of__input_declarations
90
provided
a UDP
Defining A
HDL
Verilog
(UDP).
primitives
UDP
an
the built-in primitive
chapter describesthe
is instantiated
A UDP
we looked at
chapter,
previous
[
Reg_declaration
[
Initial_statement
]
]
, List_of_inputs
);
is, the
Combinational
UDP
SECTION
6.2
table
tries
List_of_table_en
endtable
endprimitive UDP
definition
outside
of a
A appears
text
separate
does
module
and not depend on a module definition can also be definition. A UDP definition
can have
only
one
output
port must be the output port. x (z is not allowed).If a value
1 or
z appears
The following two kindsof behavior /. Combinational.
ii.
the
can
their
is an
0,
as an x.
UDP.
level-sensitive).
In a combinationalUDP, the table specifiesthe specified
is treated
in an
be described
The
have the value
UDP
Combinational
and combinations
or moreinputs.
the output can on the input, it form of a table.
and
(edge-triggered
Sequential
have one
and may
In addition,
The behavior of a UDPis describedin
.2
a
file.
A UDP first
thus in
output values.
corresponding
x for
the output. Hereis an
primitive
(Z, Hab, Bay,
MUX2xl
Any
of a
example
various
combination
2-to-l
input that
is not
multiplexer.
Sel);
Z;
output
Hab, Bay,
input
Sel;
table
//Hab 0
Bay
?
Sel
Z
1
0
1
?
1
1
?
0
0
0
?
1
0
1
0
0
X
0
1
1
X
1
Note:
This
endtable
endprimitive
91
Primitives
User-Defined
character representsa don't-carevalue, of the input ports must match order
The ?
or x.
The
that
first column
the
is,
Olx (there for
other
in
table
the
is no
there
multiplexer,
are others as well);in
this
to the first
table
entry
example of a 4-to-l 2-to-1 using multiplexerprimitives. Here is an
A
the
module is Sel.
In
input combination
defaults to an x (as
also
I
I
I
\\MUX2xl \\muazxi/
MUX2xl
6-1
Figure
A 4-to-l
MUX4xl (Z, C,
B,
A,
A,
B,
6-1, formed
CD
B I
in Figure
shown
multiplexer,
MUX2xl/ Sel[l] _\\^iuA/xi/
input
column
entries).
unspecified
module
in
input
third
one
for
the output
case,
of entries
and the
is Bay
either be a 0, 1 in the table,
it could
is, order
corresponds
is Hab), secondcolumn
port list (which the table for the
that the
Se/[1]
Sel[2]
multiplexer
built
using
UDPs.
D, Sel);
C,
D;
[2:1] Sel;
input
output Z;
parameter MUX2xl
tFALL)
#{tRISE,
{TL, A,
B, Sel[l])
(TP, C,
D,
(Z,
tFALL = 3 ;
- 2,
tRISE
Sel[l])
, ,
Sel[2]) ;
TL, TP,
endmodule In caseofa UDPinstantiation, in value
the
above 0 or
example.
a value
up
1, or the
value
be specifiedas shown can either get a output is no turn-off delay).
to two
This is because the x (there
delays can of
an UDP
SequentialUDP
\342\226\272.3
In a
sequential UDP,the
The
this
of
value
There are
and another the next
determine
to
Initializing the State of a
state
The
initial
i.3.2
models
sequential
UDP, one
the
of the (and
register
level-
models
that
behavior.
edge-sensitive value
current
using a 1-bit register. UDP.
register and
the
input
the output).
consequently
Register UDP can
sequential
be initialized
by
using
an initial
assignment statement. This is of the = 0,
reg_name
statement
initial
This
the
of sequential
that
value of
one procedural
has
statement that
output
UDP uses the
A sequential
of
kinds
different
two
is described
state
internal
is the
register
behavior
sensitive
1.3.1
6.3
UDP
Sequential
values
SECTION
1 or x;
within the UDP
appears
form:
definition.
Level-sensitive Sequential UDP Here
D-type output,
else
is
an
the
of a
example
latch. As
level-sensitive sequential UDP that is 0, data passes from the input
long as the
clock
remains
latched.
value
Latch
primitive
output
Clk,
(Q,
models
a
to the
D);
Q;
Q;
reg
Clk,
input
D;
table
//
Clk
Q(next)
D
Q (state)
:
?
:
1 ;
0
1 0
: ?
:
0 ;
1
p
: ?
:
\342\200\224 ;
0
endtable endprimitive
93
CHAPTER
Primitives
User-Defined
6
The - characterimpliesa stored
6.3.3
in register
the state
of
the
UDP
is
of a
modeled as a D-type edge-triggeredflip-flop is used to initialize the statement sequential UDP. An initial
an
is
that
Note
change\".
Sequential UDP
Edge-triggered Here
\"no
Q.
example
edge-triggered of the flip-flop. state
D_Edge_FF (Q, Clk, Data);
primitive Q;
output
Q;
reg
Data, Clk;
input
initial
Q
=
0;
table
Clk
//
p
O(next) 0
1
?
1
1 0
1
1
0
(01) (Ox) (Ox) //
Q (s tate)
Data
(01)
0
edge of
negative
Ignore
(?0)
0
// Ignore
?
:
?
data changeson : ? :
(? ?)
?
clock:
- ;
:
steady
clock:
\342\200\224 ;
endtable
endprimitive
(01) indicates a
The table entry
a transition 1, or x) to
from 0,
transition, the
0 to
and output
x, the entry (?0)
the entry defaults
Given the UDP definition just like a primitive
a module bit
94
register.
from
transition
indicates a
(??) indicates to an of gate
the
any
1, the entry (Ox) indicates from transition any value (0,
0 to
transition.
For
any unspecified
x. it can now be instantiated D_Edge_FF, in the following example
as shown
in
of a 4-
Sequential
module Reg4
SECTION6.3
Dout);
Din,
(Clk,
UDP
Clk;
input
input [0:3] Din; Dout;
[0:3]
output
D_Edge_FF
Din[0])
,
DLABO
(Dout[0]
Clk,
DLAB1
(Dout[l]
Clk, Dinll]),
Clk, Din[2]),
DLAB2 (Dout[2] DLAB3
Clk, Din[3]);
(Dout[3]
endmodule
5.3.4
Mixing
one
It is
possible to
table.
In such
the
an
primitive
D_
.Async
is,
the
D-type flip-flop
_FF (Q,
and edge-triggered
entries
in
are processed before the levellevel-sensitive entries override the
with
an
asynchronous
clear.
Clk, Clr, Data);
Q;
output
reg
of a
example
transitions
edge
that sensitive onesare processed, edge-triggered entries.
Hereis
entries
level-sensitive
mix
a case,
Behavior
Level-sensitive
and
Edge-triggered
Q;
input
Clr,
Data,
Clk;
table
// Clk
(01)
Clr 0 0 0 0
(01) (Ox)
(Ox)
Data
Q(next)
Q(state)
0
:
?
:
0
1
:
?
:
1
:
0
1:1 0:0
:
1
// Ignore negative edgeof clock: \342\200\242 ?... \342\200\242 ? . _ /\342\200\242 (?0) 0
(??)
1
?
:
?
:
0;
\342\226\240p
1
?
:
?
:
0;
endtable
endprimitive
95
CHAPTER
6.4
Primitives
User-Defined
6
Another
Example
Hereisa UDP
of
description
input vector
a 3-bit
has two or more1's.
primitive
A, B,
Z,
ty3
Majori
.A,
input
circuit. The output
majority
is
1 if
the
C) ;
C;
B,
Z;
output
table
//A 0 0
B
C
Z
0
?
0
?
0
0
0
0
p
0
1
1
?
1
1
?
1
1
1
1
1
\342\226\240p
endtable endprimitive
6.5
Summary For that
could
sake
of Table Entries listed
of completion, be used
in a
Symbol
the
are all the
below
table
Meaning
0
logic 0
1
logic
X
1
unknown
7
any of 0,
b
any of
-
(AB)
96
in
table entry.
no
1,or
x
0 or 1
change
value change
from A
to B
possible values
Exercises
SECTION6.6
Meaning
Symbol
*
sameas (??)
r
same
f
same as (10)
as (01)
P
any
of (01),
(Ox), (xl)
n
any
of (10),
(lx),(x0)
Exercises
1. How is a combinational
2.
A
3.
Can
4.
Write a
5.
data
input
is
0,
clock
negative
6. Modela
Verify
from
a sequential
UDP?
the
to initialize priority
a combinational
encoder
UDP?
circuit shown
in
Figure
using a test bench.
for a toggle-type flip-flop. In a toggle flip-flop, if not change. If data input is a 1, then on every output does that the triggering clock edge is a Assume toggles. output edge. Verify the model using a test bench.
description
clock edge,the
K, are J is 1
be used
the model
a UDP
different
more outputs.True or False?
UDP descriptionfor
Verify
Write
one or
statement
initial
an
5-12.
have
can
UDP
UDP
triggered
rising-edge
does 0, output and K is 0, then
the model
not
JK
change.
output
is
inputs, flip-flop as a UDP. If both If J is 0 and K is a 1, then output 1. If J and K are both 1, output
J and is 0.
If
toggles.
using a test bench.
\342\226\241
97
7
Chapter
Modeling
Dataflow
This
the continuous
describes
chapter
Continuousassignmentsmodel dataflow (the
assignments Combinationallogic
7.1
topic
behavior
assignment feature of Verilog HDL. in contrast,
behavior;
procedural
chapter) model sequentialbehavior. be best modeled using continuousassignments.
of next can
Continuous Assignment A assign
continuous a value
to a
assignment assigns a value to a net (it cannot be used to register). It has the following form (a simple form):
= RHS__expression;
LHS_target
assign
Forexample, wire
[3:0]
assign 98
Z
Z,
Preset,
= Preset
&
Clear; Clear;
// Net //
declaration.
Continuous
assignment.
Continuous
of
The target continuous
is Z and the right-hand assignment Note the presence of the keyword assign
continuous
the
& Clear\".
\"Preset
expressionis
7.1
side in the
assignment.
assignment execute? Whenever
a continuous
does
When
a change of value)
event is
on
occurs
an operand used and if the result
expression, the expression is evaluated then assigned to the left-hand side target.
In
above
the
event
(an side
right-hand
value is different,
it is
Z.
net
the
a continuous
in
can be
assignment
one of the
following.
net
Scalar
i.
an the
if either Preset or Clear change,the entire rightis evaluated. If this results in a change of value, then the
resultant value is assignedto The target
in
example,
side expression
hand
SECTION
Assignment
ii. Vector net
Hi. Constantbit-selectofa vector iv. Constant of a vector part-select of any
of the above
Here are more examplesof continuous
assignments.
Concatenation
v.
BusErr
assign
Z
last continuous
The in
assign
A, B,
C, D, and
evaluated
= -
= Parity (A
\\
(C
| D)
&
;
OP)
(E
\\
F)
;
assignment executes whenever there is a changeof value the entire right-hand side expressionis which case, to the target Z. result is then assigned
the
target
is a
concatenation
+ B
+ Cin;
of a scalar net
and
a
net.
wire
Cout,
wire
[3:0]
assign
Since of
&
&
E or F, in
In the next example,the vector
B)
| (One
A
a 5-bit
and 4 bits
Cin; Sum,
{Cout,
A,
B;
Sum) = A
B are 4-bits wide, the result of addition can producea maximum result. The left-hand sideis specifiedto be five bits (one bit for
and
of
Sum).
The assignment
therefore causes
the
rightmost
four
Cout
bits of
99
CHAPTER
Dataflow
7
Modeling
the right-hand side expressionresult to (the carry bit) to Cout.
The next example shows
how
be
can be
assignments
multiple
and the
to Sum
assigned
bit
fifth
in
written
one
statement.
continuous
assign
=
Mux
(S ==
0) ? A : == 1) ? B : == 2) ? C : == 3) ? D :
Mux = (S
This is a short
Mux
=
(S
Mux
=
(S
'bz;
the following
of writing
form
'bz,
'bz, 'bz, four separatecontinuous
assignments.
assign
assign assign assign
7.2
An
== 0) (S == 1) (S == 2) (S == 3)
Mux = (S
?A
Mux = Mux = Mux =
?B ?C
:
?D
:
:
'bz;
:
'bz; '
bz ;
'bz;
Example
Hereis an exampleofa 1-bitfull-adder module input
(A,
FA_Df A,
B,
the dataflow
using
style.
Sum, Cout) ;
Cin,
B,
described
Cin;
output
Sum, Cout;
assign
Sum
assign
Cout
= A A B A Cin;
= (A
&
Cin)
|
(B
&
Cin)
|
(A
&
B)
;
endmodule
In this
example, there are two
concurrent assignments
hand evaluated,
in
the
execute
continuous
assignments.
These
side expression. If A changes, side that is, the right-hand
assigned to the left-hand
are
assignments
These
that they are order independent. based on events that occur on operands
sense
side targets
both
the continuous
expressions are evaluated concurrently.
continuous
used
in
the
right-
assignments are and
the
results
are
Net
7.3
Net Declaration continuous
A
SECTION7.3
Assignment
Assignment can appear as part of a is called a net declarationassignment.
assignment
an assignment
Such
Declaration
itself.
declaration
net
is an
Here
example.
wire
Sum = 4 ' bO ;
[3:0]
wire Clear =
wire A net assignment. continuous
'bl; > B,
= A
A_GT_B
= B
B_GT_A
> A;
declaration assignmentdeclaresthe net along It is a convenient form of declaringa net and the example
See
assignment.
with then
a continuous writing a
below.
wire Clear;
assign Clear to the net
is equivalent
wire Clear
=
=
'bl;
declaration assignment: 'bl;
net declaration
Multiple
assignments on
multiple assignmentsare necessary,continuous
7.4
the
same
net
are not must
assignments
allowed. If be used.
Delays If no delay is specifiedin examples,
the
of the
assignment
target occurs
zero
with
continuous assignment
assign
as shown
#6
Ask
delay.
a continuous
assignment,
as
in
the
previous
right-hand side expressionto the left-hand A delay can be explicitlyspecifiedin a
in the = Quiet
side
following example. \\ \\
Late;
101
Chapter
Dataflow Modeling
7
the right-hand side and the leftThe delay specified,#6,is the delay between on Late at time 5, then occurs the hand side. For example, if a change of value is evaluated at time 5 and on the right-hand side of the assignment expression is Ask will be assigneda new value at time 11 (= 5 + 6). Thedelay concept in
illustrated
7-1.
Figure
Quiet
20
10
Late 15 6
*- 6
,
Ask
11
What
propagate to applied.
if the
happens
Here
the
is an
side? that
continuous assignment.
side changes before it had a case, the latest value
right-hand
left-hand
example
>6
Delay in a
7-1
Figure
-
In such shows
this
a chance change
to
is
behavior.
#4 Cab = Drm;
assign
7-2 shows the effect. The changes on the right-hand side that occur within the delay interval are filtered For example, out. the rising edge on Drm at 5 gets scheduled to appear on Cab at 9, however since Drm goes back to 0 at 8, the scheduled value on Cab is deleted.Similarly, the pulse on Drm 18 and 20 gets filtered out.This corresponds to the inertial delay occurring between that is, a value on the right-hand side must hold steadyfor at behavior; change least the delay period before it can propagate to the left-hand side; if the value on the right-hand side changes within the delay period, the former value does Figure
not
propagate
to the
output.
For each delay specification, up
/. Rise
delay
ii.
Fall
delay
Hi. Turn-off
102
delay
to
three
delay
values can
be specified.
7.4
SECTION
Delays
Drm
5
8
18
13
Cab
26
20
4
L
4..^
Lj 1
\342\226\240\"
30
17
is the syntax
Here
Here are three
delay
for specifyingthe
#( rise
assign
, fall ,
some examplesthat
#4
Ask
interval.
delays.
turn-off how
show
= Quiet
assign #(4, 8)
Ask
assign #(4, 8,
6)
assign Bus = first
three
delay
)
= RHS_expression
LHS_target
delays
;
when zero to
are interpreted
are specified.
values
assign
In the
Values changing faster than
7-2
Figure
^
'
\\ \\
= Quick;
-
Arb
the transition to x
&
:4]
MemAddr[7
DataBus;
;
delay are
II
One delay
value.
II
Two delay
values.
II
Three
//
No
delay
values.
delay
value.
delay, the fall delay and
the rise
statement,
assignment
Late;
turn-off
the
second is 8 and the transition to x and z the same, which is the minimum of 4 and 8, which is 4. In the third delay are the rise delay is 4, the fall delay is 8 and the turn-off assignment, delay is 6; the transition to x delay is 4 (the minimum of 4, 8 and 6). In the last statement, all and
delay
statement, the rise delay
is 4,
the
same,
which
is 4. In the
the fall delay
delaysare zero. What
a rise
does
goes
from a
hand
side
delay mean
non-zero
value
value
to
goes to z, then
for a vector net target? If the
a zero
vector, then fall delay
turn-off delay is used;elserise
right-hand
side
is used. If rightdelay
is used.
103
CHAPTER
7.5
Dataflow
7
Modeling
Net Delays A
can
delay
also be
specified
a net
in
such as
declaration,
in
the
following
driver
for
declaration.
wire
#5 Arb;
This delay indicatesthe and
the net Arb itself.
a change
between
delay
Consider
the
of value of a
continuous
following
assignment
Arb
to the
net Arb.
assign An
event
on Bod, If
evaluated.
the
= Bod
Arb
#2
say
result
at
&
Cap;
10, causes
time
is different,
it
is
the right-hand side expressionto be to Arb after 2 time units, that assigned
12. However since Arb has a net delay specified, the actual net Arb occurs at time 17 (= 10+ 2 + 5). The waveforms in assignment to the the different delays. 7-3 illustrates is,
at time
Figure
Cap
20
40
Bod 10
Arb
3
0
, 7 .
.r 7 >
47
17
Figure 7-3
Net
delay
with
assignment
delay.
The effect of a net delay is best described as shown in is used then and assignment delay any net delay is added
If a delay net delay but for
104
A,
2 time
is present an
assignment
units is the
Figure
7-4. First the
on.
declaration assignment, then the delay is not a delay. In the following net declarationassignment
in a net
assignment delay,not
the
net
delay.
SECTION7.6
Examples
wire
A =
#2
B
- C;
II
delay.
Assignment
Driver 1 Net
target B; A < B;
Exercises
1.
an
Give
of how
example
turn-off delay
is used in
a continuous
assignment.
2.
3.
When
there
effective
value
are two for
the target model
a dataflow
Write
or more assignmentsto the
10. Use only two
same
target,
how is the
determined?
for the parity generator
circuit shown in
Specify rise and
assignment statements.
fall
Figure
5-
delays
as
well.
4.
Using continuousassignmentstatements, priority
circuit
encoder
shown
in Figure
describe
the
behavior
5-12.
5. Given: triO
Qbus;
[4:0]
assign
Qbus =
assign Qbus What is the
106
-
Sbus; Pbus;
value on Qbus if
both
Pbus
and Sbus
are all z's.
of the
8
Chapter
Modeling
Behavioral
In and
chapters,
previous UDP
assignments.
This
chapter
which is, behavioral may
5.1
describes
of all the
examined gate-level modelingusing gate modeling using continuous in Verilog HDL, of modeling style of Verilog HDL, a model use the full power
dataflow the third To
modeling.
a mix
contain
we have and
instantiations,
three styles of modeling.
Procedural Constructs The
primary
following
two
mechanisms
for modeling
the behavior
i.
Initial statement
ii.
Always
statement
number of initial These statements execute concurrently with to respect order of these statements in a module is not important. A
module
of a design are the
statements.
may contain an arbitrary
or
always
each An
other,
execution
statements. that
is,
of an
the
ini-
107
CHAPTER
8
Behavioral
tial or an statements
8.1.1
Modeling
starts always statement execute concurrently
control flow.
a separate at
starting
All
initial
and
always
0.
time
Statement
Initial
only once. It
executes
statement
initial
An
which is at time
simulation
0. The syntax
begins its executionat initial
the
for
statement
start
of
is:
initial [
] procedural_statement
timing_control
is one of:
a procedural_statement
where
procedural_assignment (blockingor non-blocking) procedural_continuous_assignment
conditional_statement
case_statement
loop_statement
wai t__statement
disable_statement even t_ trigger
sequential_block
parallel_block
statement. Here
to becometrue. The statement
to execute
time 0. It
may
controls
complete
in the
present
Here is an
example
reg Yurt;
initial Yurt
108
most
the
timingjcontrolcan be a delay
event control,
or an
time,
system)
block (begin...end) is
The sequential certain
or
(user
task_enable
= 2;
that
of
execution
once. Note execution
an that
at
control,
for an
procedural statement. of an
used
procedural
for a event to occur or a condition initial statement causes the procedural an initial statement starts execution at a later time dependingon any timing
wait
is,
commonly
initial statement.
that
is, wait
Procedural
The initial
statement
contains
The
statement
executes
initial
value 2
no
with
control.
timing
the assigned this time
control.
a timing
with
assignment
which causes Yurt to be is another example of an initial statement,
0. Here
time
at
a procedural at time 0,
SECTION8.1
Constructs
reg Curt;
initial = 1;
Curt
#2
Curt gets assignedthe at time 0 but completes
Register execution
Here is an
initial
a sequential
with
starts
statement
block.
SIZE = 1024;
parameter
reg [7:0] RAM[0: reg
execution
2. The at time 2.
time
initial statement
of an
example
1 at
value
SIZE-l];
RibReg;
initial
begin:
SEQ_BLK_A
Index;
integer
= 0;
RibReg
for (Index = 0; Index]
RAM[
Index
<
SIZE;
= Index
Index
+ 1)
= 0;
end
The sequential block, demarcatedby such as
language label
is
example,
if
by a all
integer
programming
memory
Here is another
locations example
has been locally declared block containsoneprocedural
Index
the sequential
for-loop statement.
this example, the timing
a high-level
is the label for the sequential block; this local declarations are present in the block, for for Index were outside the initial no label statement,
required. An
Furthermore,
initializes
in
C. SEQ_BLK_A
required declaration
the
followed
as
contains
begin...end,
keywords
sequentially,
if no
not
would be block.
execute
that
statements
procedural
the
This initial
with value of an
statement,
upon
within
this
assignment
execution,
0.
initial statement
with
a sequential
block.
In
sequential blockcontainsproceduralassignmentswith
controls.
109
CHAPTER 8
Behavioral Modeling
//
Waveform
generation:
APPLY_DELAY = 5 ;
parameter
reg [0:7] Port_A;
initial
begin =
Port_A
'h20;
%APPLY_DELAY Port_A
= ' hF2 ;
#APPLY__DELAY
Port_A
=
#APPLY_D\302\243L.AY
Port_A
= 'hOA;
'h41;
end
Upon execution, Port_A
will
get
as shown
values
in
8-1.
Figure
Port_A
'hF2
'h20
Figure 8-1 initial
An generation
8.1.2
shown
as
10
5
0
A
'hOA
\"h41
waveform
using
produced
statement is mainly used in the examples above.
15
an
initial
and
initialization
for
statement.
waveform
Always Statement In
to the
contrast
the initial
like
Just repeatedly.
time 0. The syntax
for
initial statement, an
always statement
statement, an always an always
statement
statement
executes also
begins
execution
is:
always [
where
timing_control
procedural
] procedural_statement
^statement and
timing^controlare as describedin
previous section.
Here
110
is an
example of an
always
statement.
the
at
Procedural
always Clk =
- Clk;
II Will
This always
SECTION8.1
Constructs
loop indefinitely.
assignment. Since the always control the is no specified, repeatedly timing will loop indefinitely in zero time. Therefore, statement procedural assignment always statement must always have some sort of timing control. statement
one procedural
has
statement
and there
executes
HeFe is the
same
always #5 Clk =
II
this time
statement,
always
with
a delay
of period
Clk
on
10.
This always statement, upon execution,producesa waveform 10 time units. an
event
reg [3:0] wire
always statement
with
with
a sequential
a period
block
of
that is
control.
InstrReg;
[0:5]
reg
of an
example
controlled by an
control.
~ Clk;
Waveform
Hereis
an
Accum;
ExecuteCycle;
always
@(ExecuteCycle)
begin
case (InstrReg[0:1]) Store
(Accum,
InstrReg[2:5]);
2'bOO
:
2'bll
: Load (Accum, InstrReg[2 : Jump (InstrReg[2 :5]) ;
2'bOl
:5])
;
2'blO : ; endcase end
//
Store,
//
tasks
Statementswithin respect
to each
Load and
defined
block
a sequential
other. This
occurs on ExecuteCycle,that
user-defined
are
Jump
elsewhere.
always is,
execute sequentially with that whenever an event implies changes, execute the sequential
(begin...end)
statement
whenever
it
111
CHAPTER
8
Behavioral
Modeling
of the
block; execution withinthe
block
block
sequential
executing
implies
all statements
sequentially.
another example.The model is that D-type flip-flop with an asynchronous preset. Here is
DFF {Clk, D, Clk, D, Set;
module input
output
Set,
Q,
Qbar)
of
a negative
edge-triggered
;
Qbar;
Q,
Q, Qbar;
reg
always
wait (Set
==
1)
begin
1; #2 Qbar = #3 Q=
0;
wait (Set
==
0)
;
end
always
@(negedge
Clk)
begin
if (Set != 1)
begin #5
Q =
D;
#1 Qbar =
~Q;
end end endmodule This module has
two
statement
8.1.3
has
first
block.
a sequential with
always
statement
The second
a sequential
has
a
always
block.
In One Module module
A
statements.
starts
contain
may Each
execution
Here is an statements.
112
with
timing control
an edge-triggered
The
statements.
always
level-sensitive event control
statement
at time example
multiple always statements and multiple initial Each starts a separate control flow. statement
0. of a
module
with
one
initial
statement
and two always
module
SECTION
Constructs
Procedural
8.1
TestXorBehavior;
reg Sa, Sb, Zeus;
initial
begin = 0 ;
Sa
Sb = 0;
#5 Sb =
1;
= 1;
Sa
#5
#5 Sb =
0;
end always @
or
(Sa
Zeus =
Si?)
Sa
A
Sb;
always
@(Zeus)
$display
time
(\"At
Sa,
$time,
Sa = %d,
%t,
Sb = %d, Zeus =
%b\",
Zeus);
Sb,
endmodule
The orderof the three statements execute concurrently. The initial
in the
module is not
since
important
they
the
causes
executed
when
statement
all first
in the sequential block to execute, that is, Sa gets assigned 0; the after next statement executesimmediately line zero delay. The #5 in the third a \"wait for a 1 of the initial statement indicates 5 time units\". Thus Sb gets another 5 time units and finally a 0 after 5 time Sb gets units, Sa gets a 1 after block is after another 5 time units. After the last statement in the sequential the initial statement forever. executed, suspends statement
statement waits for
The first always Whenever
such and
executed
event
an
the
event
an
the statement
within
to occur the
always
on Sa or Sb. is
statement
always
statement again waits for an on the values assigned to Sa and based statement will be executed at times
the always
then
Sb. Noticethat statement,
occurs,
on Sa or
to occur
event Sb
in the
0,
5, 10
initial
and 15 time
units. Similarly
the
second
always
on Zeus. In
such a case, the
statement
waits
always
the when
again
statement
Sdisplay
system
for an event
waveforms produced on Sa, the module is simulated.
Sb and
executes whenever an event task is executed and then
to occur on Zeus.Figure Zeus.
Here
is the
output
occurs the
8-2
shows
produced
113
CHAPTER
8
Behavioral
Modeling
At time
5, Sa
= 0, Sb=
l,Zeus= 1
10,Sa=l.Sb=l.Zeus =
time
At
At time
= 0,
15, Sa=l,Sb
0
Zeus= 1
Sa Sb
Zeus
15
10
8-2
Figure
8.2
timing
control
may
be associated
control is of two forms:
8.2.1
i.
Delay
control.
ii.
Event
control.
Delay Control A
delay
control
is of the
form:
tidelay procedural_statement
as in
the
example:
#2
114
Sa,
Sb and
Zeus.
Controls
Timing A
Waveforms producedon
Tx =
Rx- 5;
with
a procedural
statement.
Timing
control specifiesthe
A delay
before executing the
reached;
it
is
to wait
equivalent
8.2
statement is \"wait
means
above example, the
two time units for 2 time units and
is executed
statement
procedural assignment
In the
statement.
the time the
executes. Basicallyit
time the statement
to the
encountered
initially
for delay\"
from
duration
time
SECTION
Controls
Timing
after then
statement
the
is
the
execute
assignment.
is another
Here
example.
initial
begin Wave
#3
=
#6 Wave = Wave
#7
'bOlll;
'bllOO;
= 'bOOOO;
end
The initial statement executesat time 0. First, wait for 3 time units, execute the first assignment, wait for another 6 time units, execute the second statement and then suspend for 7 more time units, execute the third statement, wait
indefinitely. A
delay
can also
control
be specified in
form:
the
#del ay ;
This statement is executed.
causesa wait
Here
for
is an example
the
specified
of such an
ON_DELAY = 3,
parameter
delay before the
next statement
usage.
= 5;
OFF_DELAY
always
begin #
II
ON_DELAY;
RefClk
wait
for
ON__DELAY.
for
OFF_DELAY.
= 0;
# OFF_DELAY; = 1;
II wait
RefClk
end
The delay not be
in
a delay
control
can be an arbitrary
restricted to a constant.Seethe
following
expression, that
is,
it need
examples.
115
BehavioralModeling
CHAPTER8
^Strobe
= Tx
Compare
Clock = ~
Clock;
of the
value
delay expression
An
explicit at
If the If
the
zero
delay
the
current
time does
simulation
value
delay
all causes a wait until time are simulation
other
an explicit
zero
that are waiting
to be
is called
events
completed, before it
the
resumes;
not advance.
of a
value is used as the
is the
same
the
two's
as zero
delay.
complement
delay.
Control
Event
With an event
two kinds of event i.
control, a
event
Edge-triggered
An
edge-triggered
@
as in the
event
control control
event
control
procedural_statement
example: @
(posedge
Curr^State
based
Control
Event
Edge-triggered
executes
statement
control.
ii. Level-sensitive event
116
it
delay expression is an x or a z, it evaluates to a negative value, expression
signed integer
8.2.2
is 0, then
// Explicitzerodelay.
#0; executed
Mask;
I 2)
#(PERIOD
If the delay.
A
Clock)
= Next_State;
is of the
form:
on events.
There are
Timing Controls An
control
event
statement
until
delays the execution
statement
a procedural
with
of the specified
occurrence
the
SECTION
event. In
the
above
of the if a
example,
statement executes, positive edge occurs on Clockthe assignment execution is suspendeduntil a positive edge occurs on Clock.
8.2
otherwise
Hereare somemoreexamples. @
Count
i?eset)
(negedge
= 0;
GCla
Zoo = Foo;
In the
first
the assignment
statement,
edge occurs on Reset.In the event occurs on Cla, that is, occur, assign Foo to Zoo.
@
event
exampleof
causes a wait
an usage
such
for
wait
also be
statement executes only when a negative an Foo is assigned to Zoo when an event to occur on Cla, when it does
statement,
of the form:
;
statement
This
can
control
Event
second
in
until
the
specified
statement
initial
an
clock.
event occurs. Here is an that determines the on-period
of a
time RiseEdge,
OnDelay,
initial
begin
// Wait @
until positive edge on = $time;
RiseEdge
// @
Wait
until
negative
edge on
clock occurs:
ClockA);
(negedge
OnDelay
occurs:
clock
ClockA);
(posedge
= $time
$display
(\"The
- RiseEdge;
on-period
of
clock
is %t.\",
end can
Events shown
in
the
also
following
be or'ed
to indicate
\"if
any
of the
OnDelay);
events occur\".
This is
examples.
117
CHAPTER
8
Behavioral
Modeling
@
Clear
(posedge
or negedge
Reset)
Q = 0; @
or
(Ctr1_A
Dbus = ' bz;
Note that
the
and
edge
following
or does not
keyword
posedge positive
Ctr1_B)
imply a logical-orsuchas in
and negedge are keywordsin Verilog a negative edge respectively. A negative
expression.
a of the
indicate
that
HDL
an
is one
edge
transitions:
x
1 ->
1 -> z
1 -> 0 x -> 0
z
A positive
->
0
edge is one of the following
0 ->
x
0 ->
z
->
1
x ->
1
0
transitions:
z -> 1
Level-sensitive
Control
Event
In a
level-sensitive becomes
a condition
wait
event control, true. This
the
is delayed
statement
procedural
event control is written
in
until
form:
the
(condition)
procedural_statement The procedural statement executes only until the condition becomes true. If the statement is reached,then the procedural The proceduralstatement is optional. Here
118
are some
examples.
if the
condition is
condition
statement
true,
is already
is executed
else
it waits
true when the
immediately.
Block
8.3
SECTION
Statement
(Sum > 22)
wait
= 0;
Sum
wait
{DataReady)
Data = Bus;
wait (Preset); first
the
In
assignment
DataReady execution is
5.3
simply delayeduntil
true.
becomes
Preset
Statement
Block
a provides like a single
statement
block
A
act
to
only when Sum becomes greater than 22 will the Sum occur. In the second example,Bus is assignedto Data only if the is true, that is, DataReady has the value 1. In the last example,
statement,
0 to
of
syntactically
Verilog HDL.
i.
mechanism to group two or more statements
statement. There are two
in
of blocks
kinds
These are: block
Sequential sequentially
the
in
ii. Parallel
are executed
Statements
(begin...end):
order.
given
block (fork.,join):Statements
in
this
execute
block
concurrently.
can be
block
A
labeled optionally. If so labeled,registerscan be declared for a block. Blocks can also be referenced; example,
can be
disabled using a disablestatement.
a
to
way
All local
registers are static,
Sequential
previous
syntax
of a
a
sequential
is relative
statement
with
is,
block
label,
However, there their
values
in addition,
is one word
remain
valid
sequence.
A
of
block
provides caution. the
throughout
Block
Once
statement.
continues
that
A
run.
Statements in each
registers.
identify
uniquely
simulation
entire
8.3.1
the
within
locally
the
next
sequential
block
execute
in
delay
value
in
to the simulation time of the executionof the block completes execution,execution
a sequential
statement
following the
sequential block.Hereis the
block.
119
CHAPTER
8
Behavioral
Modeling
begin [ : block_id
{ declarations
)
]
(s)
procedural_statement
end
Here is an
//
example of a sequentialblock.
Waveform
generation:
begin
= 1;
#2 Stream
= 0;
Stream
#5
#3 Stream = #2 Stream = -
Stream
#5
1;
= 0;
Stream
#4
1; 0;
end gets executed at 10 time units. The first executes after 2 time units, that is at 12 time units. After this statement execution has the next statement is executedat 17 time units (because of completed, so on. is executed at 20 time units and the delay). Then the next statement the waveform due to the Figure 8-3 shows produced sequential execution
Assume
behavior
the
that
of
this
block
sequential
example.
Stream
10 12 8-3
Figure
17
Delays are cumulative
Here is another exampleof a sequential begin
Pat @
= Mask
FF = end
120
&
| Mat; Clk)
(negedge Pat;
20
24
in
block.
26
a sequential
31
block.
SECTION8.3
Block Statement
In this example, the Of
executes.
statement
when a negative
first and then the
executes
statement
first
the assignment in on Clk. Here appears
the
course,
edge
second
statement
second occurs only
is another exampleof a sequential
block.
SEQ_BLK
begin:
[0:3]
reg
Sat
=
FF =
Mask A
Sat; & Data;
Sat;
end
blockhas a label SEQ_BLK declared. is register Upon execution,the first statement example, the sequential
In this
second
2
and
executed,
a local then the
it has
is executed.
statement
Block
Parallel A
block
parallel
concurrently.
has the
delimiters fork and join
begin and end). Statements
the delimiters
values
Delay
specified
in each
in
a parallel
statement
within
(a
sequential
block
has
block execute a parallel
block
are
in the the time the block starts its execution.When the last activity block has execution need not be the last statement), (this completed parallel executioncontinuesafter the block statement. Stated another way, all within the parallel block must complete executionbeforecontrol statements passes of a parallel block. out of the block. Here is the syntax relative
to
fork { declarations
: block__id
[
procedural_statement
} ]
(s)
join
Hereis an //
example.
Waveform
generation:
fork #2
Stream
= 1;
#7 Stream = 0 ;
#10 Stream = #14
Stream
1;
= 0;
121
CHAPTER
8
Behavioral
Modeling
#16 Stream =
1;
#21 Stream=
0;
join
parallel block gets executedat 10 time and all delay values are relative to concurrently If the
assignment
and so on.Figure
all statements
10.Forexample, the
time units, the fifth assignment executes shows the waveform produced.
at 20
executes
units,
8-4
execute third
at 26
time units,
Stream
Figure Here is an emphasize
8-4
Delays
that
example
uses
24 26
20
17
12
10
relative
are
always #4
SEQ_A
= 5;
Dry
fork:
begin:
= 7;
// PI
SEQ_B
//
P2
Box;
//
S6
= Exe;
//
S7
3;
Exe = #5
SI
// S2
PAR_A
Cun
#6
//
Jap
end #2 Dop = Gos
#4
#8 Pas
//
P3
= 2 ;
//
P4
= 4;
//
P5
join #8
Bax
= 1;
#2 Zoom = #6
end
122
$Stop;
52;
parallel block.
of sequentialand
a mix
their differences.
begin:
in a
// S3
//
S4
//
S5
31
parallel
blocks
to
SECTION8.4
Procedural Assignments
Gos
= 2
Dop = 3 Cun =
7
= 5
Dry
8 9
10
28
22
2D
Pas = 4
= Box
Exe
12
$stop
= l
Bax
Zoom
= 52
Jap = Exe
Figure 8-5 Delaysdue
The always the
within
the
always
a mix
of sequential
block
statement
executes at time 0,
the
within
block PAR_A parallel
and parallel blocks.
a sequential block SEQ_A and all (SI, S2, S3, S4, S5) execute sequentially.
sequential
and the parallel statements
contains
statement
to
begins
block (PI,
its
Dry gets assigned execution
5 at
at 4 time
statements Since
4 time units,
units.
All
P2, P3, P4, P5)execute
concurrently,
that
units. Thus Cun gets assigneda value at 10 time units, Dop gets at 12. The Gos gets assigned at 8, and Pas getsassigned 4 sequential block starts at time execution units, SEQJi causing statements S6 and at 9. Since all statements within the then S7 to execute. Jap gets its new value block PAR_A complete execution at time S3 is executed 12, statement parallel at 12 time to Box occurs at 20, then statement S4 executes, units, assignment the assignment to Zoom occurs at 22, then the next statement executes. Finally the task at 8-5 shows events that occur executes time 28. system $stop Figure statement. upon the execution of the always is, at
4 time
assignedat
6,
Procedural A
procedural
Assignments assignment
is an
assignment
always statement. It is usedto assign hand side of the assignment can be any
to
only
expression.
within
an
a register Here
initial
statement
or an
data type. The rightis an example.
123
Chapter 8
Behavioral
Modeling
reg
[1:4]
#5
Enable
is then
side expression A statements
& -
B;
is initially
executes
it. Here
around
appear
its value
and
The
encountered.
right-hand
is assigned to Enable.
sequentially
is an
statement
the assignment
control,
delay
evaluated
assignment
procedural that
A
after the statement
units
5 time
executes
-
=
B;
A,
register.Due to the
is a
Enable
Enable,
with
example
to other
respect
always statement.
of an
always @
C or
B or
or
(A
Temp2;
Tempi,
reg
Tempi = A
& B;
Temp2 = C & D; = Tempi Tempi Z = ~ Tempi;
end
/* It is Z
= -
the
second
within
block
on A, B,
the always
occurs.
There are two
value
of Tempi
the
124
illustrate
the
to
such
sequential
takes
Tempi
of Tempi and
third
computed
assignment in
the
third
Temp2
place first.
an
Then
computed
statement.
in
The last
statement.
kinds of proceduralassignments.
i.
Blocking.
ii.
Non-blocking.
before we discuss these, let us intra-statement delays.
But
as
to
The values
assignment are used in
assignmentusesthe
with
statement starts execution when
C or D.Theassignment
assignment
the previous
statements
nature of the statements in a
block*/ occurs
four
above
such as:
((A & B) | (C Sc D)) ; it has been used here
sequential
sequential
Temp2;
the
However,
event
\\
possibleto replace
one statement,
The
D)
AOI
begin:
first
briefly
discuss
the
notion
of
Procedural
Intra-statement A
is an
Delay on the
appearing
delay
intra-statement is
it
The important
statement
assignment
delay by which the right-hand the left-hand side target. Hereis an
about this delay is that the delay, then the wait
delays and
inter-statement
in an
expression
to note
before
to the left-hand
assigned
an
side
is
value
example.
'bl;
thing
evaluated
to
applied
= #5
Done
left of
It is the
delay.
delayed before
expression is
8.4
SECTION
Assignments
the
right-hand
occurs and
then
side is
value
the
side target. To understand the difference intra-statement delays,hereare someexamples
between that
this.
illustrate
Done -
// Intra-statement
#5 'bl;
delay
control.
the same as:
//is
begin =
Temp
'bl;
// Inter-statement delay control.
= Temp;
#5 Done
end Clk)
@(posedge
Q=
//is
the
D;
II Intra-statement
event control.
// Inter-statement
event control.
as:
same
begin
Temp = D; @
Clk)
(posedge
Q = Temp;
end In
form
to the
addition
control)
that
called
can
the repeat
delay.It is of the repeat
two forms of timing controls for intra-statement specified
event control that
can
be
(delay
control
and event
delay, there is yet another used to specify intra-statement
form:
( expression
)
@
)
( event_expression
form of control is usedto specify a delay of or more occurrences one events.Hereis an This
of
be
that is
based on the
number
example.
125
CHAPTER 8
Behavioral Modeling
Done = repeat (2) @
This statement when executedevaluates + BJieg, waits for two negative is, A_Reg the
assigns
event
repeat
A__Reg + B_Reg;
ClkA)
(negedge
value
the
of the
right-hand side, ClkA and then
edges
right-hand side to Done. Theequivalent is shown next. example
of the
value control
that
on clock
of this
form
begin + B_Reg;
= A__Reg
Temp @
{negedge
ClkA);
@
(negedge
ClkA);
= Temp;
Done
end
This form or with a count 8.4.2
Blocking A
is useful
delay
Procedural
executed.
in which
edges
operator is an
\"=\"
is a
=52;
before
assignment.A
any
statements
of the is
statement
executed
is another
Here
that
@
(A
or
B or
begin.reg
example.
Tl =
Cin)
CARRY__OUT
Tl,
A
T2,
end
T3;
& B;
T2 = B & Cin; T3 = A & Cin; = Tl Cout |
blocking follow
completely
always
126
the assignment
procedural assignment. For example,
blocking procedural
assignment
to certain
assignments
synchronizing
Assignment
assignment
RegA
executed
in
of edges.
procedural
blocking
is a
of
T2 | T3;
procedural it are
assignment
executed,
that
before the next
is,
statement
is the is
Procedural
The 77
assignment occursfirst,
executes,
72
assigned,
and
then the second
is computed,
is executed
statement
third
8.4
statement and T3 is
so on.
is another
Here
77
and then the
is assigned
SECTION
Assignments
intra-statement
example of a blockingprocedural
assignment
using
delays.
initial
begin
Clr=
#5
Clr=
#4 1;
0;
Clr = #10
0;
end executes at time 0 and Clr gets assigned 0 after 5 time statement the then second statement executes Clr to a units, get assigned 1 after causing 4 time units (9 time units from time 0), and then the third statement executes 10 time units (19 time units from time 0). The causing Clr to get a 0 after is on Clr in waveform shown 8-6. Figure produced first
The
Clr
19
Figure 8-6 Blockingprocedural assignmentswith is another
Here
intra-statement
delays.
example.
begin Art
= 0;
Art
= 1;
end In this case, assigned
0,
then
Art
gets
assigned
the next
delay.Thereforethe
the value
1. This
statement executes
assignment
of 0
to
Art
that
is
is because,first
causes
Art
Art
to get 1
gets
after zero
lost.
127
BehavioralModeling
CHAPTER8
8.4.3
Non-blocking Procedural Assignment In
a non-blocking
used.Here
are
begin Load 1)
(InLatch
&&
(Stop
begin
Result InLatch
= .Result = InLatch
end
if
226
<
(InLatch
Stop
= 1;
1)
*
InLatch;
- 1;
== 0) )
(Reset
== 1) )
SomeMore Examples Section11.6
//
Normalization:
for
1=1+1)
I
256)
begin
= Result
Result
Exponent
=
I 2; + 1;
Exponent
end
end
end
assign
Done
assign
FacOut
assign
ExpOut
=
Stop;
= .Result; =
Exponent;
endmodule
module
FAC_TB;
parameter
OUT_MAX = 8 ;
= 5,
IN_MAX
RESET_ST= 0,
parameter
START_ST
= 3
WAIT_RESULT_ST
=
1,
APPL_DATA_ST
= 2,
;
Start;
reg C2A:, Heset,
wire Done;
reg
:
[IN_MAX-1
wire
Data;
0] :
[OUT_MAX-l
Fac_Out,
0]
Exp_Out;
Next_State;
integer
parameter
MAX_APPLY
=20;
Num_Applied;
integer
initial
Num_Applied = 1;
always
begin: #6
CLK_P
= 1;
Clk
#4 Clk = 0
;
end
always @
Clk)
(negedge
II
Falling
edge transition.
case (Next_State) RESET_ST:
begin
Reset
= 1;
Start
= 0;
227
Chapter11
Verification
= APPL_DATA_ST;
i\\fext_State
end APPL_DATA_ST:
begin
Data = Num_Applied; = START_ST;
Next_State
end
START_ST :
begin
Start
=
1;
= WAIT_RESULT_ST;
Wext_State
end WAIT_RESULT_ST:
begin
Reset
= 0;
Start
= 0;
wait (Done== if
1)
;
==
(Num_Applied
* ('hOOOl \302\253Exp_Out)) result from factorial\",
Fac_Out $display
(\"Incorrect \"
Num_Applied
if
for
model
value
input
= Num_Applied
%d\",
Data);
+ 1;
< MAX_APPLY)
(Num_Applied
= APPL_DATA_ST;
Next_State
else
begin
$display (\"Testcompleted successfully\;
$
//
finish;
Terminate
simulation.
end
end
default : = START_ST;
JVext_State
endcase
// Apply FACTORIAL
to module Fl
under test: (Reset,
Start,
Fac_Out, Exp_Out) endmodule
228
Data, Done,
Clk, ;
Some More
A
Here is
its
a modelfor
test
detector.
a sequence
consecutive one's on
data
the
Figure 11-10 shows the
of clock.
edge
Section 11.6
Detector
Sequence
of three
Examples
line. state
The model checks for a sequence Data is checked on every falling Here is the model with diagram.
bench.
module
(Data, Clock, Detect3_ls);
Count3_ls
input Data, Clock; Detect3_ls;
output
Count;
integer
reg Detect3_ls;
initial
begin = 0;
Count
= 0;
Detect3_ls
end
always @
begin
Clock)
(negedge
(Data == 1)
if
+ 1;
= Count
Count
else
Count = 0;
if
(Count
>=
3)
= 1;
Detect3_ls
else
= 0;
Detect3_ls
end endmodule
module
Top;
reg
Data,
integer
Clock;
Out_File;
II Instantiate Count3_ls
module
Fl
under
test;
(Data, Clock, Detect);
initial
begin
229
Chapter
11
Verification
- 0;
Clock
forever Clock
#5
-
-Clock;
end
initial
begin
Data =
0;
= 1;
Data
#5
#40 Data = 0 Data
#10
= 1
#40 Data = 0 #20
//
$stop;
Stop simulation.
end
initial
begin
//
monitor
Save
Out_File
information
= $fopen
in
file.
(\"results.vectors\;
$fmonitor (Out_File, \"Clock
= %b,
Clock,
Data,
= %b. Detect);
Data
Detect
end
endmodule
Figure 11-10 A
230
sequence
detector.
=
%b\",
Section 11.7
Exercises
1.7
Exercises
1.
and
an on-period
with
a clock
Generate
an
and 10ns
of 3ns
off-period
respectively.
2.
HDL model that
a Verilog
Write
the
generates
shown
waveform
in
Figure
11-11.
a clock
Generate
4.
ClockV that
[Hint:
Using
Write
5.
a test
bench
that
module
a
starts
clock
positive
is set to
two clocks, ClockA while ClockB starts with
have
is 2ns.
ClockB is synchronizedwith
same
on-off
the
of ClockA
edges
of 40ns. the
but
such
ClockA
ClockB.
and a delay
period, on-period is Ins while
clocks
the
a
an
checks
detector
edge for a pattern 10010. If 1, else it is set to a 0.
generates
of 10ns
a delay
with
the clock Clk_D The phase-delayis 15ns. may not be appropriate].
from
phase-delayed
a sequencedetector.The
that tests the output
is found,
Write
waveform.
A
Gen_Clk_D (Figure 11-6). a continuous assignment statement
input data stream on every
a pattern
is
23
module
in
described
30ns
27
22
16
11-11
Figure 3.
17
15
10
Both
off-period
has
opposite
polarity.
6.
Describe a behavioral
model with described values
and
two
test the
within
monitored
7. Describean on
a
4-bit
ALU
model for
bench.
All
a 4-bit
input
that
operands.
the expectedresult from
and
itself. Dump the values to a text file.
test bench output
Write a
test bench that
expected
input
all the relational
performs a text
/ subtracter.
adder
values
values,
Exercise this values
are
expected
operations (=) reads
the
test patterns
and
file.
231
Chapter 11
Verification
8.
a module
Write
that
shift of an input vector. with a default value of as a parameter with a default value of a module which performs an arithmetic an arithmetic
performs
of the
size
Specify the
a parameter
as
input
specify the amount of shift a test bench that tests such on a 12-bit vector and shifts
9.
clock of an of
period
10.
the
edge reference
on an
input
clock].
that
a model
Write
shift
8 times.
times clock multiplier. The input is a reference The be should output synchronized with frequency. of the reference clock. [Hint:Determine the clock
unknown
positive
every
1. Write
for an N
model
a
Write
Also
32.
displays
the time
whenever
a 0
occurs
to 1 transition
clock.
clock pulses is Count_Flag 1.If count exceeds at the the Overflow MAXjCOUNT, output is set and counter stays to limit. The rising edge of Count_Flagcausesthe counter MAXjCOUNT reset to 0 and start Write a test bench to test this model. counting again.
11. Write
a model for
12.
a model
Write
of 3. The counter The
a 4-bit
13.
Gray
gets
a
toggle
is 1,
asynchronously
the
output
code
reset
counter.
when the
it to a size Default variable Resetis 0.
negative edge of a clock.Then instantiate test bench and test the model.
on every
code counter
behavioral
Write
the number of
during the period
for a parameterizedGray
transitions
counter
that counts
a counter
occur
that
(positive edges)
in
model toggles
a
for an asynchronous reset toggle flip-flop. between 0 and 1. If toggle is 0, output
in previous state. Then, using the specify block,specify a setup 2ns and a hold timeof 3ns.Verify the model a test bench. using
If stays
time
of
\342\226\241
232
12
Chapter
Examples
Modeling
This
Verilog
L2.1
chapter
A
of hardware
modeling examplesusing
Elements
Simple
Modeling
HDL
a number
provides
HDL.
basic
hardware
as a
net data
is a
element
type. Considera
describednext.
wire. 4-bit
A
and
wire
can
gate,
be modeled the behavior
in
Verilog
of which is
timescaleIns / Ins module
input
And4
B,
(A,
[3:0] B,
output
[3:0]
assign
#5
A
C) ;
C;
A; = B & C;
endmodule
233
Chapter
12 ModelingExamples
The delay represented
by
model
this
logic is specifiedto be 5ns.The
& (and)
the
for
is shown
in
12-1.
Figure
B[l] C[l]
B[2] C[2]
B[3] C[3]
C[0]
B[0]
gate delay
A[l]
A[2]
A[3]
Figure
12-1
A
(xor)
= 5ns
A[0]
A 4-bit
This exampleand the one following modeled as expressionsin continuous modeledas net data types. For example, represents
hardware
and gate.
show
that
Wires can
following description,
that connects
Boolean_Ex
input
E);
D;
output
wire
(D, G,
E;
G,
F;
assign F = - E;
assign
D
= F A G;
endmodule
D
Figure
A
the following behavior shown in Figure 12-3.
Consider representationas
12-2
combinational
circuit.
and its correspondinghardware
be
F
the output of the ~ (not) operator to the input 12-2 showsthe circuitrepresented the module. by operator. Figure
a wire
module
234
can be
equations
statements.
assignment
in the
Boolean
of
the
Simple
Modeling
Elements
SECTION 12.1
module Asynchronous;
wire
D;
C,
B,
A,
assign
C=A
reassign
A =
|
~ (B
&
C) ;
endmodule
\342\226\240-^Of^O^'
Figure 12-3
An
asynchronous
loop.
asynchronous loop. If the model were simulated with a time would never advance because 1, D = 0), simulation the two assignments. the simulator would always be iterating between The be time be two extracaution iteration would zero delays. Therefore, must that have exercised when values are assigned to nets using continuous assignment are used in expressions. zero delay and when these samenet values circuit has an
This
of values
set
certain
In certain
(B =
cases,
it
is
desirable
to have
such an asynchronous
loop. An
such an asynchronous represents loop is shown next; the statement waveform with a cycle of 20ns. Its hardware representationis shown an always statement needs an initial statement in Figure 12-4. Note that such that initializes the register to eithera 0 or a 1, else the register will be stuck of
example
a
periodic
the
value
at
x.
reg Ace;
initial Ace = 0; always
#10
Ace
= ~
Ace;
Elements of a vector net element
called
bit-select,
or a
or
a register
slice called
can be
accessed, as eithera single
part-select.Forexample,
235
CHAPTER
12
Examples
Modeling
Ace
Ace
Figure 12-4 reg
A
clock
generator.
A;
reg [0:4]
C;
reg [5:0] B,
D;
always
begin
D[4:0]
= B[5:l]
| C;
// D[4:0] andB[5:l]
are part-selects.
D[5]=A&B[5]; //D[5]
andB[5]
are
bit-selects.
end
The
first
D[4]
D[3]
implies:
assignment
procedural
= B[5] |
C[0];
=
C[l];
B[4]
I
and vectors can
Bit-selects, part-selects For example,
be concatenatedto form
larger
vectors.
wire
[7:0] C, CC;
wire
CX;
assign
C = {CX,
CC[6:0]};
It is also possibleto referto an element computable only at runtime. For example, Adf
= Plb
[K] ;
of a
vector whose
index value
is
Modeling SimpleElements whose output is Adf,
a decoder
implies
Plb is a vector;it
behavior
the
models
Shift operationscan be performed shift
Alternately,
K specifies
decoder. the
using
be modeled
can
operations
and
of the
the selection
the
address.
shift operators.
predefined
using
12.1
SECTION
concatenation
operator.
For example,
wire
[0:7]
assign
Z =
assign assign
Z;
A,
A[0]};
{A[l:7],
Z
=
[A[l],
Z
=
{A[l:7],
// // //
A[0:6]}; 1'bO};
A
left-rotate
A
right-rotate
A
left-shift
operation. operation. operation.
called part-select,can also be used in expressions. in which the consider a 32-bitinstruction register, Instr_Reg, denote the address, next 8 bits representthe opcode,and the of a vector,
Subfields
For example, 16
first
bits
8 bits
remaining
Given the following
declarations,
Memory [0:1023];
[31:0]
reg
the index.
represent
wire [31:0] Instr_Reg;
wire [15:0]
Address;
Index;
wire
[7:0]
wire
[0:9] Prog_Ctr;
Op_Code,
wire Read_Ctl; one
way
to
continuous
are
statements.
assignment
to specific
assigned
assign
Address
assign
Op_Code
InstrJReg is to use three of the
The part-selects
instruction
register
wires.
assign Instr_Reg =
assign
information from the
the subfield
read
;
[Prog_Ctr]
Memory
= Instr_Reg[31:16] =
Instr_Reg[
15:8]
Index = Instr_Reg[l
-. 0]
; ;
;
always
Read_Ctl)
@(posedge
Task_Call A assignment
tristate statement.
gate An
(Address, Op_Code,Index);
be modeled is: example
can
behaviorally using a
continuous
237
Chapter 12
Examples
Modeling
has
12.2
a high
impedance
then
the in
multiplies
The
Enable
is 0,
input C.
it with
first modeling are
statements
C,
(A, A;
input
[0:3]
C;
input
ClkB;
output [0:11] wire
buffered
Z;
SI; = Si
*
C;
assign
Z
assign
SI = ClkB ?
endmodule
multiplier.
style is the dataflow style to model the circuit.
[0:7]
input
A
in which
used
module Save_Mult_Df
238
When
Triln.
of the
examples
gives
Figure 12-5
assignment
of
TriOut
three different modeling styles dataflow, behavioral, and structural. Considerthe circuit language: of the input A into a register and 12-5, which saves the value Figure
section
This
shown
value
: l'bz;
Styles of Modeling
Different
provided by
gets the value.
1, TriOut
is
Enable
When
? Triln
= Enable
TriOut
wire
A
:
SI;
ClkB,
Z) ;
continuous
Different Styles of
does
This representation it.
describes modeled
program
module
statement
with
Save_Mult_Seq
been
is to
(A,
model it
C,
as
a sequential
block.
a sequential
Z) ;
ClkB,
A;
input
[0:7]
input
[0:3] C;
input ClkB; output [0:11]
Z;
Z;
[0:11]
reg
implicitly
is very clear. The registerhas
the circuit
describe
to
way
an always
using
but
12.2
control.
a clock
The second
structure,
any
imply
directly
its functionality
However,
using
not
SECTION
Modeling
always @
(A
C or
or
begin:
ClkB)
SEQ
so that a local register SI
The block is labeled can be declared.
II II
[0:7] si;
reg
if
(ClkB)
Si
= A;
= Si
Z
* C;
end
endmodule
This model alsodescribes the either
an if
but
behavior,
In this case,
or implicitly.
explicitly
does
not imply any
the register has
been
structure,
modeled
using
statement.
The third assuming
way
the Save_Mult
to describe
the existence of an
8-bit
register
module SaveJiult_Netlist [0:7]
A;
input
[0:3]
C;
input
ClkB;
input
output [0:11] Si,
(A,
circuit is to model it 8-bit multiplier.
as
a netlist
and an
C,
ClkB,
Z) ;
Z;
S3;
wire
[0:7]
wire
[0:15] S2;
239
Chapter12
Examples
Modeling
Rl
Reg8
Mult8 endmodule
Ml
the structure, but the behavior is and and Mult8 modulenames are arbitrary, have any behavior associated with them. is because
This
could
they
Of
describes
the Reg8
three different modeling styles, the behavioral the fastestto simulate.
these
is generally
12.3
.Z(Z));
C}) ,
.B({4'b0000,
(.A(S1),
This description explicitly unknown.
.Dout(Sl));
.Clk(ClkB),
(.Din(A),
of modeling
style
Modeling Delays a 3-input
Consider continuous
assignment,
assign statement
This
such
represents
the
on
appears
signal
nor
gate. Its
as shown
in
behavior can be modeledusing
the
#12 GatejOut = ~
(A
example.
following
\\
B
\\
C) ;
the nor gate with a delay an event on signal A, B, An event could be any GatejOut.
models time
from
of 12 or C value
delays
in
the
time
wereto be explicitly
delay
value
for example,
change,
0.
and the fall time such as: assignment,
rise
the
time units. This
until the result
-> z, x -> 0, or1 -> If
a
use
modeled,
x
two
assign #(12, 14) Zoom = ~ (A \\ B \\ C) ; and /* 12 is the rise delay, 14 is the fall delay = 12 is the transition to x 14) min(12, delay */ In
is the
case turn-off
of logic delay,
that can be assignedthe value z, a third delay can also be specified, such as:
assign #(12,14, is // Rise delay
10)
12,
= A
Zoom
fall
//is min(12,14,10),
and
240
> B
delay turn-off
? C : 'bz; is 14,
transition
delay
is
10.
value, which
to x delay
ModelingDelays delay values can
of the
Each
the following
as in
such
notation,
also be represented using
min.typ.max
example.
= A > assign #(9:10:11, 11:12:13,13:14:15)Zoom
A
Delays in the specifying primitive
delay
and
The output
rise
been
has
3)
in
For
Al
'bz;
and UDPs can be modeledby instances instantiation. Here is an example of a 5-input
In2,
ml,
(Ot,
In3,
In4, In5) ;
specified as 2 time units
has been
delay
and
the
output
at port boundaries can be specifiedusing a here is an example of a half-addermodule.
a module
example,
module
Hal\302\243_Adder
input
(A,
B, S,
specify
C) ;
B;
A,
output
fall
time units.
as 3
specified
Delays
block.
in the
C:
gate.
and #(2,
delay
gate
primitive
values
B ?
be an expression.
in general
could
value
delay
12.3
SECTION
S,
C;
S)
=
(1.2,
0.8);
=
(1.0,
0.6);
=
(1.2,
1.0);
=
(1.2,
0.6);
specify (A
=>
(B => S) (A
=>
C)
(B => C) endspecify
assign
S=A
assign
C = A
A
\\
B; B;
endmodule
Instead
of modeling
been modeledusing
the delays in a specify
the
block.
continuous
Is there
assignments,
a way
to
specify
the delays
have
the delays
is to use the SDF (Standard Format) Delay and the backannotation mechanism possiblyprovided simulator. by a Verilog If this information needsto be specifiedin the Verilog HDL model explicitly, external to
the
module?
One option
1. SeeBibliography.
241
Chapter
12
Modeling Examples
one approachis to createtwo module each
a different
with
module Half_Adder input
modules
dummy
set of
on top
of the Half_Adder
delays.
(A,
S, C) ;
B,
B;
A,
output
S, C;
assign
S=A
assign
C = A
A
1
B; B>
endmodule
module Ha_Opt
input
(A,
C) ;
B, S,
B;
A,
S, C;
output
specify (A
=>
=
S)
(B => S) = (A
=>
=
C)
(B => C) =
(1.2, 0.8)
(1.0, 0.6)
(1.2, 1.0)
(1.2,
0.6)
endspecify Hi
Hal\302\243_Adder
B, S,
(A,
C)
endmodule
module Ha_Pess (A,
B,
C)
S,
,\342\200\242
B;
A,
input
S, C;
output
specify (A
=>
S)
(B => S) {A => =>
(B
=
(0.6,
0.4)
=
(0.5,
0.3)
C) = (0.6, 0.5) C) = (0.6, 0.3)
endspecify Half_Adder
H2
(A,
B, S,
C)
endmodule With
and
these
depending
the module Half_Adder on which delay mode that you
modules,
appropriatetop-levelmoduleHajOpt orHa_Pess. 242
is independentof would
like to
any
delays,
use, simulate the
SECTION 12.3
Delays
Modeling
TVansport Delays
inertial with
assignment
and gate-level
assignments
using delay. Transport delay can be modeled an intra-statement delay. Here is an example.
module
primitives
a non-blocking
(WaveA, DelayedWave);
Transport
parameter
= 500;
TRANSVORTJDELAY
WaveA;
input
output
reg
continuous
in
specified
Delays
model
DelayedWave;
DelayedWave;
always
^^^ 0
Input
^^
STO^^
^>^ 0 STl ^^
STl
A
(Entries
in table
next state and
are output
Z)
>^^^ 0
Present state
Figure 12-16 State transition module
Clock,
(A,
Mealy_FSM
table
for a
Mealy machine.
Z) ;
A, Clock;
input
output Z;
reg Z;
parameter reg
[1:2]
STO
=
0,
P_State,
STl
= 1,
ST2 = 2, ST3 =
3 ;
N_State;
always
@(negedge Clock) P_State
II
Synchronous
part.
= N_State;
259
CHAPTER 12
Modeling Examples
always
@(P_Stateor case
A)
COMB_PART
begin:
(P_State)
STO:
if
(A)
begin
Z =
1;
N_State
= ST3;
end
else Z
= 0;
:
STi
if
(A)
begin
Z =
0;
N_State
= STO;
end
else =
Z
1;
:
ST2
if
(~A)
Z =
0;
else
begin Z
=
1;
ALState
= STI;
end
ST3 :
begin Z
if
=
0;
(-A)
N_State
= ST2;
else
N_State
=
STI;
end
endcase
end endmodule
260
// Sequential
block
COMB_PART
Blackjack Program
A Simplified
type of finite state machine,it event list for the combinational part
In this in the
may directly
does
block
sequential
clock. Such a condition
of the
machine since outputs
state changesoccursynchronously
A Simplified
to put the input signals since the outputs
important
independent
inputs
Moore finite state
in a
occur
not
states and
2.11
depend on the
is
on
12.11
SECTION
only
depend
on
clock.
Program
Blackjack
machine description of a simplifiedblackjack is played with a deck of cards. Cards 2 to 10 program have values equal to their face value, and an ace has a value of either 1 or 11. The object of the game is to accept a number of random cardssuch that the total score of values of all cards) is as closeas possible to 21 without (sum section
This
a state
presents
program.Theblackjack
21.
exceeding
value of the a new
card is
a new
When
card.
card. If a
Lost is set to true indicating
that
the
Clock.
The
input
inserted, Card__Rdy
sequenceof cards is acceptedsuch it has
that
indicating
and
true
when the
indicates
RequestjCard
is
program is ready the
that
lost; otherwise
has the
CardJValue
Won
total is
set
to
accept
exceeds to true
21,
won. The state sequencing is controlledby and outputs of the blackjack program are shown in Figure
game
has been
12-17.
Card_Rdy
^
>
Request_Card
>
Lost
Card_Value
Blackjack Clock
> Won
Figure 12-17 The behavior of the
view
External
of blackjack
program.
following module least 17. The first ace as a 11 unless the score exceeds counted 21, in which case 10 is subtracted that the value of 1 is used for an ace. Three registers are used to store the values of the program: Total to hold the sum, Current_Card_Value to hold declaration.The
program
program
accepts
cards
is described until
its
in the
score
is at
is so
the
261
CHAPTER
12
Modeling
Examples
card read (which
value of the remember
blackjack
is stored
program
module
1 through
be
could
counted as a
ace was
an
whether
in
of
to
Ace__As__ll
a 1.
The state
BJ_State.
register
(Card__Rdy, Card__Value,
Blackjack
Reguest_Card,
Won,
Clock);
Lost,
Clock;
Card__Rdy,
input
10), and
11 instead
input [0:3] Card_Value;
output Reguest_Card,Lost, Reguest_Card,
reg
INITIAL_ST-
parameter
0
GETCARD_ST
,
= 1,
ADD_ST = 3 , CHECK_ST= BACKUP_ST = 6, LOSE_ST = 7 ;
= 2 ,
REMCARD_ST
=
WIN_ST
Won;
Won;
Lost,
5,
reg
[0:2]
BJ_State;
reg
[0:3]
Current__Card_Value;
4,
reg [0:4] Total;
reg
Ace_As__ll;
always
Clock)
@(negedge
case
(BJ_State)
INITIAL_ST :
begin
Total
=
0;
= 0;
Ace_As_ll =
Won
0;
= 0;
Lost
=
BJ_State
GETCARD_ST;
end
GETCARD_ST
:
begin
RequestJCard
if
- 1;
(Card_i?dy)
begin
= Card^alue;
Current__Card__Value
BJ_State end
end
262
=
REMCARD_ST;
//
Else
stay in
GETCARD__ST
state.
of
the
A
if
Wait
//
:
REMCARD_ST
Blackjack
Simplified
Program
for card
SECTION 12.11
to be removed.
(Card_Rdy)
= 0;
Reguest__Card
else
= ADD_ST;
BJ_State :
ADD_ST
begin
if
[~Ace_As_ll
&&
Current__Card__Value)
begin
Current_Card_Value
= 11;
Ace__As_ll = 1;
end
Total
=
= CHECK_ST;
end :
CHECK__ST
if
+ Current_Card_Value;
Total
BJ_State
< 17)
(Total
BJ_State = GETCARD_ST; else
begin
if
(Total
< 22)
BJ_State
=
WIN_ST;
else
= BACKUP_ST;
BJ_State
end :
BACKUP_ST
if
(Ace_As_22)
begin
Total = Total =
Ace_As_22
- 10;
0;
= CHECK_ST;
BJ_State
end
else
BJ_State LOSE_ST
=
LOSE_ST;
:
begin
Lost
= 1;
i?eguest_Card =
1;
263
Chapter
12
Modeling Examples
if
(Card_Rdy)
= INITIAL__ST;
BJ_State
stay in this
II Else
state.
end
:
WIN_ST
begin
Won = 1;
= 1;
Reguest_Card
if
(Card_Rdy)
= INITIAL_ST;
BJ_State
stay in this
II Else
state.
end
endcase
endmodule
12.12
Blackjack
//
Exercises
1.
model for a mango juice drink machine. The costs 15 cents. Only nickels and machine a can of mango juice that dispenses dimesare accepted.Any change must be returned. Test the model using a Write
HDL
a Verilog
test bench.
2. 3.
a model
preset
and clear.
a model for a 4-bit shift register with a clock and parallel-outdata. Test the model
Write
4. Describea D-type module,write a 5.
the behavior of a
that describes
Write
Write
a
test
using
flip-flop
model
bench
for a
behavioral
with
flip-flop
serial-in
using
data,
a test
constructs.
synchronous
parallel-in
data,
bench. Then using this
8-bit register.
that tests
the blackjack model describedin
Section
12.11.
6.
Using the shift operator,
test bench.The number
264
describe a decodermoduleand then test to the decoder is specifiedas: inputs
of
it with
a
Exercises '
NUM_INPUTS 4
define
7.
the
out
8-bit parallel to
for a
a model
Write
operator to figure
Use the shift of decoder]
[ Hint: outputs
SECTION
12.12
number
of
serialconverter.The input
is
a 8-bit
bits out, one bit at a time, starting from the most after only rising edge of a clock.Readthe next input been sent vector have out. previous input
vector. Send the
bits of
8.
all the
on the
significant bit
the
8-bit serial to parallelconverterthat does the opposite Samplethe input stream after a small delay from the the models positive edge of clock to account for transmissiondelay. Connect written in this exercise and the one in Exercise 7 using a top level module test it out using a test bench. and for a
a model
Write
of Exercise 7.
9.
the counterholds
its
when
value,
and starts counting again.Write
10. Write
for a
a model
of words in
queue
If the hold is a 1, with a hold control. is reset to 0 hold goes to 0, the counter test bench to test this model.
N-bit counter
for a
a model
Write
a
generic queue,
in M.
InputData
sizeof word is the word
in that
queue gets
is N
and number
written
into
the
to the queue when input AddWord is a 1. A word queue; the word is added the word is read from that is read from the queue is stored in OutputData; Full are set is a 1. Flags Empty and the queue when input ReadWord All transactions occur at the falling edge of clock ClockA. appropriately. a test bench to test out the model. Write
11. Write
a model
output clock synchronized the
for
is 2*N to
the
divider. The period of clock clock. The output input a test bench of the clock. Write input edge clock
a parameterizable
times rising
that
of
the
the
is
and test
model.
a
265
A
Appendix
Reference
Syntax
This
the
presents
appendix
complete
of
syntax
the
Verilog
HDL
language.
A.l
Keywords
Following
lowercasenames
are
of the
Verilog
HDL
language.
and
assign
begin
buf
bufifO
bufifl
case
casex
casez
cmos
deassign
default
defparam
disable
here
Note
that
only
keywords.
always
1. Reprinted
266
are the keywords
from IEEE
Std 1364-1995,Copyright
\302\251 1995,
IEEE,
All rights reserved.
Keywords
A. 1
SECTION
end
endcase
endmodule
endprimitive
endspecify
endtable
endtask
for
force
forever
fork
function
highzO
highzl
if
ifnone
initial
inout
input
macromodule
medium
module
nand
negedge
nmos
nor
not
notifO
notifl
or
output
parameter
pmos pullup
posedge
primitive
pullO
realtime
reg
release
rpmos
rtran
rtranifO
specparam
strongO
time triO
tran
tranifO
tril
triand
weakO
weakl
while
edge
endfunction
else
event
integer
join
large
pulll
rcmos
repeat rtranifl
real rnmos
pulldown
scalared
small
specify
strongl
supplyO
supply 1
table
task
tranifl
tri
trior
trireg
vectored wait
wand
wire
wor
xnor
267
APPENDIX
A.2
A
Reference
Syntax
Conventions
Syntax
The following described
using
i.
The syntax rules are organized left-hand nonterminal name.
ii.
Reserved
words, operators
the syntax appear in A name
Hi.
italics
in
semantic
The vertical
v.
Square
vi.
Curly
an
alphabetical
and punctuation
marks
in
order by their that
are part
to a
nonterminal name
with
associated
that
([...]) denoteoptional an item non-bold, ({...}) identify
braces,
representsthe
non-bold,
brackets,
Square characters(such
as
characters
that
The
viii.
ix. Theterminal
A.3
The
,;) appearing are part of the in
names
bold
that is
used
( [ ...
in this
always
statement
binary_base ::= \342\200\242bl'B
x
I
::= X I z I Z I 0 I 1
::=
binary_number
[ size ] binary_base binary_operator
+
268
I
-1
{
binary_digit
_ I binary_digit}
::= *
I
==
I
& | | |
I
/1 %
| \302\273= | ===
| \302\273== | &&
a | a_ |
| |
| |<
_a | \302\273| \302\253
], (
... ), {...})
grammar appear in
::=
binary_digit
braces and other indicate
\"source_text\".
Syntax always_construct
repeated
syntax.
name is
nonterminal
starting
and curly
parentheses,
items.
items.
zero or moretimes.
vii.
of
name.
nonterminal
bar symbol,non-bold,(I) separatesalternative
brackets,
is
boldface.
prefixed
meaning
iv.
the syntax, which
used in describing Form (BNF).
are
conventions
Backus-Naur
the
| | >=
upper
case.
The
SECTIONA.3
Syntax
blockJtem_declaration::= parameter_declaration I
reg_declaration
I
integer_declaration
I
real_declaration
I
time_declaration
I
realtime_declaration
I
event_declaration
::=
blocking_assignment
regjvalue = [ delay_or_event_control ::= casejtem
] expression
}:statement_or_null expression {, expression I
[: ] statement_or_null
default
::=
case_statement
case (expression) casejtem{casejtem} endcase
I
casez
I
casex
(expression
) casejtem
(expression
) casejtem
{ casejtem { casejtem
} endcase } endcase
charge_strength::=
(small)
I
(medium)
I
(large)
::=
cmos_switch_instance
[ name_of_gateJnstance
] (outputjerminal,
inputJerminal,
ncontrolJerminal,pcontrolJerminal) ::=
cmos_switchtype
cmos
I
rcmos
::=
combinationaLbody
table combinationaLentry
endtable
{combinational_entry}
::=
combinationaLentry
output_symbol
leveljnputjist:
;
comment ::= short_comment I
long_comment
commentjext
::=
{ANY_ASCII_CHARACTER}
concatenation ::=
{expression{, expression conditional_statement if
(expression
}}
::= ) statement_or_null
[ else
statement_or_null
]
269
APPENDIX
A
Syntax Reference
constant_expression::= constant_primary I
unary_operator
I
constant_expression
I
constant_expression
I
string
constant_primary
constant_expression binary_operator : constant_expression ? constant_expression ::=
constant_mintypmax_expression
constant_expression I
: constant_expression
constant_expression
: constant_expression
::=
constant_primary number I
paramete/Jdentifier
I
consfanLconcatenation
I
consfanf_multiple_concatenation
::=
continuous_assign
assign
[ drive_strength
] [
delay3 ]
list_of_net_assignments;
::=
controlled_timing_check_event
specify_terminal_descriptor
timing_check_event_control
]
[ &&&timing_check_condition
::=
current_state
leveLsymbol data_source_expression::= expression
::=
decimal_base \342\200\242dl'D
::=
decimal_digit
011I2I3I4I5I6I7I8I9
decimaLnumber
::=
[ sign] unsigned_number I
[
size
] decimal_base
unsigned_number
delay2 ::=
# delay_value
I
# (delay_value
[, delay_value
])
[, delay_value
[, delay_value ] ])
delay3::=
# delay_value
I
# (delay_value
delay_control
I
::=
# delay_value # ( mintypmax_expression
delay_or_event_control ::= delay_control
270
)
The
I
event_control
I
repeat
Syntax
SECTIONA.3
) event_control
(expression
delay_value ::= unsigned_number I
parameter_identifier
I
constant_mintypmax_expression
::=
description
module_declaration I
udp_declaration
::=
disable_statement
disable fas/cjdentifier ; disable
I
;
Woc/cjdentifier
drive_strength ::=
(strengthO,strengthl I
(strengthl,
I
(strengthO,
I
(strengthl
I
(highzl
I
(highzO,
)
strengthO) highzl
)
,highzO) , strengthO
)
strengthl
)
::=
edge_control_specifier
edge [ edge_descriptor[, edge_descriptor
]
]
::=
edge_descriptor
01 I
10
I
Ox
I
x1
I
1x
I
xO
::=
edge_identifier
posedge
I
negedge
::=
edge_indicator
(level_symbol level_symbol) I
edge_symbol
::=
edge_inputjist
{level_symbol} edge_indicator {level_symbol} ::=
edge_sensitive_path_declaration
parallel_edge_sensitive_path_description I
= path_delay_value = path_delay_value
full_edge_sensitive_path_description
edge_symbol ::=
rl
R
If
I
Flpl
PI
n INI*
enable_gate_instance ::= [
name_of_gate_instance
] (outpuMerminal,
inpuMerminal,
enable_terminal)
271
APPENDIX
A
Reference
Syntax
::=
enable_gate_type I
bufifO
bufifl
I
notifO
I
notifl
::=
enable_terminal
sca/ar_expression
escaped_identifier ::= \\ {
::=
event_control @ I
} white_space
ANY_ASCII_CHARACTER_EXCEPT_WHITE_SPACE
evenMdentifier
@ (event_expression
event
)
::=
event_declaration
evenMdentifier
{,
\342\200\242
evenMdentifier}
::=
event_expression
expression I
evenMdentifier
I
posedge
expression
I
negedge
expression
I
event_expression
or event_expression
event_trigger ::=
-> evenMdentifier
;
::=
expression
primary I
unary_operator
I
expression
I
expression
I
string
primary binary_operator ? expression
expression
: expression ::=
full_edge_sensitive_path_description
([ edge_identifier ] list_of_path_inputs [
*> list_of_path_outputs
)
]: data_source_expression
polarity_operator ::=
full_path_description
(list_of_path_inputs
[
] *>
polarity_operator
list_of_path_outputs)
function_call ::= (expression
fcyncf/'onjdentifier I
[
] funcf/onjdentifier
range_or_type
function_item_declaration
statement
endfunction function_item_declaration
block_item_declaration I
272
{, expression
::=
function_declaration
function
})
{, expression [ (expression
name_of_system_function
input_declaration
::=
;
{function_item_declaration}
}) ]
The Syntax
Section A.3
gatejnstantiation ::= [
n_input_gatetype
{, I
};
]
[ drive_strength
enable_gatetype
] n_output_gate_instance
delay2
] enable_gate_instance
delay3
[
};
{, enable_gate_instance
] mos_switch_instance
[ delay3
mos_switchtype
[
};
{, n_output_gate_instance
I
]
[ drive_strength
n_output_gatetype
I
] n_input_gate_instance
] [ delay2
drive_strength
n_input_gate_instance
{, mos_switch_instance }; I
pass_switchtype
I
pass_en_switchtype
I
cmos_switchtype
I
pullup
I
pulldown
{, pass_switch_instance ] pass_en_switch_instance
pass_switch_instance [ delay3
{, pass_en_switch_instance
};
};
] cmos_switch_instance
[ delay3
{, cmos_switch_instance } ; [ pullup_strength
{/ pull_gate_instance
{, pulLgate_instance } ;
] pull_gate_instance
] pull_gate_instance
[ pulldown_strength
};
hex_base ::= \342\200\242hl'H
::=
hex_digit
xlXIzIZ I
011I2I3I4I5I6I71819
I
alblcld
lelfIAIB
hex_number [
El
ICI DI
F
::=
size
hex_digit { _
] hex_base
I
hex_digit}
:=
identifier
IDENTIFIER [{.IDENTIFIER}] /* The period may not be followed
by a
or preceded
space */
::=
IDENTIFIER
simple_identifier I
escaped_identifier
::=
init_val
1'b0 11'b1
11'bx 11'bX11'BO
I
1'B1
11'Bx
11'BX 11
::=
initial_construct initial
statement
::=
inout_declaration
inout [ range ] Iist_of_port_identiffers; ::=
inout_terminal
term/na/jdentifier I
[ constant_expression
term/na/Jdentifier ::=
input_declaration
input
[
range
] list_of_port_identifiers;
]
I
0
APPENDIX A
Syntax Reference
input
::=
^identifier
/npuf_po/t_identifier I
/nouLportJdentifier
::=
inputjerminal
sca/ar_expression
integer_declaration ::=
integerlist_of_register_identifiers
;
::=
leveUnPutJist
level_symbol {level_symbol} ::=
level_symbol
IxI
011
X
I
?IbIB
::=
limit_value
constant_mintypmax_expression
::= list_of_module_connections {, ordered_port_connection
ordered_port_connection I
{, named_port_connection
named_port_connection
}
}
::=
list_of_net_assignments
net_assignment {, net_assignment} ::=
list_of_net_decl_assignments
{, net_decl_assignment}
net_decl_assignment ::=
list_of_net_identifiers
nefjdentifier
{, neHdentifier}
list_of_param_assignments ::= {, param_assignment}
param_assignment
list_of_path_delay_expressions
::=
f_path_delay_expression I I
fnse_path_delay_expression, fnse_path_delay_expression
tfa//_path_delay_expression , tfa//_path_delay_expression,
tz_path_delay_expression I
f07_path_delay_expression,
fOz_path_delay_expression, f I
7z_path_delay_expression,
f07_path_delay_expression,
fOz_path_delay_expression, f
7z_path_delay_expression,
fOx_path_delay_expression, f
7x_path_delay_expression,
fxz_path_delay_expression, list_of_path_inputs
tzO_path_delay_expression f 70_path_delay_expression,
tz7_path_delay_expression, tzO_path_delay_expression,
fx7_path_delay_expression, fxO_path_delay_expression,
tzx_path_delay_expression {, specify_input_terminal_descriptor}
::=
specify_output_terminal_descriptor
274
tz 7_path_delay_expression,
::=
specify_input_terminal_descriptor list_of_path_outputs
f 70_path_delay_expression,
{, specify_output_terminal_descriptor}
The Syntax
SECTION
::=
list_of_port_identifiers
{, porHdentifier}
porHdentifer ::=
list_of_ports
(port
{, port}) ::=
list_of_real_identifiers
{, rea/Jdentifier}
rea/_identifier
::=
list_of_register_identifiers
{, register_name
register_name
}
list_of_specparam_assignments: := {, specparam_assignment}
specparam_assignment
::=
long_comment
I* comment
*/
Jext
::=
loop_statement
forever statement I
repeat
I
while
I
for
) statement
(expression ( expression
) statement reg_assignment)
expression;
(reg_assignment;
statement
::-
mintypmax_expression
expression I
expression
: expression
: expression
module_declaration
::=
module_keyword
modu/ejdentifier
[ list_of_ports
];
{modulejtem}
endmodule
modulejnstance ::= ([
name_of_jnstance
module_instantiation
list_of_module_connections
::=
modu/ejdentifier[
parameter_value_assignment
};
{, modulejnstance
moduleJtem ::= moduleJtem_declaration I
parameter_override
I
continuous_assign
I
gatejnstantiation
I
udpjnstantiation
I
modulejnstantiation
I
specifyjDlock
I
initial_construct
I
always_construct
moduleJtem_declaration
::=
parameter_declaration I
input_declaration
I
output_declaration
]) ] modulejnstance
A.3
Appendix
A
Syntax Reference
I
inout_declaration
I
net_declaration
I
reg_declaration
I
integer_declaration
I
real_declaration
I
time_declaration
I
realtime_declaration
I
event_declaration
I
task_declaration
I
function_declaration
::=
module_keyword
module
I
macromodule
::=
mos_switch_instance
] (outpuMerminal,
[ name_of_gate_instance
inpuMerminal,
enablejerminal)
::=
mos_switchtype
nmos
I
I
pmos
rnmos
I
rpmos
::=
multiple_concatenation
{, expression}}}
{expression {expression ::=
n_input_gate_instance
] (outpuMerminal,
[ name_of_gate_instance
inpuMerminal
{, inpuMerminal}) ::=
n_input_gatetype
and
I
nand
I
or
I
nor
I
xor
I
xnor
::=
n_output_gate_instance
] (outpuMerminal
[ name_of_gate_instance inpuMerminal)
n_output_gatetype buf I not
::=
::=
name_of_gateJnstance
[
\302\243fate_/'nstencejdentifier
name_ofJnstance
]
range
:.=
[ range ]
modu/e_/nsfanceJdentifier
name_of_systemJunction::= identifier
::=
name_of_udpJnstance
udp_/'nstencejdentifier
[ range ]
named_port_connection ::=
. porHdentifier
ncontroljerminal
([
expression
::=
sca/ar_expression
276
])
{, outputjerminal},
The
Section
A.3
] list_of_net_identifiers
;
Syntax
::=
net_assignment =
net_lvalue
expression
::= neMdentifier = expression
net_decl_assignment
::=
net_declaration
neMype
vectored
[
[ vectored
I
trireg
I
net_type
I I
scalared
]
[
delay3
]
] [ charge_strength
] [ delay3
range
[
]
;
list_of_net_identifiers [ vectored
] [ range
scalared
I
scalared
] [ drive_strength
]
[
] [ delay3
range
]
;
list_of_net_decl_assignments
netjvalue ::= neMdentifier
[ expression ] [ ms\302\243>_constant_expression
I
neMdentifier
I
neMdentifier
I
nef_concatenation
: fe\302\243>_constant_expression
]
::=
net_type
wire
I
tri
I
trh
I
I
supplyO
wand
I
triand
I
triO
I
supplyl
I
wor
I
trior
::=
next_state
output_symbol
I
-
.:=
non_blocking_assignment
reg_lvalue
specify_input_terminal_descriptor
]
[ polarity_operator
specify_output_terminal_descriptor
]:
data_source_expression) ::=
parallel_path_description
(specify_input_terminal_descriptor
[
polarity_operator
] =>
specify_output_terminal_descriptor)
::=
param_assignment
paramete/Jdentifier= constant_expression ::=
parameter_declaration
;
list_of_param_assignments
parameter
parameter_override::= ;
list_of_param_assignments
defparam
::=
parameter_value_assignment
# (expression {, expression ::=
pass_en_switchtype
tranifO
I
})
tranifl
I
rtranifl
I
rtranifO
::=
pass_en_switch_instance
[ name_of_gate_instance
] (inouMerminal, inouMerminal,
enablejerminal) ::=
pass_switch_instance
] (inouMerminal,
[ name_of_gate_instance
pass_switchtype ::= tran
I
rtran
path_declaration
::=
simple_path_declaration; I
edge_sensitive_path_declaration
I
state_dependent_path_declaration;
path_delay_expression
::=
constant_mintypmax_expression
278
;
inouMerminal)
The Syntax
A.3
SECTION
::=
path_delay_value
list_of_path_delay_expressions I
(list_of_path_delay_expressions)
::=
pcontrol_terminal
sca/ar_expression ::=
polarity_operator
+ 1-
port ::=
[ port_expression] I
. portjdentifier
([ port_expression
])
{, port_reference
}}
port_expression::= port_reference I
{port_reference
port_reference ::= portjdentifier I
portLidentifier
[ constant_expression
I
portjdentifier
[ msb_constant_expression
]
: feb_constant_expression
::=
primary
number I
identifier
I
identifier
I
identifier
I
concatenation
[ expression ] [ msb_constant_expression
I
multiple_concatenation
I
function_call
I
(mintypmax_expression)
.:=
procedural_continuous_assignment
reg_assignment ;
assign I
deassign
I
force
reg_assignment
I
force
net_assignment
I
release
I
release
regjvalue;
regjvalue; netjvalue
; ; ;
procedural_timing_control_statement
::=
delay_or_event_control statement_or_null ::=
pull_gate_instance [
] (outputjerminal)
name_of_gate_instance
::=
pulldown_strength
(strengthO, I
(strengthl
I
(strengthO)
pullup_strength
strengthl
, strengthO
)
)
::=
(strengthO,
strengthl
)
: teb_constant_expression
]
]
APPENDIX
A
Syntax Reference
I
(strength
1 ,strengthO
I
(strength
1 )
)
::=
pulse_control_specparam
PATHPULSE$= (re/'ecf_limit_value
I
I*no space; =
$specify_output_terminal_descriptor
[, errorJimit_value
]) ;
[, erro/-_limit_value
PATHPULSE$specify_input_terminal_descriptor
continue*!
(re/'ecfjimit_value
]) ;1
range ::=
[ ms\302\243>_constant_expression I
I
integer
realtime
I
time
;
::=
unsigned_number.
[ sign ] [
I
list_of_real_identifiers
real_number I
real
::=
real_declaration
real
]
::=
range_or_type
range
: fe\302\243>_constant_expression
] unsigned_number
sign
unsigned_number
[. unsigned_number
] e [ sign ]
[. unsigned_number
] E [ sign ]
unsigned_number I
[
] unsigned_number
sign
unsigned_number
realtime_declaration ::= realtime
;
list_of_real_identifiers
::=
reg_assignment
reg_lvalue = expression ::=
reg_declaration
reg
[
range
;
] list_of_register_identifiers
::=
regjvalue
reg_identifier I
reg_identifier
[ expression
I
regudentifier
[
I
recjLConcatenation
register_name
] : fe\302\243)_constant_expression
ms\302\243>_constant_expression
::=
re\302\243f/ster_identifier I
[ uppe/\"_//m/f_constant_expression
memoryjdentifier
]
/oiver_//m/f_constant_expression
scalar_constant ::=
1'bO11'b111'BO 11'B1 I 'bO
scalar_timing_check_condition
I
'b1
I
'BO
I
'B1
::=
expression I
~
I
expression
expression == scalar_constant
= (5,3); 1. For example,PATHPULSE$CLK$Q
280
11
I
0
:
]
The
I
expression
I
expression
I
expression
==
Syntax
A. 3
SECTION
scalar_constant
!= scalar_constant !== scalar_constant
seq_block ::=
begin
[: Woc/cj'dentifier {block_item_declaration}
]
{statement}
end
seq_input_list ::= I
level_input_list
edge_input_list
::=
sequential_body
[ udp_initial_statement
]
table
sequentiaLentry
{sequentiaLentry} endtable
::=
sequentiaLentry
::=
short_comment
// comment_text sign
: next_state;
current_state
seqjnputjist:
\\n
::=
+ 1-
simplej'dentifier ::= [a-zA-Z|[a-zA-Z_$0-9] \342\200\242.:=
simple_path_declaration
= path_delay_value
parallel_path_description I
= path_delay_value
full_path_description
size ::= unsigned_number
source_text
::=
{description}
specify_block ::=
specify
{specifyj'tem} endspecify
:=
specify_input_terminal_descriptor:
inputjdentifier I
inputjdentifier
I
inputjdentifier
specifyj'tem
[ constant_expression [ ms\302\243>_constantjaxpression
] : fe\302\243>_constant_expression
]
::=
specparamjdeclaration
281
APPENDIX
A
Reference
Syntax
I
path_declaration
I
system_timing_check
:=
specify_output_terminal_descriptor:
outputjdentifier I
outputjdentifier
I
outputjdentifier
]
[ constant_expression [ ms\302\243>_constant_expression
: /ab_constant_expression
::=
specifyJerminal_descriptor
specifyJnputJerminal_descriptor I
specify_outputJerminal_descriptor
::=
specparam_assignment
= constant_expression
specparamjdentifier I
pulse_control_specparam
specparam_declaration
\342\200\242.:=
specparam
list_of_specparam_assignments
::=
state_dependent_path_declaration if
) simple_path_declaration
( co/iaW/o/ia/_expression
I
if (
I
ifnone
;
) edge_sensitive_path_declaration
co/ic//f/o/ia/_expression simple_path_declaration
::=
statement
blocking_assignment ; I
nonjDlocking_assignment;
I
procedural_continuous_assignment
I
proceduralJiming_control_statement
I
conditional_statement
I
case_statement
I
loop_statement
I
wait_statement
I
disable_statement
I
eventjrigger
I
seq_block
I
par_block
I
task_enable
I
systemJask_enable
statement_or_null
;
\342\200\242.:=
statement
I
;
::=
strengthO
supplyO
I
strongO
I
pullO
I
weakO
I
strongl
I
pulM
I
weakl
1 ::=
strength
supplyl ::=
string \"
{
ANY_ASCII_CHARACTERSJEXCEPTJSIEWLINE
systemJask_enable
::=
system Jask_name
282
[ (expression
{, expression})];
\"
}
]
The
SECTION
Syntax
A. 3
system_task_name ::= identifier
be
$ cannot
/* The
followed
by
a space
7
system_timing_check ::=
$setup(timing_check_event, [, notify_register I
$hold
I
I
$width
I
[,
]) ;
notify_register
timing_check_event,
(timing_check_event,
timing_check_event,
(controlled_timing_check_event,
$recovery
notifyjegister]) ;
(timing_check_event,
$setuphold
timing_check_limit
]) ;
notify_register
timing_check_limit [, I
timing_check_limit,
(controlled_timing_check_event,
$skew
[,
timing_check_limit
notify_register
constant_expression I
timing_check_limit
]);
(controlled_timing_check_event, ]) ;
$period
[,
timing_check_event,
(timing_check_event,
[ / notify_register
timing_check_limit
timing_check_event,
]) ;
timing_check_limit,
timing_check_event,
timing_check_limit
[,
notify_register
]) ;
task_declaration ::=
task tes/c_identffier
;
{task_item_declaration}
statement_or_null
endtask
task_enable ::= fas/c_identifier
[
{, expression
(expression
}) ] ;
::=
task_item_declaration
block_item_declaration I
input_declaration
I
output_declaration
I
inout_declaration
time_declaration
time
::=
list_of_register_identifiers;
::=
timing_check_condition
scalar_timing_check_condition I
(scalar_timing_check_condition)
::=
timing_check_event
] specify_terminal_descriptor [ &&&timing_check_condition ]
[ timing_check_event_control ::=
timing_check_event_control
posedge I
negedge
I
edge_control_specifier
timing_check_limit
::=
expression
283
APPENDIX
A
Reference
Syntax
udp_body ::= combinational_body I
sequential_body
::=
udp_declaration
primitive
(udp_port_list);
udp_identifier
udp_port_declaration
{udp_port_declaration}
udp_body
endprimitive ::=
udp_initial_statement
initial
udp_output_portJdenX\\f\\er
=
init_val
;
::=
udp_instance
[ name_of_udp_instance
] (output_port_connection
, input_port_connection
})
{, input_port_connection
::=
udp_instantiation
[
udp_identifier
drive_strength
] [ delay2
] udp_instance
{, udp_instance
::=
udp_port_declaration
output_declaration I
input_declaration
I
reg_declaration
::=
udp_port_list
input_portJdenX\\i\\er
output_port_\\denXW\\er,
unary_operator ::=
+ I -1!
~ I &
I
I
~&
I
I I
~ I I A I ~A
\342\200\242.:=
unsigned_number
{_
decimal_digit
I
decimal_digit}
::=
wait_statement
wait (expression ) statement_or_null ::=
white_space
space
284
I
tab
I
newline
I
A~
{, input_portJdenX\\i\\er}
};
Bibliography
1.
Arnold
M.,
Digital
Verilog
PrenticeHall,NJ, 1998.
2.
Bhasker Publishing,
J.,
ISBN
1998,
PA,
3.
Lee J., Verilog
4.
Palnitkar
Prentice
HDL
Verilog
S.,
Hall,
Synthesis: A 0-9650391-5-3. Kluwer
Quickstart,
HDL:
5. SagdeoV.,CompleteVerilog 6. Smith D., HDL Chip Design, 7. SternheimE., R. Singh and Verilog
8.
Thomas
9.
IEEE
HDL,
Practical
Star Galaxy
Primer,
MA, 1997.
Academic,
Digital Design and Synthesis, 1996, ISBN 0-13-451675-3.
Verilog
NJ,
Design: Algorithms to Hardware,
Computer
Automata
A Guide to Kluwer
Book,
Doone Y
Publications,
MA, 1998.
1996.
Design and Synthesiswith 1993. CA, Company,
Trivedi,
Publishing
Academic,
Digital
D. and P. Moorby, The Verilog Hardware Description Kluwer Academic, MA, 1991, ISBN0-7923-9126-8.
Hardware
Standard
Hardware
Description
Description
Language,
Language
IEEE Std
Based on
Language,
the
Verilog
1364-1995,IEEE,1995.
285
Bibliography
10.
Open
Verilog
International,
OVI Standard
Delay File(SDF)
Format
Manual.
\342\226\241
286
Index
- character -
173,222
$fmonitor
94
57
operator
173
$fmonitorb
62
$fmonitorh
173
: 61
$fmonitoro
173
:= 61
$fopen 172
$fstrobe 173,222
181
$bitstoreal
18,113,169,205
$display
$displayb
169
$displayh 169 $displayo 169 182
$dist_exponential
$dist_normal 182 $dist_poisson 182 $dist_t
173
$fstrobeo
173 173
173
$fwriteb
173 $fwriteo 173 $fwriteh
182
$hold
$itor
177
181
$monitor
182
182
$dist_uniform
$dumpall
$fstrobeh $fwrite
182
$dist_chi_square
$dist_erlang
173
$fstrobeb
194
$dumpfile 193
$monitorb
21,171,205 171
$monitorh
171
$monitoro
171
$dumpflush
195
$monitoroff
172
$dumplimit
195
$monitoron
172
$dumpoff 194 194
$dumpon
193
$dumpvars
$fclose 173
$fdisplayh
$fdisplayo $finish
179
$period 178 $printtimescale 175 \342\200\242 $random
$fdisplay 173,222 $fdisplayb
$nochange
$readmemb
181
43,174, 205,219
173
$readmemh 43,174,205
173
$realtime
173
$realtobits
176,205
180
181
$recovery 178
287
= assignment symbol
181
$rtoi
==
177
$setup
177
$setuphold
$skew 178 $stime 180 $stop 123,176,205
=== 61
=> 198 > 60 60
>=
\302\273 66
170,205
$strobe
$strobeb
170
? character
$strobeh
170
A
$strobeo 170
A~ 63
175,180
$timeformat
$width
34,92,136
63,65
vcelldefine 31
26,180,206
$time
126
61
177
Mefault_nettype 28,40,
$write 169,205
selse 28
$writeb
169
vendcelldefine31
$writeh
169
sendif
$writeo 169
28
28
vifdef
% character 169
include
28,191
%B 169
Vesetall
29
%b 169
stimescale
%
57
operator
169
%D
II 62
-
169
~| 65
%0 169 169
169
absolute delay 209
%s 169
always statement
169
%t
%V
169
and gate
%v 169,202 62
(??)
94
assignprocedural 57
asynchronousloop preset
asynchronous
asynchronous state
188
57
base
< 60,66
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