IR Drop Analysis

IR Drop Analysis ~ VLSI Basics And Interview Questions

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What is IR Drop Analysis? How it effects the timing?

The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current start flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. This Drop is called as IR Drop. For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this context can allow upto 0.4 volts drop which does not effect the timing and functionality of design. How it effects the timing? Get this off IR Drop is Signal Integrity(SI) effect caused by wire resistance and current drawn file:///C|/Users/COMSOL/Desktop/IR%20Drop%20Analysis.htm[7/16/2014 8:22:07 PM]

IR Drop Analysis ~ VLSI Basics And Interview Questions

from Power (Vdd) and Ground (Vss) grids. According to Ohms law, V = IR. If wire resistance is too high or the current passing through the metal layers is larger than the predicted, an unacceptable Voltage drop may occur. Due to this un acceptable voltage drop, The power supply voltage decreases. That means the required power across the design is not reaching to the cells. This results in increased noise susceptibility and poor performance. The design may have different types of gates with different voltage levels. As the voltage at gates decreased due to unacceptable voltage drop in the supply voltage, the gate delays are increased non-linearly. This may lead to setup time and hold time violations depending on which path these gates are residing in the design. As technology node shrinking, there is decrease in the geometries of the metal layers and the resistance of this wires increased which lead to decrease in power supply voltage. During Clock Tree Synthesis, the buffers and inverters are added along the clock path to balance the skew. The voltage drop on the buffers and inverters of clock path will cause the delay in arrival of clock signal, resulting hold violation.

What are the tools used for IR Drop Analysis? In which stage IR Drop Analysis performed ? Various tools are available for IR Drop Analysis. Voltagestorm from Cadence, Redhawk from Apache are mainly used to show IR Drop on chip. Here we are going to discuss about IR Drop using Redhawk. IR Drop Analysis using Redhawk is possible at different stages of the design flow. When changes are in expensive and they don't effect project's schedule, It is better to use Redhawk for IR drop analysis from start of the design cycle. It can identify and fix power grid problems in the design. This also reduces changes required in sign-off stage where final static and dynamic voltage (IR) drops performed. So Redhawk can be used anywhere in the design starting from the floorplanning stage through initial and final cell placement stages.

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IR Drop Analysis ~ VLSI Basics And Interview Questions

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Related Posts: Floorplan Control Parameters The following are the Control Parameters during Floorplan 1. Aspect Ratio: Core Utilization Aspect ratio (H/W) Row/Core ratio 2.Width and Height: Width Height Row/Core ratio 1. Aspect Ratio (Ar): Aspect ratio i… Read More Physical Design Flow Physical Design Flow: The design flow of the physical implementation is mentioned above in the figure. The physical design stage of the design flow is also known as the “place and route” stage. This is based upon t… Read More IR Drop Analysis What is IR Drop Analysis? How it effects the timing? The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the design. These metal layers have finite amount of resistance. When v… Read More Basic Terminology in Physical Design Design: A circuit that performs one or more logical functions. Cell: An instance of a design or library primitive within a design. Port: The input or output of a design. Pin: The input or output of a cell. Net: A wire t… Read More Floorplanning Floorplanning: Floorplanning includes macro/block placement, pin placement, power planning, and power grid design. What makes the job more important is that the decisions taken for macro/block placement, I/O-pad placement… Read More

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Popular Posts Static Timing Analysis (STA) Interview Questions Static Timing Analysis Interview Questions Static Timing Analysis plays major role in physical design(PD) flow. It checks the design... IR Drop Analysis What is IR Drop Analysis? How it effects the timing? The power supply in the chip is distributed uniformly through metal layers (Vdd a... Physical Design (PD) Interview Questions - Floorplanning 1. What is floorplaning?

A. Floor planing is the process of placing Blocks/Macros in the chip/core

file:///C|/Users/COMSOL/Desktop/IR%20Drop%20Analysis.htm[7/16/2014 8:22:07 PM]

IR Drop Analysis ~ VLSI Basics And Interview Questions

area, thereby determining ... Clock Tree Synthesis (CTS) - Overview Clock Tree Synthesis Clock Tree Synthesis (CTS) is the process of inserting buffers/inverters along the clock paths of the ASIC design to... Low Power Design Power Planning: Power is limiting factor affection performance and features in most important products. When you decided to buy a mobile,... IR Drop Analysis Interview Questions IR Drop Analysis Interview Questions 1. What is IR Drop Analysis? A. The power supply in the chip is distributed uniformly through met... Static Timing Analysis (STA) Overview Timing Analysis: Timing Analysis is a method of validating the timing performance of a design. i.e. How fast the design is going to oper... Physical Design Flow Physical Design Flow: The design flow of the physical implementation is mentioned above in the figure. The physical design stag... Basic Terminology in Physical Design Design: A circuit that performs one or more logical functions. Cell: An instance of a design or library primitive within a design. P... Power Planning - Power Network Synthesis (PNS) Power Planning - Power Network Synthesis (PNS) In ICC Design Planning flow, Power Network Synthesis creates macro power rings, creates th...

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