IntroToSV_orgi

Intro To SystemVerilog SystemVerilog for Verification

Day One

Welcome Welcome to the “Intro to SystemVerilog for Verification” class Requirements Some HDL programming experience Some Unix experience Familiarity with some Unix editor Unix account in Folsom, Chandler, Dupont, or Penang.

Assumes use of Modelsim. Intel Confidential

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Scope Of Course Introduction to SystemVerilog for verification Hands-on lab assignments Students will not be SystemVerilog experts at the end of this class. Class is an introduction only. Advanced classes go into more details. Next Classes: Functional Coverage/Temporal language/Checkers How to write a SV Test How to write an SV BFM

Length: 2 days Intel Confidential

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Typographic Conventions Regular Text

Course Content

Courier Bold

Code examples, command line keyboard input

Courier Regular

Screen output

Italic

Placeholders for data user should input Intel Confidential

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What is SystemVerilog SystemVerilog is an IEEE extension to the Verilog language. SystemVerilog adds testbench features such as classes, constraints, and temporal expressions to Verilog.

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Getting More Information SystemVerilog LRM http://www.eda.org/sv/SystemVerilog_3.1a.pdf

AVC Wiki http://wwwfmec.fm.intel.com/twiki/bin/view/Chipset/SystemVerilog

Comprehensive information on SV:

http://carmel.fm.intel.com/sites/CPDCDTG/DATE/FEDAO/SystemVerilog%20Deployment%20Doc %20Lib/Forms/AllItems.aspx

Additional Information www.accellera.org Intel Confidential

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Using SystemVerilog To setup your environment to use SystemVerilog, type the following at the unix prompt:

% source

Next, create a training directory, and create a work library: % mkdir svtraining; cd svtraining % vlib work % vmap work work

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Hello World module helloWorld(); initial begin: hello $display("Hello World"); end: hello endmodule: helloWorld

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Compiling SystemVerilog To compile your program, type the following: % vlog hello.sv

Note: If you do not name your file ending in .sv, you must use the –sv option to vlog. To run your program, use the following command: % vsim -c -do "run -all;q -f" helloWorld Intel Confidential

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Commenting Your Code Like C++, SystemVerilog supports two types of comments /* Block comments that can span * multiple lines */ // And single line comments $display(“hello”);

// This is a comment

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Lab 1: Hello World Create a module that prints “Hello World” using the $display command.

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Basic Data Types

Integer Data Type shortint int longint byte bit logic reg integer time

2-state (1, 0), 16 bit signed 2-state, 32 bit signed 2-state, 64 bit signed 2-state, 8 bit signed 2-state, user-defined vector size 4-state (1,0,x,z) user-def 4-state user-defined size 4-state, 32 bit signed 4-state, 64 bit unsigned

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Signed/Unsigned byte, shortint, int, integer and longint defaults to signed Use unsigned to represent unsigned integer value Example: int unsigned ui;

bit, reg and logic defaults to unsigned To create vectors, use the following syntax: logic [1:0] L; // Creates 2 bit logic // vector

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Strings string – dynamic allocated array of bytes SV provides methods for working with strings Str1 == Str2

Equality

Str1 != Str2

Inequality

=

Comparison

{Str1, Str2, … Strn}

Concatenation

Str1[index]

indexing – return 0 if out of range Intel Confidential

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String Methods len putc getc toupper tolower compare icompare substr

atoi, atohex, atoct, atobin atoreal itoa hextoa octtoa bintoa realtoa

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Literal Values Integer Literal – Same as verilog value – unsized decimal value size’base value – sized integer in a specific radix Ex: 4’b0101; 4’hC; 32’hDEAD_BEEF; 2’b1Z

Real Literal value.value Ex: 2.4 Base Exponent ( E/e)

Logic Value 0, 1, [z|Z], [x|X]

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Lab 2: Data Types Write a top level module that displays the following output. Use of the following data types: 1. int both signed and unsigned 2. logic 3. string Hint:

int i, h; $display(“%d %h”, i, h); string str; $sformat(str, “%b”, l) $display(“Logic value in upper case %s”,str.toupper());

Output: # The integer i is 0x00000014 # The unsigned integer ui is 0xdeadbeef # The logic L is 1Z # string str1 is "Hello World" # string str2 is "Cruel World“

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Operators Logic Operators &

|

~

^

~&

~|

~^ >

Arithmetic Operators +

-

%

/

*

** >

Assignment Operators = += -= *= /= %= &= |= ^= = =

Example: a += 3; Equivalent to: a = a + 3;

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Operators Auto-increment (++) Auto-decrement(--) Example: a = 1; a++; a now contains 2.

Comparison Operators ==

!=

===

!==

=?=

!?=

>

<

=

Example: a = 1'bZ; b = 1'bZ; if (a != b) $display(“Z != Z”); if (a === b) $display(“Z === Z”); Intel Confidential

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Concatenation The { } operator is used for concatenation. Example: s = {“Hello”, “ “, “World”}; v = {32’b1, 32’b10}; // v = 64b vector

Can also be used on left hand side: {a, b, c} = 3’b111;

Sizes of assignment have to match. If LHS is smaller then assignment gets truncated. Intel Confidential

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Lab 3: Operators Write a SystemVerilog module to calculate the following, and print the result as an integer to the screen: (1101001 XOR 11111001) ÷ 5 Ignore remainder.

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Flow Control Constructs How to go with the flow

SystemVerilog additions Verilog includes: if-(else-(if)), case, forever, repeat, while, for, ?: (ternary) SystemVerilog: Enhances for Adds do..while, foreach

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if Verilog ‘if’ expressions Then branch taken for any nonzero known value of expr (no ‘x’ or ‘z’), equivalent to expr != ‘0’ Chain ‘if’ statements: if (expr) begin … end else if (expr) begin … end else begin … end

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?: Operator, but conditional expr ? then_val : else_val

Some call this the “ternary” operator, in the same vein as “unary” and “binary”, with 3 operands. Ex: var_m = (x == 1) ? a : b;

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case 4-value exact matching, runtime evaluation, no fallthrough, bit length of all expressions padded to same length case (expr) item: begin statement end item2, item3, item4: begin statement end default: statement endcase Intel Confidential

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casez, casex Handle wild cards with either casez or casex casez: ‘z’ bit in either item or expression will be treated as a match for that bit casex: ‘z’ or ‘x’ bits will both match casex (8’bx100z011 ^ reg_a) 8’b1x1001?1: $display(“x”); 8’b01z10zx1: $display(“y”); 8’b11z01011: $display(“z”); endcase

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forever Continuous execution, without end, of body statement(s) Used with timing controls Usually last statement in some block initial : clock_drive begin clk = 1’b0; forever #10 clk = ~clk; end : clock_drive Intel Confidential

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repeat Repeat a block ‘x’ times, no conditional test repeat (expr) statement

What happens with expr = ‘x’ or ‘z’? Example x = 0; repeat (16) begin $display(“%d”, x++); end Intel Confidential

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while Executes statement as long as expr evaluates to true

while (expr) statement Example:

while (reg_i) begin something_happens(); reg_i = reg_i – 1; end

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for ‘C’ inspired for loop for (initial_assignment; condition; step_assignment) statement

Equivalent to begin initial_assignment; while (condition) begin statement; step_assignment; end end Intel Confidential

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Enhanced for SystemVerilog adds: Loop variable declaration Multiple statements in init and step blocks (comma separated) ++ and -- operators (Mentioned in operator section) for (int i; i < arr.size(); j+=2, i++) begin arr[i] += 200; arrb[i]--; end

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do..while do statement while (expr); What’s the difference?

x = 0; 1) while (x) begin $display(“%d”, x); x--; end 2) do begin $display(“%d”, x); x--; end while (x);

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Lab 4: Flow control Write a SystemVerilog module to display the first 20 Fibonacci numbers. Fn = Fn-1 + Fn-2 Hint: F1 = F2 = 1

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User Defined Types and Enumerated Types

User Defined Types SystemVerilog supports a new keyword: typedef Syntax:

typedef

typedef int inch ;

// inch becomes a new type

inch foot = 12, yard = 36;

// these are 2 new variables of type ‘inch’

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Copyright © 2005 Mentor Graphics Corporation

Enumeration Syntax: enum [enum_base_type] { enum_name_declaration {,enum_name_declaration} } enum_base_type: default is int Enumeration is a useful way of defining abstract variables. NOTE:

Define an enumeration with “ enum ” enum {red, green, yellow} traf_lite1, traf_lite2; Values can be cast to integer types and auto-incremented enum { a=5, b, c} vars; // b=6, c=7

Default assigned values start at zero 0 1 2 enum {red, green, yellow} lite;

A sized constant can be used to set size of the type enum bit [3:0] { bronze=4’h3, silver, gold} medal; // All medal members are 4-bits Define a new type typedef enum {NO, YES} bool; // bool is NOT a SystemVerilog type bool myvar; // but it just became one “myvar” will now be checked for valid values in all assignments, arguments and relational operators 8-39 • SV for Verification Using Questa: Functional Coverage

Copyright © 2005 Mentor Graphics Corporation

Enumeration example Modelsim now allows viewing of enum types in waveforms similar to VHDL enum types. To use enumerated types in numerical expressions the language provides the following functions: prev(), next(), first(), last(), num() and name().

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Example typedef enum {red, green, blue, yellow, white, black} Colors; Colors col_ps; Colors col_ns; always @(col_ps) col_ns = col_ps.next(); always @(posedge clk) col_ps delete()

Deletes the item at the specified index position. Q.delete (i)

pop_front()

=> Q = ‘{Q[0:i-1], Q[i+1,$]}

Removes and returns the first element of the queue. e = Q.pop_front ()

pop_back()

e = Q[0]; Q = Q[1,$]

=>

e = Q[$]; Q = Q[0,$-1]

Inserts the given element at the front of the queue. Q.push_front (e)

push_back()

=>

Removes and returns the last element of the queue. e = Q.pop_back ()

push_front()

Q = ‘{Q[0:i-1], e, Q[i,$]}

=> Q = ‘{e, Q}

Inserts the given element at the end of the queue. Q.push_back (e)

=> Q = ‘{Q, e}

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Prototype: function void delete (int index); Prototype: function queue_type pop_front(); Prototype: function queue_type pop_back(); Prototype: function void push_front (queue_type item); Prototype: function void push_back (queue_type item);

Copyright © 2005 Mentor Graphics Corporation

Queue Example module queues (); int q [$]; // declare the q

//

// // // //

initial begin: store_disp Push elements into the queue q.push_back(1); q.push_back(0); Display its contents $display("Size of queue = %0d", q.size()); Delete the element of queue at index 1 q.delete(1); Push to front of the queue q.push_front (0); Display all the contents in the queue for (int i = 0; i < q.size(); i++) $display("q[%0d] = %0d", i, q[i]); end: store_disp

endmodule: queues Intel Confidential

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Lab 6: Queues Write a SystemVerilog program with specification as defined in lab6.sv The output will look as follows: # Loading work.lab6 # run –all # Size of queue = 3 # q[0] = 0 # q[1] = 1 # q[2] = 3 # q -f Intel Confidential

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Associative Arrays Associative arrays are used when the size of the array is not known or the data is sparse. Syntax: data_type array_name [index_type]; In other words value_type array_name [key_type]; It implements a lookup table of the elements of its declared type. Data type used as an index serves as lookup key and imposes an order. Associative array do not have their storage allocated until it is used.

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Index Types String Index Types Ex: int a [string]; a[“joe”] = 21;

Integer Index Types Ex: bit [1:0] a [int]; a[5] = 2’b11;

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Associative Array Methods Function

Use

num()

Returns number of entries

delete()

Index for delete optional. When specified used to delete given index else whole array.

exists ()

Returns 1 if element exists at index else 0

first (), last ()

assigns to the given index variable the value of the first/last (smallest/largest) index in the associative array. It returns 0 if the array is empty, and 1 otherwise.

next (), prev ()

finds the entry whose index is greater/smaller than the given index.

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Associative array methods - Example module asoc_arry (); int db [string]; // Define an associative array initial begin: test string s; db ["joe"] = 21; // store values at indexes of associative array db ["jill"] = 19; // Display the size of the associative array $display("Size of hash = %0d", db.num()); if (db.exists("jill")) // check if index exists and change value begin db["jill"] = 25; end // print the contents of associative array if (db.first(s)) do begin $display("Name = %s -- Age = %0d", s, db[s]); end while (db.next(s)); end: test endmodule: asoc_arry Intel Confidential 56

Lab 7: Associative Arrays 1.

Define an associate array named 'assoc' assoc has the following attributes: INDEX - Name of person VALUE - Age

2.

Make the following entries into assoc NAME AGE ---------------John 25 James 30 Jane 24

3. 4.

Display the size of the hash using $display statement Check if name Jane exists in the associative array and if it does

change her age to 40. 5.

Print the contents of the associative array.

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Procedural Blocks

Triggering sensitivity @() waits for an edge on before executing the next statement Edge-sensitive signal detection @(posedge clk) – waits for a rising edge clock @(negedge rstb) – waits for a falling edge on rs wait() waits for a condition to become true before executing the next statement. Level-sensitive signal detection If the signal is already true, execution continues without stopping

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Initial Block An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution independently of other blocks. Multiple behavioral statements must be grouped, typically using begin and end.

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Example module stimulus; reg a,b; initial begin #5 a = 1’b1; #25 b = 1’b0; end endmodule

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Always Block The always block statement starts evaluating sensitivity list at time 0 and executes statements in the always block continuously in a looping fashion. This statement is used to model a block of activity that is repeated continuously. Intel Confidential

Example module clock_gen; bit clock; initial begin clock = 1’b0; forever #10 clock = ~clock; end always @(posedge clk) begin ; end endmodule

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Final Blocks The final block is like an initial block, defining a procedural block of statements, except that it occurs at the end of simulation time and executes without delays. A final block is typically used to display statistical information about the simulation.

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Example final begin $display("Number of cycles executed %d",$time/period); $display("Final PC = %h",PC); end

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Lab 8: Procedural Blocks Create a SystemVerilog module: 1. Define an initial block such that it generates a clock clk time period = 10ns NOTE: Need to initialize clock even though the bit data type is automatically done. 2. Create an always blocks that stores the value of signal 'clk' into queue 'q' at positive edge of the clock. 3. Increment 'counter' when always block is triggered 4. When counter reaches 4 call $finish system call Hint: Use if statement 5. Define a final block to print the size of 'q' at the end of simulation Hint: Use final blocks Output: # Size of q = 4

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Types of Assignment Blocking Nonblocking

Blocking Assignment The simulator completes a blocking assignment (=) in one pass [execution and assignment]. Execution flow is blocked until a given blocking assignment is complete. If there is a time delay on a statement then the next statement will not be executed until this delay is over. Intel Confidential

Example initial begin a = 30; #10; a = 5; c = #10 a; b = 2; end // at time 0 a = 30 //at time 10 a = 5, b = x, c = x // at time 20 a = 5, b = x, c = 5 // at time 20 a = 5, b = 2, c = 5 65

Nonblocking Assignment The simulator completes a nonblocking assignment (> operator. The statement executes without blocking and it creates a nonblocking assign update event in the time in which the event occurs. The effect of this event is felt during the nonblocking assignment region of a simulation cycle.

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Example always @(posedge clk) begin if (counter == 2) ->> a; counter++; end initial begin forever @(a) $display("event a triggered @ %0t, $time); end

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Waiting for an event @ is used to wait for an event. The @ operator blocks the calling process until the given event is triggered.

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Example module event_testing (); event a, b, c; bit clk; always @(posedge clk) -> a; always @(negedge clk) -> b; always @(a or b) -> c; initial begin clk = 1'b0; forever #10 clk = !clk ; end endmodule 152

Event Sequencing: wait_order() wait_order construct suspends the calling process until all specified events are triggered in the given order [left to right]. If any events are triggered out of order then it causes a fail of the operation. Intel Confidential

Example bit success; wait_order (a, b, c) success = 1; else success = 0; // event must occur in the // following order // ->a ->b ->c if not it fails.

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Event Variables [1] Merging Events When one event variable is assigned to another, both merge into one event variable. Executing -> on either one of the events affects processes waiting on either event variable.

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Example event a, b; a = b; -> a; // also triggers b -> b; // also triggers a

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Event Variables [2] Reclaiming Events When an event variable is assigned the special null value, the association between the event variable and the underlying synchronization queue is broken.

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Example event E1 = null;

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Event Variables [3] Event Comparison Event variables can be compared against other event variables or the special value null. Equality (==) with another event or with null. Inequality (!=) with another event or with null.

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Example event E1, E2; if ( E1 ) // same as if ( E1 != null ) E1 = E2; if ( E1 == E2 ) $display( "E1 and E2 are the same event" );

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Semaphores Can be described as counters used to control access to shared resources by multiple processes [threads]. Printer1 Printer1 [1] [0]

Print manager

Printer2 [1] 3 keys 2 keys Printer3 [1]

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Semaphore Methods Semaphore provides following built-in methods: Method

Use

new()

Create a semaphore with specified number of keys.

put()

Return one or more keys back.

get()

Obtain one or more keys.

try_get()

Try to get one or more keys without blocking.

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Semaphore example initial begin:init2 #5 spr.get(2); $display(" inital2 takes 2 keys at %0t",$time); #5 spr.put(1); $display(" inital2 returns 1 key at %0t",$time); end endmodule: semaphore_test

module semaphore_test (); semaphore spr = new(2); initial begin:init1 #1 spr.get(1); $display("initial1 takes 1 key at %0t", $time); #6 spr.put(1); $display("initial1 returns 1 key at %0t",$time); #1 spr.get(1); $display("initial1 takes 1 key at %0t", $time); end Output: # initial1 takes 1 key at 1 # initial1 returns 1 key at 7 # inital2 takes 2 keys at 7 # inital2 returns 1 key at 12 # initial1 takes 1 key at 12 # q -f Intel Confidential

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Mailboxes Mailbox is a communication mechanism that allows messages to be exchanged between different processes.

Process 1

Process 2

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Mailbox Types Mailboxes can be classified as: Unbounded mailboxes No restrictions placed on size of mailbox. put() will never block. Ex: mailbox m = new ();

Bounded mailboxes Number of entries is determined when the mailbox is created. Bound value should be positive. put() will be blocked if the mailbox is full. Ex: mailbox m = new (5); // mailbox of depth = 5

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Mailbox Methods Messages are placed in strict FIFO order. This does not guarantee order of arrival but that the arrival order shall be preserved. Mailboxes provides following built-in methods: Method

Use

new()

Create a new mailbox.

put()

Place a message in a mailbox.

get()

Retrieve a message from mailbox.

try_get()/ try_peek()

Try to retrieve a message from the mailbox without blocking.

try_put()

Try to place a message in mailbox without blocking. Useful only for bounded mailboxes.

peek()

Copies a message from mailbox without actually removing it. Intel Confidential

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Mailbox example module mailbox_ex (); class Xaction; rand bit [2:0] addr; endclass typedef mailbox #(Xaction) mbx; mbx mb = new (); initial begin: t Xaction xaction; int mb_size;

mb_size = mb.num(); for (int i=0; i (y < 100 && y > a.x)

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std::randomize() {BACKUP} Procedural invocation of constraint solver Any variables can be the random variables “with” block for constraints Normal .randomize() cannot include variables outside scope of class

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Disabling rand/constraints {BACKUP} rand_mode – method to toggle the “rand” attribute off on a class variable constraint_mode – method to toggle the application of a named constraint

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Random Stability {BACKUP} SV has thread random stability

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