Introduction To Fpgas

 

Introduction to FPGAs Field Programmable Gate Arrays

CSET 4650 Field Programmable Logic Devices Dan Solarek

 

Hierarchy o Logic !m"lemen#a#ions The diagram below is a modified version of the one we first used to discuss the role of FPLDs in logic implementation This version more closely reflects the details as we have come to know them Logic

Standard Logic

""L

ASIC

C#$S

SPLDs (eg! PALs)

Programmable Logic Devices

SemiCustom

Full Custom

(FPLDs)

ICs

ICs

CPLDs

FPGAs

Gate Arrays

Cell-Based ICs

2

 

FP$% Develo"men# fro m Gate rrays FPGs evolved from rrays Parallel with development of !PLDs ASIC Programmable Logic Devices

SemiCustom ICs

(FPLDs)

SPLDs (eg! PALs)

CPLDs

FPGAs

Gate Arrays

Full Custom ICs

Cell-Based ICs

3

 

chnology ogy &'()0s &'()0s* $a#e %rray Technol &'()0s** #ask$Programmable Logic Devices #PLDs as compared to FPLDs Programmed as part of fabrication process

#ask$Programmable Gate rrays  specific type of #PLD %uild standard layout of transistors on chip !ustomer specifies wiring to connect transistors into gates and gates into systems &nly has to go through last few mask steps of fabrication  process Faster than full$custom chip fabrication "

 

chnology ogy &'()0s &'()0s* $a#e %rray Technol &'()0s** (imple logic gates )se transistors to implement combinational and se*uential logic

+nterconnect

,ires to connect inputs and outputs to logic blocks

+-& blocks (pecial blocks at periphery for e.ternal connections

dd wires for connections Done when chip is fabricated /mask$programmable logic device0

!onstruct any circuit

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Evol+#ion o #he FP$% arly FPGs )sed mainly for /glue logic0 between other components interfacing4 (imple !ombinational Logic %locks !L%s4 (mall number of inputs and outputs Focus was on implementing /random0 logic efficiently

s capacities grew5 other applications emerged FPGs used as an alternative to custom +!6s for entire applications !omputing with FPGs

1

 

Evol+#ion o #he FP$% FPGs have changed to meet new application demands !arry chains5 better support for multi$bit operations +ntegrated memories5 such as the block 8#s (peciali9ed units5 such as multipliers5 to implement functions that are slow-ineffici ent in !L%s sl ow-inefficient  :ewer devices incorporate entire !P)s; $" Power P! !P)s

$" Power P! !P)s

Devices that don6t have !P) hardware generally support synthesi9ed !P)s

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C+rren# FP$%s, -a.or Elemen#s !urrent commercial FPGs have the same general structure but differ among ma@or components; Programmability Technology Technology used to program device +nternal logic cell structure !ombinational and se*uential !omple.ity

8outing mechanisms mechanisms +nterconnecting wires and their layout ?

 

The Plan or Today ,e will look at a generali9ed overview of FPGs and their structure #ore of our e.amples than not will be from B

 

%rrays FieldProgrammable $a#e %rrays %ased on !onfigurable Logic %locks !L%4 as the logic cells C CLB

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C+rren# FP$%s, Logic Cells !urrent commercial FPGs use logic cells that are more re of the following;  based one one or mo more Tr Transistor ansistor pairs %asic small gates eg5 two$input ::D or 2

 

FieldProgrammable $a#e %rrays %rrays 8e*uires some form of progr programmable ammable interconnect interconnect at crossovers C CLB

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C+rren# FP$%s, Programming (tatic 8# (witch is a pass transistor controlled by the state of the (8# bit

P8&# (witch is a floating$gate transistor that can be turned off  by in@ecting charge onto its floating gate

ntifuse

(witch is a device that5 when electrically programmed5 forms a low resistance path

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C+rren# FP$%s vers+s -PLDs Programmable switches occupy larger chip areas e.hibit higher parasitic resistance and capacitance power dissipation and propagation delay result4

dditional chip area re*uired for switch  programming circuitry The more switches5 the more fle.ible Fle.ibility re*uires higher /overhead0

FPGs are slower than #PLDs >'

 

C+rren# FP$%s, Programming FPG ntifuse$  programmed

Actel ACT1 ACT1 & 2 Quicklogic’s pASIC Crosspoint’s CP20K 

(8#$  programmed +sland Xilinx LCA AT&T Orc Alter !lex

P8&#$  programmed

!ellular   Tos"i# Plesser’s $%A Atel’s CLi

Alter’s 'AX A'(’s 'c" Xilinx’s $PL(

>1

 

%rchi#ec#+res +res FP$% %rchi#ec# %rchi#ec#+r rchi#ec#+res es FPGs are commercially available in many different architectures and organi9ations lthough each company6s offerings have uni*ue characteristics5 FPG architectures can be generically classified into one of four categories; (ymmetrical rray 8ow %ased Eierarchical PLD (ea of Gates

>7

 

%rchi#ec#+res +res FP$% %rchi#ec# %rchi#ec#+r rchi#ec#+res es The !onfigurable Logic %locks !L%s4 are organi9ed in a two dimensional array separated by hori9ontal and vertical wiring channels ach !L% contains flip$flops45 multiple.ers5 and a combinatorial function block which operates as an (8# based table look$up

!L%

!onnections between !L%s are customi9ed by turning on pass transistors which selectively connect the !L%s to the interconnection resources >?

 

%rchi#ec#+res +res FP$% %rchi#ec# %rchi#ec#+r rchi#ec#+res es Pass transistors selectively connect the interconnect lines  between the hori9ontal and vertical wiring channels (8# cells which are distributed around the chip hold the state of the interconnect switches

!L%

(urrounding the !L% array and interconnect channels are the programmable +-& blocks which connect to the package  pins >A

 

%rchi#ec#+res +res FP$% %rchi#ec# %rchi#ec#+r rchi#ec#+res es s in a CL? Inputs

Look-Up   Table   (LUT)

Ou

State Clock Enable

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CL @ariables  :umber of inputs to L)T L )T L) T Trade off number of !L%s re*uired vs si9e of !L% and routing area

Eow is logic implemented L)T vs programmable and$or$invert vs other  Technology used to hold configuration program4 of !L%

Flip$flop in !L% dditional Functionality !arry chains

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SAi#ch De#ail Programmable (witch #atri. !onnections !onnections are controlled  by 8# bits #ore later 

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Programmable SAi#ch -a#ri9 p r og r a mma mm bl es wi t c hel e me me nt

t ur ni ngt hec or ner ,et c .

3?  

The Fi##er>s Bob Partition logic functions into !L%s rrange the !L%s +nterconnect the !L%s +nterconnect !L%sof !L%s used #inimi9e thethe number #inimi9e the si9e and delay of interconnect used ,ork with constraints /Locked0 +-& pins !ritical$path delays (etup and hold times of storage elements

3A  

!n"+#8+#"+# locks &ne +&% per FPG pin llows pin to be used as input5 output5 or bidirectional tri$state4

+nputs Direct 8egistered Drive dedicated decoder logic for address recognition

+&% may also include logic for boundary scan HTG4

"B  

!:8 blocks Looks like a !PLD macrocell

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ilin9 4000series FP$%s

"2  

FP$%s, S+mmary Eistorically5 FPG architectures and companies samee time as !PLDs !PLDs  began around the sam FPGs are closer to /programmable (+!s0 (+!s0 $ large FPGs are to /programmable (+!s0 (+!s0 $ large emphasis oncloser interconnection routing  Tim Timing ing is difficult to predict $ multiple hops vs the fi.ed delay of a !PLD6s switch switc h matri. switch %ut more /scalable0 to large si9es

FPG configurable logic blocks have a few inputs and >$2 flip$flops5 but there are many more of them compared to the number of macrocells in a !PLD

"3  

Common CPLD  FP$% Problems Pin locking (mall changes5 and certainly large ones5 can cause the fitter to pick a different allocation of +-& blocks and pinout Locking too early may make the resulting circuit slower or not fit at all

8unning out of resources Design may /blow up0 if it doesn6t all fit on a single device &n$chip interconnect resources are much richer than off$ chip Larger devices are e.ponentially more e.pensive

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FP$%s, Pros 8easonably !heap Good for low$volume parts5 more e.pensive than +! for high$volume  parts

(hort Design !ycle I>sec programming time4 8eprogrammable !an download bug fi. into units you6ve already shipped

Large capacity " million gates or so5 though we won6t use any that big4 FPGs in the lab are /rated0 at 3BBJ gates

#ore fle.ible than PLDs $$ can have internal state #ore compact than #(+-((+

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FP$%s, Cons Lower capacity5 speed and higher power consumption than building an integrated circuit (ub$optimal mapping of logic into !L%6s Less dense layout and placement due to programmability &verhead of configurable interconnect and logic blocks

PLDs may be faster than FPG for designs they can handle  :eed sophisticated tools FPG tools to map design to FPG