INEL 4225 Manual Lab Oratorio

1

EXPERIMENT 01

RTL Circuits Objectives 1. Examine the RTL characteristics. 2. Familiarize with the internal working of the RTL circuits. 3. Design and analyze an RTL inverter and determine its input-output characteristics, Propagation delay, and noise margins.

Required Equipments

• • • • •

Oscilloscope Power supply Function generator  Digital Multimeter  Bread-Board o Protoboard

Required Parts list

• • • • •

10 K Ω ¼-watt resistor. 0.1 μF capacitor  470 Ω ¼-watt resistor. 2N2222 NPN silicon transistor, or equivalent 1N4001 Diode semiconductor 

Background Resistor-Transistor Resistor-Transistor Logic (RTL) refers to the obsolete technology for designing and fabricating digital circuits that employ logic gates consisting of nothing but transistors and resistors. resistors. RTL gates are now seldom used, if at all, in modern digital electronics design because it has several drawbacks, such as bulkiness, low speed, limited fan-out, and poor noise margin. A basic understanding of what RTL is, however, would  be helpful to any engineer who wishes to get familiarized with TTL, which for the past many years has become widely used in digital devices such as logic gates, latches,  buffers, counters, and the like. Basically, RTL replaces the diode switch with a transistor switch. If a +5V signal (logic 1) is applied to the base of the transistor (through an appropriate resistor to limit   base-emitter forward voltage and current), the transistor turns fully on and grounds the output signal. The output signal rise to +5 volts if the input is grounded (logic 0), the transistor is off. In this way, the transistor does invert the logic sense of the signal, but it

2

also ensures th t the outp t voltage will alway   be a valid logic le el under all circumstances. RTL gates also exhibit limited 'f  n-outs'. The fan-out of a gate is th ability of i s outp t to drive several other  gates. The more gates it can drive, the higher  is its fan-ou t. The an-out of a gate is limited by the c rrent that it output can supply to t e gate inpu s connected to it hen the ou put is at lo ic '1', since at this stat it must be able to drive the c nnected in ut transisto s into satur  tion. Another  eakness of an RTL gate is its poor  noise margin. The noise margin of  a logic gate for logic level “0”, Δ0, is defi ed as the difference between the m ximum inp t voltage that it will recognize as a “0” (VIL) and the aximum voltage that may be applied to it as a “0” ( OL of the riving gate connected to it). For  logic level '1', the noi e margin Δ1 is the difference etween the minimum i  put voltage that may b applied to it as a ''1' (VOH of  he driving gate connected to it) a d the mini um input voltage that it will ecognize as a '1' (VIH). Mathematically, Δ0 = VIL-VOL and Δ1 = OH-VIH. Any noise that cause a noise m rgin to be vercome will result in a “0” bein erroneously read as a '1' or vice versa. In other word , noise mar gin is a measure of the i munity of a gate rom readin an input logic level in orrectly. In an R  L circuit, the collect r output connected to the base resisto of the driven transisto that in such an a rangement, the differe ces betwee VIH, are not that large. This is why RT gates are com arison to D L and TTL gates.

f the driving transist r is directl y . Circuit a alysis woul easily sho VIL and V L, and bet een VOH and nown to have poor noise margins in

Some ye rs ago, when RTL ICs were the standard lo ic devices used in bo h com ercial and experiment l digital cir cuits, transistors typica ly had a fo ward curre t gain of about 3 . With im roved man facturing techniques, modern tra sistors sho current gains of  100 or mo e. There is also far le s variation   between tr nsistors of  a give type. As a result, we can tolerate much low r input curr ent to drive the transist r  relia ly into sa uration. T e resistor  values in the schem tic diagra reflect t e capa ilities of  odern transistors; they are significantly highe than the values used in RTL ICs, allowi g working ircuits to b built that r  quire far less operating current.

RT

Inverter

The out ut signal of a NO logic g te (Inverter) is the complemen of the inp t signal. T at is, w en the inp t signal is ow “0”, th output sig al is hi h “1” and ice versa. NOT gate can be easily obtained by means of an inverting amplifier circuit as shown in Figure 1.

2

also ensures th t the outp t voltage will alway   be a valid logic le el under all circumstances. RTL gates also exhibit limited 'f  n-outs'. The fan-out of a gate is th ability of i s outp t to drive several other  gates. The more gates it can drive, the higher  is its fan-ou t. The an-out of a gate is limited by the c rrent that it output can supply to t e gate inpu s connected to it hen the ou put is at lo ic '1', since at this stat it must be able to drive the c nnected in ut transisto s into satur  tion. Another  eakness of an RTL gate is its poor  noise margin. The noise margin of  a logic gate for logic level “0”, Δ0, is defi ed as the difference between the m ximum inp t voltage that it will recognize as a “0” (VIL) and the aximum voltage that may be applied to it as a “0” ( OL of the riving gate connected to it). For  logic level '1', the noi e margin Δ1 is the difference etween the minimum i  put voltage that may b applied to it as a ''1' (VOH of  he driving gate connected to it) a d the mini um input voltage that it will ecognize as a '1' (VIH). Mathematically, Δ0 = VIL-VOL and Δ1 = OH-VIH. Any noise that cause a noise m rgin to be vercome will result in a “0” bein erroneously read as a '1' or vice versa. In other word , noise mar gin is a measure of the i munity of a gate rom readin an input logic level in orrectly. In an R  L circuit, the collect r output connected to the base resisto of the driven transisto that in such an a rangement, the differe ces betwee VIH, are not that large. This is why RT gates are com arison to D L and TTL gates.

f the driving transist r is directl y . Circuit a alysis woul easily sho VIL and V L, and bet een VOH and nown to have poor noise margins in

Some ye rs ago, when RTL ICs were the standard lo ic devices used in bo h com ercial and experiment l digital cir cuits, transistors typica ly had a fo ward curre t gain of about 3 . With im roved man facturing techniques, modern tra sistors sho current gains of  100 or mo e. There is also far le s variation   between tr nsistors of  a give type. As a result, we can tolerate much low r input curr ent to drive the transist r  relia ly into sa uration. T e resistor  values in the schem tic diagra reflect t e capa ilities of  odern transistors; they are significantly highe than the values used in RTL ICs, allowi g working ircuits to b built that r  quire far less operating current.

RT

Inverter

The out ut signal of a NO logic g te (Inverter) is the complemen of the inp t signal. T at is, w en the inp t signal is ow “0”, th output sig al is hi h “1” and ice versa. NOT gate can be easily obtained by means of an inverting amplifier circuit as shown in Figure 1.

3

Volt ge Transf  r Characte istic The volt ge transfer  characteristic (VTC) i nothing b t a sketch of the outp t voltage as a function of the i  put voltage. In this cas , the input oltage is increase from 0 to its maximum alue (VBB). When the i  put voltage is zero, the transistor is OFF and t e outp t voltage i 5 V. This is the maxi um outpu voltage that we can o  btain for this circuit. Let us la el this voltage as VOH. he transist r remains i its cutoff s tate (OFF) s long as the input voltage is l ss than 0.6 . Tran istor operation charact eristics • Base-to-emitter cut-i (turn-ON) voltage VBE(ON) = 0.6 • Base-to-emitter volta e in the active region BE = 0.7 V • Base-to-emitter volta e in the sat ration regi n VBE(sat) 0.8 V • Collector -to-emitter voltage in th saturation region VCE(sat) = 0.2 V

As soon as the inpu voltage re ches 0.6 V, the transi tor is ready to turn O . Thus, 0.6 V is the maximum input voltage that we can apply to the transist r and keep it in its cutoff mod . Let us label it as VIL. hese volta es are sho n in Figure 2.

Figure 2: Transfer ch racteristic f an RTL I verter  When th input voltage increases above 0.6 V, the tr ansistor enters its active region. As soon as the input voltage goes above 0.7 V, the base-to-emitter  oltage in t e active region is 0.7 V. The remainder  f the applied voltage i the voltag drop acro s RB, hich resul s in the base current a d thereby t e collector  current. As the collect r 

4

current begins to flow in the transistor, the output voltage begins its decline. As the input voltage increases, the base current increases, the collector current increases, and the collector-to-emitter voltage decreases. The operation in the active region continues until the collector-to-emitter voltage becomes equal to its saturation voltage. The transistor is now at the verge of saturation. The collector current is 10.21 mA. If β = 100, the base current is 0.1021 mA. Let us denote de note the input voltage that forces the transistor to enter the saturation region as VIH. Note that VIH is the minimum value of the high-input voltage and is given as

If we denote the corresponding low output voltage as VOL, then VOL = VCE(sat) = 0.2 V. These voltages are also shown in Figure 2. As the input voltage increases above 1.82 V, the output remains at 0.2 V and the transistor goes into deep saturation. The operation in the deep saturation region continues until the input voltage reaches its maximum value. SUMMARY: In the above discussion we have defined some terminology pertaining to the RTL circuit. We will use this terminology for all types of gates. Therefore, let us formally define it.

Voltage Transfer Characteristic VOH = Nominal High Output Voltage This is the output voltage that corresponds to logic 1 (high) and it may vary with the loading and temperature. The manufacturers usually specify its minimum value in order  to compensate for the component tolerances and variations in the loading conditions. VOL = Nominal Low Output Voltage This is the gate output voltage that corresponds to logic 0 (low). The manufacturers usually specify its maximum value. VIH = High input voltage at which |dvo/dt| = 1 The minimum input voltage that is interpreted as logic 1 (high) by the gate. VIL = Low input voltage at which |dvo/dt| = 0 The maximum input voltage that is interpreted as logic 0 (low) by the gate. Transition Region: The region between VIL and VIH is called the transition region.

Transition region is mostly the active region and it is the forbidden region for the logic circuit. The input voltage should either be low (less than or equal to VIL) or high (greater than or equal to VIH). If there is a random noise in the system, it should be small enough such that it does not drive the transistor into the forbidden region. Transition Width: It is the difference between the two input voltages (VIH – VIL). For  RTL gate, the transition width is 1.22 V.

5

 Logic Swing: The difference between the two output voltages (VOH – V OL) is designated as the logic swing. For the RTL under discussion, the logic swing is 4.8 V.

 Noise Margins The input signal to a gain can be corrupted by some unwanted and unexpected signal. If the gate is not properly designed the unwanted signal can force the gate to malfunction. A noise margin is the figure of merit for the gate. If the noise margin is high the gate is less susceptible to malfunction. We define the noise margin for each level of  the input signal. Thus, we have the definitions for the lower- and upper-noise margins for  the low- and high-level of the input signal. These margins are defined as follows: The Lower Noise Margin: NML = VIL – VOL

By definition, it is the difference between the maximum allowed input voltage that can be interpreted as low by the gate and the actual low output voltage of the   preceding stage driving the gate. For the RTL circuit we just analyzed, the maximum input voltage that can be interpreted by the gate as low is 0.6 V. The gate usually receives the input signal from the other gate whose minimum output is 0.2 V. Then the lower  noise margin is 0.4V=(0.6V – 0.2V). Keep in mind that each gate generates a random noise voltage, however small it may be. For the RTL gate under discussion, the largest random noise voltage that can corrupt the low input signal is 0.4 V. The reason, of  course, is that when the random noise voltage is added to the input voltage, the total voltage should be less than or equal to the maximum input voltage that is interpreted as low by the gate. Since the actual input signal voltage is 0.2 V, the maximum input voltage that can be added to it is 0.4 V, which is simply the lower noise margin. The Upper Noise Margin: NMH = VOH – VIH

By definition, it is the difference between the actual output voltage of the  preceding stage driving the gate and the minimum value of the input voltage that can be interpreted as high by the gate. For the RTL gate under discussion, the maximum input voltage is VBB=5 V. The minimum input voltage that the gate can interpret as high is 1.82 V. Then, the upper noise margin is 3.18 V = (5V – 1.82V). This simply means that the largest random noise voltage that the gate can tolerate is 3.18 V. The logic circuit should still be able to interpret the input voltage as high when the upper noise margin is subtracted from the input signal. All our discussion pertains to a single RTL circuit. When it is used as a driver for other gates, its noise margins are bound to change, as we will show later.

6

Dynamic Response of Logic Gates An important figure of merit to describe logic gates is their response in the time domain. The rise and fall times, tf  and tr , are measured at the 10% and 90% points on the transitions between the two states as shown by the following expressions: V10% = VL + 0.1ΔV V90% = VL + 0.9ΔV = VH – 0.1ΔV Where ΔV = VH – VL. Rise and fall times usually have unequal values; the characteristic shapes of the input and the output waveforms also differ.

Propagation Delay •

Propagation delay describes the amount of time between a change at the 50%   point input to cause a change at the 50% point of the output described by the following: V 50%

=

V H

+ V L 2

7

•

The high-to-low propagation delay, τPHL, and the low-to-high propagation delay,

τPLH, are usually not equal, but can be described as an average value: τ P

=

τ PLH

+ τ PHL 2

8

Pre – Laboratory RTL Inverter Propagation Delay In this laboratory the concept of propagation delay is addressed for the RTL inverter using PSPICE to simulate Transient behavior. The RTL inverter circuit is shown in Figure 5.

Figure 5: RTL Inverter Schematic Circuit Circuit description and specific parameters

The input voltage

vin is a PULSE waveform with an amplitude of 5V, the rise time

(TR) and fall time (TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of  200 NS and a period (PER) of approximately 500 NS.

The transistor used in all simulations will be a 2N2222 with the following model  parameters for both Netlist and Schematic circuit.

.MODEL parameters for the npn transistor are: IS=1E-14 A, BF=50, VAF=80 V, TF=0.45NS, TR=5NS, CJE=7.6PF, CJC=3PF, RB=13, RC=6.2

9

Pre – Laboratory Procedure 1

1. Use PSPICE to get the transient response for the circuit shown in Figure 5. 2. Plot both Vin and VCE as outputs superimposed on the same plot. 3. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's questions. 4. Determine τPHL and τPLH for the simulation and record the values in the report's questions. 5. Print the plot.

Pre – Laboratory Report 1. What are the values for : VIL =

_____ 

VIH =

_____ 

VOL =

_____ 

VOH =

_____ 

2. Calculate τPLH and τPHL for the simulation.

τPLH =  __________________ 

τPHL =

_________ 

3. What is the propagation delay of the gate?

τP =

1

_________ 

First become familiar with the MicroSim PSPICE software installed on the PC Lab (INCADEL or 

CRAY). Refer to the manual for PSPICE for getting started in the construction of a circuit, adding Specific

Parameters

for

Transient

https://ece.uprm.edu/seminarios/.

Analysis

and

for

other

tips

for

plots

or

visit

10

Laboratory rocedure RT

Inverter

oltage T ansfer Ch racteristi

1. Wire he circuit s own in Fig re 6. 2. With your Multi eter, meas re the base-emitter, base-collector, collector-e itter, and collector DC voltages,

ith respec to ground, and meas re the bas and

collector DC curr ents, recording your val es in table 1 of the rep rt. 3. Use t e Oscilloscope with th Y-axis se sitivity set o 1 Volt/di ision and t e Xaxis sensitivity at 0.5 Volts/division. 4. Adjust the X zer  reference to the scre n center and the Y ref  rence belo

the

cente . 5. The i  put VS is a sine wave rom a function generat r with a pe k amplitud of 5 Volts and frequency of 100 Hertz. 6. Draw a rough sk etch of the characteris ic displayed on the oscilloscope in the Grap ic 1(Indica e the scales that were used) of the eport and ask the question.

7. Deter  ine VIL, V IH, V OL, an VOH for th VTC displayed on the oscilloscope and recor  the values in the repor  's questions.

Figure 6

11

Laboratory Report Table 1

DC Parameters

 I C   I  B V C  V  BC  V  BE  V CE 

Graphic 1

Measured Measured Valued Valued Vin = 0V Vin = 5V

12

1. Record the values of VS corresponding to the VC values given below from the transfer curve displayed on the oscilloscope. VC = 4V

Vin =______V.

VC = 3V

Vin =______V.

VC = 2V

Vin =______V.

2. What are the values for : VIL =

_____ 

VIH =

_____ 

VOL =

_____ 

VOH =

_____ 

3. What are the noise margins for the Gate?  NMH = ____________   NML = ____________ 

13

EXPERIMENT 02 7400 Standard NAND Gate: Transient Analysis and Voltage Transfer Characteristic. Objectives 4. Examine the TTL characteristics. 5. Familiarize with electrical properties of logic gates built from bipolar transistors (TTL). 6. Build and test logic gate networks for measure its voltage transfer characteristics, Propagation delay, Fan-Out, and power dissipation of the 7400 TTL NAND.

Required Equipments

• • • • •

Oscilloscope Power supply Function generator  Digital Multimeter  Bread-Board o Protoboard

Required Parts list

• • • • • •

1 200 Ω ¼-watt resistor  1 510 Ω ¼-watt resistor  2 1 K Ω ¼-watt resistors 1 10 K Ω potentiometer  1 1N4148 Diode 1 7400 TTL NAND gate

Background  Now that we have studied the characteristics of the saturating transistor inverter, we have the knowledge in place to understand the behavior of the transistor-transistor  logic or TTL. For years, TTL has been a workhorse technology for implementing digital functions and for providing “glue logic” necessary in microprocessor system design. TTL is interesting from another point of view since it is the only circuit that we shall encounter  that makes use of transistors operating in all four regions of operation—forward-active, inverse-active, saturation, and cutoff. The classical TTL inverter shown in Figure 1 solves is the typically circuit found in TTL unit logic in which several identical gates are packaged together in a single dualin-line package, or DIP. Transistor Q1 controls the supply of base current to Q2. Input voltage V i causes the current iB1 to switch between either the base-emitter diode or the  base-collector diode of Q1. Q2 forces the output low to VCESAT2. The load resistor is an

14

active pull-up circuit formed by transistor Q4 and diode D1. Q3 and D1 are required to ensure that Q4 is turned off when Q2 is turned on and vice versa.

Figure 1 A complete standard Two-input TTL NAND gate is shown in the schematic in Figure 2. If any one of the two input emitters is low, then the base current to transistor Q 3 will be zero and the output will be high, yielding Y =  AB .

15

Figure 2 In this lab, you will know the electrical properties of logic gates built from bipolar  transistors (TTL) Power Dissipation

Power dissipation is the power lost in the transistors of a logic gate. Since modern integrated circuits involve millions of transistors, it is important to minimize this power  loss (the very first Pentium CPU had 3.2 million transistors). y measuring the input characteristics and the transfer characteristics of all the chips, we can assess the power loss of each chip. The current flowing into a gate at any  point is a good indication of power dissipation. To assess the amount of power dissipated  by a gate at a specific state, we simply measure the current flowing into the gate at that state. A comparison of the output voltage to the input voltage during a change in state of  a logic gate can provide information on how much power is lost as the gate switches. In the plot of output voltage versus input voltage, the slope indicates the amount of power  dissipation. A steeper slope indicates smaller power dissipation.

Pre-Laboratory Procedure Perform the following simulations for the 7400 TTL NAND of the Figure 2. 1. DC transfer characteristics: Use the DC command to step Vin from 0 to 5V in

16

0.1V increments. Obtain the plot of the DC transfer curve Vout versus Vin using PROBE. 2. Transient response: Carry out a transient simulation and obtain the plot of Vin and Vout using PROBE. Use Vin as a PULSE waveform with an amplitude of 5 Volts, rise and fall times equal to 2 NS and delay time equal to 0 NS, set the pulse duration for 50 NS and pulse period for 100 NS.

Pre-Laboratory Report 1. For the 7400 TTL NAND gate, determine VIH, VOH, VIL, VOL and the break   points from the DC simulations. 2. From the transient simulations, determine τPHL and τPLH and calculate the average  propagation delays for TTL NAND gate. 3. Calculate the average power dissipation for the circuit.

Laboratory Procedure Part A: Electric Characteristics

1. Assemble the circuit in Figure 3 using the 7400. a. Mount the 7400 (TTL) carefully and firmly with the pins in the center rows of  your breadboard. Connect the 5-volt DC supply to VCC and connect ground to GND of the 7400.  b. Connect pin 1 to the +5V supply via the 1k Ω resistor, connect pin 2 to one of  the probes of the digital Multimeter (DMM), and leave the other probe unconnected. Use the DMM to measure the input current when the second   probe is connected to +5V via the 1k  Ω resistor (pin 2 is pulled high), and when the second probe is connect to ground via the 510Ω resistor (pin 2 is  pulled low). Use the DMM to measure the output voltage at pin 3 as the input voltage is changed. Record the readings, indicating the polarities, in the Table 1 of the report. c. Remove the 7400, and replace it with the 74LS00 and repeat step a and b. You can use the same circuit configuration because the pin locations for all two chips are exactly the same.

17

Figure 3 2. Assembl the circuit n Figure 4 sing the 74 0. 3. Vary the input voltage from zero to maximu  by adjusti g the poten iometer. 4. Measure he indicate voltages, i and VO, u ing either t e digital M ltimeter or  the oscill scope. Rec rd the read ngs in Table 2 of the re ort. 5. Remove he 7400, and replace it ith the 74 S00 and re eat step 3 a d 4.

Figure 4 Note: For the de ails of the pin-outs and other devic characteristics, see the specificatio sheets at the bac of your manual, or the Motorola eb site.

18

Part B: Dynamic Behavior

1. Assembl the circuit n figure 5 using the 74 0 2. Using th function enerator, p oduce a 5  peak-to-p ak triangular wave at 1 KHz. Adjust the DC Offset on the function enerator to create a positive unipol r  wave, which means t e signal ne er drops below zero. 3. Use chan el 1 of the oscilloscop to measure Vi and cha nel 2 to measure VO. S t  both cha nels of the scilloscope to DC coupling. 4. Sketch the waveform of V O vers s V i on the graphic 1 provided in the laborato y report. Indicate the scales that were used. 5. To display the output voltage (V ) versus th input volt ge (Vi) waveform on t e oscillosc   pe, Turn Time/divisio button to XY. The waveform th t you obtain displays hannel 2 ( O) versus channel 1 (Vi). Chann l 2 is on t e y-axis and channel 1 is on the x-axis. 6. Remove he 7400, and replace it

ith the 74 S00 and re eat step 2 t 5.

Figure 5 art C: Fan-Out for th 7400 TTL NAND

1. Connect he circuit as shown in figure 6 usin the 7400. 2. VS is a sine wave with ampli ude of ap roximately 5 Volts a d frequency approximately 100 H . Set the o cilloscope in the DC a d X-Y mod s. 3. Plot the C transfer  urve displayed on the scilloscope for a fan-o t of 6 on t e graphic 2 of the repo t. Indicate t e scales th t were used.

19

Figure 6 4. Connect he output f one gate to the six i   puts of the remaining three NAN gates (as shown in Figure 7) and plot the D transfer c rve for a fa n-out of 6 on the graphic 3 of the r  port. Indicate the scale that were used. 5. Determine the average power dissipation in t e IC by m asuring the current being supplied y V CC. Use an analog DC Multi eter for the dc current easurement.  Do NOT  se the digit al Multimet  r for the current measurement. 6. Remove he 7400, and replace it

ith the 74 S00 and re eat the step 1 to 5.

Figure 7

20

Laboratory Report Table 1 V-I Characteristic Input current when pin 2 is high Output voltage when pin 2 is high Input current when pin 2 is low Output voltage when pin 2 is low

7400

Table 2 Voltage Characteristics

v

i

0V 2V 4V 6V 8V 10V

Graphic 1(7400 and 74LS00)

7400 vO

74LS00 vO

74LS00

21

1. From the input current values that were measured in Part A-1, which is the power  dissipation for both chips? Explain your reasoning.

2. Using the table of measured values that you obtained in Part A-4 plot VO versus Vi for the 7400 and 74LS00 in different colors.

3. Refer to the data sheet of the DM7400 to obtain the value of VIH. VIH is the Manufacturer’s minimum level for an input 1. On the graph you just plotted, draw a vertical line at Vi =VIH. Does the chip operate within this specification? Explain your reasoning. You may want to look at the typical values for V OH  and V OL.

22

4. From the data sheet of the DM7400, find the value of VIL. This is the manufacturer’s maximum level for and input 0. On the graph of the previous   page, draw a vertical line at Vi = VIL. Does the chip operate within this specification? Explain your reasoning.

5. Compare the static and dynamic measurements of the transfer characteristics for  the 7400 and explain your conclusions.

Graphic 2(7400 and 74LS00)

23

Graphic 3(7400 and 74LS00)

6. What are the noise margins (NML and NMH) for a fan-out of 2 and 6 for both chips?

7. How much is average power dissipation in both chips?

24

EXPERIMENT 03 Analysis of a Schottky RTL inverter Objectives 7. 8. 9.

Examine the Schottky RTL characteristics. Familiarize with the internal working of the Schottky RTL circuits. Design and analyze a Schottky RTL inverter and determine its input-output characteristics, Propagation delay, and noise margins.

Required Equipments • • • • •

Oscilloscope Power supply Function generator  Digital Multimeter  Bread-Board o Protoboard

Required Parts list • • • • • •

10 K Ω ¼-watt resistor. 470 Ω ¼-watt resistor. 0.1uF capacitor. 1N4148 diode rectifier. 2N2222 NPN silicon transistor or equivalent.  NTE583 or NTE584 Schottky diode.

Background A serious problem that severely limits the switching speed of BJT inverter is the amount of time required to remove the enormous stored charge from the base of a saturated BJT. The Schottky-clamped transistor drawn in figure 1 was developed to solve this problem. The Schottky-clamped transistor consists of a metal semiconductor  Schottky barrier diode (SBD) in parallel with the collector-base junction of the  bipolar transistor.

When conducting, the forward voltage drop of the Schottky diode is designed to be approximately 0.30 to 0.45 V, so it will turn on before the collector-base diode of the bipolar transistor becomes strongly forward-biased. Referring to Figure 1, we see that

v

CE  =

v

 BE  −

v

SBD

= 0.70V − 0.30V = 0.4 V

25

Figure 1: Schottky-clamped transistor.

If the input current in increased, the SBD will begin to conduct at VSBD(ON) = 0.3V. Hence, the base-collector junction reaches the forward-bias of VBC = 0.3V. Any further increase in current i B entering this configuration will be diverted from the base of  the BJT, though the SBD, and turn into the collector of the BJT. Thus, VBC is limited to VSBD(ON) = VBC(HARD)= 0.3V. This BJT – SBD combination is called a Schottkyclamped BJT (SBJT) or Schottky transistor and the BJT cannot operate in saturation. Hence, the time consuming saturation stored-charge removal (and insertion) for the base is eliminated. ’

The mode of operation where the BJT is forward active and the Schottky diode is conducting is referred to as the “on hard” mode. This mode is similar to saturation with VBE increased to 0.8V, except VBC is only forward biased to 0.3V. An SBJT inverter is shown in Figure 2.

Figure 2: Schottky RTL inverter  Invention of this circuit required a good understanding of the exponential dependence of the BJT collector current on base-emitter voltage as well as knowledge of the differences between Schottky and PN  junction diodes. Successful manufacture of the circuit relies on tight process control to maintain the desired difference between the forward drops of the base-emitter and Schottky diodes.

26

Pre – Laboratory Schottky RTL Inverter Propagation Delay

In this laboratory the concept of propagation delay is addressed for the Schottky RTL inverter  using PSPICE to simulate Transient behavior. The Schottky RTL inverter circuit is shown in Figure 3.

Figure 3: Schottky RTL Inverter  Circuit description and specific parameters

The input voltage VS is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time (TF) equal to 10 NS, delay time (TD) equal to 0 NS, a duration (PW) of 200 NS and a period (PER) of  approximately 500 NS. The transistor used in all simulations will be a 2N2222.

Pre – Laboratory Procedure 6.

Use PSPICE to get the transient response for the circuit shown in Figure 3.

7.

Plot both

8.

Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's

v

questions.

in

and

v

OUT

as outputs superimposed on the same plot.

27

9.

Determine τPHL and τPLH for the simulation and record the values in the report's questions.

10. Print the plot.

Pre – Laboratory Report 4.

5.

What are the values for :

VIL =

_____ 

VIH =

_____ 

VOL =

_____ 

VOH =

_____ 

Calculate

τPLH and τPHL for the simulation.

τPLH =  __________________  6.

τPHL =

_________ 

What is the propagation delay of the gate?

τP =

_________ 

Laboratory Procedure Schottky RTL Inverter Voltage Transfer Characteristic 8.

Wire the circuit shown in Figure 4, the input voltage VS = 0V.

9.

With your Multimeter, measure the base-emitter, base-collector, collector-emitter, and collector  DC voltages, with respect to ground, and measure the DC currents and record your values in table 1 of the report.

10. Set the input voltage at 5V and repeat the step 2. 11. Use the Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at 0.5 Volts/division. 12. Adjust the X zero reference to the screen center and the Y reference below the center.

28

Figure 4 13. Wire the circuit shown in Figure 5. 14. The input

v

S

is a sine wave from a function generator with a peak amplitude of 5 Volts and

frequency of 100 Hertz. 15. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1(Indicate the scales that were used) of the report and ask the question.

16. Determine VIL, VIH, VOL, and VOH for the VTC displayed on the oscilloscope and record the values in the report's questions.

Figure 5

29

Laboratory Report Table 1

DC Parameters

V C  V  BC  V  BE  V CE   I’ B  I  B  I SBD  I’C   I C  Graphic 1

Measured Measured Valued Valued Vs = 0V Vs = 5V

30

4.

Record the values of VS corresponding to the VC values given below from the transfer curve displayed on the oscilloscope.

5.

6.

VC = 4V

VS =______V.

VC = 3V

VS =______V.

VC = 2V

VS =______V.

What are the values for : VIL =

_____  VIH = _____ 

VOL =

_____  VOH = _____ 

What are the noise margins for the Gate?  NMH = ____________   NML = ____________ 

7.

Compare this experiment’s results with experiment one’s result.

1

EX ERIME T 04 NMOS Inverter Obj ctives 1. 2. 3.

Design and analyze an N OS Inverter. Determine he voltage transfer characteristic (VTC) of NMOS inve ter  Calculate a d measure th propagation elays of the MOS inverter .

Required Eq ipments • • • • •

Oscillosco e Power supply Function g nerator  Digital Multimeter  Bread-Boa d o Protoboar 

Required Parts list • • •

10 K Ω ¼- att Potentiom ter  100 nF cap citor.  NMOS

Bac ground A MOSF T can be u sed to achieve logic inversion in the sa e fashion as the BJT inve rter. The gener  lized NMOS inverter is shown in Figur e 1. The load evice may be a resistor, lik e that used in the BJT inverter, but in an actual MOSFET inverter  a better  choic for a load is another MOSFET. The inp t to this inverter is applied irectly to the gate. Hence, the input voltage is equal to t e gate to sour  e voltage VIN = VGS   No input r  esistor is needed to limit he input curre t since the ate current G of a MO SFET is essentially Zero. Th output is tak  n at the drain, and thus VOUT = VDS   Note that the voltage L across the load in Figur  1 can be dir ectly expressed as a functi n of the outpu as follows VL = VL(VOUT) = V DD - VOUT Also, since the input curr ent is negligible, the current though the lo d is equal to the drain curre t throu h the channel of the MOSF T IL = ID

2

These relations between t e voltages and currents of t e inverting N OS and the load device are used to determine th e VTC and po er dissipatio for NMOS. Figure 2 shows the  NMOS inverter wit  resistive loa , R L. The inp t to the inver  er is at the ga te of the  N-channel output transistor  NO and VIN= GS. The outp t is at the dr  in and VOUT VDS = V DD - IL R L. For VIN < VT, O is cutoff an does not conduct drain cur  ent. Since the resistor curre t is equal to t e drain urrent, with IN < VT, IRL = ID (OFF) = 0 a d the output i s VOUT = V DD.

As the inp t in increased slightly above the threshold voltage, NO b gins to condu t. At this poi t, only a small current flows and the drain voltage s slightly less than VDD. As long as VDS ≥ VGS –  VT NO is operating in the saturation region. ith further i crease of the nput, a larger  drain current onducts and t e outpu voltage conti ues to fall. T e analytical f  rm of the VT can be foun  by equating the drain curre t with t e resistor cur  ent to obtain ID (sat) =IR L or 

k 

2

(V G

− V T  ) = 2

 DD

− V  DS

 R L

Substitutin VGS = VIN and VDS = VOUT yields

k 

2

(V  IN  − V T  )2

=

V   D − V OUT   R L

Solving for VOUT, we hav e

V OUT  = −

kR L

2

(V  IN  − V T  )2 + V  DD

As V IN is f  rther increased, I D increase and the volt ge drop across RL can beco me sufficient to reduc the drain voltage such that VDS ≤ VGS –  VT. Under this condition N operates in t e linear regio n. The VTC of the resistor loaded N OS inverter h as the form sh own in Figure 3.

33

Propagation Delay

MOS logic families have the lowest power dissipation per gate of any of the logic families. This is  because of the large values of MOSFET resistance and consequently small current levels. An NMOS gate dissipates power in the same manner form as the BJT gates. That is, the power  dissipated is given by the product of the power supply voltage and average current for a NMOS inverter 

P DD

= V  DD

 I  DD (OH ) + I  DD (OL)

2

Significant additional power dissipation also occurs for NMOS families driving switching from one logic state to another. An expression for the MOS power dissipation during transient switching, called the dynamic power dissipation, is given by

P D

2 = C  L vV  DD

where CL is the total capacitance at the output of the gate and v is the frequency at which the gate is switched. Since the gate terminal is always an input terminal and the gate sinks zero current for all input voltages fan-out for MOS families is unlimited. This is true for all load devices including a P-channel MOSFET as is the case for the CMOS inverter. Thus, the fan-out based upon current limitations is infinite for all NMOS gates. The maximum fan-out is restricted, however, by the maximum propagation delay tolerable.

Resistor Loaded NMOS Inverter Dynamic Response

4

A capacita ce is present etween every  pair of termin als for a MOS FET. The gate capacitance is the dominant capaci ance and can e evaluated as the approxi ated sum of t e gate-source, gate-drain, a d gate-body capacitan e. The total ate capacitan e is the inpu t capacitance   between the ate and grou d of a resist or  loade  NMOS inver ter. When the input logic st te to a resisto loaded NMOS inverter is s witched low-t high r high-to-lo , this input ( gate) capacitance must be charge or discharged, depending upon t e direction of the input change. Load Capacitanc NMOS Inverter

on a Resistor Loade

When on resistor l aded NMO inverter drives ot er resistor l oaded NMO inverters, the inpu capacitance of each loa inverter must b charged or discharge simultaneously. A l ad capacitan e on a resisto r  loade NMOS inver ter is shown in Figure 4. The dyna ic response of a resisto r  loade NMOS inver ter is determi ed considerin this c  pacitance loa .

35

Output High-to-Low Transition

The transient characteristics of interest during the Output High-to-Low Transition are the fall time

τf  and the High-to-Low propagation time τPHL. The fall time τf  and the High-to-Low propagation time τPHL are expressed as

τ  f 

=

⎛ 1.9V  DD − 2V T  − 0.9V OL  ⎞⎤ C  L ⎡ 2(V T  + 0.1V OL − 0.1V  DD ) 1 ⎜⎜ ⎟⎟⎥ + ln ⎢ 2 ' ' W  0 . 1 0 . 9 V  + V  − ( ) k  V  V  ( ) k  V  − V   DD OL ⎝   ⎠⎦  DD T   DD T   L ⎣

and

τ  PHL

As with τf ,

=

2C  LV T  k  (V  DD '

− V T  )2

+

⎛ 1.5V  DD − 2V T  − 0.5V OL  ⎞ ⎟⎟ ' − 0 . 5 0 . 5 V  V   DD OL  ⎠ k  (V  DD − V T  ) ⎝  C  L

ln⎜⎜

τPHL is directly proportional to the load capacitance and inversely proportional to

W/L. Output Low -to-High Transition

The analysis of the output low-to-high transition involves the charging of the output load capacitance through the load resistor R L of the inverter. The transient characteristics of interest during the output low-to-high transition are the rise time τr  and the low-to-high propagation time τPLH. The rise time τr and the low-to-High propagation time τPLH are expressed as

τ r 

⎡ 0.9V  DD − 0.9V OL ⎤ =  R L C  L ln ⎢ ⎥ ⎣ 0.1V  DD − 0.1V OL ⎦

and τ  PLH 

=  R L C  L ln(2)

6

Pre-Laboratory NM S Invert r Propagation Delay Simulate t e NMOS inverters using SPICE to de termine the voltage transfer characterist ic (VTC and calculat and measure the propagati n delays. The NMOS inver ters are shown in Figures 5, 6 and 7.

Circu t description nd specific pa rameters

37

The input voltage VIN is a PULSE waveform with an amplitude of 5V, the rise time (TR) and fall time (TF) equal to 2

ηS,

delay time (TD) equal to 0

ηS,

a duration (PW) of 500

ηS

and a period (PER) of 

approximately 1 μS. VGG = 10V.

The transistors used in the simulation will be a NMOS with the following model parameters for both  Netlist and Schematic circuit.

.MODEL parameters for the NMOS are: (VTO=1 KP = 20u GAMMA = 0.37 PHI = 0.6 CBD = 3.1E-15 CBS=3.1E-15) M1 (W=10u L =5u) M2 (W=5u L =20u)

Pre – Laboratory Procedure 11. Use PSPICE to get the DC operating point for the circuits shown in Figures 5, 6, and 7 and complete the Table 1 of the pre-laboratory report. 12. Use PSPICE to get the transient response for the circuit shown in Figure 5. 13. Plot both VIN and VDS as outputs superimposed on the same plot. 14. Determine VIL, VIH, VOL, and VOH for the simulation and record the values in the report's questions. 15. Determine τPHL and τPLH for the simulation and record the values in the report's questions. 16. Print the plot. 17. Vary W/L ratio of the NMOS M1 for the circuit shown in Figure 5 and repeat step 2 to 5 18. Vary R L for the circuit shown in Figure 5 and repeat step 2 to 5

38

Pre – Laboratory Report Table 1

NMOS Inverters

DC Parameters

Measured Valued VIN=0V

Measured Valued VIN=5V

 I  D  Resistor Load 

V  DS(OUT)  I  D

Saturated Load 

V  DS(OUT)  I  D

 Linear Load 

7.

8.

V  DS(OUT)

What are the values for :

VIL =

_____ 

VIH =

_____ 

VOL =

_____ 

VOH =

_____ 

Calculate

τPLH and τPHL for the simulation.

τPLH =  __________________  9.

τPHL =

_________ 

What is the propagation delay of the gate?

τP =

_________ 

10. Make a comparative analysis of the table 1 data and explain yours reasoning.

9

Laboratory rocedure NM S Invert r Voltage

ransfer

haracteri tic

1.

Conne t the NMOS i nverter shown in figure 5.

2.

Using the DC pow r supply, var  the input voltage from

to 5 V an d use the di ital Multimeter to

determine the voltage at the outp t, and measu re the drain urrent, recording your values in table 1 of the report. 3.

Vary t e 10 k Ω pote tiometer and record the values in Table

4.

of the report.

Replace the DC input voltage VI with a sine wave from

function generator with peak amplitud

of 5

Volts nd frequency f 100 Hertz. 5.

Use th Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at 0.5 Volts/division. Adjust the X ze o reference to the screen center and the Y reference bel w the center.

6.

Draw

rough sketch of the charac eristic displayed on the oscilloscope in th Graphic 1(Indicate

the scales that were used) of the r eport. Comm nt on the imp ortant points f the graph such as V OH , V OL, V  M , noise

argins, etc.

7.

Attach a load capacit nce of 100 n to the output node.

8.

Apply a 200 Hz 0 to 5 volt square wave to the in put of the inv rter. Set the

C offset to be 2.5V.

Use th oscilloscope to plot vIN and vOUT. Determine the propagation delays,

PHL

and τPLH, of the

inverter. 9.

Draw

rough sketch of the charac eristic displayed on the oscilloscope in th Graphic 2(Indicate

the scales that were sed) of the re ort. Commen on the impor  ant points of t he graph such as

τr , τP L and τPLH.

τf ,

40

Laboratory Report Table 1

Potentiometer  Position 1K Ω 

5 K Ω 

10K Ω 

Graphic 1

DC Parameters

 I  D V  DS  I  D V  DS  I  D V  DS

Measured Measured Valued Valued VIN=0V VIN=5V

41

Graphic 2

8.

Record the values of V IN corresponding to the VDS values given below from the transfer curve displayed on the oscilloscope.

9.

VDS = 4V

VIN =______V.

VDS = 3V

VIN =______V.

VDS = 2V

VIN =______V.

What are the values for : VIL =

_____  VIH = _____ 

VOL =

_____  VOH = _____ 

10. What are the noise margins for the Gate?  NMH = ____________   NML = ____________ 

42

EXPERIMENT 05 CMOS Technology Objectives 4. 5. 6. 7.

Familiarize with the CMOS structure. Design and analyze a CMOS Inverter. Determine the voltage transfer characteristic (VTC) of CMOS inverter  Calculate and measure the propagation delays of the CMOS inverter.

Required Equipments • • • • •

Oscilloscope Power supply Function generator  Digital Multimeter  Bread-Board o Protoboard

Required Parts list • • •

.22 nF capacitor. 22 nF capacitor.  NMOS and PMOS transistors

Background A CMOS inverter is an ingenious circuit which is built forms a pair of NMOS and PMOS transistors operating as complementary switches as illustrated in Figure3.2. The main advantage of a CMOS inverter  over many other solutions is that it is built exclusively out of transistors operating as switches, without any other passive elements like resistors or capacitors. From Figure 1 note that the PMOS (pull-up transistor) is connected between V DD and the output node, VOUT, whereas the NMOS (pull - down transistor) is connected between the output node, VOUT, and the ground, GND. The principle of operation is as follows (refer also to the right part of Figure 2).

•

•

For small values of the input voltage, VIN, the NMOS transistor is switched off, whereas the pull-up PMOS transistor is switched on and connects the output mode to VDD. For large values of the input voltage, V IN, the PMOS transistor is switched off, whereas the pulldown NMOS transistor is switched on and connects the output mode to GND = 0V.

43

A better inside into the working of the CMOS inverter can be obtain by looking at its transfer and current characteristics presented in Figure 2.

The transfer characteristic  presents the output voltage vOUT versus the input voltage vIN. Note that when the input voltage increases from 0V to 5V the output voltage decreases from 5V to 0V. The current characteristic   presents the current flowing through the transistors between VDD and GND also versus the input voltage V IN. From the above characteristics we can observe the existence of three basic regions of operations denoted 1, 2, 3 in Figure 2.

•

In region 1 when 0 _ VIN < VTN The NMOS transistor is cut off, the PMOS switch is closed and V OUT = VDD i D = 0

•

In region 3 when VIN > VDD - VTN The PMOS transistor is cut off, the NMOS switch is closed and V OUT = 0 and i D=0

The fact that in regions 1 and 3 no current flows between V DD and GND, is very attractive because there is no power dissipation at this stages. This very fact is the reason that all digital circuitry is now build in the CMOS technology. In region 2 when V N < VIN < VP The transistor remains only for a short period of time, when the input voltage switches between V L and VH. 



In this region there is non-zero current flowing between V DD and GND, and some power  dissipation, which is converted into heat.

 Note that the same current flows through the PMOS and NMOS transistors, that is,

44

IDp = IDn Transient properties of the CMOS inverter In this section we will investigate basic transient properties of the CMOS inverter, that is, its dynamic  behavior during switching the input signals from low-to-high or high-to-low voltages and associated power  dissipation. Propagation delay Let us consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms are shown in Figure 3. Basic characterization of the dynamic behavior of an inverter is given by its two propagation delay times, τHL and τLH as illustrated in Figure 3. Note that these propagation times are specified with respect to the mid voltage V0.5:

Figure 3.7: Input/output waveforms for a CMOS inverter.

The propagation delay times, τHL (τLH) specifies the input-to-output time delay during the high-to-low (lowto-high) transition of the output voltage. Often, it is convenient to refer to the average propagation delay, required for the input signal to p ropagate through the inverter:

Similarly, we can define the fall time, τF , and the rise time, to change between V90% and V10% .

τ p which

specifies the average time

τR , as the time required for the output voltage

Where V10% = VL + 0.1(VH − VL) , and V90% = VL + 0.9(VH − VL)

45

The physical reason for the propagation time delay is the existence of the parasitic capacitances associated with a MOS transistor. We can combine all such capacitances into an equivalent load capacitance, Cld, as illustrated in Figure 4.

As illustrated by the voltage and current characteristics from Figure 2, during transition between low and high input voltages, there is a current flowing through the transistors forming the inverter. A part of this current charges and discharges the load capacitance which is responsible for propagation delays. If we approximate the current flowing through the load capacitance by its average value,  I avg, then the  propagation time can be estimated as:

where ΔV indicates the voltage change across the load capacitance, that is, the change of the output voltage. The value of the load capacitance of the inverter without the interconnecting lumped capacitance is in the order of 0.01pF = 10fF. We can estimate that the propagation time is in the order of τ p = 100ps = 0.1ns

Pre-Laboratory CMOS Inverter Propagation Delay Simulate the CMOS inverters using PSPICE to determine the voltage transfer characteristic (VTC) and calculate and measure the propagation delays. The CMOS inverter is shown in Figure 5.

6

Figur e 5: CMOS In verter  Circu t description nd specific pa rameters

The input voltage VIN is a PULSE waveform with an mplitude of  V, the rise ti e (TR) and fa ll time (TF)

qual to 2 η , delay time (TD) equal t

0 ηS, a du ation (PW) o f 500 ηS and a period (P R) of 

appro imately 1 μS.

The transi tors used in the simulation will be a   NMOS and MOS with t e following model  parameters for both

Pre

etlist and Sc ematic circuit.

Laborat ry Proced re 19. Use PSPICE to get he DC operat ng point for t he circuits sh wn in Figures 5 and compl te the Table 1 of the pre-la oratory repor  . 20. Use P PICE to get t e transient re  ponse for the circuit shown in Figure 5. 21. Plot b th VIN and VOUT as outputs superimposed  n the same pl ot. 22. Deter  ine VIL, VIH, VOL, and V OH for the si ulation and record the values in the r eport's questi ns. 23. Deter  ine τPHL and τPLH for the si ulation and r ecord the values in the repor t's questions. 24. Print t e plot.

47

25. Vary W/L ratio of the MOSFETs for the circuit shown in Figure 5 and repeat step 2 to 5 26. Vary CL for the circuit shown in Figure 5 and repeat step 2 to 5

48

Pre – Laboratory Report Table 1

Circuit

DC Parameters

Measured Valued VIN=0V

 I  D V OUT 

CMOS Inverter

V OUT 

11. What are the values for :

VIL =

_____ 

VIH =

_____ 

VOL =

_____ 

VOH =

_____ 

12. Calculate

τPLH and τPHL for the simulation.

τPLH =  __________________ 

τPHL =

_________ 

13. What is the propagation delay of the gate?

τP =

_________ 

Measured Valued VIN=5V

9

Laboratory rocedure CM S Invert r Voltage

ransfer

haracteri tic

10. Conne t the CMOS i verter shown in figure 6. 11. Using he DC power  supply, vary the input oltage from 0 to 5 V and u se the di ital Multimeter to determi ne the

voltage

at

the

output,

a d

measu e the drain c rrent, recordi g your v lues in table 1 of the report. 12. Replace the DC in ut voltage

IN

with a sine wave rom a function genera or with peak  amplitude of  5 Volts nd frequency f 100 Hertz. 13. Use th Oscilloscope with the Y-axis sensitivity set to 1 Volt/division and the X-axis sensitivity at 0.5 Volts/division. Adjust the X ze o reference to the screen center and the Y reference bel w the center. 14. Draw

rough sketch of the charac eristic displayed on the oscilloscope in th Graphic 1(Indicate

the scales that were used) of the r eport. Comm nt on the imp ortant points f the graph such as V OH , V OL, V  M , noise

argins, etc.

15. Attach a load capacit nce of 22 nF o the output node. 16. Apply a 200 Hz 0 to 5 volt square wave to the in put of the inv rter. Set the Use th oscilloscope to plot vIN and vOUT. Determine the propagation delays, inverter.

C offset to be 2.5V. PHL

and τPLH, of the

50

17. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 2(Indicate the scales that were used) of the report. Comment on the important points of the graph such as

τr , τPHL and τPLH.

τf ,

51

Laboratory Report Table 1

CL .22nF 

22nF 

Graphic 1

DC Parameters

 I  D V OUT   I  D V OUT 

Measured Measured Valued Valued VIN=0V VIN=5V

52

Graphic 2

11. Record the values of VIN corresponding to the VOUT values given below from the transfer curve displayed on the oscilloscope.

VOUT = 4V

VIN =______V.

VOUT = 3V

VIN =______V.

VOUT = 2V

VIN =______V.

12. What are the values for : VIL =

_____  VIH = _____ 

VOL =

_____  VOH = _____ 

13. What are the noise margins for the Gate?  NMH = ____________   NML = ____________ 

53

EXPERIMENT 06 Logic Interfacing Objectives 8. 9.

Familiarize Familiarize with TTL o pen-collector devices, three state outputs and transceivers. Design logic interface between different logic families.

Required Equipments • • •

Digital Multi-meter  Digit-lab Bread-Board o Protoboard

Required Parts list • • • • • •

10 K Ω ¼-watt Potentiometer  470Ω TTL Open-collector NAND Gate 7401 TTL NAND Gate 7400 74244 Three stage buffer gate 2 LEDs

Background Situation often arise where many components in digital system must share a common path to be able to transfer data to one another. To reduce the number of interconnections, a small set of shared lines called bus may be used. In general, outputs from different devices cannot be simultaneously present on the   bus. Consequently, for proper operation, that is, to prevent bus contention, only one of the devices connected to a shared bus can place information on the bus at any time. TTL open-collector devices permit the simultaneous connection of the outputs of two or more devices to form a bus. In many applications such as bus-organized digital systems where various outputs must be ANDed, using TTL gates with totem-pole outputs would require an AND gate with as many input lines as there are signals to be ANDed. Additional logic is created when the outputs of two or more open-collector gates are tied together, as in Figure 1. This scheme is called the wired-AND and is used to save logic gates in comparison with other methods.

54

It is not possible to interconnect TTL gates with totem-pole output stages in the configuration. configuration. Figure 2 depicts the high level current path when the outputs of totem-pole gates are tied together. Gate A dissipate a large amount of power, and Q3B is required to sink a current which may exceed its guaranteed 16mA sink  capacity. Although the main application of  the open collector gate is to allow the formation of the wire-AND, it is also useful for driving an individual load like an LED or relay. The output stage for the two-input open-collector NAND gate 7401 consists solely of the commonemitter transistor without even a collector  resistance. This gate, when supplied with a proper load resistor R L, may be   paralleled with other similar TTL gates. At the same time, it will drive from one to nine standard loads of its own series. When no other open-collector gates are tied, it may be used to drive ten loads. Their main disadvantage is that these gates are inherently slowly and more subject to noise than their totem-pole counterpart. The pull-up resistor bias can   be raised to any voltage within the  breakdown voltage of the driver transistor 

55

to enable interfacing to a system employing voltage swings, like a CMOS. To determine the value of the external pull-up resistor, we should find the upper and lower limits of the range of values the resistor can take. A maximum value is found which will ensure that sufficient source current to the loads and off current through paralleled outputs will be available when the output is logical 1. Therefore, the total leakage current determines the maximum value of R L when all driving transistors are off, as shown in Figure 4. When Vo is high so that the drivers are off, the voltage drop across R L must be less than VRL(max) = VCC – VOH(min) On the other hand, the total current through R L is the sum of the load current IIH and the leakage current IOH through each driver. Therefore, IRL = ηIOH + NIIH Where η is the number of gates wired-AND connected, and N is the number of standard loads. Note that IOH is into the output terminal and hence positive. Using equations 1 and 2, we find R L(max) L(max) = VRL(max)/IRL R L(max) L(max) = (VCC – VOH(min))/ (ηIOH +  NIIH) A minimum value for the   pull-up resistor is established when Vo is logical 0, so that the current through R L and the total sinking current from the load gates do not cause the output voltage to rise above VOL(max) even if only one driving gate is sinking all the current. Therefore, the current must be limited to the recommended maximum I OL, which will ensure that the low-level output voltage will be   below VOL(max). Since part of I OL will be supplied from the loads, the amount of current that can be allowed through R L will be reduced. Hence, neglecting the leakage currents of the turned-off drivers, we have R L(min) L(min) = VRL(min)/IRL R L(min) L(min) = (VCC – VOL(max))/ (IOL(max) – N|IIL|)

Logical 0 circuit conditions to calculate R L(min) L(min) are illustrated in Figure 5. Table 1 provides the electrical characteristics of the 7401 open-collector NAND gate.

56

Table1: Electrical Characteristics of the two-Input NAND Gate 7401

VOH (min) 2.4V VIH (min) 2V VOL (max) .4V

IOH (min) 250uA IIH (min) 40uA IOL (max) 16mA

VIL (max) .8V

IIL (max) -1.6mA

PLH

35ns PHL

8ns CL 15pF RL

4k Ω for τPLH 400Ω for τPHL

57

Three-State Outputs Another useful variant of TTL that can solve the problem of driving a common bus line by two or  more logic circuits is the three-state output arrangement shown in Figure 6. The term tri-state is also used. However, it is registered trademark of National Semiconductor Corporation, which introduced this design concept in 1970.

Figure 6 By combining the high-speed advantage of the totem-pole output with the advantages of an opencollector output, the three-state gates enable the connection of a number of gates to a common output line or bus. In addition to a totem-pole output, these gates have another terminal, called the output enable, which permits the device to function normally or the output signal to be disconnected from the rest of the circuit by going into a third state in which both output transistors are turned off, resulting in an extremely high output impedance. Therefore, a disabled gate can be assumed to have an open circuit in its output line, so that the high impedance state may be equated to the voltage level of a conductor that has no sources connected to it, that is, it is floating. The two most frequently used three-state ICs in the standard TTL logic subfamily are the 74125 and 74126 quadruple-bus buffers with independent output controls. Both are non-inverting buffers, but the former’s output for the 74125 is enabled by a logical 0 while the 74126 is enabled by an active high signal.

Three-State CMOS Buffers The CMOS three-state output buffer  has logic elements in the gate connections to each of the transistors in the final inverter, so that both may be turned off under the control of  an enable function. Figure 7 illustrates the logic diagram of such a buffer with active low-enable input. Note that additional inverters are added as  buffers or to optimize timing. The truth table of  the CMOS Buffers is shown in table 2.

58

G' 0 0 1 1

A VGP VGN 0 0 0 1 1 1 0 1 0 1 1 0 Table 2: Truth table

Y 1 0 Z Z

59

Pre-Laboratory TTL Open-Collector Outputs

60

Pre – Laboratory Procedure 27. Simulate the circuit shows in Figure 8 using PSPICE. Use 7401 and 7400 TTL OpenCollector NAND and standard NAND respectively. 28. Sweep the value of the pull-up resistor and determine the value maximum and minimum for  optimum performance and complete the Table 1 of the pre-laboratory report. 29. Connect the circuit shows in Figure 9 using PSPICE and determine how many TTL inputs can drive. 30. Simulate the circuit of Figure 10 using PSPICE and find the DC operating point and complete the Table 2 of the pre-laboratory report. 31. Simulate the circuit shows in Figure 11 using PSPICE and prove the truth table of the circuit.

Pre – Laboratory Report Table 1

TTL 7401 Figure 8

RL(Max)

RL(Min)

IRL(Max)

IRL(Min)

DC parameters

How many TTL inputs can drive the circuit of Figure 7

Table 2

Figure 10 DC parameters

VRL (High)

VOL

IOL

61

Laboratory Procedure Open-Collector TTL Outputs 18. Connect the circuit of Figure 12 with the 7401 and 7400 TTL Open-Collector NAND and standard  NAND respectively. Vcc = +5V 19. Add load to the output in order to determine the fan-out of the gate. Use the digital Multimeter to determine the output voltage and the currents in the circuit when you are adding a gate and record your values in table 1 of the report.

20. Co nnect the circuit of

Figure

13

using 7401 and 7400 TTL NAND and AND gate respectively with high input voltages and record your values in Table 1 of the report. Vcc = +5V 21. Vary the 10 k Ω potentiometer and record the values in Table 1 of the report. 22. Using the Digit lab DC switch to vary the input voltage from 0 to 5 V and use the digital Multimeter to determine the voltage at the output, and the currents in the circuit recording your values in table 1 of the report. 23. Connect the circuit shown in Figure 14. 24. Using the Digit lab DC switch to vary the input voltage from 0 to 5 V and use the digital Multimeter  to determine the voltage at the output, and the currents in the circuit recording your values in table 3 of the report. 25. Change the 7401 TTL Open-Collector NAND by the 7400 standard NAND and repeat step 7.

62

26. Connect the circuit shown in Figure 15. 27. Using the Digit lab DC switch to vary the input voltage from 0 to 5 V and use the digital Multimeter to determine the voltage at the output, and the currents in the circuit recording your values in table 4 of the report.

63

Laboratory Report Table 1

Loads VOL

VOH

IOH

IIH

IOL

IIL

1 2 3 4 5 Table 2

DC Parameters

 I  RL(OH)=  I  RL(OL)=  I  RL(OH)=  I  RL(OL)=  I  RL(OH)=  I  RL(OL)=  I  RL(OH)=  I  RL(OL)=

R L Value 410Ω  1k Ω  2.3 k Ω  5 k Ω 

VOL

VOH

IOH

IIH

IOL

IIL

64

Table 3

Figure 14

VRL (High)

VOL

IOL

VOH

IOH

VRL (High)

VOL

IOL

VOH

IOH

7401 7400 Table 4

Figure 15 7400

Compare the results obtain in table 3 and table 4 and explain your conclusions

Conclusions

65

EXPERIMENT 07 Regenerative circuits Objectives 1. 2. 3.

Wire and observe the operation of an R-S flip-flop. Wire and observe the operation of a Master-Slave J-K flip-flop level and edge triggered. Compare the wave shaping action of a regular TTL IC with a Schmitt trigger IC.

Required Equipments • • • •

Digit-lab Bread-Board o Protoboard Function Generator  Oscilloscope

Required Parts list • • • • • • • • •

7402 2-input NOR gate IC 7404 inverter TTL IC 7414 Schmitt trigger inverter TTL IC 74104 or 74105 J-K Master-Slave flip flop 74109 Dual J-K Positive-Edge-Triggered Flip-Flop with Clear and Preset 74112 Dual J-K Negative-Edge-Triggered Flip-Flop with Clear and Preset 74279 S-R flip flop with NAND 3 LEDs (2) 150Ohms resistors

Background Multivibrators are regenerative circuits that are used used to implement a variety of  simple two-state systems such as oscillators, timers and flip-flops. The most common form is the astable or oscillating type, which generates a square wave - the high level of harmonics in its output is what gives the multivibrator its common n ame. There are three types of multivibrator circuit:

• •

•

Astable, in which the circuit is not stable in either state - it continuously oscillates from one state to the other. Monostable, in which one of the states is stable, but the other is not - the circuit will flip into the unstable state for a determined period, but will eventually return to the stable state. Such a circuit is useful for creating a timing period of fixed duration in response to some external event. This circuit is also known as a one shot. A common application is in eliminating switch bounce. Bistable, in which the circuit will remain in either state indefinitely. The circuit can be flipped from one state to the other by an external event or trigger. Such a circuit is important as the fundamental building block of a register or memory device. This circuit is also known as a flipflop. A similar circuit is a Schmitt trigger .

In electronics and digital circuits, the flip-flop or bistable multivibrator is a pulsed digital circuit capable of serving as a one- bit memory. A flip-flop typically includes zero, one, or two input signals; a clock signal; and an output signal, though many commercial flip-flops additionally provide

66

the complement of the output signal. Some flip-flops include a clear input signal, which resets the current output. Because flip-flops are implemented as integrated circuit chips, they also require power and ground connections. Pulsing, or strobing, the clock causes the flip-flop to either change or retain its output signal, based upon the values of the input signals and the characteristic equation of the flip-flop. Strobing here means changing the clock; some flip-flops change output on the rising edge of the clock, and other change on the falling edge. Flip-flops can be split into two main categories: level-triggered and edge-triggered. They can further be divided into four types that have found common applicability in clocked sequential systems: these are called the T ("toggle") flip-flop, the SR ("set-reset") flip-flop, the JK flip-flop, and the D ("Data") flip-flop. The behavior of the flip-flop is described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Q(next), in terms of the input signal(s) and/or the current output, Q. Level-triggered flip-flops respond whenever a signal level changes.

Set-reset flip-flops (SR flip-flops) The SR (set-reset) flip-flop has two inputs: S (set) and R (reset). If R is active, the output goes to zero. If S is active, the output goes to one. If neither is activated, the previous state is maintained. Both inputs should not be activated simultaneously; however, if they are, the typical response is for both the inverted and non inverted outputs to have the same level.

The behavior of an SR flip-flop can be written in the form of a truth table: NOR

NAND

S

R

Q

Q(next)

S

R

Q

0

0

Q

0

1

1

1 1

0 1

0 1 Undetermined

Q(next)

Q(next)

0

0

undetermine

0

0

1

x

0

1 1

0 1

x Latch

1 Latch

Truth table for an SR flip flop with NOR and NAND gates We can implement a SR flip-flop with a pair of either  NAND or  NOR gates. The NOR version is conceptually easier as it has active high inputs. However, the NAND version is more widely known and used, as NAND gates were cheaper in transistor-transistor logic. We can also easily add an enable input. If this is implemented in the same gates as the flip-flop, then it serves to further invert the inputs - meaning a NAND based device will now have active high inputs. This input may be regarded as a clock but the flip-flop is still unsuitable for sequential design. When the clock goes high, the signal will propagate through all flip-flops, not just from one to the next.

7

S flip-flops cir  uit diagrams nd the symbols for an un-cl cked SR flip- flop

clocked SR fli p-flop and the ymbol for a clocked SR flip -

A flop

E ge-triggered flip-flops nly change state on a particular ed e (rising, f  lling, or ve y occa ionally bot directions) of a design ted clock signal. JK flip-flop

T e JK flip-flop augments the behavior of the S flip-flop b interpreting the S = R = 1 co dition as a "flip" command. Specifically, the combination J = 1, K = 0 is a command to se the flip-flo p; the combination J = 0, K = 1 is command to reset the flip-flop; and the combination J = K = 1 is a comman to toggle the flip-flop, i.e., chang its output o the l gical comp ement of its current val e. Setting = K = 0 results in a D- ype flip-flo . The K flip-flop is therefore a universal lip-flop, because it can be configur ed to work  s an S flip-flop, D flip-flop or a T flip- lop. The symbol for a clocked J-K flip- lop A circuit s mbol for a JK  flip-flop, wh re > is the clo ck input, J an K  are data inputs, Q is the stored dat output, and Q' is the invers of Q.

The char  cteristic eq ation of the JK flip-flo is:

and t e correspo ding truth table is: J

K

Q

Q(n xt)

0

0

Latch

Lat h

0

1

1

0

1

0

0

1

1 1

1 1

0 1

1 0

68

SCHMITT TRIGGER In electronics, a Schmitt (or  Schmidt) trigger is a comparator circuit that incorporates positive feedback. When the input is higher than a certain chosen threshold, the output is high; when the input is  below another (lower) chosen threshold, the output is low; when the input is between the two, the output retains its value. The trigger is so named because the output retains its value until the input changes sufficiently to trigger a change. This dual threshold action is called hysteresis, and implies that the Schmitt trigger has some memory. The benefit of a Schmitt trigger over a circuit with an only single input threshold is greater  stability (noise immunity). With only one input threshold, a noisy input signal near that threshold could cause the output to switch rapidly back and forth from noise alone. A noisy Schmitt Trigger input signal near one threshold can cause only one switch in output value, after which it would have to move to the other threshold in order to cause another switch. The Schmitt trigger was invented by US scientist Otto H. Schmitt. The symbol for Schmitt triggers in circuit diagrams is a triangle with a hysteresis symbol.

Pre-Laboratory Regenerative circuits Wire and test one J-K flip flop from the CMOS 4027 dual J-K flip flop IC. Observe and record your  values in table 1.

Pre – Laboratory Report Table 1 Inputs Mode of operation

Asynchronous

Outputs

Synchronous

PS

CLR

CLK 

J

K

Asynchronous Set

0

1

x

x

x

Asynchronous reset

1

0

x

x

x

Prohibited

0

0

x

x

x

Hold

1

1

0

0

Reset

1

1

0

1

Set

1

1

1

0

Toggle

1

1

↑ ↑ ↑ ↑

1

1

Preset

Clear

Clock 

Data

Data

Q

Q'

1

1

No change

Laboratory Procedure Regenerative circuits 1.

Wire the logic circuit of the R-S flip-flop shown in Figure. Wire outputs Q and Q’ to two LEDs.

9

2.

Operate the input switches R and S as s own in the tr  th table in Ta le 2. Observe and record the results in t e Q and Q’ co lumns.

3.

In the right column of Ta le 1, write the name of the condition of th outputs. Use the term “Hold,” “S t,” or “reset.”

4.

Operate the input switches R and S as s own in the tr  th table in Ta le 3 using the 74279 R-S fli flop and re ord the results in the Q and

5.

’ columns.

ire outputs Q and Q’ to two LEDs.

In the right column of Ta le 2, write the name of the condition of th outputs. Use the term “Hold,” “S t,” or “reset.”

6.

Construct t e circuit of th e clocked R-S flip flop with  NAND. Wire outputs Q and Q’ to two LEDs.

7.

Operate the input switches R and S as s own in the tr  th table in Ta le 4. Observe and record the results in t e Q and Q’ co lumns.

8.

Insert the 74LS112 IC into the mountin board.

9.

Wire the synchronous inputs PS and CL R to two swit hes. Wire the asynchronous inputs J an K to switche and the CLK  input to a sin le pulse clock . Wire outputs Q and Q’ to t o LEDs.

70

10. Operate the asynchronous inputs PS and CLR and record the results in Table 5. 11. In the right-hand column of Table 5 write the condition of the output. Choices are listed. 12. Disable the asynchronous inputs (PS and CLR to 1). 13. Operate the synchronous inputs J, K and CLK of the 74LS112 IC according to the truth table in Table 6. Observe and record the results in column Q and Q’. 14. In the right-hand column of Table 6 write the condition of the output. Choices are listed. 15. Insert the 7404 and 7414 ICs into the mounting board and wire the circuits shown in the Figure.

16. Set Vin with the function generator. Set the function generator to sine wave. Set the frequency from 50 to 200 Hz. Adjust the function generator voltage to 2 to 4 V p-p. 17. Use the Oscilloscope to observe the output waveforms for the circuits. Draw a rough sketch of the characteristic displayed on the oscilloscope in the Graphic 1 and 2(Indicate the scales that were used) of the report.

71

Laboratory Report Table 2

NOR Name of S

R

0

0

0

1

1

0

1

1

Q

Q(next)

condition

Table 3

R-S flip-flop 74279 Name of S

R

0

0

0

1

1

0

1

1

Q

Q(next)

condition

Table 4 Inputs

Clock CLK

Outputs

Data

Before clock pulse

After clock pulse Q

S

R

Q

Q'

0

0

0

1

0

1

0

1

1

0

0

1

1

1

0

1

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

0

Q'

 Name of condition

Prohibited

Prohibited Hold, reset, or set

72

Table 5 Inputs

Outputs

Clear

Preset

0

0

0

1

1

0

1

1

Q

Q'

Name of Condition Prohibited

Clear Q to 0 Disable Preset Q to 1

Table 6 Inputs

Outputs

Before clock 

After clock 

 pulse

 pulse

Clock

Data

CLK

J

K

Q

Q'

↑

0

0

0

1

↑

0

1

0

1

↑

1

0

0

1

↑

1

1

0

1

↑

0

0

1

0

↑

0

1

1

0

↑

1

0

1

0

↑

1

1

1

0

PS and CLR=1

Q

 Name of condition Q'

Hold, reset, set, or toggle

73

Graphic 1(7404)

Graphic 2(7414)

Which IC seems to do the best job of converting the sine wave into a sharp square wave?

4

EX ERIME T 08 D\A and A/D converters Obj ctives 4. 5. 6. 7.

To connect an analog-toTo calculate A/D accurac To connect an analog-toTo calculate D/A accurac

igital (A/D) c rcuit and perf  rm an A/D co nversion and resolution igital (D/A) c rcuit and perf  rm an D/A co nversion and resolution

Required Eq ipments • • • • •

Digit-lab Bread-Boa d o Protoboar  Function Generator  Oscillosco e Digital Multimeter 

Required Parts list Resistors • • • • • •

1 K (3) 2 K (6) 10 K 30 K 100 2.5k

Integrated Circuits • •

LM741 DAC0808

Potencio eters •

10 K

(2)

Diodes •

Led (2

Ca acitors •

15 pF

Bac ground Analog-to-Digital Converter  The proces of converting an analog voltage to a digit l coded signal is known as analog-to-digit l conve sion. It is usu lly referred to as A-to-D (A D) conversio . When an a alog signal i digitized, the signal is conve ted to an e uivalent digital number at regular  interv ls, called sam ple intervals, s seen in Figure

Fig re 1: Analog ignal is sampled at regular i tervals

75

The typical A/D converter will have eight output lines. Each line is capable of being a logic 1 or 0. Each binary digit is called a bit –an acronym for  binary digit . Thus such an A/D device is called an 8 nit A/D converter. Now assuming that each of the eight output lines could be a logic 1 or 0, there are 28, or  256, different binary codes which can be represented by the 8-bit A/D converter. Assume an input voltage of 0V to the A/D converter; its output would be the binary equivalent, or 00000000. For each input voltage level there will be a specific equivalent binary output on the eight output lines. Resolution and accuracy

Resolution of an A/D converter is defined as the smallest increment input voltage that can be determined by the converter. Resolution is primarily a function of the number of output bits. For example, if the converter has 256 different outputs codes, the input signal is represented by binary numbers from 00000000 to 11111111. If the input ranges from 0 to 5 V, the resolution is

5V  256

= 0.0195V 

Thus, the binary output of 00000001 represents 0.0195 V. Likewise, 00000010 represents 0.039 V, and so on. What would be the binary representation of, say, 3.042V? Clearly,

3.042V  0.0195

= 156

which, when converted to binary, is 10011100. The accuracy of the A/D converter is determined by how closed the actual converter output is to the theoretical output. For example, if the 8-bit A/D converter had an accuracy expressed as ± 1 least significant bit (LSB), the accuracy could be expressed as

accuracy =

1 28

*100 =

1 256

*100 = 0.4%

Digital-to-Analog converter  In electronics, a digital-to-analog converter (DAC or D-to-A) is a device for converting a digital (usually binary) code to an analog signal (current, voltage or electric charge). Digital-to-analog converters are the interface between the abstract digital world and the analog real life. Simple switches, a network of  resistors, current sources or capacitors may implement this conversion.

The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a physical quantity, usually an electrical voltage. Normally the output voltage is a linear function of the input number. Usually these numbers are updated at uniform sampling intervals and can be thought of as numbers obtained from a sampling process. These numbers are written to the DAC, sometimes along with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant output (Figure 2). This is equivalently a zero-order hold operation and has an effect on the frequency response of the reconstructed signal.

The fact that practical DACs do not output a sequence of dirac impulses (that, if ideally low-pass filtered, result in the original signal before sampling) but instead output a sequence of piecewise constant values or rectangular pulses, means that there is an inherent effect of the zero-order hold on the effective frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (a 3.9224 dB loss at the Nyquist frequency). This zero-order hold effect is a consequence of the hold action of the DAC

6

and is not due to the sample and old that mig t precede a c nventional a alog to digital converter as is often isunderstood.

Figure 2: Piece ise constant s ignal typical of a practical D AC output.

77

Laboratory Procedure D\A and A/D converters 1.

Wire the circuit of the D/A converter as shown in Figure 1.

Figure 1: Digital-to-Analog Converter  2.

Operate the input switches as shown in the Table 1. Observe and record the results of the OPAMP output voltage. The output voltage can be calculated with the standard op-amp theory.

3.

Connect the circuit shown in Figure 2.

4.

Apply the digital inputs shown in Table 2. For each input measure the analog output voltage and record it in the table 2.

5.

Wire the circuit of the D/A converter as shown in Figure 3.

6.

Vary the potentiometers to change the comparator input voltage.

7.

Determine the switches combination to set on the LED indicator. Observe and record the results of the OPAMP output voltage.

8.

Repeat steps 5 to complete the table 3.

78

79

Laboratory Report Table 1

Output Voltage

Input Voltage

Calculated

Measured

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 2 Binary Inputs

00000001 00000010 00000011 00000100 00001000 00010000 00100000 01000000 10000000 11111111 Table 3

Measured analog output

% Error