IEEE-754 floating point multipler in Verilog

December 18, 2018 | Author: Shyam Shankar | Category: Subtraction, Multiplication, Arithmetic, Theory Of Computation, Physics & Mathematics
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Short Description

Verilog code and documentation for implementing a single precision floating point multiplier (IEEE-754 format)....

Description

+1.12462746 × 214

+1.729574441

−1

.241768056 × 2

26

.705788373 × 246

−1 69

×

+1.300467252

×

27

+1.455946207 × 222

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