HDL_MANUAL09-10

HDL LAB

IV Sem EC/TE

EXPERIMENT 1 HDL code to realize all logic gates AIM: To Simulate and realize all logic gates. COMPONENTS REQUIRED: FPGA board, FRC’s and power supply. THEORY :A logic gate is an electronic circuit/device which makes the logical decisions alternatively a logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented using diodes or transistors. The logic gates are broadly classified into 3 types: Basic gates: AND, OR, NOT / INVERTER Universal gates: NAND, NOR Special gates: XOR, XNOR Truth table with symbols

Dept. of EC/TE, VKIT

2010

Page 1 of 64

HDL LAB

IV Sem EC/TE Generalizing, c d e

a

f g h i

LOGIC GATES

b

Truth Table inputs a 0 0 1 1

b 0 1 0 1

c 0 0 0 1

d 0 1 1 1

e 1 1 0 0

VHDL CODE

g 1 0 0 0

h 0 1 1 0

i 1 0 0 1

VERILOG CODE module allgates ( a, b, c, d, e, f, g, h, i); input a, b; output c, d, e, f, g, h, i; assign c = a & b; assign d = a | b, assign e = ~a , assign f = ~(a & b), assign g = ~(a | b), assign h = a ^ b; assign i = ~(a ^ b); endmodule

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity allgates is port ( a, b : in std_logic; c, d, e, f, g, h, i : out std_logic); end allgates; architecture dataflw of allgates is begin c