GSM MODEM (GL865 DUAL) INTEGRATION WITH ARM LPC810 CORTEX FOR SURVEILLANCE APPLICATION AND VALUE ENGINEERED POWER MANAGEMENT

GSM MODEM (GL865 DUAL) INTEGRATION WITH ARM LPC810 CORTEX FOR SURVEILLANCE APPLICATION AND VALUE ENGINEERED POWER MANAGEMENT Produced by: SALEEM, Muhammad Umair Masters of Electrical Engineering Matriculation Number 25279 HS-Weingarten Supervising Professor: Prof. Dr.-Ing. Andreas Siggelkow Professor für Elektrotechnik und Elektronik Hochschule Ravensburg-Weingarten

Submission date: 2nd JUNE 2014 Faculty of Electrical Engineering Department Masters of International Engineering Program Scientific project for Summer Semester 2014 SS2014

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PREFACE AND ACKNOWLEDGMENT The motivation for this project based on surveillance application for vehicles and private possessions was provided by Prof. Dr.-Ing. Andreas Siggelkow. From the inception of this idea to the completion, Prof. Dr.-Ing. Andreas Siggelkow has been really instrumental and helpful in certain ideas and problem solving solutions for corroboration of system design. On the other hand, technical support was provided by Dipl. –Ing. (FH) Christoph Weber at different points in the entire life of this project. And lastly, my appreciation goes to the Electrical department laboratories for providing instrumental support, crucial to putting together the system in the first place. To all the above mentioned personnel and department, I present my humble gratitude and I am grateful to have you as my senior instructors.

SALEEM, Muhammad Umair Masters Electrical Engineering Matriculation number 25279 Engineering project for SS2014

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CONTENTS

1. Introduction ____________________________________ 4 2. Requirement analysis __________________________ 4 3. Specification ____________________________________ 4 3.1. LPC 810 ARM cortex ______________________ 4 3.2. GPS sensor MT3329 ______________________11 3.3. GSM modem GL865 telit dual _____________16 3.4. Telit software user guide _________________28 3.5. Power supply units ______________________31 3.6. Quad tri-state buffer ______________________34 4. 5. 6. 7.

Schematic diagram of the system _________________37 Hardware of the system __________________________38 Further improvements ___________________________39 Bibliography ____________________________________39

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1- INTRODUCTION The requirement of the construction of an apparatus that tracks on basis of GPS specifications is a well-established product of the current consumer lobby in high end policy insurance for security, tracking for monitoring basis or etc. the acquisition of data performed requires a simple GPS satellite receiver apparatus which relays data over to the controller unit for control of program logic, where its decided upon further parameters as to how it should be dealt with and finally, the data is relayed over the GSM modem via an asynchronous serial receiver and transmitter. The report presented here is to further provide insight into the general method prescribed above is carried out.

2- REQUIREMENT ANALYSIS The requirements of the project are outlined as to receive the coordinate specified data from the GPS satellite receiver antenna and transmit it to the handy as a proper structured text message. However a lot more goes into this work. Here a brief summarization of the very top level of design management for the project will be provided so as to create a picture of data reception and transmission from GPS modem to the handy. The GPS coordinates are received via the MTK 3329 satellite receiver antenna. A lot more detail about the specification of operations of the satellite receiver antenna are provided below. The data acquisition done from this stage is of the GPRMC packet. For reasons defined in detailed in the specification section of the receiver, it will be mentioned why the GPRMC provides a better standoff alternative as compared to the 3D-fix technique. The hub of the tracking apparatus can be very well the 74LS125 tri-state quad buffer. The functionality of the tri-state buffer is to get programmed with the GPIO ports of the LPC810 controller and provide for a queue session for buffering data received from the antenna and storing it in the LPC array, and finally relaying it over to the GPS modem on timely delays, via the UART. It is at this point that the AT commands are engaged for the GPS modem and data is relayed over to the handy via the telecommunication provider (SIM carrier) resource.

3- SPECIFICATION Specification details along with the functionality usage and the program coding chunks will be provided in this section of the report. The order of specification is selected as to the novelty of the model, followed by their functional description.

3.1- LPC 810 ARM CORTEX The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM. The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self-wake-up timer, and stateconfigurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. The features and benefits as described by this cortex’s user manual are as followings: System features include:

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ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single cycle I/O port. Built-in Nested Vectored Interrupt Controller (NVIC). Serial Wire Debug (SWD) and JTAG boundary scan modes supported. And Micro Trace Buffer (MTB) supported. Memory support of Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase. And Up to 4 kB SRAM. ROM API support: 

Boot loader.

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USART drivers.

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I2C drivers.

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Power profiles.

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Flash In-Application Programming (IAP)

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In-System Programming (ISP).

Digital peripherals include: 

High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 GeneralPurpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable opendrain mode, input inverter, and glitch filter.

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High-current source output driver (20 mA) on four pins.

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High-current sink driver (20 mA) on two true open-drain pins.

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GPIO interrupt generation capability with boolean pattern-matching feature on eight

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GPIO inputs.

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Switch matrix for flexible configuration of each I/O pin function.

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State Configurable Timer (SCT) with input and output functions (including capture and match) assigned to pins through the switch matrix.

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Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.

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Self-Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.

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CRC engine.

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Windowed Watchdog timer (WWDT).

Serial interfaces: Three USART interfaces with pin functions assigned through the switch matrix. Two SPI controllers with pin functions assigned through the switch matrix. One I2C-bus interface with pin functions assigned through the switch matrix.

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The LPC 810 cortex MCU comes in several packages, out of which the one employed here will be the DIP08 A block diagram for the general cortex ARM MCU is given as follows:

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Pining of the DIP: Pining information in line with the DIP08 packing module is as follows

One of the most important and novel features to the ARM LPC cortex MCU is the switch pin matrix tool. This tool, as provided with in the IDE or SDK can help alter or change the functional aspects of allowable GPIO pins in line with the functionality required.

Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in detail in the datasheet and are used according to application specifications. Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. The table describes in detail the assignment to the various pins as opposed to the vector interrupt setting or the general purpose I/O setting for configurations. Alongside this table in the IDK, there exist corresponding hex files for the respective pin assignment as well. Another feature of the LPC expresso IDK is the switch pin matrix tool. This tool is essentially a GUI (graphic user interface) designed for ease of assignment for the pin declaration as described a little earlier.

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The interface for the switch pin matrix tool in the expresso is given as under:

Pin interrupt/pattern match engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are located on the IO+ bus for fast single-cycle access. A few features are provided as under:     

Up to eight pins can be selected from all digital pins as edge- or level-sensitive Interrupt requests. Each request creates a separate interrupt in the NVIC. Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. Level-sensitive interrupt pins can be HIGH- or LOW-active. Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and powerdown mode.

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 

Up to 8 pins can be selected from all digital pins to contribute to a Boolean expression. The Boolean expression consists of specified levels and/or transitions on various combinations of these pins. Each min-term (product term) comprising the specified Boolean expression can generate its own, dedicated interrupt request.

This is the point which naturally leads us to the discussion of the UART in the LPC cortex. The LPC81X series makes use of the UARTs for serial transmission of data. The data is transmitted as a serial 8 bit data. The use of UART in cortex ARM MCU is used for the propagation of GPRS $GPRMC data protocol along the usb over serial UART.

UART for ARM: All UART functions are movable functions and are assigned to pins through the switch matrix. 

Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins except PIO0_10 and PIO0_11.

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7, 8, or 9 data bits and 1 or 2 stop bits

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Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option.

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Multiprocessor/multi-drop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.)

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Parity generation and checking: odd, even, or none.

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One transmit and one receive data buffer.

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RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output.

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Received data and status can optionally be read from a single register

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Break generation and detection.

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Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

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Built-in Baud Rate Generator.

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A fractional rate divider is shared among all UARTs.

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Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected.

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Separate data and flow control loopback modes for testing.

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Supported by on-chip ROM API.

Some other fascinating and novel characteristics of the LPC 81X series is the SPI/O is also an integral part of the LPC 81X cortex. All SPI functions are movable functions and are assigned to pins

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through the switch matrix. Comes with a Master and slave operation. Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory. This is feature is followed up by the I2C bus application. However this portion is not required and not utilized in this prevailing project, but the extension of this project into GSM add-ons may possible make use of such advantageous features. So for the lack of interest at this stage, they will not be discussed here in detail. However it is assumed that the reader of this report knows the basic ideology of the I2C application which is merely synchronization of system clock with data lines for transmission. The values given as under the limiting factors are the governing factors for the supply voltage as well current. Given below is the table from the data sheet, which includes these factors:

The operating stance of the FTDI and the LPC cortex are within the maximum limit range. So for the application purpose described at length here, the current and voltage parameters do not necessarily effect the overall performance of the system. The interrupt handler for the UART is described as under for the serial receiving of data from the GPS module and the serial transmission along the lines of the usb over serial protocol of the FTDI breakout board. The code for UART interrupt handler taken from the Expresso suit is as follows:

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void UART0_IRQHandler(void) { unsigned char temp=0;

temp = LPC_USART0->RXDATA;

if(mydevice_stat.GPS)//mydevice_stat.GPS==1 | mydevice_stat.GPS=0 { if(!myFlags.serial_data_recvd) { if(temp=='$') myFlags.start_filling=1; if(myFlags.start_filling) { myreg.buffer[myreg.counter]=temp; myreg.counter++; } if(temp==0x0A)//actual check WILL BE on 0x0A { myFlags.start_filling=0; myreg.counter=0; myFlags.serial_data_recvd=1; } } }

3.2- GPS SENSOR MT3329 The GlobalTop FGPMMOPA6C is an ultra-compact POT (Patch On Top) GPS Module, The module utilizes the MediaTek new generation GPS Chipset MT3339 that achieves the industry’s highest level of sensitivity (-165dBm ) and instant Time-to-First Fix (TTFF) with lowest power consumption for precise GPS signal processing to give the ultra-precise positioning under low receptive, high velocity conditions. Up to 12 multi-tone active interference canceller (ISSCC2011 award), customer can have more flexibility in system design. Supports up to 210 PRN channels with 66 search channels and 22 simultaneous tracking channels, FGPMMOPA6C supports various location and navigation applications, including autonomous GPS, SBAS(note) ranging (WAAS, EGNO, GAGAN, MSAS), AGPS. FGPMMOPA6C is excellent low power consumption characteristic (acquisition 82mW, tracking 66mW), power sensitive devices, especially portable applications, need not worry about operating time anymore and user can get more fun.

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GPS SoC MT3329 The FGPMMOPA6 is a POT (Patch On Top) GPS Module. This GPS receiver provides a solution that has high position and speed accuracy as well as high sensitivity and tracking capabilities in urban conditions. It supports NMEA 0183 and PMTK protocol. Features 

Sensitivity

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Position Accuracy : Without aid: 3.0 m (50% CEP) DGPS (SBAS(WAAS,EGNOS,MSAS)): 2.5 m (50% CEP)

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TIFF(Time to First Fix) :

: Acquisition -148 dBm , Tracking -165 dBm

Cold Start: