gem5

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Short Description

description of gem5...

Description

gem5 An Architectural Simulator

What do we want ? ●

To play with our ideas



What sort of Ideas





Multicore Architecture



Cache Hierachy



Cache Coherency Protocol



Microarchitecture Ideas



Interconnection Topologies

Flexible and Modular Simulation framework –

28 Aug 2013

To test ideas in diverse fields CADSL Seminar: The gem5 Simulator

2

gem5 is Flexible ●





4 CPU Models –

AtomicSimple (Fastest)



TimingSimple



InOrder



O3 (Detailed)

2 System execution modes –

System-call Emulation (SE)



Full-System (FS)

2 Memory Systems (Classic, Ruby)

28 Aug 2013

CADSL Seminar: The gem5 Simulator

3

CPU Models ●



AtomicSimple –

Minimal single IPC



Non-pipelined



Attempts to F, De, Ex, Cm on every cycle.



No memory access latency



Good choice for fast-forwarding

TimingSimple –

28 Aug 2013

+ Simulates timing of memory reference CADSL Seminar: The gem5 Simulator

4

CPU Models ●



InOrder –

“execute-in-execute” CPU



Configurable pipeline stages



Issue Width



Supports multi-threading



Instruction Timing and Memory latency

OoO (O3)

28 Aug 2013



Outer of Order



Parameterizable pipeline resources CADSL Seminar: The gem5 Simulator

5

Execution Modes ●



System-call Emulation (SE) –

Emulates most system calls (e.g. read())



Passes system call to host OS



Simplified address translation model



No thread scheduling

Full-System (FS)

28 Aug 2013



For workloads that require OS services



Support for interrupts, exceptions



More realistic CADSL Seminar: The gem5 Simulator

6

Features Available ●



For research in Micro-architecture –

Configurable superscalar architecture



Parameters for OoO in O3CPU.py

For System level

28 Aug 2013



Clock Freq



# of cores



# of threads



Parameters in Options.py CADSL Seminar: The gem5 Simulator

7

Features Available ●





Creating Checkpoint –

Beneficial if simulation time is large



To analyse in detail the region of interest

Switch over –

Switching between CPU models on fly.



From fast atomic to slow detailed

ISA Supported –

28 Aug 2013

Alpha, ARM, MIPS, Power, SPARC, x86 CADSL Seminar: The gem5 Simulator

8

Features Available ●



SLICC –

Language for Cache Coherence Protocol



Performs all operations at cache-block granuality. (Word-level X)



One can make own Cache Controller

Interconnection Network –

28 Aug 2013

CADSL Seminar: The gem5 Simulator

9

Example ●

N Queens Benchmark –

28 Aug 2013

Placing N queens on an N x N chessboard such that no queen can attack any other

CADSL Seminar: The gem5 Simulator

10

N Queens Benchmark ●

Compile: arm­linux­gnueabi­gcc ­DUNIX \  ­o ./queen/queens ./queen/queens.c ­static



Run: ./build/ARM/gem5.opt \  configs/example/se.py ­c ./queen/queen ­o 8  ­­caches –cpu­type=arm_detailed



Checkpoint: –

Compile: arm­linux­gnueabi­gcc ­DUNIX  ­o ./queen/queens ./queen/queens.c  util/m5/m5op_arm.S ­static

28 Aug 2013



Create checkpoint



Restore from checkpoint CADSL Seminar: The gem5 Simulator

11

Features yet unexplored ●

Hacking gem5



Debugging code in gem5



How multicores can communicate



How SMT can be used on multicore



Writing own cache controller

28 Aug 2013

CADSL Seminar: The gem5 Simulator

12

IMP References ●

The gem5 simulator http://dl.acm.org/citation.cfm?id=2024718



Gem5 webpage www.m5sim.org



Discussion pages http://thread.gmane.org/gmane.comp.emulators.m5.users/  http://www.mail­archive.com/gem5­[email protected]



Tutorial www.m5sim.org/Tutorials

28 Aug 2013

CADSL Seminar: The gem5 Simulator

13

Thanks :) Questions are welcome

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