gem5

gem5 An Architectural Simulator

What do we want ? ●

To play with our ideas

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What sort of Ideas

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Multicore Architecture

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Cache Hierachy

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Cache Coherency Protocol

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Microarchitecture Ideas

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Interconnection Topologies

Flexible and Modular Simulation framework –

28 Aug 2013

To test ideas in diverse fields CADSL Seminar: The gem5 Simulator

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gem5 is Flexible ●

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4 CPU Models –

AtomicSimple (Fastest)

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TimingSimple

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InOrder

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O3 (Detailed)

2 System execution modes –

System-call Emulation (SE)

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Full-System (FS)

2 Memory Systems (Classic, Ruby)

28 Aug 2013

CADSL Seminar: The gem5 Simulator

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CPU Models ●

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AtomicSimple –

Minimal single IPC

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Non-pipelined

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Attempts to F, De, Ex, Cm on every cycle.

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No memory access latency

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Good choice for fast-forwarding

TimingSimple –

28 Aug 2013

+ Simulates timing of memory reference CADSL Seminar: The gem5 Simulator

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CPU Models ●

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InOrder –

“execute-in-execute” CPU

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Configurable pipeline stages

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Issue Width

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Supports multi-threading

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Instruction Timing and Memory latency

OoO (O3)

28 Aug 2013

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Outer of Order

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Parameterizable pipeline resources CADSL Seminar: The gem5 Simulator

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Execution Modes ●

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System-call Emulation (SE) –

Emulates most system calls (e.g. read())

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Passes system call to host OS

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Simplified address translation model

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No thread scheduling

Full-System (FS)

28 Aug 2013

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For workloads that require OS services

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Support for interrupts, exceptions

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More realistic CADSL Seminar: The gem5 Simulator

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Features Available ●

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For research in Micro-architecture –

Configurable superscalar architecture

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Parameters for OoO in O3CPU.py

For System level

28 Aug 2013

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Clock Freq

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# of cores

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# of threads

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Parameters in Options.py CADSL Seminar: The gem5 Simulator

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Features Available ●

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Creating Checkpoint –

Beneficial if simulation time is large

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To analyse in detail the region of interest

Switch over –

Switching between CPU models on fly.

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From fast atomic to slow detailed

ISA Supported –

28 Aug 2013

Alpha, ARM, MIPS, Power, SPARC, x86 CADSL Seminar: The gem5 Simulator

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Features Available ●

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SLICC –

Language for Cache Coherence Protocol

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Performs all operations at cache-block granuality. (Word-level X)

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One can make own Cache Controller

Interconnection Network –

28 Aug 2013

CADSL Seminar: The gem5 Simulator

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Example ●

N Queens Benchmark –

28 Aug 2013

Placing N queens on an N x N chessboard such that no queen can attack any other

CADSL Seminar: The gem5 Simulator

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N Queens Benchmark ●

Compile: arm­linux­gnueabi­gcc ­DUNIX \  ­o ./queen/queens ./queen/queens.c ­static

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Run: ./build/ARM/gem5.opt \  configs/example/se.py ­c ./queen/queen ­o 8  ­­caches –cpu­type=arm_detailed

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Checkpoint: –

Compile: arm­linux­gnueabi­gcc ­DUNIX  ­o ./queen/queens ./queen/queens.c  util/m5/m5op_arm.S ­static

28 Aug 2013

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Create checkpoint

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Restore from checkpoint CADSL Seminar: The gem5 Simulator

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Features yet unexplored ●

Hacking gem5

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Debugging code in gem5

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How multicores can communicate

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How SMT can be used on multicore

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Writing own cache controller

28 Aug 2013

CADSL Seminar: The gem5 Simulator

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IMP References ●

The gem5 simulator http://dl.acm.org/citation.cfm?id=2024718

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Gem5 webpage www.m5sim.org

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Discussion pages http://thread.gmane.org/gmane.comp.emulators.m5.users/  http://www.mail­archive.com/gem5­[email protected]/ 

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Tutorial www.m5sim.org/Tutorials

28 Aug 2013

CADSL Seminar: The gem5 Simulator

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Thanks :) Questions are welcome