GATE+ISRO DIGITAL LOGIC AND COMPUTER ORGANIZATION 2015_sequential circuits

GATE + ISRO 2015 ( Quick Reference )

Computer Science & Information Technology ( Digital Logic + Computer Organization ) ( First Edition )

REJIN R

ARAVIND PRASAD A G

 MTech  MTech CSE,

MTech MTech CSE,

Coll ollege of Engi ngineering, Triv rivand andrum

Coll ollege of Engi ngineering, Triv rivand andrum

 BTech  BTech IT,

BTech BTech CSE,

Govt. Engineering College, Idukki

College of Engineering, Chengannur 

“ There There is noth nothing ing new new under under the sun sun . It has has all all been been done done befo before. re. ”  – [A Study in Scarlet]

Sir Arthur Conan Doyle Doyle

Preface Dear Reader, Please hang on a minute and just read through before proceeding further. “ If you want to know the answer answer of any ‘ Computer Computer Organizat Organization ion ’ or ‘ Digital Logic Logic ’ previous previous years years ‘ GATE  /   ISRO ’ question, don’t go and search the Google!, just search through this th is book.” book.”  /  ISRO

This book is dedicated to all those preparing preparing for GATE, GATE, ISRO and other competitiv competitivee examinations examinations.. It is organized organized into two parts covering subjects Digital logic & Computer organization. First part on Digital logic and second part on Computer organization. Each Each part part is futher divided divided into sections. sections. Each Each sectio section n include includess the required required theory theory part part in brief brief as well well as the previous previous years GATE GATE and ISRO ISRO questions questions with explanations explanations.. We tried to include GATE  questions  from 1992 till 2014  and  ISRO questions from 2007 till 2014 . Each and every question is answered in simple and lucid manner. Pattern Pattern based question ordering ordering is used in this book. Questions Questions having similar structure structure are grouped in a manner that the answers can be linked. We believe, “ Pattern based question ordering ” will help you to improve your skills in problem solving in those areas described described in the book. The theory parts in brief will help you as a “ Quick reference ” to revise the concepts and formulas. We hope, this book will give you a clear insight into the solutions and the way of solving problems. Constructive suggestion and criticism always go a long way in enhancing any endeavor. We request you to respond with your valuable comment  /  views  /  feedback feedback for the betterment betterment of this book at: https: // www.facebook.com www.facebook.com / gateplusisro gateplusisro Wish Wish you all the best.

REJIN R

ARAVIND PRASAD A G

Part I

D I G I TA TA L L O G I C

1 SEQUENTIAL CIRCUITS

A sequential circuit is a digital logic circuit, whose output value depends on present and past inputs. It includes a combinational circuit and memory element.

1.1   f l i p - f l o p s A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed directed by an input signal to switch states. states. 1.1.1

Basic Flip-flop circuits circuits

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1.1.2

  Note:

percentage of one period in which signal is active. active. Duty cycle of 60% means the Duty cycle :  It is the percentage signal is ON for 60% of time and OFF for 40% of time. after the clock edge. Propagation delay : It is the time a flip-flop takes to change its output after flip flop, flop, when when J=1 and K=1 a toggling toggling occurs occurs.. Since Since clock clock pulse Race around condition : In JK flip is more than propagation delay, within on clock pulse the output keep on toggling again and again and output become indeterminate. This situation is known as  race around condition.

arrangement,, in which first one (master) (master) responds Master Slave Flip flops :  This is a cascade of flip flop arrangement with clock high and second (slave) (slave) responds with clock low. low. Thus the final output changes only when clock is low. Thus race around condition is get eliminated.

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1.1.3

Flip-flops - [GATE [GATE Questions]  Questions] 

1. In an SR latch made by cross-coupling cross-coupling two NAND NAND gates, if both S and R inputs are set to 0, then it will result in

[GATE-2004 CS] [1 mark] [ISRO-2007]

2. Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND NAND gates may lead to an oscillation?

[GATE-2007 IT] [1 mark]

3. In the sequential circuit circuit shown below, below, if the initial value value of the output Q1 Q0 is 00 is  00,, what are the next four values of  Q  Q 1 Q0 ?

[GATE-2010 CS &  [2 mark] [ISRO-2014] & IT]  

4. The following following arrangement arrangement of master-slav master-slavee flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

[GATE-2000 CS] [2 mark]

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5. The following following synchronous synchronous sequential sequential circuit built using JK flip-flops is initialized initialized with Q2 Q1 Q0  = 000.

The state sequence for this circuit for the next 3 clock cycles cycles is

[GATE-2014 SET-3] [2 mark]

6. Conside Considerr the circuit circuit in the diagram diagram.. The ⊕  operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared)

The following data: 100110000 is supplied to the "data" terminal in nine clock cycles. After that the values of q2 q1 q0  are :

[GATE-2006 CS] [2 mark]

7. Consider Consider the following following state diagram diagram and its realization realization by a JK flip-flop.

The combinational circuit generates J and K in terms of x,y and Q. The Boolean expression for J and K are:  x ⊕ y ⊕

x ⊕ y x ⊕ y

x ⊕ y ⊕

⊕ ⊕

[GATE-2008 IT] [2 mark]

16

8. You are given a free running clock with a duty cycle of 50% and a digital waveform waveform f  which changes only at the negative negative edge of the clock. Which one of the following following circuits (using clocked clocked D flip-flops) flip-flops) will delay ◦ the phase of  f  by 180 ? (a)

(b)

(c)

(d)

[GATE-2006 CS] [1 mark]

9. Consider Consider the following following circuit. circuit.

The flip-flops are positive edge triggered D flip-flops. Each state is designated as a two bit string Q 0 Q1 . Let the initial state be 00. The state transition transition sequence is:

(a)

(b)

(c)

(d)

[GATE-2005 CS] [2 mark]

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10. Consider Consider the following following circuit with initial initial state Q0 =Q1 =0. The D Flip-flops are positive edge triggered and have set up times 20 ns and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C ≥40 ns. Which one is the correct plot of Y?

[GATE-2001 CS] [2 mark]

11. Consider the following circuit involving involving a positive edge triggered D flip-flop.

Consider the following timing diagram. Let Ai  represent the logic level on the line A in i th clock period.

Let A’ represent the complement of A. The correct output sequence on Y over the clock period 1 through 5 is 0

1

1

3

4

0

1

2

3

4

1

2

2

3

4

1

2

3

4

5

[GATE-2005 CS] [2 mark]

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1.1.4

Flip-flops - [ISRO [ISRO Questions]  Questions] 

1. In an RS flip-flop, if the S line(Set line(Set line) is set high(1) and the R line(Reset line(Reset line) is set low(0), low(0), then the state of the flip flop is

[ISRO - 2011 CS]

2. The characteri characteristic stic equation equation of an SR flip flop is given by n+ 1 n+ 1

S 

n

n +1

n

n +1

Qn S Qn R

n

[ISRO - 2007 CS]

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1.2   r e g i s t e r s

1.2.1

&   counters

  Registers

Registers Registers are memory devices devices that can be used to store more than one bit of information. information.

Shift Registers A register that provide the ability to shift its contents is known as shift registers.

 Linear Feedback Shift Registers A Linear Feedback Shift Register is a shift register whose input bits is a linear function of previous state.

In the above example input bit at A 3  is determined determined by XORed combination of bits A 0  and A2 , with every operation operation a bit is shifted shifted right. 1.2.2

  Counters

Counters are sequential circuits which goes through a sequence of states upon application of input pulses. Modulus pulses.  Modulus of  of a counter is the number of unique state a counter may have. Two types of counters: • Ripple counter (Asynchronous) •   Synchronous counter 

 Ripple counter In a Ripple counter, counter, the flip flop output transition transition serves as a source for triggering triggering other flip flops.

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Synchronous counters In synchronous sequential circuits, all the flip flop’s clock input are applied to the same clock signal, so that all flip flop output changes at the same time.

 Ring counter A Ring counter is composed of a circular shift register, where the output of last shift register is fed back to input of first register. This counter circulates a single  1 around  1  around the ring.

A ring counter can also be represented using a combination of up counter and n to 2 n decoder circuit.

In a ring counter, count is read by noting which flip flop is in state 1. The output pulse of one stage is delayed by a time T from a pulse in the preceding stage. Thus a ring counter is analogous to Stepping to  Stepping switch where switch where each triggering pulse causes an advance of switch by one step. Pattern Pattern produced produced by Ring counter : 1000, 0100, 0010, 0001, 1000, ....

 NOTE  NOTE : Ring Ring coun counte terr is the the cost costli lies estt synch synchro ronou nouss counter. With  n  flip flops  maximum modulus =  N 

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 Johnson counter (Twisted Ring counter) Johnson counter is a variation of Ring counter obtained by taking feedback output from  Q  (instead of Q in Ring counter), to the first stage.

Pattern Pattern in Johnson counter : 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, ....

 Note : Johnson counter performs gray counting  Maximum modulus modu lus = 2n

1.2.3

Counters - [GAT [GATE E Questions]  Questions] 

1. What is the final value stored stored in the linear feedback feedback shift shift register register if the input is 101101?

[GATE-2007 IT] [2 mark]

2. The minimum number number of D flip-flops needed needed to design a mod-258 mod-258 counter is

[GATE-2011 CS &  [1 mark] & IT]  

3. How How many many pulses pulses are needed needed to change change the conten contents ts of a 8-bit 8-bit up counte counterr from from 10101100 10101100 to 00100111 00100111 (rightmost (rightmost bit is the LSB)?

[GATE-2005 IT] [1 mark]

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4. Let Let  k  =  2 n . A circuit is built by giving the output of an n-bit binary counter as input to an bit decoder. This circuit is equivalent to a

[GATE-2014 SET-2] [1 mark]

5. For the initial initial state of 000, the function performed performed by the arrangement arrangement of the J-K flip flops in figure is :

[GATE-1993 CS] [2 mark]

Common Data Questions[6-7] Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

6. If all the flip-flops were reset to 0 at power power on, what is the total number of distinct outputs (states) represented by PQR generated generated by the counter?

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7. If at some instance instance prior to the occurance occurance of the clock edge, P, P, Q and R have a value 0, 1 and 0 respectiv respectively ely,, what shall be the value of PQR after the clock edge?

[GATE-2011 CS &  [2 mark] & IT]  

8. The control signal function function of a 4-bit binary counter counter are given below( below( where X is "don’t "don’t care"):

The counter is connected as follows: Assume that the counter and gate delays are negligible. If the counter

starts at 0, then it cycles cycles through the following following sequence.

[GATE-2007 CS] [2 mark]

9. Consider Consider the circuit given given below with initial state Q0 =  1, Q1 =  Q 2 =  0. The state of the circuit is given by the value 4Q2  + 2Q1  + Q0

Which one of the following following is correct correct state sequence of the circuit? circuit?

[GATE-2001 CS] [2 mark]

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10. Consider Consider the partial partial implementation implementation of a 2-bit counter using T flip-flops flip-flops following following the sequence sequence 0-2-3-1-0, as shown below.

To complete the circuit, the input X should be 2

2

1

1  ⊕  Q2

1  ⊕  Q2

[GATE-2004 CS] [2 mark]

1.2.4

Counters - [ISRO [ISRO Questions] 

1. Ring counter counter is analogous analogous to to

[ISRO - 2007 CS]

2. In a three three stage counte counter, r, using using RS flip flops flops what what will be the value value of the counter counter after after giving giving 9 pulses pulses to input? Assume that the value value of counter counter before giving any pulses is 1.

[ISRO - 2013 CS]

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1.3

S e q u e n t i a l Ci r c u i t s – An s w e r s

1.3.1

Flip-flops - [GATE]  [GATE] 

1.3.2

Flip-flops - [ISRO] 

1.3.3   Registers &  Counters - [GATE] 

1.3.4   Registers &  Counters - [ISRO] 

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1.4 1.4.1

Answers

with

Explanations

Flip-flops - [GATE]  [GATE] 

1. Ans: Ans: (d) indeterminate indeterminate state 2. Ans: Ans: (a) 11, 11, 00 In a cross coupled R-S flip-flop realized using NAND gate, for input 11 the output will be the previous output. Input 00 leads to oscillation. oscillation. 3. Ans: Ans: (a) 11, 10, 10, 01, 00

Initial values of Q1 Q0 = 00 0

Q0( prev)

∵

1

Q1( prev)

∵

0

1

1( prev)

∵

0

0

4. Ans: Ans: (a) 1, 0

In the above configuration input of D flip flop is the output P of JK flip flop. Since, 1 is constantly given as input to JK flip flop, each time the output toggles.

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5. Ans: Ans: (c) 100, 110, 110, 111

Initial values are Q 2 Q1 Q0  = 0 0 0 The state sequence for next 3 clock cycles is given by :

6. Ans: Ans:   (c) 010

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7. Ans: Ans:   (d) x⊕ y and x⊕ y

From the above table:   J(X,Y,Q) = (2,4) + φ (1,3,5,7)

∴

J =  X Y+XY  = X⊕Y

K(X,Y,Q) =

∴

  (3,5) + φ (0,2,4,6)

K =  X Y+XY  = X⊕Y

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8. Ans: Ans: (c)

9. Ans: Ans: (d)  (d)

State transition sequence of Q 0 Q1  is :

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10. Ans: Ans:  (a)

11. Ans: Ans:   (a) A0 A1 A1 ’A3 A4 From the given figure:  A i X + Q’.X’

∴

1.4.2

Answer is  (a) A0 A1 A1 ’A3 A4

Flip-flops - [ISRO] 

1. Ans: Ans: (a) Set Set to 1 2. Ans: Ans:   (d) Qn+1 =S+ RQn

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1.4.3

Counters - [GATE]  [GATE] 

1. Ans: Ans:   (a) 0110

2. Ans: Ans:   (a) 9 A mod -258 counter counts from 0 to 257. ∴ Number of bits required =   log  257   = 9 2 ∴ Number of D flip flops required = 9 3. Ans: Ans:   (d) 123 (10101100)2  = (172)10 (00100111)2  = (39)10 Since this is an 8 bit counter it counts from 0 to 255. The The coun counte terr coun counts ts from from 172 172 to 255 255 (83 pulses) Then from 0 to 39 (40 pulses) ∴ Total number of pulses = 40+83 = 123 4. Ans: Ans: (c) k-bit ring ring counter 5. Ans: Ans: (c) Mod-6 counter The given counter is Johnson counter. Number of flip flops, n flops, n = 3 With n flip flops maximum mod = 2n = 6 6. Ans: Ans:   (b) 4 From the figure, P Next state  = R Q Ne xtstate  =  P  + R R Ne xtstate  = Q R Given that, all the flip flops were reset to 0 on power on.

∴

Number of states = 4.

7. Ans: Ans:   (d) 011 From the above answer it is clear that, if current current state is  010 then be  011  010  then next state will be 011 32

8. Ans: Ans: (c) 0, 0, 1, 2, 3, 3, 4 Here count starts from 0. Counter counts next until clear  =  1. From the above configuration, clear  = 1 when A3  and A1  becomes 1. i.e., 0101 (5).   which counts from  0 to 4. ∴ The given counter is a  mod-5 counter  which is  (c) 0, 1, 2, 3, 4 ∴ The sequence is (c) 9. Ans: Ans: (b) 1, 2, 2, 5, 3, 7, 6, 4

10. Ans: Ans: (d) Q1  ⊕  Q2

1.4.4

Counters - [ISRO] 

1. Ans: Ans: (c) Stepping Switch 2. Ans: Ans:   (b) 2 Since the given counter is three stage counter, it can count from  0 to 7 ( 7  ( ∵ 23 = 8). Initially the value is 1. By applying first 6 pulse it will count upto 7 upto  7.. For the  next 3 pulses  it will count: 0, 1 and 2 and  2.. 33

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