Fundamentals of Logic Design 6th Edition Chapter 13

Unit 13 Problem Solutions 13.2

Notice that this is a shift register. At each falling clock edge, Q3 takes on the value Q2 had right before the clock edge, Q2 takes on the value Q1 had right before the clock edge, and Q1 takes on the value X had right before the clock edge. For example, if the initial state is 000 and the input sequence is X = 1100, the state sequence is = 100, 110, 011, 001, and the output sequence is Z = (0)0011. Z is always Q3, which does not depend on the present value of X. So it’s a Moore machine. See FLD p. 653 for the state graph.

13.3 (a) A+ = AKA' + A'JA= A (B' + X) + A'(BX' + B'X) B + = B'JB + BKB' = AB'X + B (A' + X') Z = AB A+ A B

X

B+ 0

1

00

0

1

01

1

11 10

X

A B

0

1

00

0

0

0

01

1

1

0

1

11

1

0

1

1

10

0

1

Present State

Next State (A+B +)

AB

X=0 X=1 00 10 11 01 01 10 10 11

00 01 11 10 0 0

13.3 (b) X = 0 1 1 0 0 AB = 00 00 10 11 01 11 Z = (0) 0 0 1 0 1

1

1

00 0

10 0

Z 0 0 1 0

0 11 1

1

0

01 0

1

13.3 (c) See FLD p. 653 for solution.

13.4 (a) Q2 Q3

X Q1 00

01

11

10

Q2 Q3

X Q1 00

01

11

10

X Q1 00

01

11

10

Q2 Q3

X Q1 00

01

11

10

0

0

1

1

00

1

1

1

1

00

1

01

1

1

1

1

01

0

0

1

1

1

1

11

0

0

1

1

11

1

1

0

0

0

0

10

0

0

1

1

10

1

1

0

0

00

0

0

0

0

00

0

0

0

0

01

0

0

0

0

01

1

1

1

11

0

0

0

0

11

1

1

10

1

1

1

1

10

0

0

Q1+ = D1

Q2 Q3

Q 3+ = D 3

Q2+ = D2

Z

Z depends on the input X, so this is a Mealy machine. Because there are more than 2 state variables, we cannot put the state table in Karnaugh Map order (i.e. 00, 01, 11, 10), but we can still read the next state and output from the Karnaugh map. For example, when the input is X = 1 and the state is Q1Q2Q3 = 110, we can read the next state and output from the XQ1Q2Q3 = 1110 position in the Karnaugh maps for Q1+, Q2+, Q2+, and Z. So in this case, the next state is Q1+Q2+Q3+ = 101 and the output is Z = 0. The entire table can be derived from the Karnaugh maps in this manner. Note: We can also fill in the state table directly from the equations, without using Karnaugh maps. See FLD p. 653 for the state table and state graph.

13.4 (b - d) See FLD p. 654 for solutions.

91

13.5 (b)

13.5 (a) Mealy machine, because the output, Z, depends on the input X as well as the present state.

Z B C

13.5 (c - d) See FLD p. 654 for solutions.

X A 00

01

11

10

00

0

0

1

1

01

0

0

1

1

11

1

1

0

0

10

1

1

0

0

Note: Not all Karnaugh map entries are needed. See FLD p. 654 for the state table. 13.6 (a) After a rising clock edge, it takes 4 ns for the flip-flop outputs to change. Then the ROM will take 8 ns to respond to the new flip-flop outputs. The ROM outputs must be correct at the flip-flop inputs for at least the setup time of 2 ns before the next rising clock edge. So the minimum clock period is (4 + 8 + 2) ns = 14 ns. 13.6 (b) The correct output sequence is 0101. See FLD p. 655 for the timing diagram. 13.6 (c) Read the state transition table from ROM truth table. See FLD p. 655 for the state graph and table. Present State

Q1Q2 00 01 10 11

Next State (Q1+Q2 +)

Z X=0 X=1 X=0 X=1 10 10 0 0 00 11 0 0 11 01 0 1 01 11 1 1

Alternate solution: Using Karnaugh map order, swap states S2 and S3 in the graph and table. 13.7 (a) Notice that Z depends on the input X, so this is a Mealy machine. Q1+ = J1Q1' + K1'Q1 = XQ1'Q2 + X'Q1 Q2+ = J2Q2' + K2'Q2 = XQ1'Q2' + X'Q2 Z = Q2 ⊕ X = XQ2' + X'Q2

State

Present State

S0 S1 S2 S3

Q1Q2 00 01 11 10

Next State (Q1+Q2+)

Q1 Q2

Z

X

0

1

00

0

0

01

0

11 10

Alternate solution: Swap states S2 and S3.

92

X

0

1

00

0

1

1

01

1

1

0

11

1

0

10

Q1+

X=0 X=1 X=0 X=1 00 01 0 1 01 10 1 0 11 00 1 0 10 00 0 1

Q1 Q2

X

0

1

00

0

1

0

01

1

0

1

0

11

1

0

0

0

10

0

1

Q2+

Q1 Q2

Z

0

1

S2

0 1

0

1

1

S3

0

1

1 0

S1

0

Clock X Q1

S0

1 0

13.7 (b)

0

Q2 Z

1

{

13.7 (a) (contd)

false

13.8 (a) Notice that Z does not depend on this input X, so this is a Moore machine. Q1+ = X1X2Q1 + Q1Q2 + X1Q2 Q2+ = Q1' (X1 + X2) + Q2 (X1' + X2') = X1Q1' + X2Q1' + X1'Q2 + X2'Q2 Z = Q1Q2' Q1 Q2

X1 X2 00 01

11

10

Q1 Q2

X1 X2 00 01

1

1

1

0

0

1

1

01

1

1

1

1

1

0

0

1

1

11

1

1

0

1

1

0

10

0

0

0

0

0

0

01

0

0

1

11

1

1

10

0

0

Q1+

S0 S1 S2 S3

0

1

0

Q1Q2 00 01 11 10

Q1

Q2

0

0

Present State

10

00

00

State

11

Z

Q2+ Next State X1X2

00 00 01 11 00

01 01 01 11 00

11 01 11 10 10

Z 10 01 11 11 00

00

00, 01 S0

01, 10, 11

0

0 0 0 1

0

00, 01, 10 S3 1

11

S1

11

10, 11 S2 0

00, 01, 10

13.9

13.8 (b)

Clock

Clock

X1

X Q1

X2

Q2 Q3

Q1

Z {

Q2

false

Correct output: Z = 1, 0, 1, 1

Z Correct output: Z = 0, 0, 0, 1, 1, 0

93

13.10

Clock X Q1 Q2 Q3 {

{

Z false

false

Correct output: Z = 0, 0, 1, 1

13.11 (a) Q2 Q3

X Q1 00

01

11

10

Q2 Q3

X Q1 00

01

11

10

Q2 Q3

X Q1 00

01

11

10

01

11

10

0

0

1

1

1

01

0

0

1

1

1

1

11

1

1

0

0

0

1

1

10

1

1

0

0

D3 =

Q 3+

0

0

0

1

00

0

0

0

0

00

1

1

1

1

01

0

0

0

1

01

1

1

1

1

01

1

1

1

11

0

0

0

1

11

1

1

1

1

11

0

0

10

1

1

1

1

10

1

1

0

0

10

0

D2 =

Q 2+

D 1 = Q 1+ Present State

S0 S1 S2 S3 S4 S5 S6 S7

Q1Q2Q3 000 001 010 011 100 101 110 111

Next State (Q1+Q2+Q3+)

Z

0

X=0 X=1 X=0 X=1 001 101 0 1 011 111 0 1 110 101 1 0 010 111 1 0 001 001 0 1 011 011 0 1 110 101 1 0 010 011 1 0

S0 0

0 1

0, 1

S4

0

1

0

S3 1

1

S7

0

1

1

0, 1 0

0

1

Z

1

0

S1

1

S5 1

0 0

1

1

0

0

0

1

S6

1

S2

13.11 (c) From diagram: 0, 1, (0), 1, 0, 1 From graph: 0, 1, 1, 0, 1 (they are the same, except for the false output)

Clock X Q1

13.11 (d) Change the input on the falling edge of the clock (assuming negligible circuit delays).

Q2 Q3 Z {

13.11 (b)

State

X Q1 00

00

00

Q2 Q3

false

94

13.12 (a) Q2 Q3

X Q1 00

01

11

10

Q2 Q3

X Q1 00

01

11

10

Q2 Q3

X Q1 00

01

11

10

00

1

1

0

0

00

0

1

1

1

00

0

0

1

1

01

0

0

0

0

01

0

0

1

1

01

0

0

1

11

0

0

0

0

11

0

0

0

0

11

0

1

10

1

1

0

0

10

0

1

1

0

10

0

1

13.12 (b)

State

Present State

S0 S1 S2 S3 S4 S5 S6 S7

Q1Q2Q3 000 001 010 011 100 101 110 111

Next State (Q1+Q2+Q3+)

1

Z

X=0 X=1 X=0 X=1 100 011 1 0 000 011 0 1 100 000 1 0 000 000 0 1 110 011 1 0 000 011 0 1 111 011 1 0 001 001 0 1

0

01

11

10

00

1

1

0

0

1

01

0

0

1

1

1

0

11

0

0

1

1

1

0

10

1

1

0

0

1

S0 0

0

0

1 0, 1

0

1

S5 0

0

1

1

1

S3 1

S1

Z

0

S2 0

1

S4

0

0

1

0

S6 0

1 0

1

1

0, 1

1

S7

13.12 (c) From diagram: 1 0 1 (0) 1 1 From graph: 1 0 1 1 1 (they are the same, except for the false output)

X Clock

Q1

13.12 (d) Change the input on the falling edge of the clock (assuming negligible circuit delays).

Q2

{

Q3 Z

X Q1 00

D3 = Q 3+

D 2 = Q 2+

D 1 = Q 1+

Q2 Q3

false

13.13

Clock Cycle Information Gathered 1 Q1Q2 = 00, X = 0 ⇒ Z = 1, Q1+Q2+ = 01 2 Q1Q2 = 01, X = 0 ⇒ Z = 0; X = 1 ⇒ Z = 1, Q1+Q2+ = 11 3 Q1Q2 = 11, X = 1 ⇒ Z = 1; X = 0 ⇒ Z = 0, Q1+Q2+ = 10 4 Q1Q2 = 10, X = 0 ⇒ Z = 1; X = 1 ⇒ Z = 0, Q1+Q2+ = 00 5 Q1Q2 = 00, X = 1 ⇒ Z = 0, Q1+Q2+ = 10 6 Q1Q2 = 10, X = 1 ⇒ (Z = 0); X = 0 ⇒ (Z = 1), Q1+Q2+ = 11 7 Q1Q2 = 11, X = 0 ⇒ (Z = 0); X = 1 ⇒ (Z = 1), Q1+Q2+ = 01 8 Q1Q2 = 01, X = 1 ⇒ (Z = 1); X = 0 ⇒ (Z = 0), Q1+Q2+ = 00 9 Q1Q2 = 00, X = 0 ⇒ (Z = 1) Note: Information inside parentheses was already obtained in a previous clock cycle.

Present State

Next State (Q1+Q2+)

Q1Q2

X=0 X=1 01 10 00 11 11 00 10 01

00 01 10 11

0

00 1

1

0

01 1

0

0 1 0 1 0

0

0

0

10

95

0

1

Z

1 0

1

11

1

1

1 0 1 0 1

13.14

13.15

Clock Cycle Information Gathered 1 Q1Q2 = 00, X = 0 ⇒ Z = 0, Q1+Q2+ = 10 2 Q1Q2 = 10, X = 0 ⇒ Z = 1; X = 1 ⇒ Z = 0, Q1+Q2+ = 01 3 Q1Q2 = 01, X = 1 ⇒ Z = 0; X = 0 ⇒ Z = 1, Q1+Q2+ = 10 4 Q1Q2 = 10, X = 0 ⇒ (Z = 1), Q1+Q2+ = 11 5 Q1Q2 = 11, X = 0 ⇒ Z = 0, Q1+Q2+ = 11 6 Q1Q2 = 11, X = 0 ⇒ (Z = 0); X = 1 ⇒ Z = 1, Q1+Q2+ = 01 7 Q1Q2 = 01, X = 1 ⇒ (Z = 0), Q1+Q2+ = 00 8 Q1Q2 = 00, X = 1 ⇒ Z = 1, Q1+Q2+ = 11 9 Q1Q2 = 11, X = 1 ⇒ (Z = 1) Note: Information inside parentheses was already obtained in a previous clock cycle.

Clock Cycle 1 2 3 4 5

Present State

Next State (Q1+Q2+)

Q1Q2

X=0 X=1 10 11 10 00 11 01 11 01

00 01 10 11 00 1

0

11

Note: When Q1Q2 = 01, the outputs Z1Z2 vary depending on the inputs X1X2, so this is a Mealy machine.

13.16 (a)

Q1+Q2+

Z1Z2

X1X2=

Q1Q2 00 01 11 10

00 01 11 10 00 01 11 10 ? 01 ? ? ? 10 ? ? ? 11 ? 10 ? 01 11 10 ? ? ? ? ? 01 ? ? ? ? 01 ? ? ? 00 00

X1X2=

X1 X2 Clock Q1 Q2 Z1 Z2 false

Correct output: Z1Z2 = 10, 10, 00, 01

96

1

0

0

0

0 0 1 1 0

1 1 0 0 1

0

01 1

1

Information Gathered Q1Q2 = 00, X1X2 = 01 ⇒ Z1Z2 = 10, Q1+Q2+ = 01 Q1Q2 = 01, X1X2 = 01 ⇒ Z1Z2 = 01; X1X2 = 10 ⇒ Z1Z2 = 10, Q1+Q2+ = 10 Q1Q2 = 10, X1X2 = 10 ⇒ Z1Z2 = 00; X1X2 = 11 ⇒ Z1Z2 = 00, Q1+Q2+ = 01 Q1Q2 = 01, X1X2 = 11 ⇒ Z1Z2 = 11; X1X2 = 01 ⇒ (Z1Z2 = 01), Q1+Q2+ = 11 Q1Q2 = 11, X1X2 = 01 ⇒ Z1Z2 = 01

Present State

1

Z

1

0

0

0

10 1

1

13.16 (b)

Present State

X1X2=

Q1Q2 00 01 10 11

00 00 11 11 10

Q1+Q2+

01 00 11 00 01

10 01 10 11 10

11 01 10 00 01

00 10 00 00 00

01 10 10 00 00

10 11 10 10 01 11 01 01 00 00

13.17 Transition table using a straight binary state assignment: State

Present State

S0 S1 S2 S3 S4

Q1Q2Q3 000 001 010 011 100

00 10 01 10

Z1Z2

X1X2=

00 01 00 11 01

10

10 11 10 , 10 10 11 01, 11 00 10 00 , 01 00 10 00, 00

01 01 00 11 00

00 00 01 10

11

Clock

X

Next State (Q1+Q2+Q3+)

Z

Q1

X=0 X=1 X=0 X=1 001 011 0 0 010 011 0 0 001 011 0 1 100 000 0 0 011 000 0 1

Q2 Q3 Z Correct output: Z = 0, 0, 1, 0, 0, 1

13.18 (a)

5ns

10ns

15ns

20ns

25ns

30ns

35ns

Clock

X A

B JA

KA

JB = KB Z All flip-flop inputs are stable for more than the setup time before each falling clock edge. So the circuit is operating properly. 13.18 (b) If X is changed early enough: Minimum clock period = Flip-flop propagation delay + Two NAND-gate delays + Setup time = 4 + (3 + 3) + 2 = 12 ns X can change as late as 8 ns (two NAND-gate delays plus the setup time) before the next falling edge without causing improper operation.

97

13.19

Correct output: Z = 1 0 1 0 1

Clock

Deriving the State Table: JK flip-flop equation: Q+ = JQ' + K'Q ∴ A+ = (X'C + XC') A' + X'A [As, JA = X'C + XC', KA = X, Q = A] = A'X'C + A'XC' + X'A Similarly, B+ = XC' + XA + X'A'C C+ = 0' · C + (XB'A) · C' = C + XB'A Z = XB + X'C' + X'B'A

A B C X

{

Z

false

A+ B C

B+

X A 00

01

11

10

00

0

1

0

1

01

1

1

0

11

1

1

10

0

1

B C

X A 00

C+ 01

11

10

00

0

0

1

1

0

01

1

0

1

0

0

11

1

0

0

1

10

0

0

B C

Z

X A 00

01

11

10

00

0

0

1

0

0

01

1

1

1

1

0

11

1

1

1

1

10

0

0

X A 00

B C

01

11

10

00

1

1

0

0

1

01

0

1

0

0

1

1

11

0

0

1

1

0

0

10

1

1

1

1

From the Karnaugh maps, we can get the state table that follows:

13.20 (contd)

State

Present State

S0 S1 S2 S3 S4 S5 S6 S7

ABC 000 001 010 011 100 101 110 111

State

Present State

S0 S1 S2 S3

AB 00 01 10 11

X1X2=

00 11 11 10 10

13.20

Next State (A+B+C+)

Z

X=0 X=1 X=0 X=1 000 110 1 0 111 001 0 0 000 110 1 1 111 001 0 1 100 011 1 0 101 011 1 0 100 010 1 1 101 011 0 1

A+B+

01 01 01 00 00

10 10 01 10 11

X1X2=

11 00 01 10 01

00 10 11 01 00

T = X1'BA + X1'B'A' B+ = BT' + B'T = B(X1'BA + X1'B'A')' B' (X1'BA + X1'B'A')' = B [(X1'BA)' (X1'B'A')'] + X1'B'A' = B [(X1 + B' + A') (X1 + B + A)] + X1'B'A' = (BX1 + BA') (X1 + B + A) + X1'B'A' = BX1 + BX1 + BX1A + BA'X1 + BA' + X1'B'A' = X1B(1 + 1 + A + A') + A' (B + X1'B) = X1B + A'B + X1'A'

Z1Z2

01 10 00 00 00

10 00 11 01 00

R = X2 (X1' + B) S = X2' (X1' + B') A+ = A[(X2 ) (X1' + B)]' + X2' (X1' + B') = A (X2' + X1B') + X2'X1' + X2'B' A+ = AX2' + AX1B' + X2'X1' + X2'B'

01 10 11 00 11 00

11 00 00 00 00

01 10

S1 00 11

11

11

00

S0

00 00 10 10 00

S3

98

10 00

00 00

10 00

01 00

S2 00 10 11 01 01 00