Full Adder Design Using Verilog HDL in three modeling styles

Share Embed Donate

Short Description

it contains the lab manual for Full Adder design implemented using Verilog HDL and the design contains all the three mod...


Design of Full adder using 3 modeling styles Aim: To simulate and to synthesize Full Adder in the three modeling styles using Verilog HDL and to generate RTL schematic Theory and applications:

A one bit full adder adds three one bit numbers represented by A, B, Cin in the above block diagram. It generates two outputs S and Cout which are 1-bit numbers. A and B are the operands in the current stage while Cin is the bit carried in from the next less significant stage. The outputs S and Cout are sum and carry of the current stage respectively. Actual output of the full adder is given as Sum = 2 x Cout + S Where S and Cout are given as

Cout = A.B + B.Cin + Cin.A Requirements: Tool used: Xilinx ISE 9.2i FPGA used: Spartan-3E Circuit:

The same can be represented as

Truth table:

HDL Code: Data flow modeling:

module FAdataflow(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; assign#4 sum=a ^ b ^ c; assign#4 carry =( a & b | b & c ) | c & a; endmodule Behavioral modeling:

module FAbehavioral(a, b, c, sum, carry); input a;

input b; input c; output sum; output carry; reg sum,carry; reg p1, p2, p3; always @ (a or b or c) begin sum = ( a ^ b ) ^ c; p1 = a & b; p2 = b & c; p3 = a & c; carry = ( p1 | p2) | p3; end endmodule Structural Modeling: module FAstruct(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; wire t1,t2,t3,s1; xor x1 (s1, a, b), x2 (sum, s1, c); and a1 (t1, a, b), a2 (t2, b, c), a3 (t3, a, c); or o1 (carry, t1, t2, t3); endmodule testbench code: module testFA;

reg A,B,C1; wire S1,C2; FAdataflow fff(A,B,C1,S1,C2); //this is for dataflow modeling style. FAdataflow should be replaced by FAbehavioral and FAstruct for //behavioral and structural modeling styles respectively. Initial Begin A=0; B=0; C1=0; #2 C1=1; #2 B=1; C1=0; #2 C1=1; #2 A=1; B=0; C1=0; #2; $stop; end endmodule Procedure: 1. 2. 3. 4. 5. 6. 7. 8. 9.

Create a new project in Xilinx ISE 9.2i. In the edit window opened, type the HDL code for the required modeling style Check for errors in the code using the options given on the left side of the window If there are no errors, run the test bench for the code and get the simulated outputs. Generate the RTL schematic of the written code and compare it with the expected schematic Write the net-list for the given series of FPGA Connect FPGA using J-Tag connector and power-up the FPGA board Synthesize the code by using the option ‘place and route’ onto the FPGA board Check the outputs on FPGA board by giving all possible combinations of inputs and compare the results with the simulated waveform

Precautions: 1. The HDL code shouldn’t contain the keywords or attributes which are not synthesizable 2. Test-bench should not be placed while synthesizing the code on FPGA

3. Proper power supply should be connected to FPGA to avoid the failure of the board Test-bench waveform:


Cout = A.B + B.Cin + Cin.A Inference: (conclusions) The truth-table of the full adder is verified in all the three modeling styles and its RTL schematic is generated. The same is synthesized on FPGA Viva quest: min 5 1. What is the difference between traditional languages like C, C++ and HDLs like VHDL, Verilog, etc.,. Ans: HDLs are concurrent while traditional languages are sequential in nature w.r.t executions and simulations 2. How to design 4-bit full adder using 1-bit full adder Ans:

3. What is the difference between simulation and synthesis Ans: Verifying the design is simulation. It is the study of the design irrespective of timing parameters and gate delays. Synthesis is the conversion of the design or description into equation or components based on the target to be synthesized. 4. What is the importance of test-bench in HDLs Ans: Test-bench is used to verify the design by feeding known inputs to the design. It will generate the corresponding outputs. The inputs and outputs are plotted on a single time scale which helps to analyze the design at every instant when the input changes 5. What is the difference between full custom and semi custom design in VLSI Ans: Full custom is to design from the lower abstraction levels while semi custom is to design using modules which are already simulated and well tested. 6. What are the different abstraction levels in VLSI Ans:

View more...


Copyright ©2017 KUPDF Inc.