FPGA Temp Sensor

FPGA based Temperature Sensor and Control A Project Report Submitted As Essential Part of the Course

Hardware Design Methodology (M. Tech. MI)

Submitted by

ANKITA VERMA (IMI2012003) RAJAN BHARTI (IMI2012018) Under the Guidance of:

Dr. Satish Kumar Singh Assistant Professor

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY ALLAHABAD-211 012 (INDIA) May-2013

Abstract: We need temperature control in various places . It can be used to control the temperature of furnaces or also room

temperature.We have used LM35

as

temperature sensor whose output is compared to the user input desired value, the resulting signal is used to control the temperature.

Introduction: Field programmable gate arrays (FPGAs) are extensively used in rapid prototyping and verification of a conceptual design and also used in electronic systems when the mask-production of a custom IC becomes prohibitively expensive due to the small quantity. Many system designs that used to be built in custom silicon VLSI are now implemented in Field Programmable Gate Arrays. This is because of the high cost of building a mask production of a custom VLSI especially for small quantity. In this the main objective is to design a FPGA based temperature sensor and control. We are using LM35 temperature sensor IC. The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has an advantage over linear temperature sensors calibrated in ˚ Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling.Its analog output is given to the analog to digital module converter board (AD7476). Its digital output can be read using FPGA.

Block diagram:

The LM35 is rated to operate over a −55˚ to +150˚C temperature range. Calibrated directly in ˚ Celsius (Centigrade). It has Linear scale factor of +10.0mV/˚C. Its output is given to 12 bit A/D converter.

Methodology and Modeling: We have divided the problem into submodules.In the first module we are reading the data from the sensor output, which is a FSM according to three state. In second module, we are converting the read data to BCD format , which is further displayed on seven segment display. It contains

concurrent processes to compare user and sensor value and take suitable actions, to convert decimal to BCD which is further displayed on a seven segment display.

Implementation:

(A) RTL Description(VHDL Code): To read data from ADC library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AD1 is Port ( --General usage CLK : in std_logic; RST : in std_logic; --Pmod interface signals SDATA1 : in std_logic; SCLK : out std_logic; nCS : out std_logic; --User interface signals DATA1 : out std_logic_vector(11 downto 0); START : in std_logic; DONE : out std_logic ); end AD1 ; architecture AD1 of AD1 is

clock_divide : process(rst,clk) begin if rst = '1' then clk_counter d_out1:="11101001100"; when "0101"=> d_out1:="11100100100"; when "0111"=> d_out1:="11100001111"; when "1000"=> d_out1:="11100000000"; when "1001"=> d_out1:="11100000100"; when others => d_out1:="11100110000"; end case; end process;

process(i2,clk) begin case i2 is when "0000"=> d_out2:="11010000001"; when "0001"=> d_out2:="11011001111"; when "0010"=> d_out2:="11010010010"; when "0011"=> d_out2:="11010000110"; when "0100"=> d_out2:="11011001100"; when "0101"=> d_out2:="11010100100"; when "0111"=> d_out2:="11010001111"; when "1000"=> d_out2:="11010000000";

when "1001"=> d_out2:="11010000100"; when others => d_out2:="11010110000"; end case; end process;

process(i3,clk) begin case i3 is when "0000"=> d_out3:="10110000001"; when "0001"=> d_out3:="10111001111"; when "0010"=> d_out3:="10110010010"; when "0011"=> d_out3:="10110000110"; when "0100"=> d_out3:="10111001100"; when "0101"=> d_out3:="10110100100"; when "0111"=> d_out3:="10110001111"; when "1000"=> d_out3:="10110000000"; when "1001"=> d_out3:="10110000100"; when others => d_out3:="10110110000"; end case; end process;

process(i4,clk) begin case i4 is when "0000"=> d_out4:="01110000001"; when "0001"=> d_out4:="01111001111"; when "0010"=> d_out4:="01110010010"; when "0011"=> d_out4:="01110000110"; when "0100"=> d_out4:="01111001100"; when "0101"=> d_out4:="01110100100"; when "0111"=> d_out4:="01110001111"; when "1000"=> d_out4:="01110000000"; when "1001"=> d_out4:="01110000100"; when others => d_out4:="01110110000"; end case; end process; --------------------------------------------process(clk) begin if(rising_edge(clk)) then cld:=cld+1; if (cld=50000) then clkt:=not clkt; cld:=0; end if; end if; clk_tncs,DATA1=>data,START=>start,DONE=>do ne); bcd: BCD12SEVSEG port map(u_data=>u_data,d_in=>data,clk=>clk_i,done=> done,d_o=>d1_out, control=>control); end Behavioral; Applications and related modifications: This can be applied to many industrial application as well as in some home appliances also.

Reference: [1] Nexys 2 reference manual [2] AD7476 datasheet [3] Pmod AD1 reference sheet [4] LM 35 datasheet