Formula Sheet for Electronic Devices Final Exam

Electronic Devices Final Exam Formula Sheet

Daniel Townsend

MOSFETs Large Signal and DC Response F m

Units:

kp = kp0



W L

Cox =



 = (µp Cox )

F m2

µ=

(|VOV |)2 = (VSG − |Vtp |)2

2

m V·s

k=

A V2

PMOS     W ox W = (µp ) L tox L 1 1 = rDS = gDS kp |vOV |

lT ow nse n

NMOS        W ox W W = (µn Cox ) = (µn ) kn = kn0 L L tox L 1 1 2 2 (VOV ) = (VGS − Vtn ) rDS = = gDS kn vOV Cut-off (vGS < Vtn ) iD = 0 Tri. Region (vGS > Vtn ) & (vGD > Vtn = vDS < vOV )  1 iD = kn vOV − vDS vDS 2 Sat. Region (vGS > Vtn ) & (vGD ≤ Vtn = vDS ≥ vOV ) 1 iD = kn (VOV )2 · (1 + λvDS ) 2 Note: Do not forget the

tox = m

d

ox = 3.9o = 3.9 × 8.854 · 10−12 ' 3.45 · 10−11

Cut-off (vSG < |Vtp |) iD = 0 Tri. Region (vSG > |V tp |) & (vDG > |Vtp | = vSD < |vOV |)  1 iD = kp |vOV | − vSD vSD 2 Sat. Region (vSG > |Vtp |) & (vDG ≤ |Vtp | = vSD ≥ |vOV |) 1 iD = kp (|VOV |)2 · (1 + |λ|vSD ) 2 in the saturation equation!

MOSFETs Small Signal Response (linear region of saturation mode) NMOS gm

PMOS

id = = kn VOV vgs

VA 1 ro = = ID λID

gm

id = = kp |VOV | vgs

ro =

|VA | 1 = ID |λ|ID

D

D

gm vgs

G

gm vgs

+ vgs

ro

G

ro

+

1 gm

vgs

−

−

S

S

Hybrid-π model

T-Model

iB =

Symbol

iE β+1

Cut-off

0.7V

E

VCE > .7V

E

E B

C VEB < 0 & VBC < 0

E B

0.7V

B

βIB

0.7V

C VEC > .7V

E

iC < βiB

− +

Da

NPN

B

0.2V

− +

C

Area Base Width

Saturation C

− +

E

E

B

B

0.7V

VBE < 0 & VCB < 0

IS ∝

βIB

B

B

E

PNP

β β+1

Active C

C

C

DC Equivalent Circuits

α=

− +

iC = αiE = βib

− +

vBE VT

− +

iC = IS e

nie

BJTs Large Signal and DC Response

C iC < βiB

0.2V

For NPN change vBE to vEB

Electronic Devices Final Exam Formula Sheet

Daniel Townsend

BJTs Small Signal Response (linear region of active mode) IC VT

rπ =

VT IB

re =

VT IE

ro =

|VA | IC

re =

α gm

rπ =

β gm

rπ = (β + 1)re

d

gm =

C

lT ow nse n

C

gm vbe

gm vbe

ro

B

re

vbe

rπ B

+

vbe

ro

+ −

− E

E

Hybrid-π Model

T-Model

Amplifier Design

Rsig

Rin =

+ − +

vsig

Rin

vin iin

Av o

+

gm vin

vin −

vtest itest vi =0 or make an equivalent resistance excluding RL

vo RL

Ro

Ro =

−

vo = vin RL =∞ Av = Gv =

vo vi vo vsig

Diode Bias Models

+

P

Symbol

VD

− ID

Exponential Model

Exponential Model, iterative analysis Assume V1 = .7V, I1 = 1mA R I

VD

ID = IS e nVT

N

VDD

Constant Voltage Drop Model

P

Foward

ID > 0

N

+

− +

Ideal Diode Model

V −

P

Reverse

+ VD < 0 −

iD = IS e

VD +vd nVT

N

P

= IS e

VD nVT

e

vd nVT

Da IZ

VZO

VZ

−

VZ = Nominal Voltage

rZ

− +

+

+

VZO + rZ IZ −

N

.7V

Small Signal Model   vd vd ID vd nVT = ID e ' ID 1 + ∴ id = nVT nVT

Zener Diodes IZ

VDD − Vk R   Ik+1 Vk+1 − Vk = (2.3)(n)(VT ) log Ik Ik+1 =

− +

nie

VD = .7V

∴ rd =

nVT ID

Line / Load Regulation Small Signal

Zener Shunt Regulator

Line Regulation

Line Regulation

rd total mV ∆Vo = ∆V + RS + rd total V

rZ mV ∆Vo = ∆V + RS + rZ V

Load Regulation

Load Regulation

∆Vo mV = |rd total | ∆IL mA

∆Vo mV = |rZ | ∆IL mA