Fabrication Layout Design Rules 2005

Fabrication and Manufacturing (Basics)

• Batc Batchh proc proceesse sses

• Sili Silico conn is is nea neatt stu stuff  ff 

– Fabricati Fabrication on time time independen independentt of design complexity

• Stan Standa dard rd proc proces esss – Custom Customiza izatio tionn by mask maskss – Each Each mask mask define definess geome geometry try on one layer – Lower-l Lower-leve evell masks masks define define transistors – Higher Higher-l -leve evell masks masks define define wiring EE 261

– Oxide Oxide prote protects cts thin things gs from from impurities – Can be be etched etched sele selecti ctivel velyy on silicon or metal

• Can be be doped – Add P or As imp impuri uriti ties es

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CMOS Fabrication • CMOS transistors transistors are fabric fabricated ated on silicon silicon wafer wafer • Lithograph Lithographyy process process similar similar to to printing printing press • On each each step, step, different different materi materials als are are deposit deposited ed or or etched • Easiest Easiest to understand understand by viewing viewing both top and and cross-section of wafer in a simplified manufacturing process

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Making Chips Masks Chemicals

Processed wafer

Processing

Chips

Wafers

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Inverter Cross-section • Typica Typically lly use use p-typ p-typee substr substrate ate for for nMOS nMOS transistors • Requir Requires es n-wel n-welll for body body of pMOS pMOS tran transis sistor torss A GND

VDD

Y

SiO2 n+ diffusion

n+

n+

p+

p+ n well

p substrate nMOS transistor

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p+ diffusion polysilicon metal1

pMOS transistor

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Well and Substrate Taps • Substra Substrate te must must be tied tied to GND GND and n-we n-well ll to V DD • Metal to lightl lightly-dop y-doped ed semico semiconduct nductor or forms forms poor poor connection called Shottky Diode • Use heavil heavilyy doped doped well and and substra substrate te contac contacts ts /  taps A GND

VDD

Y

p+

n+

n+

p+

p+

n+

n well p substrate substrate tap

well tap

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Inverter Mask Set • Transi Transisto stors rs and and wires wires are are defi defined ned by masks • Cross-s Cross-sect ection ion take takenn along along dashe dashedd line line

A

Y

GND

VDD nMOS transistor

pMOS transistor well tap

substrate tap

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Detailed Mask Views n well

• Six masks – – – – – –

n-w n-well Poly Polysi sili lico conn n+ diff diffus usio ionn p+ diff diffus usio ionn Cont Contaact Metal

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

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Basic Processing Steps • N-diffusion N-diffusion created created by by dopin dopingg regions regions of the the substrate • Poly and metal metal are laid laid over the substr substrate, ate, with oxide to insulate them from substrate and each other • Wires are added added in layers, layers, alternating alternating with oxide • Vias Vias are are cut cut in the the oxi oxide de

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Fabrication Steps • Featur Features es are are patt pattern erned ed on on a wafer wafer by by a photolithographic photolithographic process –

Photo-light lithography, n. process of printing from a

plane surface on which image to be printed is ink-receptive and the blank area is ink-repellant

• Cover the wafer wafer with with a lightlight-sens sensitive itive,, organic organic mater material ial called  photoresist  • Expose Expose to ligh lightt with with the the prope properr patte pattern rn (ma (mask) sk) • Patterns Patterns left left by photoresis photoresistt can be be used used to control control where where oxide is grown or materials are placed placed on surface of wafer EE 261

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Fabrication Steps • Layout Layout contai contains ns informa information tion on what what pattern patternss have have to made on the wafer • Masks are create createdd using using the layout layout informa information tion provided by the designer • Procedure Procedure invol involves ves selecti selective ve removal removal of the the oxide oxide – Coat the oxide oxide with with photoresist photoresist,, polymerize polymerizedd by UV light (applied through mask) – Polymeriz Polymerized ed photoresist photoresist dissolv dissolves es in acid – Photoresis Photoresistt itself itself is acid-resi acid-resistan stantt

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Fabrication Steps • Start Start with with blan blankk waf wafer er • Build Build inve inverte rterr from from the the botto bottom m up • First First step step will will be to to form form the the n-we n-well ll – – – –

Cover wafer wafer with protec protective tive layer layer of SiO SiO2 (oxide) Remove Remove layer layer where where n-well n-well should should be built built Implant Implant or diffuse diffuse n dopants dopants into exposed exposed wafer wafer Stri Stripp off off SiO SiO2

p substrate

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Oxidation • Grow SiO2 on top of Si wafer – 900 900 – 1200 1200 C wit withh H2O or O2 in oxidation furnace

SiO2

p substrate

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Photoresist • Spin Spin on phot photor ores esis istt – Photoresis Photoresistt is a light-sen light-sensiti sitive ve organic polymer polymer – Softens Softens where where expose exposedd to light light Photoresist SiO2

p substrate

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Lithography • Expose Expose photo photoresi resist st throug throughh n-well n-well mask mask • Strip Strip off off expo exposed sed photor photoresi esist st

Photoresist SiO2

p substrate

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Etch • Etch Etch oxide oxide with with hydro hydroflu fluori oricc acid acid (HF) – Seeps Seeps through skin skin and eats eats bone; nasty nasty stuff!!! stuff!!!

• Only attacks attacks oxide oxide where resist has been been expose exposedd Photoresist SiO2

p substrate

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Strip Photoresist • Strip Strip off off remai remainin ningg photo photores resist ist – Use mixture mixture of acids acids called called pirana piranahh etch

• Necessary Necessary so resist resist doesn’t doesn’t melt melt in next next step

SiO2

p substrate

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n-well • n-well n-well is is formed formed with with diffus diffusion ion or ion ion implantation • Diffusion – Place Place wafer wafer in furnace furnace with arsen arsenic ic gas – Heat until As As atoms atoms diffuse diffuse into into exposed exposed Si

• Ion Ion Impl Implan anat atat atio ionn – Blast Blast wafer wafer with with beam beam of As ions – Ions Ions bloc blocked ked by SiO SiO2, only enter exposed Si SiO2 n well

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Strip Oxide • Strip Strip off the the remai remainin ningg oxide oxide using using HF • Back Back to to bare bare wafer wafer with with n-well n-well • Subsequent Subsequent steps involve involve similar similar series of steps steps

n well p substrate

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Polysilicon • Deposi Depositt very very thin thin layer layer of of gate gate oxide oxide – < 20 Å (6-7 (6-7 ato atomi micc lay layer ers) s)

• Chemic Chemical al Vapor Vapor Deposi Depositio tionn (CVD) (CVD) of silicon silicon layer – Place Place wafer wafer in furnace furnace with Silane Silane gas gas (SiH (SiH 4) – Forms Forms many small small crystals crystals called called polysilico polysiliconn – Heavily Heavily doped doped to be be good conductor conductor Polysilicon Thin gate oxide n well p substrate

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Polysilicon Patterning • Use same same litho lithogra graphy phy proc process ess to to patter patternn polysilicon

Polysilicon

Polysilicon Thin gate oxide n well p substrate

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Self-Aligned Process • Use oxid oxidee and maskin maskingg to expo expose se where where n+ n+ dopants should be diffused or implanted • N-diffusion N-diffusion forms nMOS source, source, drain, drain, and n-well contact

n well p substrate

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N-diffusion • Patte Pattern rn oxid oxidee and and form form n+ regi regions ons • Self-aligned process where gate blocks diffusion • Polysilic Polysilicon on is better better than metal metal for self-a self-aligne lignedd gates gates because it doesn’t melt during later processing

n+ Diffusion

n well p substrate

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N-diffusion cont. • Histor Historica ically lly dopant dopantss were diffus diffused ed • Usuall Usuallyy ion ion impla implanta ntatio tionn toda todayy • But regi regions ons are are still still calle calledd diffus diffusion ion

n+

n+

n+ n well

p substrate

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N-diffusion cont. • Strip off oxide oxide to compl complete ete patterning patterning step

n+

n+

n+ n well

p substrate

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P-Diffusion • Similar Similar set of steps steps form form p+ diffusion diffusion regio regions ns for pMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+

p+

p+

n+

n well p substrate

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Contacts • Now we we need need to wire wire toge togethe therr the devi devices ces • Cover Cover chip chip with with thick thick fiel fieldd oxide oxide • Etch Etch oxide oxide where where conta contact ct cuts cuts are are needed needed Contact

Thick field oxide p+

n+

n+

p+

p+

n+

n well p substrate

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Metalization • Sputte Sputterr on alumin aluminum um (coppe (copper) r) over over whole whole wafer wafer • Pattern Pattern to remove remove excess excess metal, metal, leaving leaving wires

Metal

Metal Thick field oxide p+

n+

n+

p+

p+

n+

n well p substrate

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Basic Processing Steps (Summary) • Star Startt with with waf wafer er at at curr curren entt step • Add phot photor oreesist sist • Patt Patter ernn phot photor ores esis istt with with mask • StepStep-spe specif cific ic etch, etch, implan implant,t, etc. • Wash ash of off re resist ist

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Layout • Chips Chips are are spec specifi ified ed with with set set of of masks masks • Minimum Minimum dimensio dimensions ns of masks masks determine determine transistor transistor size (and hence speed, cost, and power) • Feature si size f = distance between source and drain – Set by minimum minimum width of polysil polysilicon icon

• Featu Feature re size size impro improves ves 30% 30% every every 3 years years or so • Normaliz Normalizee for feature feature size size when when descri describing bing design design rules rules • Ex Expr pres esss rul rules es in ter terms ms of λ = f  /2 – E.g. λ = 0.3 μm in 0.6 μm process EE 261

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Design Rules • Design rules govern govern the the layout layout of indiv individual idual components: transistors, wires, contacts, vias – How small small can the gates gates be, be, and how small small can the wires be made?

• Conf Confli lict ctin ingg Dem Deman ands ds:: – component component packing: packing: more functiona functionality, lity, higher higher speed – Chip yield: smaller smaller sizes can can reduce yield (fraction (fraction of  good chips)

• Conser Conservat vative ive vs aggres aggressiv sivee design design rules rules EE 261

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Foundry Interface Layout (mask set)

Foundry

Designer Design Rules Process Parameters Krish Chakrabarty

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Geometric Design Rules • Resol solution – Width Width and spacin spacingg of lines lines on one one layer layer

• Alignment – – – –

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make sure sure interacti interacting ng layers layers overlap overlap (or don’t) Contact Contact surrou surround nd Poly Poly overla overlapp of diffus diffusion ion Well surround surround of diffusion diffusion

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SCMOS Design Rules • Scalable Scalable CMOS CMOS design design rules • Feature Feature size λ= half the drawn gate length length (poly width) • Mentor Graphics IC tool has built-in design rule checker (DRC) Example design rules: Layer Metal 1 Metal 2 Poly EE 261

Minimum Width Separation 3λ 3λ 3λ 4λ 2λ poly-poly: 2 λ poly-diff: 1 λ Krish Chakrabarty

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Simplified Design Rules • Conser Conservat vative ive rules rules to get you you start started ed

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Tub Ties and Latchup • • • • •

Substr Substrate ate must must be be connec connected ted to to power power supply supply p-t p-tub for for nMO nMOSS to to VSS (Gnd) N-t N-tub for for pM pMOS to VDD Connection Connectionss made made by special special vias called called tub tub ties ties Conservati Conservative ve design design rule: rule: place place tub ties for every every one one or two transistors • Why not place one tie tie in each tub that that has has 50 transist transistors? ors?

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Latchup • Too few few ties: ties: high high resistanc resistancee between between tub tub and power power supply, supply, leads leads to parasitic bipolar transistors inhibiting normal chip operation • Parasiti Parasiticc silicon-c silicon-contr ontrolle olledd recti rectifier fier (SCR) • When both both bipolar bipolar transist transistors ors are are off, off, SCR conducts conducts no no current current • SCR turns turns on: high current current short-c short-circui ircuitt between between VDD and Gnd.

V  DD V  DD  p+

n+

n+

 p+

 p+

n-well  R psubs

 p-source

 Rnwell

 p-substrate

(a) Origin of latchup

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 Rnwell

n+

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 R psubs

(b) Equivalent circuit

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Gate Layout • Layout Layout can be very very time time consu consumin mingg – Design Design gates gates to fit toget together her nicely nicely – Build a library library of standa standard rd cells cells

• Standa Standard rd cell cell desig designn metho methodol dology ogy – – – – EE 261

VDD and GND should abut (standard height) Adjacent Adjacent gates gates should should satisfy satisfy design design rules nMOS at bottom bottom and and pMOS at top top All gates gates include well well and substrate substrate contac contacts ts Krish Chakrabarty

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Inverter Layout • Transistor Transistor dimension dimensionss specifie specifiedd as Width / Length Length – Minimu Minimum m size size is 4λ / 2λ, sometimes called 1 unit – In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long

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Example: Inverter

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Example: NAND3 • • • • •

Horizontal Horizontal N-diffusio N-diffusionn and and p-diffusio p-diffusionn strips strips Vert Vertic ical al poly polysi sili lico conn gates gates Metal1 VDD rail at top Meta Metal1 l1 GND GND rai raill at at bott bottom om 32 λ by 40 λ

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Stick Diagrams •

Stick diagrams

help plan layout quickly

– Need Need not be to to scal scalee – Draw with with color pencils pencils or or dry-erase dry-erase marker markerss

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Stick Diagrams • Designing Designing compl complete ete layout layout in terms terms of rectan rectangles gles can be overwhelming • Stick diagram: diagram: abstra abstractio ctionn between between transis transistor tor schema schematic tic and and layout – Carto Cartoon on of of a chip chip layout layout

• Repl Replac acee rect rectan angl gles es by by line liness transistor

VDD a

a Gnd

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a Poly (red) n-type diffusion (green)

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VDD (blue) p-type diffusion (yellow) Metal 1 (blue)

VSS (Gnd) 42

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Stick Diagram VDD

Metal 1

a

b z

VDD

p-diffusion a

b

a b

Poly Gnd

n-diffusion

Metal 1 EE 261

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Wiring Tracks • A wiring track is the space required for a wire – 4 λ width, 4 λ spacing from neighbor = 8 λ pitch

• Transi Transisto stors rs also also consu consume me one one wiring wiring track track

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Well spacing • Wells Wells must must surrou surround nd tran transist sistors ors by by 6 λ – Impl Implie iess 12 12 λ between opposite transistor flavors – Leaves Leaves room for one one wire wire track track

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Area Estimation • Estima Estimate te area area by coun countin tingg wiring wiring trac tracks ks – Multip Multiply ly by 8 to expr express ess in in λ

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Example: O3AI • Sketch Sketch a stick stick diagram diagram for for O3AI and estima estimate te area area – Y = ( A+ B + C) D

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Example: O3AI Y = ( A+ B + C) D

• Sketch Sketch a stick stick diagram diagram for for O3AI and estima estimate te area area

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Example: O3AI Y = ( A+ B + C) D

• Sketch Sketch a stick stick diagram diagram for for O3AI and estima estimate te area area –

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Some Layout Hints • Plan Plan the the glo globa ball str struc uctu ture re (“big picture”), then design cells

• Wiri Wiring ng on on orth orthog ogon onal al metal layers

– Floo Floorp rpllan – Wiri Wiring ng str strat ateg egyy – Powe Powerr and and grou ground nd distribution – System Systemati aticc place placeme ment nt – Keep Keep all all pMO pMOS/ S/nM nMOS OS together – Place Place trans transis istor torss in rows: rows: share source/drain diffusion

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– Assig Assignn pref prefer erre redd directions to M1 and M2 – Use diffus diffusion ion only only for for devices, not for interconnect – Use poly poly only only for very very local interconnect

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Cell Minimization • Chip area area (cell (cell size) size) must must be minimi minimized zed caref carefully ully

Impact of die size/chip area on cost (unpackaged dies) Nominal 1% increase 15% increase Pentium die in die size in die size Wafer cost $1,460 $1,460 $1,460 2 2 Die size 160.2 mm 161.8 mm 184.2 mm2 Die cost $84.06 $85.33 $102.55 1% increase in die size leads to 3% Chips decrease in stock price for Intel! fabricated per week 498.1 K 482.9 K 337.5 K Added annual cost $63.5 M $961 M Krish Chakrabarty

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Minimize number of diffusion strips • How do we order the gate gate inputs (poly)? (poly)? • More diffusi diffusion on strips strips ⇒ more spacing, more area VDD Try a, b, c, d, e: VDD

e a

x

x

x

x

x

d

b

F

c F

a d

e

b c

x x Gnd

a

x b

c

x x d

x x e

Two n-diff gaps, zero p-diff gaps EE 261

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e

VDD

b a

a d

e

d

a

b

d

b

e

c

c

c

pMOS graph

nMOS nMOS graph graph

a e

d

b c Gnd

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• Euler path: path: Visit Visit every edge edge exactly once • Find all Euler Euler paths paths for nMOS and pMOS pMOS graphs graphs • Find pp- and n-path n-path that that have have identic identical al labeling • For exampl example: e: d, e, a, a, b, c • If no such path path exists, then break diffusion into into strips

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VDD

e

pMOS graph

b a

a e a

d d

d

b

b

c

e

c

c

nMOS nMOS graph graph VDD

x

F

a e d

b c

x

x

x

x

x

x

F

Gnd

Ordering: d, e, a, a, b, c: Zero n-diff gaps, zero p-diff gaps EE 261

x

x

Gnd d

e

a

x b

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Summary • • • •

MOS Transis Transistors tors are are stack stack of of gate, gate, oxide, oxide, silicon silicon Can be be viewed viewed as as electric electrically ally controlle controlledd switches switches Build Build logi logicc gates gates out of switc switche hess Draw Draw masks masks to specify specify layou layoutt of transis transistor torss

• Now you you know know everyth everything ing nece necessa ssary ry to start start designing schematics and layout for a simple chip! EE 261

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