Experiment Manual

University of Santo Tomas Faculty of Engineering Information and Computer Science Department

(Logic Circuit with Digital Circuit Design)

EXPERIMENT 1: ............... ............................... ............................... ............................... ................ 2 DIGITAL TRAINER AND SSI GATES FAMILIARIZATION .................... 2 EXPERIMENT 2: ............... ............................... ............................... ............................. .............. 11 OGIC GATES TRUTH TABLE DERIVATION ................................ L OGIC ................................ 11

EXPERIMENT 3: ............... ............................... ............................... ............................. .............. 15 COMBINATIONAL CIRCUIT: L OGIC OGIC GATE INTERCONNECTION......... 15 EXPERIMENT 4: ............... ............................... ............................... ............................. .............. 19 SIMPLIFICATION OF BOOLEAN E XPRESSION ........................... .............................. .... 19 EXPERIMENT 5: ............... ............................... ............................... ............................. .............. 22 ADDER

AND

SUBTRACTER CIRCUIT .......................................... .......................................... 22

EXPERIMENT 6: ............... ............................... ............................... ............................. .............. 27 NAND-NAND AND NOR-NOR IMPLEMENTATIONS .................... 27 EXPERIMENT 7: ............... ............................... ............................... ............................. .............. 33 DECODER CIRCUIT ............................................................ ............................................................... .... 33 EXPERIMENT 8: ............... ............................... ............................... ............................. .............. 38 MULTIPLEXER IMPLEMENTATION ............................................. ............................................. 38 EXPERIMENT 9: ............... ............................... ............................... ............................. .............. 42 BASIC FLIP-FLOPS ................................................... ................................................................ .............. 42 EXPERIMENT 10: ............... ............................... ................................ ........................... ........... 47 SEQUENTIAL LOGIC CIRCUIT ............................................ ................................................... ....... 47

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Experiment 1:

Digital trainer and SSI Gates Familiarization OBJECTIVES 1. 2. 3. 4. 5.

To identify the input and output terminals of a gate in an IC package. To identify the supply terminals of SSI IC. To determine the state of input and output terminals of SSI gates using Logic Probe. To be able to use the digital trainer properly To able to determine and understand the functions of the different parts of digital trainer.

BASIC INFORMATION Digital Trainer The different parts of the digital trainer are designed so that it will be convenient to construct and test simple digital circuits.

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Parts of the Digital Trainer: 1. Breadboard/ Protoboard The breadboard or protoboard serves as the temporary circuit board for experimental circuit. The components are placed in the board and connected using solid wires (jumpers). Additional breadboard can be used if the circuit is large and cannot be accommodated in the board provided in the trainer.

2. Power Supply The power supply provides a constant or regulated DC output voltage of 5V. this power supply is the same power used all throughout the trainer.

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3. LEDs There are eight LEDs available. These are activated by supplying a TTL high to each of the corresponding terminal block pins.

4. Switches There are eight available switches in the kit, six (Sw0 to Sw0) of which are ordinary toggle switched while the two others are debounced switches (Sw6 & Sw7). The common node of the single pole double throw switches is connected to the wire holder while the other two nodes to ground and Vcc.

5. 7-segment Display The two seven segment displays are driven by 7447 BCD-to-seven-segment display decoders/drivers. The said driver has 4 inputs corresponding to the binary code of the desired decimal output on the seven segment display. Inputs

not connected to any value are considered as ‘floating’ HIGH, thus causing the display to turn off when not in use.

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6. Digital Clocks Two clocks are provided by the kit, one having a fix frequency of 1KHz and the other having a variable frequency of 3- 50Hz. “OUT” is for the fix clock, and  “OUT*” is for variable clock.

7. The Logic Probe Two logic probes are provided with logic LOW, HIGH, UNDEFINED/OPEN (not high or low) CIRCUIT indicator. It is labeled “LP1” and “LP2” 

SSI Gates Some TTL circuits as shown in Figure 1-1. Each IC is enclosed within a 14 or 16 pin package. A notch placed on the left side of the package is used as reference for the pin numbers. The pins are numbered along the two sides starting from the notch and continuing counterclockwise. The inputs and outputs of the gates are connected to the package pins.

The TTL IC’s are distinguished by their numerical designation, e.g. the 5400 and 7400 series. The former has a wide temperature range is suitable for military use, while

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the latter has a narrower temperature range and is suitable for commercial use. The numerical designation of the 7400 series means that the IC packages are numbered as 7400, 7401, 7402, etc. The differences between the various TTL series are in their electrical characteristics, e.g., power dissipation, propagation delay, and switching speed. They do not differ in pin assignment NOR on the logic operation performed by the internal circuits. For example, all the ICS listed in Table 1-1 with an 86 number, no matter what the prefix, contain four exclusive OR gates with the same pin assignment in each package. MATERIALS 1 Logic Probe 1 Fixed Power Supply 1 Protoboard 1 Digital Trainer Integrated Circuits (ICs) 1 74LS00 1 74LS02 1 74LS04

1 1

Long Nose Pliers Wire Stripper Pliers Connecting Wires

1 1 1

74LS08 74LS32 74LS86

PROCEDURES 1. Examine the ICs supplied to you. The IC number is printed on the surface of each IC. 2. Connect the 74LS00 as shown in Figure 1-2. Supply the IC with 5V and Ground. 3. Using the logic probe, test the status condition or logic level at the input and output terminals. 4. Of each gate in the IC. Record the logic values in the corresponding tables. 5. Remove the IC mounted on the protoboard and replace it with another IC. 6. Repeat step 3 for each of the other ICs. 7. Repeat steps 2 to 4 using the digital trainer. Compare results.

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14

13

12

11

10

9

8

14

13

12

11

10

9

Vcc

Vcc

GND

GND 1

2

3

4

5

6

7

74LS08 - Quad 2-Input AND Gate

14

13

12

11

10

9

8

Vcc

1

2

3

4

5

6

14

13

12

11

10

9

3

4

5

6

7

74LS32 - Quad 2-Input OR Gate

13

12

11

10

9

GND 1

2

3

4

5

6

7

74LS86 - Quad 2-Input XOR Gate

8

14

13

12

11

10

9

8

Vcc

Vcc

GND

GND 1

8

Vcc

2

14

7

74LS00 - Quad 2-Input NAND Gate

GND 1

8

2

3

4

5

6

7

1

74LS02 - Quad 2-Input NOR Gate

2

3

4

5

6

7

74LS04 - Hex Inverter 

Figure 1-1 Basic Gates Pin Configuration

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5V

Power  Supply

14

13

12

11

10

9

8

VCC

GND 1

2

3

4

5

6

7

connection connection f or  logic logic p robe

Figure 1-2 Experimental Circuit Set-up

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DATA AND RESULTS Table 1-1 Test Results for 74LS00 IC Input Terminals Output Terminals Pin Logic Pin Logic No. Level No. Level 1 3 2 6 4 8 5 11 9 10 12 13

Table 1-2 Test Results for 74LS02 IC Input Terminals Output Terminals Pin Logic Pin Logic No. Level No. Level 2 1 3 4 5 10 6 13 8 9 11 12

Table 1-3 Test Results for 74LS08 IC Input Terminals Output Terminals Pin Logic Pin Logic No. Level No. Level 1 3 2 6 4 8 5 11 9 10 12 13

Table 1-4 Test Results for 74LS32 IC Input Terminals Output Terminals Pin Logic Pin Logic No. Level No. Level 1 3 2 6 4 8 5 11 9 10 12 13

Table 1-5 Test Results for 74LS86 IC Input Terminals Output Terminals Pin Logic Pin Logic No. Level No. Level 1 3 2 6 4 8 5 11 9 10 12 13

Table 1-6 Test Results for 74LS04 IC Input Terminals Output Terminals Pin Logic Pin Logic No. Level No. Level 1 2 3 4 5 6 9 8 11 10 13 12

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QUESTIONS 1. What is the logic al equivalent of the “hang” input? __________  __________ 2. Identify the following ICs with the same pin configuration.

3. Describe the pin configurations of 74LS02 and 74LS04 ICs.

4. Describe the functionalities of the Digital trainer.

5. What are the possible benefits in using digital trainer in the construction of digital circuits?

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Experiment 2:

Logic Gates Truth Table Derivation

OBJECTIVES 1.To study the operation of logic gates 2.To demonstrate the derivation of the truth table for SSI gates. 3.To determine whether the gates are working properly or not. BASIC INFORMATION Logic gates are building blocks of logic circuits that run computer hardware. Logic gates are the basic representation of the logical operations performed on Boolean expression. Functional operation of any binary expression can be translated to hardware via logic gates. They are fundamental in understanding more complex digital circuitry.  A truth table defines a logic operation by a list of the output of the operation against all the possible input combinations. 74LS00 Input  A B 0 0 0 1 1 0 1 1 74LS08 Input  A B 0 0 0 1 1 0 1 1 74LS86 Input  A B 0 0 0 1 1 0 1 1

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Output

X=(AB)’  1 1 1 0

74LS02 Input  A B 0 0 0 1 1 0 1 1

Output X= AB 0 0 0 1

74LS32 Input  A B 0 0 0 1 1 0 1 1

Output

74LS04 Input  A 0 1

X= (AB’+A’B) 0 1 1 0

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Output

X= (A+B)’  1 0 0 0

Output X= A+B 0 1 1 1

Output

X= A’  1 0

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MATERIALS 1 1

Digital Trainer Long nose pliers Integrated Circuit (IC) 74LS00 74LS04 74LS32

1 1 1

1

Cutter pliers Connecting wires

1 1 1

74LS02 74LS08 74LS86

PROCEDURE 1. Wire the 74LS00 as shown in Figure 2-1. Set the power supply to 5V. 2. Test each IC (7400, 7402, 7404, 7408, 7432, ad 7486) if all the gates inside are working properly. 3. Testing is done by comparing comparing the output of the IC with the output of the truth table using the flowchart below. Start

Connect the inputs (A, B) to switches; connect the output (X) to LED

Set the switches based on the truth table values(A, B); compare the output (X) with output in the DATA STATUS LED

Is X= LED?

NO

NO

Logic gate is faulty

YES

Set the next input combination (A, B) based on the truth table

Last input combination?

YES

Logic gate is working properly

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4. Remove the IC mounted on the breadboard and replace it with another IC. 5. Repeat step for each of the other IC’s. CIRCUIT DIAGRAMS / SCHEMETICS +5V

Ground

Terminal

Terminal

Figure 2-1 Experimental Circuit Set-up

DATA GATHERING: Fill-up the table below based on the testing procedure. Check (√) if the gate is working properly. Write (X) if a particular gate is faulty. Take note: a faulty gate does not necessary make the other gates in one IC faulty as well. IC

U1

U2

U3

U5

U6

NA NA

NA NA

7408

NA

NA

7432 7486

NA NA

NA NA

7400 7402

U4

7404

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QUESTIONS: Referring to the truth tables, write logical statements that suitably describes the function table of each of the following basic gates: 1.  AND Gate

2. OR Gate

3. INVERTER

4. NAND Gate

5. NOR Gate

6. XOR Gate

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Experiment 3:

Combinational Circuit: Logic Gate interconnection OBJECTIVES 1. 2. 3. 4. 5.

To To To To To

interconnect a basic logic gate IC with other basic logic gates. experimentally verify the output signal of the resulting circuit. compare the certain gate combinations with existing basic gates. determine the equivalent truth table of the logic circuit translate Boolean expression to logic circuit.

Basic Information Combinational logic circuit (CLC) is a type of logic circuit composed of logic gates whose output is dependent entirely on the present or current input values. The circuit construction has well-formed (WF) structure meaning no feedback path; no 2 or more outputs of gates are tied together and only cascaded arrangements of logic gates. Simple CLC is the direct translation of Boolean expression in different formats such as simplified standard sum of product (SOP) format, standard format or canonical sum of product (SOP) or product of sum (POS). Combining or interconnecting logic gates forms a logic circuit. A logic circuit is an electronic circuit that processes information by performing logical operations on it. In logic circuits, there are only two possible levels for the input and output signals: HIGH and LOW, numerically represented by the binary digits 1 and 0, respectively. The output signal, using binary notation, is controlled by the logic circuit in accordance with the input system. The basic logic gates are the AND, the OR, and the INVERTER (NOT). Often, certain combinations of logic gates are commonly used, e.g., a NAND circuit consists of NOT + AND logic gates, and a NOR for NOT + OR.

MATERIALS 1 1 1 1 1

Digital Trainer Long nose pliers Integrated Circuit (IC) 74LS00 74LS04 74LS32

1

Cutter pliers Connecting wires

1 1 1

74LS02 74LS08 74LS86

PROCEDURE: 1. 2. 3. 4.

Connect the circuit shown in Figure 3-1 Supply the circuit with +5V and ground. Derive the truth table of the circuit and record the results. Repeat Step 2 for the Figures 3-1(b), 3-2, 3-3, 3-4, and 3-5 respectively.

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CIRCUIT DIAGRAMS / SCHEMETICS

 A

X

 A

Figure 3-1(a)

X

Figure 3-1(b)

 A

 A X

B

X B

Figure 3-2

Figure 3-3

 A B X

Figure 3-4  A B X

Figure 3-5

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DATA AND RESULTS:

Figure 3-1(a)

 A NAND gate gate with input terminals shortcircuited.

Figure 3-1(b)

 A NOR gate with input terminals shortcircuited.

Figure 3-2

 An AND gate gate with input terminals inverted (Bubbled  AND).

Figure 3-3

 Ad OR gate with with input terminals inverted (Bubbled OR).

Figure 3-4

 A combination combination of INVERTER, AND, and OR gates.

Figure 3-5

 A combination combination of INVERTER, AND, and OR gates.

 A 0 1  A 0 1  A 0 0 1 1  A 0 0 1 1  A 0 0 1 1  A 0 0 1 1

X

X

B 0 1 0 1 B 0 1 0 1 B 0 1 0 1 B 0 1 0 1

X

X

X

X

QUESTIONS: 1. Construct the theoretical truth tables for Figure 3-1 to Figure 3-5. Compare these with

the “actual” truth tables. Explain the discrepancies if any.

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2. Referring to your DATA AND RESULTS, identify the corresponding basic logic gate equivalent of each of the experimental circuit.

Figure

Equivalent Gate

Figure 3-1(a) Figure 3-1(b) Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 3. Is it possible for different Boolean expressions to have the same output? Why or why not?

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Experiment 4:

Simplification of Boolean Expression OBJECTIVES 1. 2. 3. 4.

To To To To

derive the experimental truth table from the given COMPLEX Boolean expression. simplify the given Boolean expression using the algebraic simplification techniques. design and connect a logic circuit from the simplified circuit. derive the actual truth table from the designed logic circuit.

BASIC INFORMATION

MATERIALS: 1 1 1 1 1 1

Logic Probe Power supply Long nose pliers Integrated Circuit (IC) 74LS00 74LS04 74LS32

1 1

Breadboard Cutter pliers Connecting wires

1 1 1

74LS02 74LS08 74LS86

PROCEDURE: 1. Examine the ICs supplied to you. The number is printed on the surface of each IC. 2. Given the COMPLEX Boolean expression in Table 1, draw and construct the corresponding combinational circuit to derive its truth table. Record the result in Table 1: Truth Table A. 3. Simplify the COMPLEX Boolean equation, please write your simplification solution and record the simplified equation in Table 1: Simplified Equation. 4. Draw the Logic circuit and construct the logic circuit to derive its truth table. Record the result in Table 1: Truth Table B. 5. Repeat Steps 1 to 4 for Table 2.

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DATA AND RESULTS: Table 1: COMPLEX EQUATION: F = ZX + ZX’Y  SIMPLIFIED EQUATION: F= Truth Table A Truth Table B X Y Z F X Y Z 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 COMPLEX EQUATION LOGIC CIRCUIT

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SIMPLIFICATION SOLUTION:

F

SIMPLIFIED EQUATION LOGIC CIRCUIT

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Table 2: COMPLEX EQUATION: C = A’B’ + AB + A’B SIMPLIFIED EQUATION: C= Truth Table A Truth Table B  A B C A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 COMPLEX EQUATION LOGIC CIRCUIT

SIMPLIFICATION SOLUTION

C

SIMPLIFIED EQUATION LOGIC CIRCUIT

QUESTIONS: 1. Compare Truth Table A and Truth Table B are the result the same? Explain any discrepancies?

2. What is the advantage of obtaining the simplified expression?

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Experiment 5:

 Adder and Subtracter Circuit Circuit OBJECTIVES 1. To study the operation of basic adders and subtracters 2. To construct simple adders and subtracters 3. To design adders or subracters for digital application. BASIC INFORMATION  Arithmetic  Arithmetic operations are very important in digital and computer processes. The design of them can be built from the basic adders and subtracters, subtracters, in particular the half-adder and full-adder. Half-adder Half-adder is a combinational circuit that performs addition of two bits. The design is shown below: SUM

 A 0 0 1 1

B 0 1 0 1

SUM CARRY 0 0 1 0 1 0 0 1

 AND2

CARRY XOR2

The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum of products expressions are:

SUM= A’B + AB’ = A XOR B CARRY = AB Full-adder Full-adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. It can be obtained using two half-adders as shown below:

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X1

A

SUM

A

B

B

CARRY

SUM

X2 halfadder  SUM

CARRY

C CARRY OR2 halfadder 

The sum of half-adder X1 is added to C via the next half-adder X2. The two carries are ORed to get the correct value. Half- Subtracters  A half-subtracter half-subtracter is a combinational combinational circuit circuit that performs subtraction subtraction on two two bits and and produces their difference.  A

 A 0 0 1 1

B 0 1 0 1

DIFF BORROW 0 0 1 1 1 0 0 0

BORROW

B

 AND2 DIFF XOR2

The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum of products expressions are:

DIFF = A’B BORROW = AB’ + A’B = A XOR B

Full - Subtracter  A full-subtracter full-subtracter is a combinational combinational circuit circuit that performs a subtraction subtraction of three three bits. bits. It consists of three inputs and two outputs. It can be obtained using two half-subtracter as shown below:

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X1

A A

B

B

DIFF BORROW

DIFF

X2 halfsubtracter  DIFF

C

BORROW

BORROW OR2 halfsubtracter 

MATERIALS: Digital Trainer Connecting wires Integrated Circuit (IC) 1 74LS04 1 74LS32

1

Long nose pliers

1 1

74LS08 74LS86

PROCEDURE: 1. Examine the ICs supplied to you. The number is printed on the surface of each IC. 74LS04 74LS08 74LS32 74LS86 2. Connect the circuit given above for half-adder and half-subtracter. Verify the truth table. 3. Fill the truth table for full-adder and full-subtracter. 4. Draw the equivalent logic circuit for full-adder and full-subtracter. Show complete solution. 5. Construct the circuit in the digital trainer and verify if the output if there are discrepancies. DATA GATHERING: FULL- ADDER INPUT OUTPUT  A B C SUM CARRY 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

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FULL-SUBTRACTER INPUT OUTPUT A B C DIFF BORROW 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

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K-map:

Full-Adder

Full-Subtracter

6. Design an adder/ subtracter combo (A+B/ A-B) using full-adder by adding another signal S. when S=0, the circuit performs addition but when S=1, the circuit performs subtraction. Hint: Draw, construct, test and fill-up the truth table below.  ADDER/ SUBTRACTER SUBTRACTER INPUT OUTPUT S B C 0 0 0 0 1 1 1 1

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0 0 1 1 0 0 1 1

SUM/DIFF

CARRY/ BORROW

0 1 0 1 0 1 0 1

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ADDER/SUBTRACTER CIRCUIT:

QUESTIONS: 1. Design a 4-bit parallel adder/subtracter. Draw the circuit below.

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Experiment 6:

NAND-NAND and NOR-NOR Implementations OBJECTIVES 1. To study universal gates: NAND and NOR 2. To simplify the given functions using SOP (considering 1’s) and POS (considering 0’s) solutions. 3. To construct NAND-NAND and NOR-NOR Networks. 4. 0To translate standard format to NAND or NOR format. 5. To experimentally derive the truth tables of NAND-NAND and NOR-NOR networks and compared these with their theoretical truth tables.

BASIC INFORMATION Digital circuits are more frequently constructed with NAND or NOR gates. NAND or NOR are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR gates in the design of digital circuits, rule and procedure have been developed for conversion from Boolean functions implemented with AND, OR and NOT into equivalent NAND and NOR logic diagrams.

NAND Implementations The implementations of a Boolean function with NAND gates require that the function be simplified in the Sum of Products (SOP) form. The following rule and procedures are observed for obtaining the NAND logic diagram from a Boolean function. 1. Simplify the function and express it in SOP form. 2. Draw a NAND gate for each product term of the function that has at least two literals. The inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates. 3. Draw a single NAND gate in the second level with inputs coming from the outputs of the first-level gates. 4.  A term with a single literal requires an inverter in the first level or may be complemented and applied as an input to the second-level NAND gate.

NOR Implementations The NOR function is the dual of the NAND function. For this reason all procedures and rules for the NOR logic are the duals for the corresponding procedures and rules developed for NAND logic.

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The implementation of a Boolean function with NOR gates requires that the function be simplified in Product of Sums (POS) form. The rules and procedures for obtaining the NOR logic diagram from a Boolean function is similar to the three-step NAND rule, except that the simplified expression must be in the Product of Sums and the terms for the firstlevel NOR gates are the sum terms. A term with single literal requires a one-input NOR or Inverter gate, or may be complemented and applied directly to the second-level NOR gate.

 Y = A’ = (AA)’ = (A+A)’ 

NAND2

NOR

 A NA  ND or a

NOR can be used to replace by an inverter by tying the inputs together.

 Y= AB = ((AB)’)’ = (A’+B’)’  A  Y B NAND2

NAND2

A  Y B AND2 A

NOR

 Y

B

NOR

 Y= A + B = ((A + B)’)’ = (A’B’)’  A  Y B NOR2

NOR2

A  Y B A OR2  Y

NAND2 NOR

B

NAND2

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 Y = A XOR B = ((AB’)’(A’B)’)’ = (((A’+B)’ + (A+B’)’)’  A

NAND2 NAND2

 Y NAND2

B NAND2 NAND2

A  Y B

A

NOR NOR  Y

NOR

NOR

B NOR NOR

MATERIALS: 2 2

Long Nose Pliers Wire Stripper Pliers

1

Connecting Wires Digital Trainer

Integrated Circuits (ICs) 2 74LS00 2 74LS02 PROCEDURES: 1. Plot the function in the map to simplify it. Consider t he 1’s to obtain the SOP expression for the NAND-NAND network. Do the same with map of the NOR-NOR network but this time

using the 0’s for POS. 2.  After obtaining obtaining the simplified simplified function function from from the K-map, K-map, construct construct the theoretical theoretical truth table of each network. 3. Test the logic level of each IC supplied and report any damage to the Laboratory Technician for immediate replacement. replacement. 4. Connect the circuit as shown in Figure 7-2. Adjust the power to 5V. 5. Derive the truth table of the circuit by applying logic combinations of 0 and 1 to the input variables according to the specified logic level in the truth table. Record the logic signal values in the corresponding table. 6. Repeat steps 4 and 5 for the circuit of Figure 7-3.

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DATA AND RESULTS: Q(A, B, C, D) =

(0,1,2,3,7,8,10) (0,1,2,3,7,8,10) + d(5,6,11,15) d(5,6,11,15)

1.  AND-OR Network Network  A. K-Map: SOP (encircle 1’s) 00

01

11

10

00 01 11 10

B. Simplified Function: _________________________________ C. Theoretical Truth Table  A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1

’  A ’ 

Q

B’ 

D’ 

B’ D’ 

’D   A ’ 

D. Experimental Truth Table  A 0 0 0 0 1 1 1 1

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B 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1

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Q

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2. OR-AND Network  A. K-Map: SOP (encircle 0’s) 00

01

11

10

00 01 11 10

B. Simplified Function: _________________________________

Figure 7-2 NAND-NAND Network

Figure 7-3 NOR-NOR Network C. Theoretical Truth Table  A 0 0 0 0 1 1 1 1

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B 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1

Q

’  A ’ 

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B’ 

D’ 

’+D A ’+

’+D’  A ’+

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D. Experimental Truth Table  A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1

Q

QUESTIONS: 1. Explain in your own words, the procedure for implementing Boolean function with:  A. NAND-NAND Network

B. NOR-NOR Network

2. What are the advantages and disadvantages of implementing logic circuit as NAND and NOR universal gates against standard formats such as POS and SOP?

3. Which implementation is better: NAND or NOR implementation? Why?

4. Determine the NAND implementation a. F(ABC) = Σ( 0, 3, 5,7)

5. Determine the NOR implementation. a. F(ABC) = Π ( 1,2,5,7) ***For 4 and 5: Draw the logic circuit at the back of this paper

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Experiment 7:

Decoder Circuit OBJECTIVES: 1. To demonstrate the unique output lines of a decoder. 2. To implement a full-adder circuit suing a decoder and two four-input NAND gates. MATERIALS:

1

4 1 1

Digital Trainer 74LS47

10Kohms resistor 100 ohms LED display

BASIC INFORMATION Decoders  A digital decoder has 2N  outputs and accepts N inputs. Only the output that corresponds to the binary number on the input lines is activated. Decoders are used in many digital circuits. They can be used to select memory addresses, and to decode instructions in a computer. They are used whenever only one line from several possible lines must be selected.

TRUTH TABLE 3-TO-8 DECODER INPUT

OUTPUT

X 0 0 0 0 1 1 1

Y 0 0 1 1 0 0 1

Z 0 1 0 1 0 1 0

D0 1 0 0 0 0 0 0

1

1

1 0

D1 0 1 0 0 0 0 0

D2 0 0 1 0 0 0 0

D3 0 0 0 1 0 0 0

D4 0 0 0 0 1 0 0

D5 0 0 0 0 0 1 0

D6 0 0 0 0 0 0 1

D7 0 0 0 0 0 0 0

0

0

0

0

0

0

1

The 3-to-8 decoder provides 8 unique output elements and 8 unique output combinations. The logic gate that can produce one unique output based on all input combination is AND gate. So, in the design the 3-to-8 decoder has 8 AND gates.

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TRUTH TABLE: BCD TO DECIMAL DECODER INPUT

OUTPUT

0 1 2 3 4 5 6

D 0 0 0 0 0 0 0

C 0 0 0 0 1 1 1

B 0 0 1 1 0 0 1

A 0 1 0 1 0 1 0

0 0 1 1 1 1 1 1

1 1 0 1 1 1 1 1

2 1 1 0 1 1 1 1

3 1 1 1 0 1 1 1

4 1 1 1 1 0 1 1

5 1 1 1 1 1 0 1

6 1 1 1 1 1 1 0

7 1 1 1 1 1 1 1

8 1 1 1 1 1 1 1

9 1 1 1 1 1 1 1

7 8 9  A B C D E

0 1 1 1 1 1 1 1

1 0 0 0 0 1 1 1

1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1

1 1 0 1 1 1 1 1

F

1

1

1

1

1

1

1

1

1

1

1

1

1

1

The BCD-to-Decimal decoder converts Binary Coded Digit to Decimal. There are 10 unique output elements for 4-bit input combination. Only 10 out of 16 possible input combinations result to the correct decoded output. The rest are incorrect since there must be only 10 combinations for a decimal code. Notice the output is inverted meaning NAND gates are used instead of AND gate. TTL 74145 is a BCD-to-Decimal decoder that follows the above truth table. Seven-Segment Decoders  A seven segment display consists of seven elements that are made of either LCD’s (liquid crystals) or LEDs (light-em ( light-emitting itting diode). The elements are labeled from a-g.

Seven segment indicators may be of the common  –cathode type in which all anodes are connected together. With the common-anode type, you have to connect a current  –limiting resistor between each LED and ground. The common-cathode type uses a current-limiting resistor between each LED and the +V CC. IT102L IT Department

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+VCC

b

a

b

a

c

d

e

f 

c

d

f 

e

g

g

Gnd (b) common cathode

(a) common anode

 A seven-segment decoder-driver is an IC decoder that that can be used to drive a seven-segment indicator. There are two types of decoder drivers, one for common anode indicators and the other for common-cathode indicators. Each decoder-driver has 4-input pins (the BCD input) and 7 output pins (a through g segments). A TTL TTL 7447 requires a CA seven segment display while TTL 7448 needs a CK seven segment display.

DATA GATHERING: 1. Construct the circuit below. 5V

16

VCC     s      e       h     c       t      i      w     s 

6 2 1 7

10k 

D C B A

74 LS 47 GND GN D 8

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100

a

13

a

b

12

b

c

11

c

d

10

d

e

9

f 

15

g

14

e f 

a f 

b

CA

g c

e d

g Seven-segment display

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2.

Fill the truth table.

D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

LED DISPLAY

3. Design a decoder for a seven segment display. The decoder will convert binary to

octal. Show the solution and circuit design below. Write down the part’s name of the TTL IC to be used. Write down also the pin assignment of each gate in the circuit. Truth Table:

Logic Circuit:

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QUESTIONS: 1. What is the difference between decoder and encoder?

2. Cite examples where encoder and decoders are used together.

3. What is the effect/display when pin#3 of 74LS47 is connected to the ground?

4. What is the effect/display when pin#4 of 74LS47 is connected to the ground?

5. What is the effect/display when pin#5 of 74LS47 is connected to the ground?

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Experiment 8:

Multiplexer Implementation OBJECTIVES 1. To prove experimentally that MUX is a DATA SELECTOR. 2. To implement a given Boolean function using 4 x 1 MUX. 3. To construct multiplexer as universal logic circuit.

BASIC INFORMATION Multiplexing is the transmission of large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 n   input lines and n selection lines whose combinations determine which input is selected. A multiplexer is also called data selector since it selects one of many inputs and steers the binary information to the output line. It is often abbreviated as MUX. In general, a 2 n -to-1  line   line multiplexer is constructed from an n n  n-to-2  line decoder by adding to its 2   input lines, one to each AND gates. As in decoders, multiplexer ICs also have an enable input to control the operation of the unit. 14

 A

2

VCC

MULTIPLEXER TRUTH TABLE

16

B

select

DATA INPUTS

STROBE

OUTPUT

6

1C0

B

A

C0

C1

C2

C3

~G

Y

5

1C1

X

X

X

X

X

X

1

0

4

1C2

0

0

0

X

X

X

0

0

0

0

1

X

X

X

0

1

0

1

X

0

X

X

0

0

2C1

0

1

X

1

X

X

0

1

2C2

1

0

X

X

0

X

0

0

2C3

1

0

X

X

1

X

0

1

1

1

X

X

X

0

0

0

1

1

X

X

X

1

0

1

3 10 11 12 13 1 15

1Y

7

1C3

2C0 2Y

~1G ~2G

9

8 GND

74LS153

This data selector/ multiplexer contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR gates. Separate strobe inputs are provided for each of the two four-line sections. The TTL 74153 can be used to implement two 3-variable Boolean expressions as shown: Given: F1 (ABC) = Σ (1,3,5,6)

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F2 (ABC) = Σ (2,3,4)

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IMPLEMENTATION TABLE IC0 ~C C

MUX 1 IC1 IC2

IC3

2C0

MUX 2 2C1 2C2

2C3

0 1

0 1

0 1

1 0

0 0

1 1

1 0

0 0

C

C

C

~C

0

1

~C

0

VCC 5V

14

 A

2

B C

NOT

 A VCC B

6

1C0

5

1C1

4

1C2

3 10 11 12 13 1 15

16

1Y

7

F1

1C3

2C0 2Y

9 F2

2C1 2C3 2C4

~1G

8

~2G

GND

74LS153 GND

MATERIALS: 1

Digital Trainer Integrated Circuit (IC) 74LS04

1

Connecting wires 1

74LS153

DATA GATHERING: 1. Write a procedure to test the function of the TTL74153. Verify the output with the truth table. Draw the circuit.

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2. Implement the function F1 (A, B, C) = 7) using multiplexer. Show complete solution.

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QUESTIONS: 1. What part of the multiplexer circuit that determines input data selection?

2. Which is more convenient implementing Boolean function using combinational circuit or multiplexer circuit? Elaborate your answer.

3. Design a full-adder using multiplexer implementation. implementation.

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Experiment 9:

Basic Flip-flops OBJECTIVES 1. To study the operation of flip-flops. 2. To construct different types of flip-flops BASIC INFORMATION Flip-flop can be called bistable multivibrator is a basic memory element. It can be referred to as latch or memory cell as well. They can store one bit of information either 0 or 1. The term bistable refers to its memory being stable at 0 when the input is 0 and stable at 1 when the input is 1. There are 4 basic flip-flops namely: RS flip-flop, D flipflop, T flip-flop, and JK flip-flop. The circuit construction and operation are shown below: S

Q

10 11

R

0

1

11

01

Q

The state diagram clearly shows the operation of the RS flip-flop. Notice that when R becomes 1 the state will go to 0, while when S becomes 1 the state will go to 1. Input 11 will result to same state while input 00 will yield an illegal output ( Q = 1, ~Q=1).

R 

Q 10 11

S

~Q

0

1

11

01

The NOR implementation shows that input 11 will yield illegal output while input 00 will results to same output. For set (S) and reset ® it is same with NAND implementation.

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D 0

Q 0

0

1

1

1 ~Q

The D-flip-flop shown above is a modified latch. The added NAND gate acts as inverter and assures the input of the latch with only 01 and 10 combination. The input 0 represents reset and input 1 represents set. As shown in the state diagram.

11 01 01

00

0

1

00

10

10 11 The JK flip-flop shown above is a clocked flip-flop. By adding AND gates, the illegal inputs will never occur, instead a toggle condition will results to 11.

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T Q

CLK 

~Q

1 0

0

1

0

1 The T-flip-flop shown above is a modified JK flip-flop. Notice that the inut T is equivalent to either input 00 or 11 of the JK flip-flop. MATERIALS

1 1

Connecting Wires Digital Trainer 74LS02

Integrated Circuits (ICs) 1 74LS00 1 74LS08

PROCEDURES 1. Construct the RS latch (NAND and NOR implementation). Connect the inputs and

outputs properly to the digital trainer. Don’t forget to connect the DC supply. su pply. Complete the state stable 9-1. 2. Construct the D latch (NAND implementation). Connect the inputs and outputs properly to the digital trainer. Don’t forget to connect the DC supply. Complete the state table 9-2. 3. Connect the inputs and outputs properly to the digital trainer. Don’t forget to connect the DC supply. Complete the state table 9-3.

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DATA AND RESULTS State Table 9-1:

output

NAND implementation

NOR implementation

next output

next output

Q(t+1)

Q(t+1)

Input

Q 0 0 0 0 1 1 1

S 0 0 1 1 0 0 1

R 0 1 0 1 0 1 0

1

1

1

State table 9-2: Q 0 0 1 1

D 0 1 0 1

Q(t+1)

State table 9-3: JK flip-flop output Q 0 0 0 0 1 1 1 1

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input J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

next output Q(t+1)

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QUESTIONS: Referring to the truth tables, write logical statements that suitably describes the function table of each of the following basic gates: 1. What is the function of clock in the flip-flop circuit?

2. Determine the AND-NOR implementation of JK flip-flop.

3. How can you form register using D-flip-flop?

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Experiment 10:

Sequential logic Circuit

OBJECTIVES 1. To study sequential logic circuit 2. To design sequential logic circuit 3. To construct sequential logic circuit. BASIC INFORMATION Sequential logic circuit is a type of logic circuit that produces an output based on current input and previous output. The previous output is stored in a memory element like flipflop. The memory is an integral part of sequential logic circuit. The block diagram representation of sequential logic circuit is illustrated below:

The more specific representation of synchronous sequential logic circuit design is illustrated below:

CLC IN

Register Next Logic Output

clock 

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DATA GATHERING: Sequential logic Diagram: 1.Given the State diagram, determine the equivalent sequential logic circuit. C =0  V = 111 111

C =1  V = 000 1

1

000

C =0  V = 010

C =0  V = 001 U

001

U

010

U

110

101

C =0  V = 111

C =0  V = 101

U

U

100 C =0  V = 100

U

011

C =0  V = 011

Input U determines when the modulus-6 counter will increment, when U=0 no change in state, when U=1 then increment the state value by 1, C and V are outputs of the counter. State 110 and 111 are illegal state and will always go to state 000 when inadvertently occur. Determine the state table of state diagram: use any flip-flop available.

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Determine the state equation.

Draw the equivalent circuit.

Construct the circuit in the digital trainer and verify the operation with state diagram or state table.

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