K. J. Somaiya College of Engineering, Mumbai-77 Lab Manual: BE ETRX (Semester VIII)
Instructions to the student Every student is expected to bring printout of write-up of his experiment to be performed at the time of practical/tutorial session as per the time table The student must take counter signature of the concerned faculty on the same day during lab session for the verification of outcomes of the experiments The journal will content A4 size papers unless it is notified for particular subject The students can use separate blank A4 size papers if necessary while writing journal Cover page of every experiment should be in standard format as attached along with lab manual Students are expected to follow the instructions given by concerned faculty from
K. J. Somaiya College of Engineering, Mumbai – 77 CONTENTS Name of the Remark Experiment s Page Date of Date of performanc No. e Submission / Correction
This to certify that Bro./Sis. _______________________________ ______________ Roll No. ______________Exam.No._______________Class__________________ __ Div._________ Batch No.__________ has completed the specified term work in subject of ____________________________________in
inside the college of Engineering as laid by the University of Mumbai during the academic year Jul. / Jan.20___ to Nov./Apr.20___ Overall Grade: Grade: AA / AB / BB / BC / CC Staff member In-charge Department
Head of the Principal
Roll No._______________ Class:_______Branch:____________ Div: ________Batch_____
Subject: _________________________Experiment No._______
Name of the Experiment: __________________________________ Date of performance: _____________________________________ Date of Submission / correction: ____________________________ Grade: AA / AB / BB / BC / CC
Signature of the Staff In-charge with date
K J Somaiya College of Engineering Vidyavihar, Mumbai 400 077 Department of Electronics Engineering
Class: BE (A & B)
Term: Jan-May 2011
List of Experiments 1. 2. 3. 4.
7 segment / LED interface / LCD interface Keypad Interface Serial Communication Application using all above
Expts from 5 to 8 aim is to get the students familiar with ARM features (use of Keil and Proteus VSM)
5. Study of I/O Port functions of LPC2148 6. Study of external interrupts of LPC2148 7. Study of on chip UART in ARM
Experiment No. : Name of Experiment: 4X4 Keypad interfacing with microcontroller Aim: Interface 4X4 keypad with microcontroller. Theory:
Interfacing the keyboard to the 8051
At the lowest level, keyboards are organized in a matrix of rows and columns. The CPU accesses both rows and columns through ports; therefore with one 8-bit port, an 4 X 4 matrix of keys can be connected to a microprocessor. When a key is pressed, a row and a column make a contact; otherwise, there is no connection between rows and columns. Scanning and identifying the key The figure shows a 4X4 matrix connected to a single port. The rows are connected to lower bit pins as output and the columns are connected to higher nibble pins as input. If no key has been pressed, reading the input pins will yield 1s for all columns since they are all connected to high (Vcc). If all the rows are grounded and a key is pressed, one of the columns will have a 0 since the key pressed provides the path to ground. It is the function of the microcontroller to scan the keyboard continuously to detect and identify the key pressed. Grounding rows and reading the columns To detect a pressed key, the microcontroller grounds all rows by providing 0 to the output latch and then it reads the columns. If the data read from the columns is D3-D0 = 1111, no key has been pressed and the process continues until a key-press is detected. However, if one of the column bit has 0, this means that a key press has occurred. For example, if D3-D0 = 1101, this means that a key in the column D1 has been pressed. After a key-press is detected, the microcontroller
will go through the process of identifying the key. Sending the same code on column and reading the row information can do this identification. This will work only when one key is closed at a time. Algorithm: The scanning and checking of the key pressed is done in the timer interrupt. 1) Assign the Rows and Columns to the port according to the hardware connected. 2) Set the timer mode, load the count value and run the timer. 3) Enable the Timer interrupts using IE (interrupt enable) register. 4) Within the timer interrupt routine, reload the timer count and start scanning using keypad state. Circuit Diagram: Attach Print out of design file (VSM Proteus) State Diagram
Program print: Attach the List file printout Conclusion: In the above method of keyboard scanning, how number of read and write operations are reduced? What are the limitations of this method?
Experiment No. : Name of Experiment: Interface of LCD with microcontroller Aim:
Interfacing of LCD with microcontroller.
Write Code in C and write header file for LCD routines for initialization, for sending command to LCD and sending data to LCD. Theory: LCD operation: In recent years the LCD is finding widespread use replacing LEDs. This is due to the following reasons: *The declining prices of LCDs. *The ability to display numbers, characters and graphics. This is in contrast to LEDs, which are limited to numbers and a few characters. *Incorporation of a refreshing controller into the LCD, thereby relieving the CPU of the task of refreshing LCD. In contrast, the LED must be refreshed by the CPU to keep displaying the data. *Ease of programming for charters and graphics. LCD pin descriptions: Pin no.
Power supply to control contrast
register select,1=data ,0=code
Data bus bit 0
Data bus bit 1
KJSCE/BE/ETRX/VIII SEM/2010-11 9
Data bus bit 2
Data bus bit 3
Data bus bit 4
Data bus bit 5
Data bus bit 6
Data bus bit 7
Anode of LED unit
Cathode of LED unit
RS, register select: There are two Very important registers inside the LCD.The RS pin is used for their selection as follows. If RS=0, the instruction command code register is selected, allowing the user to send a command such as clear display, cursor at home, etc. If RS=1 the data register is selected, allowing the user to send data to be displayed on LCD. R/W#, read/write: R/W# input allows the user to write information to LCDor read information from it. R/W#=1 when reading.R/W#=0 when writing. E, enable: The enable pin is used by the LCD to latch infromationpresent to its data pins. When data is supplied to data pins, a high-to-low pulse must be supplied to this pin In order for the LCD to latch in the data present at the data pins. THis pulse must be a minimum of 450ns wide. D0-D7: The 8-bi data pins, D0-D7 are used to send information to the LCD or read the contents of the CD's internal registers .To display letter and number, we send ASCII codes for the letters A-Z, a-z, and numbers 0-9 to these pins while making RS=1.There are also
instruction command codes that can be sent to the LCD to clear the display or force the cursor to the home position or blink the cursor. We also use RS=0 to check the busy flag bit to see if the LCD is ready to receive information. The busy flag is D and can be read when R/W# =1 and RS=0, as follows: if R/W#=1,RS=0.When D7=1(busy flag=1),the LCD is busy taking care of internal operations and will not accept any new information. When D7=0, the LCD is ready to receive new information. Note: It is recommended to check the busy flag before writing any data to the LCD. Algorithm 1) Initialize the LCD: a)Send Command 0x38 : Initialize LCD in 2 lines ,5*7 matrix mode(0x03 and then 0x08) b)Send Command 0x0E : LCD ON, Cursor ON (0x00 and then 0x0E) c) Send Command 0x06: Shift Cursor right (0x00 and then 0x06) d) Send Command 0x80: Cursor on line 1, position 0 (0x08 and then 0x00) e) Send Command 0x01: clear LCD (0x00 and then 0x01) 2) Send Data (upper nibble first followed by lower nibble) and give appropriate delay. Circuit Diagram: Attach Print out of design file (VSM Proteus) Program print: Attach the List file printout Conclusion: Explain the difference and advantages and disadvantages of sending streams of characters to LCD 1) With busy check 2) Without busy check
Experiment No. : Name of Experiment: Transmitting and receiving data serially to PC using serial port of microcontroller. Aim:
Transmit and receive data serially to PC using serial port of microcontroller.
Theory: Basics of serial communication When a microprocessor communicates with the outside world, it provides the data in byte-sized chunks. In some cases, such as printers, the information is simply grabbed from the 8-bit data bus and is presented to the 8bit data bus of the printer. This can work only if the cable is not too long., since long cables diminish and even distort signals. Furthermore, an 8-bit data path is expensive. For these reasons serial communication is used for transferring data between two systems located at distance of hundreds of feet. Serial communication uses two methods: 1) Asynchronous 2) Synchronous The synchronous method transfers a block of data (characters) at a time, while the asynchronous method transfers a single byte at a time. It is possible to write software using either of these methods, but the programs can be tedious and long. For these reasons there are serial IC chips made by many manufacturers for serial data communications. These chips are commonly referred to as UART (universal asynchronous receivertransmitter). The 8051chip has a built in UART.
Half and full duplex transmission: In data transmission if the data can be transmitted and received, it is a duplex transmission. This is in contrast to the simplex transmissions such as with printers, in which the computer only sends data. Duplex transmissions can be half duplex or full duplex depending on whether or not the data transfer can be simultaneous. If the data is transmitted one way at a time, it is referred to as half duplex. If the data can go both ways at the same time, it is full duplex. The full duplex requires two wore conductors for the data lines(in addition to the signal ground) , one for transmission and one for reception, in order to transmit and receive data simultaneously. 8051 connection to RS232 The RS232 standard is not TTL compatible; therefore, it requires a line driver such as the MAX232 chip to convert RS232 voltage levels to TTL levels, and vice versa. The 8051 has 2 pins that are used specifically for transmitting and receiving data serially. These two pins are called TxD and RxD and are a part of the port 3 (P3.0 and P3.1). Pin 11 of the 8051(P3.1) is assigned to TxD and pin 10 (P3.0) is designated as RxD. These pins are TTL compatible; therefore, they require a line driver to make them RS232 compatible. One such line driver is the MAX232 chip. 8051 Serial Port Programming To allow data transfer between the PC and an 8051 system without any error, we must make sure that the baud rate of the 8051 system matches the baud rate of the PC's COM port.
Baud rate in 8051: The 8051 transfers and receives data serially at many different baud rates. The baud rate in the 8051 is programmable. This is done with the help of Timer 1. The 8051 divides the crystal frequency by 12 to get the machine cycle frequency. In the case of XTAL = 11.0592MHz, the machine cycle frequency is 921.6khz (11.0592Mhz/12 = 921.6khz). The 8051's serial communication UART circuitry divides the machine cycle frequency of 921.6 kHz by 32 once more before it is used by Timer 1 to set the baud rate. When the Timer 1 is used to set the baud rate it must be programmed in mode 2, that is 8-bit, auto reload mode. Baud rate calculations: With XTAL = 11.0592 MHz: For 9600 baud rate: ---- 28800 / 9600 = 3 ---- hex (-3) = FFFD ---- FD is loaded into TH1 For 2400 baud rate: ----28800 / 4800 = 6 ----hex (-6) = FFFA ---- F4 is loaded into TH1 SBUF Register: SBUF is an 8-bit register used solely for serial communication on the 8051. For a byte of data to be transferred via the TxD line, it must be placed in the SBUF register. Similarly, SBUF holds the byte of data when it is received by the 8051's RxD line. SBUF can be accessed like any other register in the 8051. The moment a byte is written into SBUF, it is framed with the start and stop bits and transferred serially via the TxD pin. Similarly, when the bits are received serially via
RxD, the 8051 deframes it by eliminating the stop and start bits, making a byte out of the data received, and then placing it in the SBUF. SCON (serial control) register: The SCON is an 8-bit register used to program the start bit, stop bit and the data bits of data framing, among other things. The various bits of SCON register are: SM0, SM1 SM0 and SM1 are D7 and D6 of the SCON register, respectively. These two bits determine framing of data by specifying the number of bits per character, and the start and stop bits. SM0 0 0
SM1 0 1
Serial Mode 0 Serial Mode 1,8-bit data, 1 stop bit, 1- start bit Serial Mode 2 Serial Mode 3
In the SCON register, when serial mode 1 is chosen, the data framing is 8-bits, 1 stop bit and 1 start bit, which make it compatible with the COM port of the PCs. Serial mode 1 allows the baud rate to be variable and is set by timer 1 of 8051. SM2 This bit enables the multiprocessing capability of 8051. We make SM2=0 since we are not using 8051 in a multiprocessor environment.
REN When REN bit is high it allows the 8051 to receive data on the RxD pin of 8051.By making REN=0 , the receiver is disabled. TI(Transmit Interrupt) Transmit Interrupt ( TI ) is an extremely important flag in the SCON bit register. When 8051 finishes the transfer of the 8-bit character, it raises the TI flag to indicate that it is ready to transfer another byte. The TI bit is raised at the beginning of the stop bit. RI (Receive Interrupt) When the 8051 receives data serially via RxD, it gets rid of the start and the stop bits and places the byte in the SBUF register. Then it raises the RI flag bit to indicate that a byte has been received and should be picked up before it is lost. RI is raised half way through the stop bit. Algorithm: 1) Set Timer 1 in 8-bit auto reload mode by loading proper value in TMOD. 2) Load TH1 with count value corresponding to the baud rate required. 3) Load SCON with 0x50 to set it in 8-bit variable baud rate mode. 4) Enable serial interrupt and run the Timer 1. 5) Transmit the data to be sent in SBUF. OR Receive the data from SBUF onto some Port. 6) Reset TI in the serial interrupt: for transmitting and reset RI in the serial interrupt: for reception. 7) The transmitted data can be seen on the HyperTerminal on a computer whereas the Received data can be obtained on any port of microcontroller.
Set timer 1 in 8 bit auto reload mode
Load TH1 : Set the Baud rate Load SCON with 0x50 : 8bit variable baud rate
Enable Serial Interrupts and Run the Timer 1
Transmitted data can be seen on Hyper For Tx: send the data to SBUF Terminal Received data canfrom be seen on For Rx: receive data the uC Port
SERIAL INTERRUPT ROUTINE reset TI : For Tx reset RI : For Rx
Circuit Diagram: Attach Print out of design file (VSM Proteus) Program print: Attach the list file printout Conclusion: How many pins of the RS-232 are used by the IBM serial cable, and why?
Experiment No. : Name of Experiment: Study of GPIO in ARM7. Aim: Display LED blink toggle at P0.21 and P0.22. Theory: LPC2141/2/4/6/8 has two 32-bit General Purpose I/O ports. Total of 30 input/output and a single output only pin out of 32 pins are available on PORT0. PORT1 has up to 16 pins available for GPIO functions. PORT0 and PORT1 are controlled via two groups of 4 registers as P0.0-P.31, P1.16-P1.31 are Input/Output pins. General purpose input/output. The number of GPIOs actually available depends on the use of alternate functions .All I/O default to inputs after reset 1) IOPIN GPIO Port Pin value registers. The current state of the GPIO configured port pins can always be read from this register, regardless of pin direction. Access: R/W 2) IOSET GPIO Port Output Set register. This register controls the state of output pins in conjunction with the IOCLR register. Writing ones produces highs at the corresponding port pins. Writing zeroes has no effect. Access: R/W 3) IODIR GPIO Port Direction control register. This register individually controls the direction of each port pin. Access: R/W 4) IOCLR GPIO Port Output Clear register. This register controls the state of output pins. Writing ones produces lows at the corresponding port pins and clears the corresponding bits in the IOSET register. Writing zeroes has no effect. Access: WO
GPIO register map (local bus accessible registers - enhanced GPIO features) 1) FIODIR Fast GPIO Port Direction control register. This register individually controls the direction of each port pin. 2) FIOMASK Fast Mask register for port. Writes, sets, clears, and reads to port (done via writes to FIOPIN, FIOSET, and FIOCLR, and reads of FIOPIN) alter or return only the bits loaded with zero in this register. 3) FIOPIN Fast Port Pin value register using FIOMASK. The current state of digital port pins can be read from this register, regardless of pin direction or alternate function selection (aslong as pin is not configured as an input to ADC). The value read is value of the physical pins masked by ANDing the inverted FIOMASK. Writing to this register affects only port bits enabled by ZEROES in FIOMASK. 4) FIOSET Fast Port Output Set register using FIOMASK. This register controls the state of output pins. Writing 1s produces highs at the corresponding port pins. Writing 0s has no effect. Reading this register returns the current contents of the port output register. Only bits enabled by ZEROES in FIOMASK can be altered. lows at the corresponding port pins. Writing 0s has no effect. Only bits enabled by ZEROES in FIOMASK can be altered. 5) FIOCLR Fast Port Output Clear register using FIOMASK. This register controls the state of output pins. Writing 1s produces lows at the corresponding port pins. Writing 0s has no effect. Only bits enabled by ZEROES in FIOMASK can be altered Fast GPIO can be selected using SCS (System Control and Status flags register) bit 0 and 1. There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is used to generate the CCLK clock (system clock) while the PLL1 has to supply the clock for the USB at the fixed rate of 48 MHz. Structurally these two PLLs are identical with exception of the PLL interrupt capabilities reserved only for the PLL0.
The PLL0 and PLL1 accept an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 10 MHz to 60 MHz for the CCLK and 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2141/2/4/6/8 due to the upper frequency limit of the CPU). Program print: Attach the C file printout Circuit Diagram: Draw the circuit diagram for the above experiment. Conclusion: Explain writing to IOSET/IOCLR .vs. IOPIN
Experiment No. : Name of Experiment: UART Example Aim: To transmit a message on hyper-terminal using UART1. Theory: UART1 has 16 byte Receive and Transmit FIFO. It has a built-in fractional baud rate generator with autobauding capabilities. The baudrate generator is a 16 bit prescaler which divides down Pclk to generate the UART clock which must run at 16 times the baud rate. The formula used to calculate the UART baud rate is Divisor = Pclk / 16* BAUD In our case at 30 MHz: Divisor = 30,000,000 / 16 * 9600 = 194 or 0xC2 This gives a true baud rate of 9665. Often it is not possible to get an exact baud rate for the UARTs . They work with up to around 5% error in the bit timing. The Divisor value is held in two registers Divisor Latch MSB (DLM) and Divisor Latch LSB (DLL) .The first 8 bits of both registers holds each half of the divisor Finally the DLAB bit in LCR register must be set to zero to protect the contents of divisor registers. Once UART is initialized, characters can be transmitted by writing to the Transmit Holding Register. Similarly, characters may be received by reading from the Receive Buffer Register Register Description 1) UART1 Divisor Latch Registers 0 and 1 (DLL0 and DLL1) The UART1 Divisor Latch is part of the UART1 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock, which must be 16x the desired baud rate The U1DLL and U1DLM registers together form a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U1LCR must be one in order to access the UART1 Divisor Latches. 2) UART1 Line Control Register (U1LCR) The U1LCR determines the format of the data character that is to be transmitted or received.
3) UART1 Modem Control Register (U1MCR ) This register is available in LPC2144, LPC2146, and LPC2148 only. The U1MCR enables the modem loop back mode and controls the modem output signals.
4) UART1 Fractional Divider Register (U1FDR - 0xE001 0028) The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at user’s discretion. This pre-scaler takes the APB clock and generates an output clock per specified fractional requirements. There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is used to generate the CCLK clock (system clock) while the PLL1 has to supply the clock for the USB at the fixed rate of 48 MHz. Structurally these two PLLs are identical with exception of the PLL interrupt capabilities reserved only for the PLL0. The PLL0 and PLL1 accept an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 10 MHz to 60 MHz for the CCLK and 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2141/2/4/6/8 due to the upper frequency limit of the CPU). Program print: Attach the printout of C file and H file. Conclusion: How Baud rate is determined in UART1.
Name of Experiment: Study of external interrupts of LPC2148 Aim: Enable a buzzer through an external interrupt Theory: External interrupt inputs The LPC2148 includes four External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode.
External Interrupt Input 0 - An active low/high level or falling/rising edge general purpose interrupt input. This pin may be used to wake up the processor from Idle or Power-down modes. Pins P0.1 and P0.16 can be selected to perform EINT0 function.
External Interrupt Input 1 Pins P0.3 and P0.14 can be selected to perform EINT1 function. LOW level on pin P0.14 immediately after reset is considered as an external hardware request to start the ISP command handler.
External Interrupt Input 2 Pins P0.7 and P0.15 can be selected to perform EINT2 function.
External Interrupt Input 3Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function
KJSCE/BE/ETRX/VIII SEM/2010-11 .
Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags, and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the microcontroller from Power-down mode. The EXT MODE and EXTPOLAR registers specify the level and edge sensitivity parameters.
External Interrupt Flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which will cause an interrupt if interrupts from the pin are enabled. Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive state. Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future. Interrupt Wakeup register (INTWAKE - 0xE01F C144)
Enable bits in the INTWAKE register allow the external interrupts and other sources to wake up the processor if it is in Power-down mode. The related EINTn function must be mapped to the pin in order for the wakeup process to take place. It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place.
This arrangement allows additional capabilities, such as having an external interrupt input wake up the processor from Power-down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power-down without waking the processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application). For an external interrupt pin to be a source that would wake up the microcontroller from Power-down mode, it is also necessary to clear the corresponding bit in the External Interrupt Flag register
External Interrupt Mode register (EXTMODE - 0xE01F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function and enabled via the VIC Int Enable register can cause interrupts from the External Interrupt function (though of course pins selected for other functions may cause interrupts from those functions).
External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function and enabled in the VIC Int Enable register can cause interrupts from the External Interrupt
function (though of course pins selected for other functions may cause interrupts from those functions). For example, if the EINT3 function is selected in the PINSEL0 and PINSEL1 registers for pins P0.9, P0.20 and P0.30, and EINT3 is configured to be low level sensitive, the inputs from all three pins will be logically ANDed. When more than one EINT pin is logically ORed, the interrupt service routine can read the states of the pins from the GPIO port using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt.
Fig. External interrupt logic
Program: Attach the C program print-out.
Conclusion: How does ARM7 respond to an interrupt.