EoSTutorial

Ethernet Over SONET/SDH tutorial

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Day In the Life of an Ethernet Over SONET/SDH Packet \ u e 0 0 0 Goal

is to understand how Ethernet, SONET and Vir Concatenation work together \ue000

Ethernet Frame Processing

\ue000

Ethernet Encapsulation \u2013 GFP-F or LAPS

\ue000

Virtual Concatenation processing

\ue000

SONET/SDH framing

\ u e 0 0 0 Follow

II M G

Ethernet Frame through each process step

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Framer

Copyright\u00a92004 Vitesse Semiconductor Corporation

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Ethernet MAC Receives a Packet II M G

MACs

Ingress FIFO Egress FIFO

2 . -4 I P S

Multi-Service MAC

Inter Packet Gap

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

\ u e 0 0 0 Ethernet

Frames Extracted Fro the Line Interface

Preamble SFD

\ue000

Ethernet Packet

Ethernet Packet

Ethernet FCS

Ethernet FCS

8B/10B Decoding For SerDes Interface

Inter Packet Gap, Preamble and Start Frame Delimiter are Stripped

\ue000

\ u e 0 0 0 At

Completion of Packet Reception, Error Conditions are Checked and Statistics Updated

Inter Packet Gap

Incoming Ethernet Packet Stream

2 . -4 I P S

Extracted Ethernet Packet

\ue000

Packet Length Check

\ue000

FCS Check

\ue000

Packet and Byte Counters Updated

Copyright\u00a92004 Vitesse Semiconductor Corporation

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Ingress FIFO Buffers Packet II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Packet Buffered as it is Received Into the Ingress FIFO Previous Packet

Ethernet Packet

Ethernet Packet

Ethernet FCS

Ethernet FCS

Extracted Ethernet Packet

Packet Added to Ingress FIFO

Errored Packets are Deleted from the FIFO Store and Forward Mode Deletes the Packet Entirely Cut Through Mode Deletes Any Remaining Data

Copyright©2004 Vitesse Semiconductor Corporation

4

Packet Sent Across SPI-4.2 Interface II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Ctrl Word Previous Packet

Begin Ethernet Packet Ctrl Word

Ethernet Packet

Another Channel’s Ethernet Data

Ethernet FCS

Ctrl Word

Next Packet

Remainder Of Ethernet Packet With FCS

Packets Sent Across SPI-4.2 Interface by MAC SPI-4.2 Control Words Identify Data Transferred Port Address

Start of Packet, End of Packet, Aborted Packet

Bursts are Scheduled between Ports on Round Robin Basis

Ctrl Word

Packet in the Ingress FIFO

Burst Interleaved Across SPI-4.2 Copyright©2004 Vitesse Semiconductor Corporation

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Packet Reassembled and Buffered II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Ctrl Word Begin Ethernet Packet

Previous Packet

Ctrl Word Another Channel’s Ethernet Data

Ethernet Packet

Ctrl Word

Ethernet FCS

Remainder Of Ethernet Packet With FCS

Packet Bursts Reassembled into Packets in the Tx Buffer

Ctrl Word

Burst Interleaved Across SPI-4.2

Packet in Tx Buffer Copyright©2004 Vitesse Semiconductor Corporation

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Packet Encapsulation – Generic Framing Protocol (GFP) II M G

MACs

Ingress FIFO Egress FIFO

2 . -4 I P S

Multi-Service MAC

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

PLI cHEC Type

2 Bytes 2 Bytes 2 Bytes

tHEC 2 Bytes Extension Header 2 Bytes eHEC 2 Bytes

Ethernet Packet

Ethernet FCS

Ethernet Packet

Ethernet FCS GFP FCS 4 Bytes

Incoming Ethernet Packet

Generic Framing Procedure (GFP) is One of Two Ethernet Encapsulation Choices PDU Length Indicator (PLI) Along with the Core Header Error Check (cHEC) form the Core Header PLI is the number of Bytes in the Entire Encapsulated Packet Excluding the Core Header Itself

Type Field describes encapsulated packet Control or Data Packet FCS Present Indicator Extension Header Indicator

Extension Header is Optionally Inserted GFP FCS

Resulting GFP Optionally Inserted CRC Encapsulated Packet Copyright©2004 Vitesse Semiconductor Corporation

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Packet Encapsulation – Link Access Procedure - SDH (LAPS) II M G

MACs

Ingress FIFO Egress FIFO

2 . -4 I P S

Multi-Service MAC

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Flag

1 Byte

Address 1 Byte Control 1 Byte SAPI

2 Bytes

Link Access Procedure –SDH (LAPS) is One of Two Ethernet Encapsulation Choices X.85 Defines IP over LAPS

X.86 Defines Ethernet over LAPS One of Several HDLC Protocols

Ethernet Packet

Ethernet Packet

Ethernet FCS

Ethernet FCS LAPS 4 Bytes FCS

Incoming Ethernet Packet

– Similar to Packet Over SONET (POS)

Resulting LAPS Encapsulated Packet

Typical Field Values: Flag – 0x7E

Address – 0x04 Control – 0x03 (Unnumbered Information) Service Access Point Identifier (SAPI) – 0xFE01

Copyright©2004 Vitesse Semiconductor Corporation

8

Virtual Concatenation Mapping II M G

MACs

Ingress FIFO Egress FIFO

2 . -4 I P S

2 . -4 I P S

Multi-Service MAC

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Each Port is Mapped to a VC Group Byte 1 Byte 2 Byte 3 Byte 4

STS-1 #5 STS-1 #12

H4

STS-1 #32

H4

Example: 3 Virtually Concatenated STS-1s (#5, 12, and 32)

Data Fetched and Placed in the Channel Buffer

H4

Byte N

Encapsulated Packet

Group Descriptor Table Denotes the Type of Group and Number of Members

Amount of Data Fetched Depends on the Size of the Concatenated Channel Bytes Interleaved Across Multiple STS-1s

Bytes Interleaved Across the Members of the Channel

H4 Bytes Generated and Passed to the Path Overhead Processor

Copyright©2004 Vitesse Semiconductor Corporation

9

SONET/SDH Overhead Processing and Transmission II M G

MACs

Ingress FIFO

2 . -4 I P S

Egress FIFO

2 . -4 I P S

Multi-Service MAC

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Path Overhead Generation for an STS-192 (STM-64) Signal Line and Section Overhead Generation

STS-1 #5 STS-1 #12

H4

Completed SONET/SDH Frame Transmitted to the Line

STS-1 #32

H4 H4

Multiple STS-1s

STS-192

Copyright©2004 Vitesse Semiconductor Corporation

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SONET/SDH Reception and Overhead Processing II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

STS-192 (STM-64) Line Interface Section and Line Termination

STS-1 #5 STS-1 #12

H4

STS-1 #32

H4 H4

STS-192

B1/B2 Error Monitoring Section and Line Overhead Monitoring

Path Overhead Processing

H4 Virtual Concatenation Byte and Payload Extraction

Multiple STS-1s

Copyright©2004 Vitesse Semiconductor Corporation

11

Virtual Concatenation Deinterleaving II M G

MACs

Ingress FIFO Egress FIFO

2 . -4 I P S

Multi-Service MAC

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

STS-1 #5

Byte 1 Byte 2 Byte 3 Byte 4

STS-1 #12

H4

H4

Byte N

Bytes Interleaved Across Multiple STS-1s

DDR RAM used for differential delay compensation

H4 Bytes are Processed

STS-1 #32

H4

Data for each Received STS-1 is Buffered in External DDR DRAM

Encapsulated Packet

Determines the Differential Delay Between Members Determines the Ordering of Members in the Virtually Concatenated Group

Based on the H4 Bytes, the Data is Extracted from DRAM and Deinterleaved to Reconstruct Packets

Copyright©2004 Vitesse Semiconductor Corporation

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Packet Extraction – Generic Framing Protocol (GFP) II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

PLI cHEC Type

2 Bytes

Generic Framing Procedure (GFP) is One of Two Ethernet Encapsulation Choices

2 Bytes 2 Bytes

tHEC 2 Bytes Extension Header 2 Bytes eHEC 2 Bytes

Core Header is Processed to Delineate Frames Type and Extension Headers are Optionally Checked and Stripped

Ethernet Packet

Ethernet Packet

Ethernet FCS

Ethernet FCS

GFP FCS is Optionally Checked and Stripped

GFP FCS 4 Bytes

Incoming GFP Encapsulated Packet

Resulting Ethernet Packet

Copyright©2004 Vitesse Semiconductor Corporation

13

Packet Extraction – Link Access Procedure - SDH (LAPS) II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Flag

Link Access Procedure –SDH (LAPS) is One of Two Ethernet Encapsulation Choices

1 Byte

Address 1 Byte Control 1 Byte SAPI

2 Bytes

Ethernet Packet

Ethernet Packet

Ethernet FCS LAPS 4 Bytes FCS

Ethernet FCS

Incoming LAPS Encapsulated Packet

Flag Character is Used to Delineate Frames All Fields are Optionally Checked and Stripped

Resulting Ethernet Packet Copyright©2004 Vitesse Semiconductor Corporation

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Receive FIFO Buffers Packet II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Previous Packet

Ethernet Packet

Ethernet Packet

Ethernet FCS

Ethernet FCS

Extracted Ethernet Packet

Packet Added to Rx FIFO

Extracted Ethernet Packets Placed in the Rx FIFO for that Group

Copyright©2004 Vitesse Semiconductor Corporation

15

Packet Sent Across SPI-4.2 Interface II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Ctrl Word Previous Packet

Begin Ethernet Packet Ctrl Word

Ethernet Packet

Another Channel’s Ethernet Data

Ethernet FCS

Ctrl Word

Next Packet

Remainder Of Ethernet Packet With FCS

Packets Sent Across SPI-4.2 Interface by VCAT Mapper SPI-4.2 Control Words Identify Data Transferred Port Address

Start of Packet, End of Packet, Aborted Packet

Burst are Scheduled between Ports on Round Robin Basis

Ctrl Word

Packet in the Receive FIFO

Burst Interleaved Across SPI-4.2 Copyright©2004 Vitesse Semiconductor Corporation

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Packet Reassembled and Buffered II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Ctrl Word Begin Ethernet Packet

Previous Packet

Ctrl Word Another Channel’s Ethernet Data

Ethernet Packet

Ctrl Word

Ethernet FCS

Remainder Of Ethernet Packet With FCS

Packet Bursts Reassembled into Packets in the Egress FIFO

Ctrl Word

Burst Interleaved Across SPI-4.2

Packet in Egress FIFO Copyright©2004 Vitesse Semiconductor Corporation

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Ethernet MAC Transmits a Packet II M G

MACs

Ingress FIFO Egress FIFO

Multi-Service MAC

2 . -4 I P S

2 . -4 I P S

Tx Buffer

Tx Payload Processor

Tx VC Mapper

Tx SONET/ SDH

Rx Buffer

Rx Payload Processor

Rx VC Mapper

Rx SONET/ SDH

VCAT Mapper

Inter Packet Gap Preamble SFD

Ethernet Packet

Ethernet Packet

Ethernet FCS

Ethernet FCS IPG

Ethernet Packet

Ethernet Frame Pulled from the Egress FIFO Included FCS Checked Statistics Updated

Extensive Packet and Byte Counters

Ethernet Frame Transmitted

8B/10B Encoding For SerDes Interfaces

Inter Packet Gap, Preamble and Start of Frame Delimiter are Inserted as Required

Outgoing Ethernet Packet Stream Copyright©2004 Vitesse Semiconductor Corporation

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