EE315B VLSI Data Conversion Circuits - Autumn 2013 Boris Murmann Stanford University
[email protected]
Table of Contents
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12
Introduction Sampling, Reconstruction, Quantization Spectral Performance Metrics Nyquist Rate DACs Sampling Circuits Voltage Comparators Flash ADCs SAR ADCs Pipeline ADCs Time Interleaving Oversampling ADCs and DACs Energy Limits in A/D Converters
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Introduction
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 1
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Motivation (1)
This course
Analog Media and Transducers
Signal Conditioning
A/D Digital Processing
Signal Conditioning
D/A
Sensors, Actuators, Antennas, Storage Media, ...
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Motivation (2) •
Benefits of digital signal processing – Reduced sensitivity to "analog" noise – Enhanced functionality and flexibility – Amenable to automated design & test – Direct benefit from the scaling of VLSI technology – "Arbitrary" precision
•
Issues – Data converters are difficult to design • Especially due to ever-increasing performance requirements
– Data converters often present a performance bottleneck • Speed, resolution or power dissipation of the A/D or D/A converter can limit overall system performance
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A/D Converter ca. 1954
http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html B. Murmann
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Data Converter Applications (1) •
Consumer electronics – Audio, TV, Video – Digital Cameras – Automotive control – Appliances – Toys
•
Communications – Mobile Phones – Personal Data Assistants – Wireless Transceivers – Routers, Modems EE315B - Chapter 1
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Data Converter Applications (2) •
Computing and Control – Storage media – Sound Cards – Data acquisition cards
•
Instrumentation – Lab bench equipment – Semiconductor test equipment – Scientific equipment – Medical equipment
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Example 1
[Poulton, ISSCC 2003]
•
High performance digital oscilloscopes rely on extremely high performance ADCs
•
Example – 20 GSample/s, 8-bit ADC – 10 W Power dissipation
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Example 2
•
Schvan, ISSCC 2008
•
Time interleaved architecture using 160 (!) SAR ADCs for optical networks
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Example 3
•
A typical cell phone contains: – 4 Rx ADCs Dual Standard, I/Q – 4 Tx DACs Audio, Tx/Rx power – 3 Auxiliary ADCs control, Battery – 8 Auxiliary DACs charge control, display, ...
•
A total of 19 data converters!
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Example 4
[Mehta, ISSCC2005]
•
Low-cost, single chip solutions require embedded data conversion
•
Example: 802.11g Wireless LAN chip – 2x 11-bit DAC, 176 MSamples/s – 2x 9-bit ADC, 80 MSamples/s
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Trend Toward Lower ADC Energy -6
10
-8
P/f s [J]
10
-10
10
-12
10
ISSCC & VLSI 2006-2013 ISSCC & VLSI 1998-2005 20
30
40
50
60 70 SNDR [dB]
80
90
100
110
B. Murmann, "ADC Performance Survey 1997-2013," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html B. Murmann
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Course Objective •
Acquire a thorough understanding of the basic principles and challenges in data converter design – Focus on concepts that are unlikely to expire within the next decade – Preparation for further study of state-of-the-art "fine-tuned" realizations
•
Strategy – Acquire breadth via a complete system walkthrough and a survey of existing architectures – Acquire depth through a midterm project that entails design and thorough characterization of a specific circuit example in modern technology
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Staff and Website
•
Teaching assistant – Vaibhav Tripathi
•
Administrative support – Ann Guerra, Allen 207
•
Lecture videos are provided on the web, but please come to class to keep the discussion intercative
•
Coursework web page – http://coursework.stanford.edu/homepage/F13/F13-EE-315B-01.html
– Please visit the discussion forum regularly – Only enrolled students have full access
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Preparation •
Course prerequisites – EE214B or equivalent • Device physics and models • Transistor level analog circuits, elementary gain stages • Frequency response, feedback, noise
– Prior exposure to Spice, Matlab – Basic signals and systems – Basic probability •
Please talk to me if you are not sure whether you have the required background
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Analog Circuit Sequence
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Assignments •
Homework: (20%) – Handed out on Tue, due following Tue after lecture (1 pm) – Lowest HW score is dropped in final grade calculation
•
Midterm Project: (40%) – Transistor level design and simulation of a data converter sub-block (no layout) – Prepare a project report in the format and style of an IEEE journal paper
•
Final Exam (40%)
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Honor Code •
Please remember you are bound by the honor code – I will trust you not to cheat – I will try not to tempt you
•
But if you are found cheating it is very serious – There is a formal hearing – You can be thrown out of Stanford
•
Save yourself and me a huge hassle and be honest
•
For more info – http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/ honorcode.pdf
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Tools and Technology •
Primary tools – Cadence Virtuoso Schematic Editor – Cadence Virtuoso Analog Design Environment – Cadence SpectreRF simulator – You can use your own tools/setups “at own risk“
•
Getting started – Read tutorials and setup info provided in the CAD section of the course website
•
EE315A/B Technology – 0.18-µm CMOS – BSIM3v3 models provided under /usr/class/ee315b/models
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Reference Books •
M. Pelgrom, Analog-to-Digital Conversion, Springer, 2010
•
Gustavsson, Wikner, Tan, CMOS Data Converters for Communications, Kluwer, 2000
•
A. Rodríguez-Vázquez, F. Medeiro, and E. Janssens, CMOS Telecom Data Converters, Kluwer Academic Publishers, 2003
•
W. Kester, The Data Conversion Handbook, Newnes, 2005 http://www.analog.com/library/analogdialogue/archives/39-06/data_conversion_handbook.html
•
B. Razavi, Data Conversion System Design, IEEE Press, 1995
•
R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2004
•
R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-toAnalog Converters, 2nd ed., Kluwer, 2003
•
J. G. Proakis, and D. G. Manolakis, Digital Signal Processing, Prentice Hall, 1995 EE315B - Chapter 1
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Course Topics
•
Ideal sampling, reconstruction and quantization
•
Sampling circuits
•
Voltage comparators
•
Nyquist-rate ADCs and DACs
•
Oversampled ADCs and DACs
•
Data converter performance trends and limits
•
Data converter testing, simulation techniques
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Sampling, Reconstruction, Quantization
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 2
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The Data Conversion Problem
•
Real world signals – Continuous time, continuous amplitude
•
Digital abstraction – Discrete time, discrete amplitude
•
Two problems – How to discretize in time and amplitude • A/D conversion
– How to "undescretize" in time and amplitude • D/A conversion B. Murmann
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Overview
•
We'll fist look at these building blocks from a functional, "black box" perspective – Refine later and look at implementations
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Uniform Sampling and Quantization •
Most common way of performing A/D conversion – Sample signal uniformly in time – Quantize signal uniformly in amplitude
•
Key questions – How much "noise" is added due to amplitude quantization? – How can we reconstruct the signal back into analog form? – How fast do we need to sample? • Must avoid "aliasing"
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Aliasing Example (1)
Amplitude
fs =
1 = 1000kHz Ts
fsig = 101kHz
Time
f v sig ( n ) = cos 2π ⋅ in ⋅ n fs
v sig ( t ) = cos ( 2π ⋅ fin ⋅ t ) t → n ⋅ Ts =
n fs
101 = cos 2π ⋅ ⋅n 1000
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Aliasing Example (2)
Amplitude
fs =
1 = 1000kHz Ts
fsig = 899kHz
Time
899 101 899 v sig ( n ) = cos 2π ⋅ ⋅ n = cos 2π ⋅ − 1 ⋅ n = cos 2π ⋅ ⋅n 1000 1000 1000
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Aliasing Example (3)
Amplitude
fs =
1 = 1000kHz Ts
fsig = 1101kHz
Time
1101 101 1101 v sig ( n ) = cos 2π ⋅ ⋅ n = cos 2π ⋅ − 1 ⋅ n = cos 2π ⋅ ⋅n 1000 1000 1000
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Consequence
•
The frequencies fsig and N·fs ± fsig (N integer), are indistinguishable in the discrete time domain
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Sampling Theorem •
In order to prevent aliasing, we need fsig ,max <
fs 2
•
The sampling rate fs=2·fsig,max is called the Nyquist rate
•
Two possibilities – Sample fast enough to cover all spectral components, including "parasitic" ones outside band of interest – Limit fsig,max through filtering
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Brick Wall Anti-Alias Filter
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Practical Anti-Alias Filter Desired Signal
Parasitic Tone Attenuation
Continuous Time 0
B
fs/2
0
B/fs
0.5
fs-B
fs
...
f
Discrete Time
•
f/fs
Need to sample faster than Nyquist rate to get good attenuation – "Oversampling"
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How much Oversampling?
[v.d. Plassche, p.41]
Alias Rejection Filter Order
fs/fsig,max
•
Can tradeoff sampling speed against filter order
•
In high speed converters, making fs/fsig,max>10 is usually impossible or too costly – Means that we need fairly high order filters
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Classes of Sampling •
Nyquist-rate sampling (fs > 2·fsig,max) – Nyquist data converters – In practice always slightly oversampled
•
Oversampling (fs >> 2·fsig,max) – Oversampled data converters – Anti-alias filtering is often trivial – Oversampling also helps reduce "quantization noise" • More later
•
Undersampling, subsampling (fs < 2·fsig,max) – Exploit aliasing to mix RF/IF signals down to baseband – See e.g. Pekau & Haslett, JSSC 11/2005
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Subsampling
•
Aliasing is "non-destructive" if signal is band limited around some carrier frequency
•
Downfolding of noise is a severe issue in practical subsampling mixers – Typically achieve noise figure no better than 20 dB (!)
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The Reconstruction Problem •
As long as we sample fast enough, x(n) contains all information about x(t) – fs > 2·fsig,max
•
How to reconstruct x(t) from x(n)?
•
Ideal interpolation formula ∞
x( t ) =
∑
x( n ) ⋅ g( t − nTs )
n =−∞
g(t ) =
•
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sin( πfs t ) πfs t
Very hard to build an analog circuit that does this…
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Zero-Order Hold Reconstruction •
The most practical way of reconstructing the continuous time signal is to simply "hold" the discrete time values – Either for full period Ts or a fraction thereof – Other schemes exist, e.g. “partial-order hold” • See [Jha, TCAS II, 11/2008]
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•
What does this do to the signal spectrum?
•
We'll analyze this in two steps – First look at infinitely narrow reconstruction pulses
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Dirac Pulses •
xd(t) is zero between pulses – Note that x(n) is undefined at these times ∞
xd ( t ) = x( t ) ⋅
∑
δ( t − nTs )
n =−∞
•
Multiplication in time means convolution in frequency – Resulting spectrum Xd ( f ) =
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1 Ts
n X f − Ts n =−∞ ∞
∑
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Spectrum
•
Spectrum of Dirac signal contains replicas of Vin(f) at integer multiples of the sampling frequency
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Finite Hold Pulse •
Consider the general case with a rectangular pulse 0 < Tp ≤ Ts
•
The time domain signal on the left follows from convolving the Dirac sequence with a rectangular unit pulse
•
Spectrum follows from multiplication with Fourier transform of the pulse sin( πfTp )
Hp (f ) = Tp
Xp (f ) =
πfTp
Tp sin( πfTp ) Ts
πfTp
⋅e
⋅e
− jπfTp
− jπfTp
n Xf − Ts n =−∞ ∞
∑
Amplitude Envelope EE315B - Chapter 2
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Envelope with Hold Pulse Tp=Ts 1 0.9 0.8 0.7 0.6 0.5
Ts
0.4
πfTp
abs(H(f))
Tp sin( πfTp )
0.3 0.2 0.1 0 0
0.5
1
1.5 f/fs
2
2.5
3
f/fs B. Murmann
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Envelope with Hold Pulse Tp=0.5·Ts 1 0.9 0.8
Tp=Ts
0.7 0.6 0.5
Ts
0.4
πfTp
abs(H(f))
Tp sin( πfTp )
Tp=0.5·Ts
0.3 0.2 0.1 0 0
0.5
1
1.5
2
2.5
3
f/fs f/f s
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Example 1
Spectrum of Continuous Time Pulse Train (Arbitrary Example)
0.5
0 0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
2
2.5
3
1
ZOH Transfer Function ("Sinc Distortion")
0.5
0 1
ZOH output, Spectrum of Staircase Approximation
original spectrum 0.5
0 0
0.5
1
1.5
f/fs
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Reconstruction Filter 1
•
Also called smoothing filter
•
Same situation as with anti-alias filter – A brick wall filter would be nice – Oversampling helps reduce filter order
0.9
Filter
0.8
Spectrum
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0
0.5
1
1.5
2
2.5
3
f/fs B. Murmann
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Summary •
Must obey sampling theorem fs > 2·fsig,max, – Usually dictates anti-aliasing filter
•
If sampling theorem is met, continuous time signal can be recovered from discrete time sequence without loss of information
•
A zero order hold in conjunction with a smoothing filter is the most common way to reconstruct – May need to add pre- or post-emphasis to cancel droop due to sinc envelope
•
Oversampling helps reduce order of anti-aliasing and reconstruction filters
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Recap
•
Next, look at – Transfer functions of quantizer and DAC – Impact of quantization error EE315B - Chapter 2
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Quantization of an Analog Signal Vq (quantized output)
Transfer Function
Slope=1
•
Quantization step ∆
•
Quantization error has sawtooth shape – Bounded by –∆/2, +∆/2
•
Ideally – Infinite input range and infinite number of quantization levels
•
In practice – Finite input range and finite number of quantization levels – Output is a digital word (not an analog voltage)
∆
eq (quantization error)
x (input) Error eq=q-x
+∆/2
-∆/2 x (input)
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Conceptual Model of a Quantizer
•
Encoding block determines how quantized levels are mapped into digital codes
•
Note that this model is not meant to represent an actual hardware implementation – Its purpose is to show that quantization and encoding are conceptually separate operations – Changing the encoding of a quantizer has no interesting implications on its function or performance EE315B - Chapter 2
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•
111 110 101 100 011 010 001 000
∆
Analog Input eq (quantization error)
Digital Output
Encoding Example for a B-Bit Quantizer
+∆/2
• http://www.analog.com/en/content/0 ,2886,760%255F788%255F91285, 00.html
•
-∆/2 •
FSR x (input)
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Example: B=3 – 23=8 distinct output codes – Diagram on the left shows "straight-binary encoding" – See e.g. Analog Devices "MT009: Data Converter Codes" for other encoding schemes
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Quantization error grows out of bounds beyond code boundaries We define the full scale range (FSR) as the maximum input range that satisfies |eq| ≤ ∆/2 – Implies that FSR=2B·∆ 28
Nomenclature •
Overloading - Occurs when an input outside the FSR is applied
•
Transition level – Input value at the transition between two codes. By standard convention, the transition level T(k) lies between codes k-1 and k
•
Code width – The difference between adjacent transition levels. By standard convention, the code width W(k)=T(k+1)-T(k) – Note that the code width of the first and last code (000 and 111 on previous slide) is undefined
•
LSB size (or width) – synonymous with code width ∆
[IEEE Standard 1241-2000]
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Implementation Specific Technicalities •
So far, we avoided specifying the absolute location of the code range with respect to "zero" input
•
The zero input location depends on the particular implementation of the quantizer – Bipolar input, mid-rise or mid-tread quantizer – Unipolar input
•
The next slide shows the case with – Bipolar input • The quantizer accepts positive and negative inputs – Represents the common case of a differential circuit
– Mid-rise characteristic • The center of the transfer function (zero), coincides with a transition level
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Digital Output
Bipolar Mid-Rise Quantizer
111 110 101 100 011 010 001 000 Analog Input -FSR/2
•
+FSR/2
0
Nothing new here…
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Bipolar Mid-Tread Quantizer In theory, less sensitive to infinitesimal disturbance around zero – In practice, offsets larger than ∆/2 (due to device mismatch) often make this argument irrelevant
•
Asymmetric full-scale range, unless we use odd number of codes
Digital Output
•
111 110 101 100 011 010 001 000 Analog Input FSR/2 + ∆/2
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0 FSR/2 - ∆/2
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Unipolar Quantizer Usually define origin where first code and straight line fit intersect – Otherwise, there would be a systematic offset
•
Usable range is reduced by ∆/2 below zero
Digital Output
•
111 110 101 100 011 010 001 000 0
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Effect of Quantization Error on Signal •
Two aspects – How much noise power does quantization add to samples? – How is this noise power distributed in frequency?
•
Quantization error is a deterministic function of the signal – Should be able answer above questions using a deterministic analysis – But, unfortunately, such an analysis strongly depends on the chosen signal and can be very complex
•
Strategy – Build basic intuition using simple deterministic signals – Next, abandon idea of deterministic representation and revert to a "general" statistical model (to be used with caution!)
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Ramp Input •
Applying a ramp signal (periodic sawtooth) at the input of the quantizer gives the following time domain waveform for eq 0.6
0.2 0
q
e (t) [∆]
0.4
-0.2 -0.4 0
50 100 Time [arbitrary units]
150
•
What is the average power of this waveform?
•
Integrate over one period eq2
T/2
1 = eq2 ( t )dt T −T∫/ 2
eq ( t ) =
∆ ⋅t T
∴ eq2
∆2 = 12
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Sine Wave Input 1
1 Vin V
0.8
q
0.6
0.6
0.4
0.4
0.2
0.2 eq(t) [∆]
[Volts]
0.8
0
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1 0
•
0.2
0.4 0.6 Time [arbitrary units]
0.8
1
-1 0
0.2
0.4 0.6 Time [arbitrary units]
0.8
1
Integration is not straightforward…
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Quantization Error Histogram • •
Sinusoidal input signal with fsig=101Hz, sampled at fs=1000Hz 8-bit quantizer Mean=0.000LSB, Var=1.034LSB2/12 120 100
Count
80 60 40 20 0 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0 0.1 0.2 0.3 0.4 0.5 0.6 e /∆ q
• •
Distribution is "almost" uniform Can approximate average power by integrating uniform distribution
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Statistical Model of Quantization Error •
Assumption: eq(x) has a uniform probability density
•
This approximation holds reasonably well in practice when – Signal spans large number of quantization steps – Signal is "sufficiently active" – Quantizer does not overload +∆ / 2
Mean
eq =
∫
−∆ / 2
Variance
eq2 =
+∆ / 2
∫
−∆ / 2
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eq ∆
deq = 0
eq 2 ∆
deq =
∆2 12
38
Reality Check (1) •
Input sequence consists of 1000 samples drawn from Gaussian distribution, 4σ=FSR Mean=-0.004LSB, Var=1.038LSB2/12 150
Count
100
50
0 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
•
0 0.1 0.2 0.3 0.4 0.5 0.6 eq/∆
Error power close to that of uniform approximation EE315B - Chapter 2
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Reality Check (2) •
Another sine wave example, but now fsig/fs=100/1000
•
What's going on here? Mean=-0.000LSB, Var=0.629LSB2/12 500
Count
400 300 200 100 0 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
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0 0.1 0.2 0.3 0.4 0.5 0.6 eq/∆
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Amplitude
Analysis (1)
fsig/fs=100/1000
Time
•
Sampled signal is repetitive and has only a few distinct values – This also means that the quantizer generates only a few distinct values of eq; not a uniform distribution
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Analysis (2) f v sig ( n ) = cos 2π ⋅ in ⋅ n fs
•
Signal repeats every m samples, where m is the smallest integer that satisfies m⋅
•
fin = integer fs
m⋅
101 = integer 1000
⇒ m = 1000
m⋅
100 = integer 1000
⇒ m = 10
This means that eq(n) has at best 10 distinct values, even if we take many more samples
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Signal-to-Quantization-Noise Ratio •
Assuming uniform distribution of eq and a full-scale sinusoidal input, we have
SQNR =
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Psig Pqnoise
=
1 2B ∆ 2 2 2
∆ 12
2
= 1.5 × 22B = 6.02B + 1.76 dB
B (Number of Bits)
SQNR
8
50 dB
12
74 dB
16
98 dB
20
122 dB
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Quantization Noise Spectrum (1) •
How is the quantization noise power distributed in frequency? – First think about applying a sine wave to a quantizer, without sampling (output is continuous time)
+ many more harmonics
[Y. Tsividis, ICASSP 2004]
•
Quantization results in an "infinite" number of harmonics
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Quantization Noise Spectrum (2) •
Now sample the signal at the output – All harmonics (an "infinite" number of them) will alias into band from 0 to fs/2 – Quantization noise spectrum becomes "white"
[Y. Tsividis, ICASSP 2004]
•
Interchanging sampling and quantization won’t change this situation
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Quantization Noise Spectrum (3) •
Can show that the quantization noise power is indeed distributed (approximately) uniformly in frequency – Again, this is provided that the quantization error is "sufficiently random" ∆2 2 ⋅ 12 fs
•
References – W. R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., pp. 446-72, July 1948. – B. Widrow, "A study of rough amplitude quantization by means of Nyquist sampling theory," IRE Trans. Circuit Theory, vol. CT-3, pp. 266-76, 1956. – A. Sripad and D. A. Snyder, "A necessary and sufficient condition for quantization errors to be uniform and white," IEEE Trans. Acoustics, Speech, and Signal Processing, pp. 442-448, Oct 1977.
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Ideal DAC •
Essentially a digitally controlled voltage, current or charge source – Example below is for unipolar DAC
•
Ideal DAC does not introduce quantization error!
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Static Nonidealities •
Static deviations of transfer characteristics from ideality – Offset – Gain error – Differential Nonlinearity (DNL) – Integral Nonlinearity (INL)
•
Useful references – Analog Devices MT-010: The Importance of Data Converter Static Specifications • http://www.analog.com/en/content/0,2886,761%255F795%255F91286,00.html
– "Understanding Data Converters," Texas Instruments Application Report LAA013, 1995. • http://focus.ti.com/lit/an/slaa013/slaa013.pdf
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Offset and Gain Error •
Conceptually simple, but lots of (uninteresting) subtleties in how exactly these errors should be defined – Unipolar versus bipolar, endpoint versus midpoint specification – Definition in presence of nonlinearities
•
General idea (neglecting staircase nature of transfer functions):
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ADC Offset and Gain Error •
Definitions based on bottom and top endpoints of transfer characteristic – ½ LSB before first transition and ½ LSB after last transition – Offset is the deviation of bottom endpoint from its ideal location – Gain error is the deviation of top endpoint from its ideal location with offset removed
•
Both quantities are measured in LSB or as percentage of full-scale range Gain Error Dout
Dout
Ideal
Vin
Ideal
Vin
Offset B. Murmann
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DAC Offset and Gain Error •
Same idea, except that endpoints are directly defined by analog output values at minimum and maximum digital input
•
Also note that errors are specified along the vertical axis
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51
Comments on Offset and Gain Errors •
Definitions on the previous slides are the ones typically used in industry – IEEE Standard suggest somewhat more sophisticated definitions based on least square curve fitting • Technically more suitable metric when the transfer characteristics are significantly non-uniform or nonlinear
•
Generally, it is non-trivial to build a converter with very good gain/offset specifications – Nevertheless, since gain and offset affect all codes uniformly, these errors tend to be easy to correct • E.g. using a digital pre- or post-processing operation
– Also, many applications are insensitive to a certain level of gain and offset errors • E.g. audio signals, communication-type signals, ...
•
More interesting aspect: linearity – DNL and INL
B. Murmann
EE315B - Chapter 2
52
Differential Nonlinearity (DNL) •
In an ideal world, all ADC codes would have equal width; all DAC output increments would have same size
•
DNL(k) is a vector that quantifies for each code k the deviation of this width from the "average" width (step size)
•
DNL(k) is a measure of uniformity, it does not depend on gain and offset errors – Scaling and shifting a transfer characteristic does not alter its uniformity and hence DNL(k)
•
Let's look at an example
B. Murmann
EE315B - Chapter 2
53
ADC DNL Example (1)
B. Murmann
EE315B - Chapter 2
Code (k)
W [V]
0
undefined
1
1
2
0.5
3
1
4
1.5
5
0
6
1.5
7
undefined
54
ADC DNL Example (2) •
What is the average code width? – ADC with perfect uniformity would divide the range between first and last transition into 6 equal pieces – Hence calculate average code width (i.e. LSB size) as
Wavg = •
7.5V − 2V = 0.9167V 6
Now calculate DNL(k) for each code k using
DNL(k) =
W(k) − Wavg Wavg
EE315B - Chapter 2
B. Murmann
55
Result Code (k)
DNL [LSB]
1
0.09
2
-0.45
3
0.09
4
0.64
5
-1.00
6
0.64
•
Positive/negative DNL implies wide/narrow code, respectively
•
DNL = -1 LSB implies missing code
•
Impossible to have DNL < -1 LSB for an ADC – But possible to have DNL > +1 LSB
•
Can show that sum over all DNL(k) is equal to zero
B. Murmann
EE315B - Chapter 2
56
A Typical ADC DNL Plot
[Ahmed, JSSC 12/2005]
•
People speak about DNL often only in terms of min/max number across all codes – E.g. DNL = +0.63/-0.91 LSB
•
Might argue in some cases that any code with DNL < -0.9 LSB is essentially a missing code – Why ?
B. Murmann
EE315B - Chapter 2
57
Impact of Noise
[W. Kester, "ADC Input Noise: The Good, The Bad, and The Ugly. Is No Noise Good Noise?" Analogue Dialogue, Feb. 2006]
•
In essentially all moderate to high-resolution ADCs, the transition levels carry noise that is somewhat comparable to the size of an LSB – Noise "smears out" DNL, can hide missing codes
•
Especially for converters whose input referred (thermal) noise is larger than an LSB, DNL is a "fairly useless" metric
B. Murmann
EE315B - Chapter 2
58
DAC DNL •
Same idea applies – Find output increments for each digital code – Find increment that divides range into equal steps – Calculate DNL for each code k using
DNL(k) = •
Step(k) − Stepavg Stepavg
One difference between ADC and DAC is that DAC DNL can be less than -1 LSB – How ?
B. Murmann
EE315B - Chapter 2
59
Non-Monotonic DAC
DNL(3) =
=
Step(3) − Stepavg Stepavg −0.5V − 1V = −1.5LSB 1V
•
In a DAC, DNL < -1LSB implies non-monotinicity
•
How about a non-monotonic ADC?
B. Murmann
EE315B - Chapter 2
60
Non-Monotonic ADC
•
Code 2 has two transition levels ⇒ W(2) is ill defined – DNL is ill-defined!
•
Not a very big issue, because a non-monotonic ADC is usually not what we'll design for in practice…
B. Murmann
EE315B - Chapter 2
61
Integral Nonlinearity (INL) •
General idea – For each "relevant point" of the transfer characteristic, quantify distance from a straight line drawn through the endpoints • An alternative, less common definition uses a least square fit line as a reference
– Just as with DNL, the INL of a converter is by definition independent of gain and offset errors
B. Murmann
EE315B - Chapter 2
62
ADC INL Example (1) •
"Straight line" reference is uniform staircase between first and last transition
•
INL for each code is INL(k) =
T(k) − Tuniform (k) Wavg
•
Obviously INL(1) = 0 and INL(7) = 0
•
INL(0) is undefined
EE315B - Chapter 2
B. Murmann
63
ADC INL Example (2) •
Can show that
k −1
INL(k) = ∑ DNL(i) i =1
•
Means that once we computed DNL, we can easily find INL using a cumulative sum operation on the DNL vector
•
Using DNL values from last lecture, we find
B. Murmann
Code (k)
DNL [LSB]
INL [LSB]
1
0.09
0
2
-0.45
0.09
3
0.09
-0.36
4
0.64
-0.27
5
-1.00
0.36
6
0.64
-0.64
7
undefined
0
EE315B - Chapter 2
64
Result
B. Murmann
EE315B - Chapter 2
65
A Typical ADC DNL/INL Plot
[Ishii, Custom Integrated Circuits Conference, 2005]
•
DNL/INL signature often reveals architectural details – E.g. major transitions – We'll see more examples in the context of DACs
•
Since INL is a cumulative measure, it turns out to be less sensitive than DNL to thermal noise "smearing"
B. Murmann
EE315B - Chapter 2
66
DAC INL •
Same idea applies – Find ideal output values that lie on a straight line between endpoints – Calculate INL for each code k using INL(k) =
•
Vout (k) − Voutuniform (k) Stepavg
Interesting property related to DAC INL – If for all codes |INL| < 0.5 LSB, it follows that all |DNL| < 1 LSB – A sufficient (but not necessary) condition for monotonicity
B. Murmann
EE315B - Chapter 2
67
How to Measure DNL/INL in the Lab? •
DAC – Apply all input codes, measure output with a precision voltmeter
•
ADC – A little more tricky – One option is to build a servo loop that finds the code transitions • See e.g. Kester, page 5.36
– A more popular approach is histogram testing
B. Murmann
EE315B - Chapter 2
68
Basic Histogram Test Setup
Kester, p. 5.39
B. Murmann
EE315B - Chapter 2
69
Histogram Example
Kester, p. 5.40
B. Murmann
EE315B - Chapter 2
70
Sinusoidal Input Kester, p. 5.42
B. Murmann
•
Preferred over ramp or triangular test signals
•
It is easier much easier to generate a “high fidelity” sinusoid
•
The histogram now takes on a bathtub shape, which can be mathematically inverted to find the DNL
EE315B - Chapter 2
71
Correction for Sinusoidal pdf •
References – M. V. Bossche, J. Schoukens, and J. Renneboog, “Dynamic Testing and Diagnostics of A/D Converters,” IEEE TCAS, Aug. 1986 – IEEE Standard 1057 – Kester, Section 5.4
•
It turns out that is not necessary to know the exact amplitude and offset of the sine wave input – There exists some confusion about this…
•
The code on the next slide does all the required math to undo the bathtub shape
B. Murmann
EE315B - Chapter 2
72
DNL/INL Code function [dnl,inl] = dnl_inl_sin(y);
% transition levels
%DNL_INL_SIN
T = -cos(pi*ch/sum(h));
% dnl and inl ADC output % input y contains the ADC output
% linearized histogram
% vector obtained from quantizing a
hlin = T(2:end) - T(1:end-1);
% sinusoid % truncate at least first and last % Boris Murmann, Aug 2002
% bin, more if input did not clip ADC
% Bernhard Boser, Sept 2002
trunc=2; hlin_trunc = hlin(1+trunc:end-trunc);
% histogram boundaries minbin=min(y);
% calculate lsb size and dnl
maxbin=max(y);
lsb= sum(hlin_trunc) / (length(hlin_trunc)); % histogram
dnl= [0 hlin_trunc/lsb-1];
h = hist(y, minbin:maxbin);
misscodes = length(find(dnl toff Vout = Vin − ∆Vout Vout = Vin −
ε=−
Col ( Vin + Vt − φL ) = Vin (1 + ε ) + Vos Col + C
Col Col + C
Vos = −
Gain Error
•
Col ( Vt − φL ) Col + C
Offset Error
Example: C=1pF, φL=0V, Vt=0.45V, W=20µm, Col’=0.1fF/µm, Col=2fF ε = −0.2%
B. Murmann
Vos = −0.9mV
EE315B - Chapter 5
50
Fast Gating φ
φ
•
Channel charge cannot change instantaneously
•
Resulting surface potential decays via charge flow to source and drain
•
Charge divides between source and drain depending on impedances loading these nodes
φH VIN + VT Surface Potential
t
Qch ΨS
φL
t < to
VO V IN
ΨS
ýV ∆V
t > to
1
(1-α)Q chch 2Q
B. Murmann
t Ε
Ε
1
αQ ch 2 Qch
EE315B - Chapter 5
51
Charge Split Ratio Data
Tf RonC2
G. Wegmann et al., "Charge injection in analog MOS switches," IEEE J. SolidState Circuits, pp. 1091-1097, June 1987. Y. Ding and R. Harjani, "A universal analytic charge injection model," Proc. ISCAS, pp. 144-147, May 2000. B. Murmann
EE315B - Chapter 5
52
Interpretation •
RonC2 and Tf are usually comparable, or at least not more than an order of magnitude apart – This brings us into the range of 0.1…1 on the chart by Wegmann
•
This means that the charge split will in practice have some dependence on the impedances seen on the two sides of the transistor
•
Remember: Slightly more charge will go to the side with lower impedance
EE315B - Chapter 5
B. Murmann
53
Fast Gating Model for t > toff Vout = Vin − ∆Vout = Vin (1 + ε ) + Vos Vout = Vin −
Col 1Q ( φH − φL ) + ch Col + C 2 C
Assuming 50/50 charge split
Qch = − WLCox [ φH − Vin − Vt ] ε=
•
1 WLCox 2 C
Vos = −
Col 1 WLCox ( φH − φL ) − ( φH − Vt ) Col + C 2 C
Example: C=1pF, φH-φL=1.8V, Vt=0.45V, W=20µm, LCox=2fF/µm Col’=0.1fF/µm, Col=2fF ε = +2%
B. Murmann
Vos = −30.6mV EE315B - Chapter 5
54
Transition Fast/Slow Gating Fast gating
Slow gating
Fast gating
| ε|
Slow gating
|Vos|
TtFf
TtfF
•
|ε| and |Vos| decrease as the fall time of φ (Tf) increases and approach the limit case of slow gating
•
Unfortunately, high-speed switched capacitor circuits tend to operate in fast gating regime
EE315B - Chapter 5
B. Murmann
55
Impact of Technology Scaling
∆V ≅
1 Qch 2 C
1
R≅ µCox
•
T 1 = s = N ⋅ RC 2fs 2
W ( V − Vt ) L GS
=
L2 µQch
L2 ∆V ≅N fs µ
Charge injection error to speed ratio benefits from shorter channels and increases in mobility (e.g. due to strain)
B. Murmann
EE315B - Chapter 5
56
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
57
Improvements •
Charge cancelation – Try to cancel channel charge by injecting a charge packet with opposite sign
•
Differential sampling – Use a differential circuit to suppress offset
•
CMOS switch – Try to balance the nonidealities of NMOS device with a parallel PMOS
B. Murmann
EE315B - Chapter 5
58
Charge Cancellation
∆Q1 = 0.5Qch1 + Qol1
S
L =L W =0.5W 1
∆Q2 ≅ Qch2 + 2Qol2 ≅ 0.5Qch1 + Qol1
2
∆Q1 − ∆Q2 ≅ 0
1
[Eichenberger and Guggenbűhl, JSSC 8/89]
•
Cancellation is never perfect, since channel charge of M1 will not exactly split 50/50 – E.g. if Rs is very small, most of M1’s channel charge will flow toward the input voltage source
•
Not a precision technique, just an attempt to do a partial clean-up
EE315B - Chapter 5
B. Murmann
59
Differential Sampling (1) φ VO1
+ VI1
C CH
VIC =
– VO2
+ VI2
VID = VI1 − VI2
C CH
VI1 + VI2 2
VOD = VO1 − VO2 VOC =
VO1 + VO2 2
VO1 = (1 + ε1 ) VI1 + VOS1 VO2 = (1 + ε2 ) VI2 + VOS2
–
ε +ε ε +ε VOD = 1 + 1 2 VID + ( ε1 − ε2 ) VIC + ( VOS1 − VOS2 ) ≅ 1 + 1 2 VID 2 2 + VOS2 ε1 + ε2 + VOS2 V V ε −ε ε +ε VOC = 1 2 VID + 1 + 1 2 VIC + OS1 VIC + OS1 ≅ 1+ 2 2 2 2 4 B. Murmann
EE315B - Chapter 5
60
Differential Sampling (2) •
Assuming good matching between the two half circuits, we have – Small residual offset in VOD – Good rejection of coupling noise, supply noise, … – Small common-mode to differential-mode gain
•
Unfortunately, VOD has essentially same gain error as the basic single ended half circuit
•
This also means that there will be nonlinear terms – Out simplistic analysis assumed that the channel charge is linearly related to Vin – This is true only to first order (consider e.g. backgate effect) • Expect to see nonlinear distortion along with gain error
EE315B - Chapter 5
B. Murmann
61
CMOS Switch φ VO
+ VIN
(
Qchp ≅ WpLpCox VIN − φL − Vtp
CH
φ
–
•
)
Assuming fast gating, 50/50 charge split and WnLn = WpLp 1 1 Qchn + Qchp C 2 ∆Vo ≅ 2 = ox C C
•
Qchn ≅ − WnLnCox ( φH − VIN − Vtn )
V − Vtp φ −φ VIN − H L + tn 2 2
Charges fully cancel e.g. for VIN = (φH-φL)/2 = VDD/2, and Vtn=|Vtp|, but there is still signal dependent residual injection
B. Murmann
EE315B - Chapter 5
62
On Resistance of CMOS Switch •
At least in principle, adding a PMOS can also help with the problem of signal dependent Ron in track mode – For increasing VIN, NMOS resistance goes up, PMOS resistance goes down φ VO
+ VIN
CCH
φ
–
R≅
1
1
W W µnCox ( VGSn − Vtn ) µpCox VGSp − Vtp L n L p
(
)
EE315B - Chapter 5
B. Murmann
63
Analysis R≅
1
1
W W µnCox ( VGSn − Vtn ) µpCox VGSp − Vtp L n L p
(
R≅
1 W W W W µnCox ( VDD − Vtn ) − µnCox − µpCox v in − µpCox Vtp L L L p L n n p
R≅
1 W µnCox VDD − Vtn − Vtp L n
(
• •
)
)
W W if µn = µp L n L p
Independent of Vin too good to be true! Missing factors – Backgate effect – Short channel effects
B. Murmann
EE315B - Chapter 5
64
Real CMOS Switch 100 NMOS PMOS NMOS || PMOS
R [Ω]
80 60 40 20 0 0
0.5
1 Vin [V]
1.5
•
Design – Size P/N ratio to minimize change in R over input range – Size P and N simultaneously to meet distortion specs
•
PMOS brings limited benefit unless the input signal range is large or centered near VDD
B. Murmann
EE315B - Chapter 5
65
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
66
Clock Bootstrapping
+ VDD -
+ VDD -
Cboot
Cboot
VGS=VDD=const.
Vin A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
•
Phase 1 – Cboot is precharged to VDD – Sampling switch is off
•
Phase 2 – Sampling switch is on with VGS=VDD=const. – To first order, both Ron and channel charge are signal independent
B. Murmann
EE315B - Chapter 5
67
Waveforms
A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999.
B. Murmann
EE315B - Chapter 5
68
Circuit Implementation
Switch
A. Abo et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-toDigital Converter,” IEEE J. Solid-State Circuits, pp. 599, May 1999
B. Murmann
EE315B - Chapter 5
69
Limitations •
Efficacy of bootstrap circuit is reduced by – Backgate effect – Parasitic capacitance between at top plate of C3
R≅
B. Murmann
Cpar
1 Cpar Cboot W µnCox VDD − Vin − Vtn [ Vin ] 1 424 3 Cboot + Cpar L n Cboot + Cpar Backgate effect
EE315B - Chapter 5
70
Alternative Implementation
Dessouky and Kaiser, "Input switch configuration suitable for rail-to-rail operation of switched opamp circuits," Electronics Letters, Jan. 1999.
•
Less complex, but Cpar tends to be larger due to two parasitic well capacitances EE315B - Chapter 5
B. Murmann
71
Performance of Bootstrapped Samplers •
Bootstrapped “top plate” sampling (as opposed to “bottom plate” – more later) tends to work very well up to ~10bit resolution
•
Example
[Louwsma, JSSC 4/2008]
B. Murmann
EE315B - Chapter 5
72
High-Speed Example without Bootstrap
[Choi and Abidi, JSSC 12/2001]
•
For lower resolution applications, it can be OK to drop the bootstrap circuit
B. Murmann
EE315B - Chapter 5
73
Bottom Plate Sampling •
What if we want to do much better, e.g. 16 bits?
•
Basic idea – Sample signal at the "grounded" side of the capacitor to achieve signal independent sampling
•
References – D. G. Haigh and B. Singh, “A switching scheme for SC filters which reduces the effect of parasitic capacitances associated with switch control terminals,” in Proc. IEEE Int. Symp. Circuits and Systems, 1983, pp. 586–589. – K.-L. Lee and R. G. Meyer, “Low-Distortion SwitchedCapacitor Filter Design Techniques,” IEEE J. Solid-State Circuits, pp. 1103-1113, Dec. 1985.
•
First look at single ended half circuit for simplicity
B. Murmann
EE315B - Chapter 5
74
Bottom Plate Sampling Analysis (1) •
Turn M2 off "slightly" before M1 – Typically a few hundred ps delay between falling edges of φe and φ
•
During turn off, M2 injects charge ∆Q2 ≅
∆Q2
1 WLCox ( φH − Vtn ) 2
•
To first order, the charge injected by M2 is signal independent
•
Voltage across C VC = Vin +
B. Murmann
∆Q 2 C
EE315B - Chapter 5
75
Bottom Plate Sampling Analysis (2)
∆Q1 ≅
B. Murmann
•
Next, turn off M1
•
M1 will inject signal dependent charge onto the series combination of C and the parasitic capacitance at its bottom plate (Cpar)
•
Looks like, this is not much different from the conventional top-plate sampling? – But wait…
1 WLCox ( φH − Vin − Vtn ) 2
EE315B - Chapter 5
76
Bottom Plate Sampling Analysis (3)
Q X = −CVin − ∆Q2 Charge injected by M2 (Signal independent)
•
Interesting observation – Even though M1 injects some charge, the total charge at node X cannot change!
•
Idea – Process total charge at node X instead of looking at voltage across C
•
The charge can be processed in two ways – Open-loop – Closed-loop (charge redistribution)
EE315B - Chapter 5
B. Murmann
77
Open-Loop Charge Processing Q X = −CVin − ∆Q2 φ1 Vin
φ2
VX = M1
QX ∆Q2 C = − Vin − C + Cp C + Cp C + Cp
C
(no term due to signal dependent charge!)
Vx
φ1e Cpar
φ1
M2
φ1e
φ2
•
Remaining drawback – Cpar (and buffer input capacitance) is usually weakly nonlinear and will introduce some harmonic distortion
B. Murmann
EE315B - Chapter 5
78
Closed-Loop Charge Processing
•
Amplifier forces voltage at node X to “zero” – Means that charge at node X must redistribute onto feedback capacitor Cf EE315B - Chapter 5
B. Murmann
79
Charge Conservation Analysis Charge at node X during φ1:
Q X1 = −CVin − ∆Q2 + 0 ⋅ Cf
Charge at node X during φ2:
Q X2 = −Cf Vout
Q X1 = Q x2
Charge Conservation:
−CVin − ∆Q2 = −Cf Vout ∴ Vout =
•
∆Q2 C Vin + Cf Cf
Offset term due to signal independent injection from M2 can be easily removed using a differential architecture
B. Murmann
EE315B - Chapter 5
80
Clock Generation
[A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," PhD Thesis, UC Berkeley, 1999]
B. Murmann
EE315B - Chapter 5
81
Fully Differential Circuit
B. Murmann
EE315B - Chapter 5
82
Analysis (1)
(
Q1m = −CVinp + ∆Q
Q2m = CVxm − Cf Vop − Vxm
Q1p = −CVinm + ∆Q
Q2p = CVxp − Cf Vom − Vxp
1)
Q1m = Q2m
2)
Q1p = Q2p
(
Vxm = Vxp
Vop + Vom 2
)
)
= Voc
EE315B - Chapter 5
B. Murmann
83
Analysis (2) •
Subtracting 1) and 2) yields Vop − Vom =
•
C ( Vinp − Vinm ) Cf
Adding 1) and 2) yields
(
)
(
)
(
−C Vinp + Vinm + 2∆Q = ( C + Cf ) Vxp + Vxm − Cf Vop + Vop Vxc =
•
)
Cf ∆Q C + V oc − V ic C + Cf C + C f C + Cf
Variations in Vic show up as common mode variations at the amplifier input – Need amplifier with good CMRR
B. Murmann
EE315B - Chapter 5
84
T/H with Common Mode Cancellation
S.H. Lewis & P.R. Gray, "A Pipelined 5 MSample/s 9-bit Analog-to-Digital Converter", IEEE J. Solid-State Circuits, pp. 954-961, Dec. 1987
•
Shorting switch allows to re-distribute only differential charge on sampling capacitors
•
Common mode at OPAMP input becomes independent of common mode at circuit input terminals (IN+/IN-)
•
Original idea: Yen & Gray, JSSC 12/1982 EE315B - Chapter 5
B. Murmann
85
Analysis (1) During 1
During 2 C
C V
C
C
V
V V
V
V
V C
V
C V C
C
•
Charge conservation at Vip,Vim and Vfloat
( Vip + Vim ) ⋅ C = ( Vfloat − Vxp ) ⋅ C + ( Vfloat − Vxm ) ⋅ C Vic = Vfloat − Vxc Vfloat = Vic + Vxc
B. Murmann
EE315B - Chapter 5
86
Analysis (2) •
Common mode charge conservation at amplifier inputs − Vic ⋅ C − Voc ⋅ Cf = − ( Vfloat − Vxc ) ⋅ C − ( Voc − Vxc ) ⋅ Cf − Vic ⋅ C = − ([ Vic + Vxc ] − Vxc ) ⋅ C + Vxc ⋅ Cf 0 = Vxc
•
Amplifier input common mode (Vxc) is independent of – Input common mode (Vic) – Output common mode (Voc)
B. Murmann
EE315B - Chapter 5
87
Flip-Around T/H
[W. Yang et al., "A 3-V 340-mW 14-b 75-MSample/s CMOS ADC With 85-dB SFDR at Nyquist Input", IEEE J. Solid-State Circuits, pp. 1931-1936, Dec. 2001]
•
Sampling caps are "flipped around" OTA and used as feedback capacitors during φ2
•
Main advantage: improved feedback factor (lower noise, higher speed)
•
Main disadvantage: OTA is subjected to input common mode variations
B. Murmann
EE315B - Chapter 5
88
Sampling Network Design Considerations φ1-
M1-
φ1+ φ1
M1
•
M1- switches only needed to set common mode; M1 is actual sampling switch – Make M1 larger than M1-
•
Ideally turn off M1- before M1 – In practice, usually OK to turn off simultaneously
•
In track mode, the total path resistance is R(M3) plus bottom plate switch resistance – Since R(M3) is signal dependent, make its resistance small compared to that of bottom plate network
φ1+
φ1-
M1[Lin, Kim and Gray, JSSC 4/1991]
φ1φ1 φ1+ φ2 B. Murmann
EE315B - Chapter 5
89
Schematic Entry and Layout of M1
•
Use antiparallel devices to implement M1 – Needed in simulation to guarantee circuit symmetry • E.g. BSIM model is not necessarily perfectly symmetric with respect to drain/source!
– Needed in layout to ensure symmetry in presence of drain/source asymmetry due to processing artifacts B. Murmann
EE315B - Chapter 5
90
What Ultimately Limits Linearity? •
Track mode nonlinearity due to R=f(Vin) – Mitigate using clock bootstrapping and proper partitioning of total path resistance – Eventually, bootstrapping falls apart high frequencies, due to parasitics capacitances inside the bootstrap circuit
•
Mismatch in half-circuit charge injection due to R=f(Vin) – Bottom plate switches in the two half circuits see input dependent impedance; this creates input dependent charge injection mismatch – Bootstrapping helps; ultimately limited by backgate effect – This effect is often fairly independent of frequency (somewhat dependent on realization of top plate switch)
•
In high performance designs, can achieve ~80-100dB linearity up to a few hundreds of MHz EE315B - Chapter 5
B. Murmann
91
Capacitors Metal-Insulator-Metal (MIM)
Vertical Parallel Plate (VPP)
[Ng, Trans. Electron Dev., 7/2005]
[Aparicio, JSSC 3/2002]
•
Typically 1-2 fF/µm2 (10-20 fF/µm2 for advanced structures) – For 1 fF/µm2, a 10 pF capacitor occupies ~100µm x 100µm
•
Both MIM and VPP capacitors have good electrical properties – Mostly worry about parasitic caps – Series and parallel resistances are often not a concern
B. Murmann
EE315B - Chapter 5
92
Plate Parasitics Ideal Capacitor Symbol
Typical Integrated Circuit Capacitor
•
Node n1 is usually the "physical" top plate of the capacitor – Makes nomenclature very confusing, since this plate is typically used as the "electrical" bottom plate in a sampling circuit (in the context of "bottom plate sampling")
•
Typical values for a MIM capacitor – α=1%, β=10%
B. Murmann
EE315B - Chapter 5
93
Proper Connection of Capacitors
•
“Fat plate” is oriented away from virtual ground nodes to avoid reduction of feedback factor and reduce potential noise coupling
B. Murmann
EE315B - Chapter 5
94
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
95
Settling and Noise Analysis
Cf
φ2
φ1 Cs
Gm CL
B. Murmann
EE315B - Chapter 5
96
First Order Amplifier Model
Piecewise linear half-circuit x
xd
o
od
2 x
n
gm v x for io = ID ⋅ sign ( v x )
o
o
gm v x < ID else
EE315B - Chapter 5
B. Murmann
97
Linear Settling (Small Input Step)
0
→Vofinal
t=0
-Vistep
(
v o (t) = Vofinal 1 − e − t / τ (ignoring feedforward zero)
•
Important parameter: Return factor or "feedback factor" β β=
B. Murmann
Cf Cf + Cs + Cx
EE315B - Chapter 5
98
)
Waveform Detail Static Error ε0
Dynamic Error εd(t) 1
V V o/V /V out o,ideal out,ideal
0.8
0.6
0.4
0.2
0 0
2
4
6
8
10
t/τ EE315B - Chapter 5
B. Murmann
99
Static Settling Error •
Ideal output voltage for t→∞ Vofinal,ideal = Vistep ⋅
•
Actual output voltage (from detailed analysis) Vofinal = Vistep ⋅
•
Cs T0 ⋅ Cf 1 + T0
T0 = β ⋅ gmro = β ⋅ avo
Define static settling error ε0 =
•
Cs Cf
Vofinal − Vofinal,ideal Vofinal,ideal
T −1 1 1 1 T + = =− ≅− 1 1+ T T
Example: T0=1000 0.1% static settling error
B. Murmann
EE315B - Chapter 5
100
Dynamic Settling Error
(
)
−t / τ − Vofinal v o (t) − Vofinal Vofinal 1 − e εdynamic (t) = = = −e − t / τ Vofinal Vofinal
N=
ts = − ln ( εd ) τ
εdynamic
N
1%
4.6
0.1%
6.9
0.01%
9.2
EE315B - Chapter 5
B. Murmann
101
Time Constant
β=
Cf C f + Cs + C x
R=
1 β gm
CLtot = CL + (1 − β ) Cf
τ=
B. Murmann
1 CLtot ⋅ β gm
EE315B - Chapter 5
102
Transconductor Current 0
→Vofinal
t=0
-Vistep
(
v o (t) = Vofinal 1 − e − t / τ
•
During linear settling, the current delivered by the transconductor is io ≅ −CLtot
•
dv o (t) V = −CLtot ofinal e− t / τ dt τ
Peak current occurs at t=0 io max = CLtot
Vofinal τ
EE315B - Chapter 5
B. Murmann
103
Slewing •
)
The amplifier can deliver a maximum current of ID – If |io|max > ID, slewing occurs io max = CLtot
CLeff
Vofinal >I 1 CLtot D ⋅ β gm
Vofinal > ID τ
⇒
gm 1 > βVofinal ID
•
Example: β=0.5, Vofinal=0.5V gm/ID > 4 S/A will result in slewing
•
Very hard to avoid slewing, unless − We are willing to bias at very low gm/ID (power inefficient) − Feedback factor is small (large closed-loop gain, CS/Cf) − Output voltage swing is small
B. Murmann
EE315B - Chapter 5
104
Output Waveform with Initial Slewing
(
v o (t) = ∆Voslew + ∆Volin 1 − e −(t −∆tslew )/ τ
v o (t) =
•
)
ID t = SR ⋅ t CLtot
Continuous derivative in the transition slewinglinear requires ∆Volin ID = τ CLtot
∆Volin =
τ ⋅ ID CLtot
EE315B - Chapter 5
B. Murmann
105
Dynamic Error with Slewing ∆t slew = ( Vofinal − ∆Volin ) ⋅
∆Voslew = Vofinal − ∆Volin
•
CLtot ID
Using the above result, we can now calculate the dynamic error during the final linear settling portion For t > ∆t slew :
(
− t −∆t slew ) / τ v o (t) = ∆Voslew + ∆Volin 1 − e (
(
)
)
− ( t −∆t slew ) / τ − Vofinal v o (t) − Vfinal ∆Voslew + ∆Volin 1 − e εd (t) = = Vfinal Vofinal
εd (t) = −
B. Murmann
∆Volin − ( t −∆t slew ) / τ e Vofinal
EE315B - Chapter 5
106
Noise Analysis
Cf
φ2
φ1 Cs
Gm CL
Noise due to switches
Noise due to amplifier and switches
EE315B - Chapter 5
B. Murmann
107
Tracking Phase (φ1)
C
•
Variable of interest is total integrated "noise charge" at node X, qx2
•
Cumbersome to compute using standard analysis – Find transfer function from each noise source (3 resistors) to qx – Integrate magnitude squared expressions from zero to infinity and add
•
Much easier – Use equipartition theorem
C V
X
B. Murmann
EE315B - Chapter 5
108
Tracking Phase Noise Charge •
Energy stored at node X is 1 q2x 1 q2x = 2 Ceff 2 Cs + Cf
C
•
C V
Apply equipartition theorem 1 q2x 1 = kT 2 Cs + C f 2
X
q2x = kT ( Cs + Cf )
•
Note that any additional parasitic capacitance at node X will increase the sampled noise charge!
EE315B - Chapter 5
B. Murmann
109
Redistribution Phase Noise 4kTRon ∆f α>1 excess noise factor
1 R≅ βGm 4kTRon1∆f
•
α
4kTγ ∆f Gm
In a proper design, Ron1 and Ron2 will be much smaller than 1/βGm, else the switches would significantly affect the dynamics, which would be very wasteful – It is much easier to design switches with low on-resistance than an amplifier with very large Gm
B. Murmann
EE315B - Chapter 5
110
Output Referred Noise Comparison 2
•
Ron1 noise referred to vo
C 2 N1 = 4kTRon1∆f ⋅ s ⋅ H( jω) Cf
•
Ron2 noise referred to vo
N2 = 4kTRon2 ∆f ⋅ H( jω)
Amplifier noise referred to vo
Na = α
2
2
•
C 4kTγ 2 ∆f ⋅ 1 + s ⋅ H( jω) Gm Cf
2
Cs 1 + Cf Na αγ = >> 1 N1 GmRon1 C 2 s Cf
•
2
Na αγ Cs = 1+ >> 1 N2 GmRon2 Cf
Amplifier noise dominates over noise due to Ron1, Ron2 EE315B - Chapter 5
B. Murmann
111
Total Integrated Amplifier Noise
1 βGm
R≅
α ⋅ 4kTγGm ⋅ ∆f v o2 1 1 = α ⋅ 4kTγ ⋅R ∆f βR jω CLtot v o2
B. Murmann
2
∞
1 R = ∫ α ⋅ 4kTγ ⋅ ∆f ⋅ βR 1 + jω RCLtot 0 EE315B - Chapter 5
2
df = αγ
1 kT β CLtot 112
Adding up the Noise Contributions φ2
φ1 q2x = kT ( Cs + Cf )
2 v o,1 =
Cs + C f kT = C2 C2f f q2x
kT Cs = 1 + C f Cf
2 v o,tot =
2 v o,2 ≅ αγ
1 kT β CLtot
kT Cs 1 kT 1 + + αγ Cf Cf β CLtot
EE315B - Chapter 5
B. Murmann
113
Noise in Differential Circuits •
In differential circuits, the noise power is doubled (because there are two half circuits contributing to the noise)
•
But, the signal power increases by 4x – Looks like a 3dB win? DRsingle
Vˆ 2 ∝ o kT C
DRdiff
2Vˆ ) ( ∝ o
2
kT C
2
=2
Vˆ o2 kT C
•
Yes, there’s a 3dB win in DR, but it comes at twice the power dissipation (due to two half circuits)
•
Can get the same DR/power in a single ended circuit by doubling all cap sizes and gm
B. Murmann
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114
Outline •
Elementary track-and-hold circuit and its nonidealities
•
First order improvements to elementary track-and-hold
•
Advanced techniques – Clock bootstrapping – Bottom plate sampling
•
Settling and noise analysis in charge-redistribution track-and-hold circuit
•
Noise simulation example
B. Murmann
EE315B - Chapter 5
115
SC Noise Simulation •
There are at least three ways to simulate noise in switched capacitor circuits
•
Basic .ac/.noise Spice simulations – Simulate noise in each clock phase separately • Activate φ1 switches, run .noise and integrate noise charge at relevant node over all frequencies and refer to output • Activate φ2 switches, run .noise and integrate noise over all frequencies at the output • Sum integrated noise from the two phases – This is analogous to the way we carried out the hand analysis
B. Murmann
EE315B - Chapter 5
116
SC Noise Simulation •
Periodic Steady State Simulation – First run PSS analysis to find the periodic operating point • Analogous to .op for .ac/noise – Next run PNOISE analysis • Computes total noise, taking all clock phases, noise aliasing, noise correlations, etc. into account
•
Transient Noise – Direct simulation of all noise sources using a transient simulation – Most physical way of simulating noise
EE315B - Chapter 5
B. Murmann
117
Example T/H Circuit •
Switches sized 5 times faster, i.e. N = 5∙10 = 50 Clp cl Clm cl
vic
vic
Cfm cf
p1
cs Csp
cs Csm
p1
voc vdd vocs
Cfp cf
vic
OTA Gm chosen such than (Ts/2) / τOTA = 10
vic
•
fs = 100 MHz, α = 2, γ = 1 Cs = Cf = 100 fF, CL = 500 fF, Cpar ≅ 0 B. Murmann
EE315B - Chapter 5
118
.Noise Simulation (f1) •
*** Compute noise charge at node X and refer to output via Cf
•
en vno 0 vcvs vol =( cs*v(x,s) + cf*v(x,f) )/cf
•
.ac dec 100 100 1000Gig
•
.noise v(vno) vdummy
(showing half circuit for simplicity)
EE315B - Chapter 5
B. Murmann
119
PSD [V2/Hz]
.Noise Simulation (φ1) 10 10 10
-15
-20
-25
Integral [uVrms]
10
B. Murmann
6
2
x 10
10
4
6
8
10 10 Frequency [Hz]
10
10
10
12
-4
406µVrms
4 2 0 2 10
10
4
6
8
10 10 Frequency [Hz]
EE315B - Chapter 5
10
10
10
12
120
PSD [V2/Hz]
.Noise Simulation (φ2) 10 10 10
-15
-20
-25
Integral [uVrms]
10
4
2
x 10
10
6
8
10 10 Frequency [Hz]
10
10
10
12
-4
266µVrms
2 0 2 10
10
2 v out,tot = B. Murmann
4
4
6
8
10 10 Frequency [Hz]
10
10
( 406µVrms )2 + ( 266µVrms )2
10
12
= 485µVrms
EE315B - Chapter 5
121
PSS Simulation Setup
Set “tstab” if your circuit needs time to reach steady state (e.g. clock bootstrap circuits) Under “options” set “maxacfreq” to the highest frequency from which you expect noise to fold down
B. Murmann
EE315B - Chapter 5
122
PSS Waveforms (Clocks) 4.75ns
B. Murmann
EE315B - Chapter 5
123
PNOISE Simulation Setup Numsidebands ≅ fmax/fs, where fmax is the maximum frequency from which you expect significant noise folding
“timedomain” means simulator computes spectrum of discrete time noise samples at the specified sampling instant
Sampling instant (4.75ns in this example)
B. Murmann
EE315B - Chapter 5
124
How to Chose Parameters • Maxacfreq must be set commensurate with the speed of the switches – Common pitfall: Use nice 1mΩ switches must consider noise from “DC to daylight” • In our example Maxacfreq ≅ 10 ⋅
1 10 = ⋅ N ⋅ fs 2πRonC π
Maxacfreq ≅ 3 ⋅ 50 ⋅ 100MHz = 15GHz
EE315B - Chapter 5
B. Murmann
125
How to Chose Parameters • In traditional PSS/PNOISE simulators (such as SpectreRF), simulation time increases rapidly for large values of Numsidebands • Berkeley Design Automation (BDA) Analog FastSPICE (AFS) automatically includes an infinite number of sidebands at significantly reduced simulation times
Numsidebands ≅
B. Murmann
Maxacfreq 15GHz = = 150 fs 100MHz
EE315B - Chapter 5
126
PNOISE Result (SpectreRF) Sampled Noise PSD
Integrated Noise
EE315B - Chapter 5
B. Murmann
127
Transient Noise Using BDA AFS •
Simulated 1000 samples
•
Only one critical setting: noisefmax = 15 GHz
B. Murmann
EE315B - Chapter 5
128
Comparison •
Very good agreement between hand calculation and all three simulation approaches
Method
φ1 Noise φ2 Noise Total Comment [µVrms] [µVrms] [µVrms]
Calculation
406
245
474
.NOISE
406
266
485
PNOISE
-
-
475
Somewhat smaller than .NOISE due to finite Maxacfreq and Numsidebands
TRAN NOISE
-
-
477
Somewhat smaller than .NOISE due to statistical fluctuations (can use more samples)
B. Murmann
Neglected switch noise during φ2 smaller value than .NOISE
EE315B - Chapter 5
129
Advantages of TRAN NOISE • Takes advantage of rapid advancements in very fast, spice-accurate transient simulators (such as BDA AFS) – Can handle much larger circuits compared to PSS/PNOISE (PSS tends to have convergence issues for large circuits) • Intuitive inspection of waveforms • No need to combine noises manually – Compared to .ac/.noise simulation flow • Applicable also to non-periodic circuits
B. Murmann
EE315B - Chapter 5
130
Further Reading on Noise •
Basics – B. Murmann, "Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques," IEEE Solid-State Circuits Magazine, vol. 4, no. 2, pp. 46-54, June 2012.
•
SC integrator noise analysis – R. Schreier, J. Silva, J. Steensgaard, and G.C. Temes, "Designoriented estimation of thermal noise in switched-capacitor circuits," IEEE TCAS1, vol.52, no.11, pp. 2358-2368, Nov. 2005.
•
Total integrated noise expressions for more complex OTAs (two-stage, etc.) – A. Dastgheib and B. Murmann, “Calculation of Total Integrated Noise in Analog Circuits,” IEEE TCAS1, vol. 55, no. 10, pp. 2988-2993, Oct. 2008.
•
Transient noise simulation example for a complete ADC – Lennart Mathe and David C. Lee, "Analog-to-Digital Converter Performance Signoff with Analog FastSPICE Transient Noise at Qualcomm," Berkeley Design Automation, www.berkeley-da.com.
B. Murmann
EE315B - Chapter 5
131
Summary – Sampling Circuits •
Three predominant implementation styles – Purely passive – Source follower T/H, up to ~9-10bit accuracy – Charge redistribution or flip-around architecture
•
In a typical, properly designed circuit only the most fundamental issues are significant – Jitter, kT/C noise
•
Charge injection is not a problem if properly handled – E.g., use bottom plate sampling
B. Murmann
EE315B - Chapter 5
132
Voltage Comparators
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
B. Murmann
EE315B - Chapter 6
1
Recap
•
Ultimately, building a quantizer requires circuit elements that "make decisions"
•
The most widely used "decision circuit" is a voltage comparator
B. Murmann
EE315B - Chapter 6
2
Preview - Flash ADC
2B-1
Dout
Vin 2B-1 Decision Levels
B. Murmann
EE315B - Chapter 6
3
Ideal Voltage Comparator
•
Function – Compare the instantaneous values of two analog voltages (e.g. an input signal and a reference voltage) and generate a digital 1 or 0 indicating the polarity of that difference – We essentially want to implement “infinite” gain
B. Murmann
EE315B - Chapter 6
4
How to Implement High Gain? •
Considerations – Amplification need not be linear – Amplification need not be continuous time if comparator is used in a sampled data system • Clock signal will tell comparator when to make a decision • We will focus on this case, since it is the predominant scenario
•
Implementation options to be looked at – Multi-stage amplification • E.g. cascade of resistively loaded differential pairs
– Regenerative latch using positive feedback • E.g. cross coupled inverters
EE315B - Chapter 6
B. Murmann
5
Input Signal Scenarios Sampled Data Input
Our focus
φ2
Continuous Time Input
B. Murmann
EE315B - Chapter 6
6
Cascade of Open-Loop Amplifiers
In each stage:
•
ωu =
gm ≅ const. Cgs
A 0 = gmR =
ωu ω0
ω0 =
ω 1 = u RC A 0
What is the best choice for a given gain requirement? – Single stage with lots of voltage gain (OTA)? – Only a few stages with moderate gain? – Lots of stages with low gain? EE315B - Chapter 6
B. Murmann
7
Step Response (1) •
When the input is a sampled data signal, we want to achieve the fastest possible amplification in response to an input step
Vout (s) = Vin (s)A(s) =
Vistep s
Av N
(1+ s ⋅ τ A ) 1/N
u
v
τu =
1 ωu
A v = AN 0
i t t − 1/N 1/N N −1 τ ⋅ A Vout (t) = Vistep A v 1 − e τu ⋅ A v ∑ u v i! i=0
A(t) B. Murmann
EE315B - Chapter 6
8
Step Response (2) 10
Step response A(t)
8
τd(N=3) 10(1-e-1)
6 4
N=1 N=3 N=5
2
Av*(1-e-1)
0 0
5
10
15
Time t/τu
•
Three stage amplifier wins! (for Av=10) EE315B - Chapter 6
B. Murmann
9
Delay versus Number of Stages
(
A( τd ) = A v 1 − e−1
)
⇒ τd
(numerically)
50 Av=10 Av=100 Av=1000
Delay time τd/τu
40
30
20
10
0
• •
2
4
6 8 10 N (Number of stages)
12
14
Using a single stage is a non-starter The optimum number of stages show a shallow minimum
B. Murmann
EE315B - Chapter 6
10
Optimum Number of Stages
Optimum number of stages
12 Numerical result ln(Av)
10 8 6 4 2 0 0 10
10
1
2
10 10 Av (Total gain)
3
10
4
10
5
Nopt ≅ ln(A v )
EE315B - Chapter 6
B. Murmann
11
Optimum Gain per Stage A0,opt (Optimum gain per stage)
5
4 3.5 3 2.5 2 1.5 1 0 10
Nopt ≅ ln(A v )
B. Murmann
Numerical result e
4.5
10
1
2
10 10 Av (Total gain) Nopt
e
3
≅ A v = A 0,opt
EE315B - Chapter 6
10
Nopt
4
10
5
⇒ A 0,opt ≅ e
12
Cascade of "Integrators" (1)
•
Intuition – Load resistors (in a cascade of open-loop amplifiers) shunt current away from load capacitance; this slows down amplification
•
Analysis using integrator stages
ω g v o1 = m vin = u vin sC s
v oN =
ωN u sN
vin
EE315B - Chapter 6
B. Murmann
13
Cascade of Integrators (2) Vistep ωN u N s s
Vout (t) = Vistep ⋅ ωN u
10
10
8
8 Step response A(t)
Step response A(t)
Vout (s) =
6
4 N=1 (with R) N=1 (integ)
2
6
4 N=3 (with R) N=3 (integ)
2
Av*(1-e-1) 0 0
B. Murmann
5
10 Time t/τu
tN N!
Av*(1-e-1) 15
0 0
EE315B - Chapter 6
5
10 Time t/τu
15
14
Cascade of Integrators (3) •
Cascade of integrators achieves faster amplification than cascade of resistively loaded stages
•
Delay time 1/N
τd = τu [(N!⋅ A( τd ))]
•
A( τd ) =
Vout ( τd ) Vinstep
Optimum number of stages approximately given by Nopt = 1.1ln [ A( τd )] + 0.79
•
[Wu, JSSC 12/1988]
Effective gain per stage is still relatively close to e=2.7183…
EE315B - Chapter 6
B. Murmann
15
Regenerative Sense Amplifier (Latch) Conceptual Circuit
t=0
Inverter Transconductance
[Figueiredo]
⋅ /
φ1: Set up initial condition (vOD0) φ2: Enable positive feedback B. Murmann
EE315B - Chapter 6
/
16
Simulation Example I4
I7
vdm vp ideal_balun vcm vm
vic
vip
vop
vim
vom
vp
vdm ideal_balun vm vcm
p2!
vid
M0 10u/0.18u
vod voc
M4 10u/0.18u p1!
vip
C3 cl
vid
vdc:vdd vdc:vic
M1 5u/0.18u
M3 5u/0.18u
C0 cl
V5 vdc:vid
B. Murmann
CL=100 fF
p2!
vic
V2
vop
p1 p1b p1e p1eb p2 p2b p2e clock_gen
p1!
vdd
V0
vim
vom
p1!
p2!
EE315B - Chapter 6
17
Transient Response Nodes vOP and vON for differential inputs of 1mV, 1µV, 1nV and 1pV
φ2 goes high
B. Murmann
EE315B - Chapter 6
18
Transient Response Differential Mode
Common Mode
EE315B - Chapter 6
B. Murmann
19
Transient Response (Log Scale)
= ⋅ భ/ = ⋅ మ/
B. Murmann
=
600ps 600ps − = = = 43
ln 10 6 ⋅ 2.3 ln
EE315B - Chapter 6
20
Comparison 10
Amplification A(t)
8
6
4 N=3 (with R) N=3 (integ) Latch
2
Av*(1-e-1)
0 0
•
5
t/τ t/τ Time
10
15
Latch is much faster than cascade of amplifiers/integrators
EE315B - Chapter 6
B. Murmann
21
Latch Gain
B. Murmann
A(τd)
τd/τ
10
2.3
100
4.6
1,000
6.9
10,000
9.2
EE315B - Chapter 6
22
"The" Architecture
•
Why bother using pre-amplification (Av)?
•
Pre-amplification may be used for several reasons – Lower offset (latch offset tends to be large) – Lower thermal noise – Attenuation of "kickback noise” – Separate input from output – Common mode rejection
B. Murmann
EE315B - Chapter 6
23
Basic Topology Examples (1) •
Class-A (constant current)
Figure from [Figueiredo, TCAS2, July 2006] B. Murmann
EE315B - Chapter 6
24
Basic Topology Examples (2) •
Class-AB – Input pair has constant bias, but latch draws current only while making a decision
Figure from [Figueiredo, TCAS2, July 2006]
B. Murmann
EE315B - Chapter 6
25
Basic Topology Examples (3) •
Fully dynamic – Draws (significant) current only while making a decision
Original paper: [Kobayashi, JSSC, April 1993]
Figure from [Figueiredo, TCAS2, July 2006]
B. Murmann
EE315B - Chapter 6
26
Offset in Latches vOP
vON
VOS,static
Inverter switching voltage: VS Initial common mode: VOC0
CLP
CLN
Load capacitor mismatch: ∆CL
•
Static offset (VOS) due to transistor mismatch (primarily Vt)
•
Dynamic offset due to load capacitor mismatch – For an analysis see Nikoozadeh, TCAS II, Dec. 2006 , ≅
1 Δ − 2
Example:
1 10 0.3 − 0.9 = 30 2 100
Minimize, if possible
EE315B - Chapter 6
B. Murmann
27
Input Referred Offset with Preamplification
σ2VOS = σ2VOS1 +
•
1 A 2v
σ2VOS2
Example: σVOS1=3mV, σVOS2=30mV, Av=10 σ VOS =
B. Murmann
( 3mV )2 +
1 10
2
( 30mV )2
EE315B - Chapter 6
= 4.2mV
28
Dealing With Offset •
Options depend strongly on the application context
•
May use an ADC architecture that inherently tolerates offset – More later
•
May use a relatively coarse tuning mechanism – E.g. tune offset to lie within ½ LSB at the 6-bit level
•
May have to apply precision techniques – Autozeroing, etc. (see EE315A), for high-end instrumentation
•
Simply use large transistors – Usually not power efficient
B. Murmann
EE315B - Chapter 6
29
Example: Coarse Offset Tuning •
The circuit below uses capacitve imbalance to tune the offset – An example of using a "bug" as a feature – See e.g. Van der Plas, ISSCC 2006
•
Watch out for PSRR degradation due to circuit imbalance
B. Murmann
EE315B - Chapter 6
30
Example: Precision Comparator [http://www.elecdesign.com/Articles/Index.cfm?ArticleID=3956]
• •
Used in the AD7671, 16-bit, 1-MS/s successive approximation ADC Uses cascaded output series offset cancellation (see EE315A)
B. Murmann
EE315B - Chapter 6
31
Electronic Noise in Latch Comparators •
Class-A topology – Integrate noise at regenerative node over all frequencies and refer to the input α·kT/CL – See Opris, Electronics Letters, July 1997
•
Dynamic topology – Very hard to analyze due to the time variant behavior – See Nuzzo, IEEE TCAS1, July 2008 – Fortunately, the end result is not too far from class-A-like noise estimation in the decision point α·kT/CL
B. Murmann
EE315B - Chapter 6
32
Kickback
E.g. Flash ADC resistor ladder
Figure from [Figueiredo, TCAS2, July 2006]
EE315B - Chapter 6
B. Murmann
33
Kickback Mitigation Techniques Neutralization
Neutralization and Switch Isolation
Figures from [Figueiredo, TCAS2, July 2006]
B. Murmann
EE315B - Chapter 6
34
Kickback Mitigation Techniques
Extra switches act similar to cascodes
[Sundstrom, MIXDES 2007]
B. Murmann
EE315B - Chapter 6
35
Other Design Considerations •
Input capacitance and linearity of input capacitance – Consider e.g. loading of the input network in a flash ADC
•
Overdrive recovery – Consider a very large input, followed by a very small input of opposite polarity
•
Metastability – What if the input is so small that the comparator cannot decide in the given amount of time?
B. Murmann
EE315B - Chapter 6
36
Overdrive Recovery Test Latch activation 1
2
Comparator input
Preamp output
•
[Razavi, p. 183]
The test is passed when the latch output changes polarity in case 1, but not in case 2 EE315B - Chapter 6
B. Murmann
37
Metastability (1) •
The plot below shows the time needed to regenerate a given differential latch input to full logic swing 35 30
treg/τ
25
ݐ ܸ = ln ݒை ߬
20 15 10 5 0 -15 10
10
-10
10
-5
10
0
v
vOD0/V/VDD
B. Murmann
EE315B - Chapter 6
38
Metastability (2) •
What if the input is so small that we run out of time?
•
This is called a metastable state, i.e. at the end of the clock cycle there is no clear logic decision
•
The following logic gates will go into an erratic state that is hard to predict, and so we classify this outcome as an error
•
In the following analysis we will try to estimate the probability at which metastable states will occur
•
Application requirements vary widely – Error correction coding in certain communication sytems can absorb probabilities of up to 10-3 – High-speed wireline links (without coding) or instrumentation equipment may require probabilities better than 10-18
EE315B - Chapter 6
B. Murmann
39
Metastability (3) •
Assume that the maximum available time is tmax
•
The minum latch input we can regenerate is then , =
•
In case, we have a preamp, we can do slightly better , =
•
ೌೣ / 1 ೌೣ /
Now assume that the input is uniformly distributed over some range, and compute the probabily of seeing a metastable state PDF
, ೌೣ / = = , ,
-vID0,max +vID0,max -vID0,min +vID0,min B. Murmann
EE315B - Chapter 6
40
Mean Time to Failure •
In some applications it makes sense to think about metastability in terms of the mean time between metastable events – Mean time to failure (MTF)
2
MTF [days]
10
=
1 ⋅
0
10
fs=10GHz
fs=100MHz
-2
10
-18
10
-16
10
-14
10
-12
10
-10
10
Pmeta
EE315B - Chapter 6
B. Murmann
41
Example: Flash ADC •
In a flash ADC, there is always (exactly) one comparator that sees an input within ± ∆/2
•
The probability of seeing a metastable state within the array is therefore found using vID0,max = ∆/2 =
•
ೌೣ / ೌೣ / = 1 V Δ 2 2 2
The graph on the next slide plots an example – Sampling rate fs = 1GHz, tmax ≅ 1/2fs = 500ps – B = 6, Av =1, VFS = VDD
B. Murmann
EE315B - Chapter 6
42
Example: Flash ADC 0
10
-5
Pmeta
10
-10
10
-15
10
-20
10
10
• •
20
30
40 50 τ [ps]
60
70
80
The curve is incredibly steep in the region of Pmeta < 10-5 Very strong incentive to minimize τ as much as possible – Ultimitaley bounded by Cgg/gm = 1/ωT
B. Murmann
EE315B - Chapter 6
43
Metastability Detectors? • •
•
Why not build a clever logic circuit that detects the metastable state and overrides it with a valid logic state? This sounds good, but is difficult to do in reality – Logic gates look like "low pass filters" compared to a latch – A latch provides the maximum possible gain per unit of time; any gate delay added after the latch (that eats into the regeneration time) is counterproductive Most (if not all) metastability detector ideas proposed in literature tend to create new metastable states – Related article: R. Ginosar, "Fourteen ways to fool your synchronizer," 2003
B. Murmann
EE315B - Chapter 6
44
Comparator Examples (1) •
Mehr & Dalton, JSSC 7/1999
B. Murmann
EE315B - Chapter 6
45
Comparator Examples (2) •
Mehr & Dalton, JSSC 7/1999
B. Murmann
EE315B - Chapter 6
46
Comparator Examples (3) •
Schinkel, ISSCC 2007: "Double tail sense amplifier"
EE315B - Chapter 6
B. Murmann
47
Comparator Examples (4) •
Miyahara, ASSCC 2009
B. Murmann
EE315B - Chapter 6
48
Comparator Examples (5) •
Lee, JSSC, April 2011
EE315B - Chapter 6
B. Murmann
49
Comparator Examples (6) •
Tripathi, ESSCIRC 2013
τ ≅ 6ps
B. Murmann
EE315B - Chapter 6
50
Selected References (1) 1. Y. S. Yee, L. M. Terman and L. G. Heller, “A 1mV MOS Comparator,” IEEE J. of Solid-State Circuits, vol. SC-13, pp. 294-297, June 1978. 2. A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” IEEE J. of Solid-State Circuits, vol. SC-20, pp. 775-779, June 1985. 3. B. J. McCarroll, C. G. Sodini, and H.-S. Lee, “A High-Speed CMOS Comparator for Use in an ADC,” IEEE J. of Solid-State Circuits, vol. 23, pp. 159-165, Feb. 1988. 4. J.-T. Wu and B. A. Wooley, “A 100-MHz Pipelined CMOS Comparator,” IEEE J. SolidState Circuits, vol. 23, pp. 1379-1385, Dec. 1988. 5. B. Razavi and B. A. Wooley, “A 12-b 5-MSample/s Two-Step CMOS A/D Converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 1667-1678, Dec. 1992. 6. B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, pp. 1916-1926, Dec. 1992. 9.
M. Choi and A. A. Abidi, "A 6-b 1.3-GSample/s A/D converter in 0.35-µm CMOS," IEEE J. Solid-State Circuits, pp. 1847-1858, Dec. 2001.
10. I. Mehr and D. Dalton, "A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive readchannel applications," IEEE J. Solid-State Circuits, pp. 912-920, July 1999. 11. I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-MSample/s Nyquist-Rate CMOS ADC,” IEEE J. Solid-State Circuits, pp. 318-25, March 2000. 12. G.R. Couranz, and D.F. Wann, "Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region," IEEE Trans. Computers, vol. C24, no.6, pp. 604-616, June 1975. B. Murmann
EE315B - Chapter 6
51
Selected References (2) 9.
H. J. M. Veendrick, “The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate,” IEEE J. Solid-State Circuits, April 1980.
10. B. Zojer, et al., “A 6-bit/200-MHz full Nyquist A/D converter,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 780-786, June 1985. 11. K.-L.J. Wong and C.-K.K. Yang, "Offset compensation in comparators with minimum input-referred supply noise," IEEE J. Solid-State Circuits, pp. 837-840, May 2004. 12. A. Graupner, "A Methodology for the Offset-Simulation of Comparators," http://www.designers-guide.org/Analysis/comparator.pdf. 13. D. Schinkel et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," ISSCC Dig. Techn. Papers, pp. 314-315, 2007. 14. P.P. Nuzzo, et al., "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures, IEEE Trans. Circuits Syst. I, pp.1441-1454, July 2008. 15. B.S. Leibowitz, et al., "Characterization of Random Decision Errors in Clocked Comparators," Proc. IEEE CICC, pp.691-694, Sep. 2008. 16. Analog Devices, "Find Those Elusive ADC Sparkle Codes and Metastable States" http://www.analog.com/en/content/0,2886,760%255F788%255F91218,00.html 19. M. Miyahara and A. Matsuzawa, "A low-offset latched comparator using zero-static power dynamic offset cancellation technique," ASSC, pp. 233-236, Nov. 2008. 20. P.M. Figueiredo, "Comparator Metastability in the Presence of Noise," IEEE TCAS1, vol. 60, no. 5, pp.1286-1299, May 2013.
B. Murmann
EE315B - Chapter 6
52
Flash ADCs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 7
B. Murmann
1
Nyquist ADC Architectures •
Nyquist rate – Word-at-a-time • Flash ADC • Instantaneous comparison with 2B-1 reference levels
– Multi-step • E.g. pipeline ADCs • Coarse conversion, followed by fine conversion of residuum
– Bit-at-a-time • E.g. successive approximation ADCs • Conversion via a binary search algorithm
SPEED
– Level-at-a-time • E.g. single or dual slope ADCs • Input is converted by measuring the time it takes to charge/discharge a capacitor from/to input voltage B. Murmann
EE315B - Chapter 7
2
ADC Survey (ISSCC & VLSI 1997-2013) Data: http://www.stanford.edu/~murmann/adcsurvey.html
10
Flash Folding Two-Step Pipeline
10
10
SAR Other 1000fs
in,hf
[Hz]
∆Σ 8
f
100fs 10
10
rms
rms
Jitter
Jitter
6
4
20
30
40
50
60
70 80 SNDR [dB]
90
100
110
120
hf
EE315B - Chapter 7
B. Murmann
3
Flash ADC Speed 7
Clock Speed [GHz]
6
Flash ADCs Microprocessors
5 4 3 2 1 0 1996
1998
2000
2002
2004
2006
2008
Year B. Murmann
EE315B - Chapter 7
4
Modern Flash ADC Architecture Vadc
Vadc Dout
T/H
•
Fast – Speed limited only by comparator decision High complexity, large input capacitance – Resolution tends to limited to 6 bits
•
B. Murmann
Wallace Encoder
CLK
Vin
Usually implemented as a fully differential circuit
EE315B - Chapter 7
5
Why Use a T/H? •
One reason: Timing offsets between comparators may cause “bubbles” in the thermometer code
Single bubble Double bubble Fast moving input
K. Uyttenhove, M.S.J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS," JSSC, pp. 1115-1122, July 2003.
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EE315B - Chapter 7
6
Bubble Problem in a “Poor Man’s” Encoder
e.g. due to timing offset between two comparators
•
Correct output: 1000, actual output: 1110 (!)
B. Murmann
EE315B - Chapter 7
7
Bubble Tolerant Encoder
•
Protects against single bubbles
•
Reference: C. W. Mangelsdorf, “A 400-MHz Flash Converter with Error Correction,” IEEE J. Solid-State Circuits, pp. 184-191, Feb. 1990.
B. Murmann
EE315B - Chapter 7
8
Modern Solution: Wallace Encoder
B. Murmann
•
Simply a “ones adder”
•
F. Kaess, et al., “New encoding scheme for high-speed flash ADCs,” ISCAS 1997, pp. 5–8
•
Complexity used to be an issue in older technology; not a problem in sub-100nm CMOS
•
Number of adders needed for N bits:
EE315B - Chapter 7
9
Alternative (or Additional) Solution •
Still want to use a T/H, even if bubbles are not a problem – Simplified comparator design – Well-behaved input impedance – T/H need not be all that complex
Source follower T/H
Y. Tamba, and K. Yamakido, "A CMOS 6 b 500 MS/s ADC for a hard disk drive read channel,“ ISSCC 1999, pp. 324-325 B. Murmann
EE315B - Chapter 7
10
How about Metastability?
• • •
Different gates interpret metastable output X differently Correct output: 0111 or 1000, actual output: 1111 (!) Again, a simple encoder does not handle this very well
B. Murmann
EE315B - Chapter 7
11
Solution 1: Wallace Encoder
B. Murmann
•
Similar reasoning as with bubbles
•
Error due to metastable input is bounded by 1LSB
EE315B - Chapter 7
12
Solution 2: Latch Pipelining
• •
Use additional latches to create extra gain before generating decoder signals Usually too power hungry and area inefficient EE315B - Chapter 7
B. Murmann
13
Solution 2: Gray Encoding Thermometer Code
Gray
T1
T2
T3
T4
T5
T6
T7
G3
G2
G1
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
• G3
B. Murmann
Binary
G2
G1
EE315B - Chapter 7
Each Ti affects only one Gi – Avoids disagreement of interpretation by multiple gates
14
Efficient Implementation
•
Reference – C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,” IEEE J. Solid-State Circuits, pp. 1132-40 , Aug. 1996.
EE315B - Chapter 7
B. Murmann
15
Offset •
Typically want offset of each comparator = 0.18µm 2.8mV 2.8mV
B. Murmann
EE315B - Chapter 7
16
Re-cap of Options •
Simply use large devices – For each extra bit, need to increase width by 4x, also need to double number of comparators – Assuming constant current density, this means each additional bit costs 8x in power!
•
Dynamic offset cancellation (autozeroing, etc.) – Tends to cost speed
•
More commonly used – Offset averaging – Offset calibration – Incorporation of redundant comparators
B. Murmann
EE315B - Chapter 7
17
Offset Averaging (1)
R2/R1=1.3
[Kattmann & Barrow, ISSCC 1991] B. Murmann
EE315B - Chapter 7
18
σDNL/σ
Offset Averaging (2)
[Bult & Buchwald, JSSC 12/1997]
[Scholtens & Vertregt, JSSC 12/2002] B. Murmann
EE315B - Chapter 7
19
6-bit Flash ADC with Averaging [Choi & Abidi, JSSC 12/2001]
Averaging networks designed to reduce input referred offset by 3x
B. Murmann
EE315B - Chapter 7
20
Offset Calibration Using Global DAC
S. Sutardja, "360 Mb/s (400 MHz) 1.1 W 0.35μm CMOS PRML read channels with 6 burst 8-20× over-sampling digital servo," ISSCC Dig. Techn. Papers, Feb. 1999. EE315B - Chapter 7
B. Murmann
21
Calibration Using one DAC per Comparator
(Reset switches not shown) 8
Voutn
Voutp
φ Dcalp
CAL
Vlo Vhi
Vrefn
8
8
4
2
1
MUX/Encoder
φ
Vinp
Vinn
φ
Vrefp
CAL
Dcaln
Vlo Vhi
[M. El-Chammas, VLSI 2010]
B. Murmann
EE315B - Chapter 7
22
Offset Calibration at Start-Up
•
Out RefIn-
INC/ DEC
Start-up calibration is reasonably stable at flash ADC resolutions The correction circuit shown on the previous slide has a relatively low temperature dependence
AVG
Control Bits
Out
•
Output oscillates between one and zero as the input-referred offset converges to zero
t
Input-referred Offset
•
In+ Ref+
Offset = 0 t
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EE315B - Chapter 7
23
Tuning Range Issue (1) •
Ideally, the trim-DAC must bring the offset well within one LSB of the flash ADC
•
The required trim-DAC resolution can become unacceptably large if near minimum-size transistors (with large Vt mismatch) in the latest technology are used
•
A clever workaround is to utilize the error correction capability of the Wallace tree encoder (ones counter)
B. Murmann
EE315B - Chapter 7
24
Tuning Range Issue (2) [Verma, ISSCC 2013]
+ Vref0
0
-
Vref0 (eff)
+ Vref1
1
+
Vref2
2
-
Vref2 (eff)
+ Vref3
-
Vref1 (eff)
3 Vref3 (eff)
EE315B - Chapter 7
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25
Ones Counting is Equivalent to Reordering + Vref0
-
[Verma, ISSCC 2013]
2 Vref0 (eff)
+ Vref1
+
Vref2
+
Vref3
-
0
Vref1 (eff)
1 Vref2 (eff)
3 Vref3 (eff)
Reduced tuning range B. Murmann
EE315B - Chapter 7
26
Comparator Redundancy (1) •
Interesting idea: Do not worry about offsets at all, just provide enough levels that properly add up on average 90mW
900mW
Wallace Encoder
Paulus et al., "A 4GS/s 6b flash ADC in 0.13um CMOS," VLSI Circuits Symposium, 2004 B. Murmann
EE315B - Chapter 7
27
Comparator Redundancy (2) •
Another idea: Build a "sea of imprecise comparators", then determine which ones to use…
C. Donovan, M. P Flynn, "A 'digital' 6-bit ADC in 0.25-μm CMOS," IEEE J. Solid-State Circuits, pp. 432-437, March 2002. B. Murmann
EE315B - Chapter 7
28
Differential Pair Redundancy •
Idea: Have multiple input pairs and use the one you like [Chen, VLSI 2013]
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EE315B - Chapter 7
29
Details
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EE315B - Chapter 7
30
Performance Comparison [Chen, VLSI 2013]
B. Murmann
EE315B - Chapter 7
31
Calibration Using Reference String
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006] B. Murmann
EE315B - Chapter 7
32
Details
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006] B. Murmann
EE315B - Chapter 7
33
Measured Results
[Park & Flynn, "A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS," CICC 2006] B. Murmann
EE315B - Chapter 7
34
Reducing Complexity •
Even with calibration, flash ADCs tend to hit a “wall” beyond 6 bits of resolution – Large calibration range – Large input capacitance – Complex encoder
•
Several techniques have been developed to “ease the pain” and potentially allow going beyond 6 bits (at the cost of some speed) – Interpolation – Folding, folding & interpolation – Subranging
EE315B - Chapter 7
B. Murmann
35
Interpolation •
Idea – Interpolation between preamp outputs
•
Reduces number of preamps – Reduced input capacitance – Reduced area, power dissipation
•
Same number of latches
•
Important “side-benefit” – Decreased sensitivity to preamp offset • Improved DNL
B. Murmann
EE315B - Chapter 7
36
Concept
[van de Plassche, p.118]
B. Murmann
EE315B - Chapter 7
37
Differential Implementation
VA + VB =0 2
B. Murmann
EE315B - Chapter 7
⇔ VA = −VB
38
Higher Order Interpolation • Resistors produce additional levels • Define interpolation factor as ratio ratio of latches and preamps • The example shown on this slide has M=8
[H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” IEEE J. of Solid-State Circuits, pp. 438-446, April 1993.
B. Murmann
EE315B - Chapter 7
39
Potential Issues with Interpolation •
Must ensure that "linear range" of adjacent preamplifiers overlaps – Sets upper bound on preamp gain
•
Resistor string reduces signal path bandwidth – Sets upper bound on interpolation factor, typically around 4
•
For interpolation factors >2, amplifier nonlinearity can limit the precision of zero crossings – See e.g. Van de Plassche, p.121
B. Murmann
EE315B - Chapter 7
40
Folding
MSB ADC
VIN
Digital Output LSB ADC Folding Circuit
• Main idea: Re-use comparator several times across the full scale range
B. Murmann
EE315B - Chapter 7
41
Simplest Variant [Verbruggen, JSSC, March 2009]
Folding circuit
B. Murmann
EE315B - Chapter 7
42
Creating Multiple Folds
•
Parameter K sets output common mode EE315B - Chapter 7
B. Murmann
43
Folder Output
Folder Output
0.5
Accurate only at zero-crossings
Ideal Folder CMOS Folder
0
-0.5 0
0.5
1
1.5
2
2.5
3
3.5
4
Lowdown
0.1
Most folding ADCs do not actually use the folds, but only the zero-crossings!
Error
0.05 0 -0.05 -0.1 0
0.5
B. Murmann
1
1.5
2 Vin / ∆
2.5
3
3.5
EE315B - Chapter 7
4
44
Multiple Folds Using Only Zero Crossings
B. Murmann
•
Way too complex, need one folder per decision in the fine ADC
•
Idea – Use interpolation to eliminate some of the folders
EE315B - Chapter 7
45
Interpolation
•
Same idea as discussed previously
B. Murmann
EE315B - Chapter 7
46
Complete Folding & Interpolating ADC
B. Murmann
EE315B - Chapter 7
•
3-bit coarse ADC
•
3-bit fine ADC – 2 folders with 4x interpolation 8 levels
•
We have therefore built a 6-bit ADC with only 16 comparators (instead of 63)
47
8-bit, 70 MS/s Folding and Interpolating ADC
[B. Nauta and G. Venes, JSSC. Dec. 1985]
B. Murmann
EE315B - Chapter 7
48
8-bit, 1.6 GS/s Folding and Interpolating ADC
[Taft et al., JSSC 12/2004]
B. Murmann
EE315B - Chapter 7
49
8b, 10GS/s Folding and Interpolating ADC
[Landolt, PRIME 2012] For Rohde & Schwarz Scope 0.25um SiGe BiCMOS 9 Watts
B. Murmann
EE315B - Chapter 7
50
Performance
EE315B - Chapter 7
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51
Subranging 4-bit Flash ADC
B. Murmann
2+2-bit Subranging ADC
EE315B - Chapter 7
52
8-bit, 1 GS/s Subranging ADC
Coarse ADC selects tap range for fine ADC [Chung, VLSI 2011] B. Murmann
EE315B - Chapter 7
53
Summary ― Flash ADCs & Extensions •
Today, flash ADC design boils down to an effective offset management approach – Calibration and/or redundancy
•
Extensions such as averaging, folding, interpolation and subranging can be used to alleviate the tradeoffs – But these techniques haven’t been popular in recent years – The reason may be the strong competition from pipelined and time interleaved architectures – More later…
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Selected References (1) Flash ADCs, Offset Averaging 1. K. Kattmann and J. Barrow, "A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters," ISSCC Digest of Technical Papers, pp. 170-171, Feb. 1991. 2. K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1mm2," IEEE J. of Solid-State Ckts., pp. 1887-1895, Dec. 1997. 3. M. Choi and A. A. Abidi, “A 6 b 1.3 Gsample/s A/D converter in 0.35µm CMOS,” IEEE J. Solid-State Circuits, pp. 1847–1858, Dec. 2001. 4. C. S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18-µm CMOS Using Averaging Termination,” IEEE J. of Solid-State Ckts., vol. 37, pp. 1599-1609, Dec. 2002. 5. X. Jiang, M-C. F. Chang, "A 1-GHz signal bandwidth 6-bit CMOS ADC with powerefficient averaging," IEEE J. of Solid-State Circuits, pp. 532- 535, Feb. 2005. Folding and Interpolating A/D Converters 6. R.C. Taft et al., "A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency," IEEE J. Solid-State Ckts., pp. 2107-2115 Dec. 2004. 7. B. Nauta and A. G. W. Venes, “A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter,” IEEE J. of Solid-State Circuits, pp. 1302-1308, Dec. 1995. B. Murmann
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Selected References (2) 8. 9.
10.
11. 12. 13. 14. 15. 16.
M. P. Flynn and B. Sheahan, “A 400-MSample/s, 6-b CMOS Folding and Interpolating ADC,” IEEE J. of Solid-State Circuits, pp. 1932-1938, Dec. 1998. H. Pan, M. Segami, M. Choi, J. Cao, F. Hatori and A. Abidi, “A 3.3V, 12b, 50MSample/s A/D converter in 0.6mm CMOS with over 80dB SFDR,” ISSCC Digest of Technical Papers, pp. 40-41, Feb. 2000. M.-J. Choe, B.-S. Song and K. Bacrania, “A 13b 40MSample/s CMOS pipelined folding ADC with background offset trimming,” ISSCC Digest of Technical Papers, pp. 36-37, Feb. 2000. G. Hoogzaad and R. Roovers, “A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2,” IEEE J. Solid-State Circuits, pp. 1796-1802, Dec. 1999. K. Nagaraj, F. Chen, T. Le and T. R. Viswanathan, “Efficient 6-bit A/D converter using a 1-bit folding front end,” IEEE J. Solid-State Circuits, pp. 1056-1062, Aug. 1999. M.-J. Choe and B.-S. Song, “An 8b 100MSample/s CMOS pipelined folding ADC,” VLSI Symposium Digest of Technical Papers, pp. 81-82, Jun. 1999. K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1 mm2,” IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997. P. Vorenkamp and R. Roovers, “A 12-b, 60-MSample/s cascaded folding and interpolating ADC,” IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997. A. G. W. Venes and R. J. van de Plassche, “An 80-MHz, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing,” IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.
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Selected References (3) 17. M. P. Flynn and D. J. Allstot, “CMOS folding A/D converters with current-mode interpolation,” IEEE J. Solid-State Circuits, vol. 31, pp. 1248-1257, Dec. 1996. 18. R. Roovers and M. S. J. Steyaert, “A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 31, pp. 938-944, Jul. 1996. 19. W. T. Colleran and A. A. Abidi, “A 10-b, 75-MHz two-stage pipelined bipolar A/D converter,” IEEE J. Solid-State Circuits, vol. 28, pp. 1187-1199, Dec. 1993. 20. J. van Valburg and R. J. van de Plassche, “An 8-b 650-MHz folding ADC,” IEEE J. Solid-State Circuits, vol. 27, pp. 1662-1666, Dec. 1992. 21. R. J. van de Plassche and P. Baltus, “An 8-bit 100-MHz full-Nyquist analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, Dec. 1988. 22. R. E. J. Van de Grift, I. W. J. M. Rutten and M. van der Veen, “An 8-bit video ADC incorporating folding and interpolation techniques,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 944-953, Dec. 1987. 23. R. E. J. van de Grift and R. J. van de Plassche, “A monolithic 8-bit video A/D converter,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 374-378, Jun. 1984. 24. R.C. Taft, et al., "A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency," ISSCC Digest of Technical Papers, pp.78-79, 79a, Feb. 2009.
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EE315B - Chapter 7
57
SAR ADCs
Boris Murmann Stanford University
[email protected] Copyright © 2013 by Boris Murmann
EE315B - Chapter 8
B. Murmann
1
Similarity Between Non-Flash ADC Architectures ε
Vin
Σ
Minimize
D/A
•
Dout
Most ADC architectures (other than flash) are based on minimizing the error between input and a D/A signal approximation – SAR ADC uses comparator to sense ε – Sigma-delta ADC minimizes ε via integration and feedback – Pipeline uses distributed DAC
B. Murmann
2
Successive Approximation Register ADC
•
Binary search over DAC output
•
High accuracy achievable (16+ Bits) – Relies on highly accurate comparator
•
Moderate speed (1+ MHz)
B. Murmann
EE315B - Chapter 8
3
High Performance Example
B. Murmann
EE315B - Chapter 8
4
Low Power Example
M.D. Scott, B.E. Boser, K.S.J. Pister, "An ultralow-energy ADC for Smart Dust," IEEE J. Solid-State Circuits, pp. 1123 -1129, July 2003. EE315B - Chapter 8
B. Murmann
5
Classical Implementation •
See e.g. [McCreary, JSSC 12/1975]
Bottom plate sampling
B
B
C1A = C1B = C B. Murmann
C2 = 2C
C3 = 4C
EE315B - Chapter 8
CB = 2B −1C 6
Sampling Phase (5-bit Example)
•
Total charge at node Vx after opening Sx Q = −Vin ⋅ 32C = −Vin ⋅ Ctotal
B. Murmann
EE315B - Chapter 8
7
Bit5 Test (MSB)
(
Q = −Vin ⋅ Ctotal = (Vx − Vref ) ⋅ 16C + Vx ⋅ 16C + Cp
)
Ctotal 1 ∴Vx = Vref − Vin ⋅ 2 Ctotal + Cp
•
Vx0.5Vref ⇒ Bit5=1
•
Vx>0 ⇒ Vin0 ⇒ Vin>1 at low frequencies – Means that NTF is 60dB
B. Murmann
EE315B - Chapter 12
10
Energy by Architecture 10
P/f s [J]
10
10
10
-6
-8
-10
Flash Pipeline SAR ∆Σ Other
-12
20
B. Murmann
30
40
50
60 SNDR [dB]
EE315B - Chapter 12
70
80
90
100
11
Flash ADC
Ecomp
B. Murmann
Eenc
EE315B - Chapter 12
12
Encoder • Assume a Wallace encoder (“ones counter”) • Uses ~2B–B full adders, equivalent to ~ 5∙(2B–B) gates
(
)
Eenc ≅ 5 ⋅ 2B − B ⋅ Egate
EE315B - Chapter 12
B. Murmann
13
Matching-Limited Comparator
Cc
Cc
C A 2VT = A 2VT c WL Cox
Offset
Cc =
A 2VT Cox + Cc min σ2VOS
Required capacitance
3σ VOS =
Simple Dynamic Latch Assuming Ccmin = 5fF for wires, clocking, etc.
Ecomp
σ2VOS ≅
B≅
1 Vinpp 4 2B
Confidence interval 3dB penalty accounts for “DNL noise”
SNR[dB] + 3 6
2 VDD 2B 2 2 ⋅ 2B − 1 ≅ 144 ⋅ 2 ⋅ Cox A VT ⋅ 2 + Cc min VDD 1 4 24 3 Vinpp Matching
(
)
Energy B. Murmann
EE315B - Chapter 12
14
Typical Process Parameters Process [nm]
AVT [mV-µm]
Cox [fF/µm2]
AVT2Cox /kT
Egate [fJ]
250
8
9
139
80
130
4
14
54
10
65
3
17
37
3
32
1.5
43
23
1.5
EE315B - Chapter 12
B. Murmann
15
Comparison to State-of-the-Art -6
10
-8
10
Flash ISSCC & VLSI 1997-2012 Eflash65nm Ecomp65nm
-10
Emin
[6]
P/f snyq [J]
10
[2]
[1]
-12
10
[5] [4]
[3]
-14
10
-16
10
15
20
25
[1] Van der Plas, ISSCC 2006 [2] El-Chammas, VLSI 2010 [3] Verbruggen, VLSI 2008 B. Murmann
30 SNDR [dB]
EE315B - Chapter 12
35
40
[4] Daly, ISSCC 2008 [5] Chen, VLSI 2008 [6] Geelen, ISSCC 2001 (!) 16
Impact of Scaling -6
10
Flash ISSCC & VLSI 1997-2012 Eflash250nm Eflash130nm
-8
P/f snyq [J]
10
Eflash65nm Eflash32nm Emin
-10
10
-12
10
-14
10
15
20
25
30
35
40
SNDR [dB]
EE315B - Chapter 12
B. Murmann
17
SC Delta-Sigma Modulator Assumptions
Model of first integrator
Closed-loop gain = ½ C
C /2
1
Infinite transistor fT (Cgs=0) Thermal noise factor (γ) equals 1
2
Bias device has same noise as amplifier device Linear settling only (no slewing)
β=
Ci Ci +
B. Murmann
Ci 2
=
2 3
Ceff = Ci (1 − β ) + CL =
EE315B - Chapter 12
1 2 Ci + CL ≅ Ci 3 3 18
SC Integrator Constraints 2
1 Vinpp 2 2 SNR ≅ kT 1 4 Ceff OSR
τ=
Thermal noise sets Ceff
Ceff T /2 Ts / 2 = s ≅ βgm 1 ln SNR ln εd
(
P = VDD
Settling time sets gm
)
gm
gm sets power
gm ID EE315B - Chapter 12
B. Murmann
19
Pulling It All Together Settling “Number 6474of 8τ”
Eint DT = 64 { ⋅ kT ⋅ SNR ⋅ ln Excess noise Finite β
(
VDD penalty
2 } VDD 1 1 SNR ⋅ ⋅ ⋅ V V gm DD 1 4inpp 24 3 ID { Supply
)
utilization Transconductor efficiency
• For settling with ~10 time constants and VDD=1V, gm/ID=1/(1.5kT/q), Vinpp=0.5V, we have
E୧୬୲ ≅ 200kT · SNR B. Murmann
EE315B - Chapter 12
20
Comparison to State-of-the-Art -6
10
[8] -8
[7]
P/f snyq [J]
10
-10
10
[1]
[2]
[4] [5]
[3]
[6] DT∆Σ ISSCC & VLSI 1997-2012 CT∆Σ ISSCC & VLSI 1997-2012 First Integrator EintCT
-12
EintDT
10
Emin
60
65
70
75
[1] Kauffman, ISSCC 2011 [2] Witte, ISSCC 2012 [3] Shettigar, ISSCC 2012 [4] Gealow, VLSI 2011
80
85 90 SNDR [dB]
95
100
105
[5] Chae, ISSCC 2008 [6] Pena Perez, ISSCC 2011 [7] Park, VLSI 2008 [8] Brewer, ISSCC 2005
EE315B - Chapter 12
B. Murmann
110
21
Overall Picture 10
P/f s [J]
10
10
-6
-8
Flash Pipeline SAR ∆Σ
-10
Other E
flash32nm,cal
E
10
-12
E E E
10
-14
20
B. Murmann
30
40
50
60 70 SNDR [dB] EE315B - Chapter 12
80
90
pipe sar CT∆Σ min
100
110
22
Discussion •
Today’s designs are very close to the predicted limits
•
The limit lines at high resolution are set by fundamental thermal noise and architectural circuit overhead – Technology scaling won’t help much
•
Sometimes it is even argued that technology scaling will deteriorate efficiency, due to low VDD – Let’s have a closer look at this…
EE315B - Chapter 12
B. Murmann
23
A Closer Look at the Impact of Technology Scaling As shown previously: 2
1 VDD 1 E∝ ⋅ ⋅ VDD Vinpp gm ID •
Low VDD hurts, but this is not the only factor
•
Designers have worked hard to maintain (if not improve) Vinpp/VDD in low-voltage designs
•
How about gm/ID?
B. Murmann
EE315B - Chapter 12
24
gm/ID Considerations (1) 30 180nm 90nm
gm/ID [S/A]
25 20 15 10 5 0 -0.2
• •
-0.1
0
0.1
0.2 0.3 VGS-Vt [V]
0.4
0.5
0.6
Largest value occurs in weak inversion ~(1.5⋅kT/q)-1 Range of gm/ID does not scale (much) with technology EE315B - Chapter 12
B. Murmann
25
gm/ID Considerations (2) 120
fT [GHz]
100
180nm 90nm
80 60 40 20 0 -0.2
• •
-0.1
0
0.1
0.2 0.3 VGS-Vt [V]
0.4
0.5
0.6
fT is small in weak inversion region Must look at gm/ID for given fT requirement to compare technologies B. Murmann
EE315B - Chapter 12
26
gm/ID Considerations (3) 30 180nm 90nm 45nm
gm/ID [S/A]
25
20
•
Example – fT = 30GHz – 90nm: gm/ID = 18S/A – 180nm: gm/ID = 9S/A
•
For a given fT, 90nm device takes less current to produce same gm – Helps mitigate, if not eliminate penalty due to lower VDD (!)
15
10
5 0
20
40 60 fT [GHz]
80
100
EE315B - Chapter 12
B. Murmann
27
ADC Energy for 90nm and Below 10
P/f snyq [J]
10
10
10
-6
-8
-10
-12
20
B. Murmann
ISSCC & VLSI 1997-2013 90nm and below 30
40
50
60 70 SNDR [dB] EE315B - Chapter 12
80
90
100
110
28
Efficiency versus Absolute Speed ௐ = 10
௦ · 2ாேை
ೞ ≅ ଶ
6
FOM W [fJ/conv-step]
2006-2013 1998-2005
10
10
4
2
0
10 4 10
10
5
10
6
10
7
10
8
10
9
10
10
f s [Hz] EE315B - Chapter 12
B. Murmann
29
Analysis 1 ∝ ∝ ை ௦
் =
3 ை 2 ଶ
∝ ் = · ௦ ௦
B. Murmann
Energy efficiency reduces with larger gate overdrive
But, large gate overdrive is needed for high transistor fT
fT is usually chosen as a multiple of the sampling rate
EE315B - Chapter 12
30
Conclusions (1) •
No matter how you look at it, today’s ADCs are extremely well optimized
•
The main trend is that the “thermal knee” shifts very rapidly toward lower resolutions – Thanks to process scaling and creative design
•
At high resolution, we seem to be stuck at E/Emin~100 – The factor 100 is due to architectural complexity and inefficiency: excess noise, signal < supply, non-noise limited circuitry, class-A biasing, …
•
This will be very hard to change – Scaling won’t help (much) – Some of the recent data points already use class-B-like amplification – Can we somehow recycle charge?
B. Murmann
EE315B - Chapter 12
31
Conclusions (2) •
At low resolutions, scaling will continue to help lower ADC energy
•
Scaling will especially help improve the efficiency of GS/s A/D converters – This is badly needed for high-speed data links (electrical and optical)
•
For non-incremental improvements, we must explore new ideas in signal processing that tackle ADC inefficiency at the system level – Compressed sensing – Finite innovation rate sampling – Other ideas?
B. Murmann
EE315B - Chapter 12
32
Example: Finite Innovation Rate Sampling of Ultrasound Signals Low BW after filtering
High BW
Analog Filter
Reconstruction
[Inspired by theoretical work of Prof. Yonina Eldar]
~100x reduction in sampling rate B. Murmann
EE315B - Chapter 12
33
