EE214 Advanced Analog Integrated Circuit Design - Winter 2011 Boris Murmann Stanford University
[email protected]
Table of Contents
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10
Introduction BJT Devices MOS Devices and Gm/ID-based Design Review of Elementary Circuit Configurations Two-Port Feedback Circuit Analysis Frequency Response of Feedback Circuits Wideband Amplifiers Noise Analysis Distortion Analysis Opamps and Output Stages
Chapter 1 Introduction
B. Murmann Stanford University
Analog Circuit Sequence
Fundamentals for upperlevel undergraduates and graduate entry-level y g students
Analysis and design techniques for highperformance circuits in p advanced Technologies
Design of mixedsignal/RF building bl k blocks
EE314 — RF Integrated Circuit Design EE114 — Fundamentals of Analog Integrated Circuit Design
EE214 — Advanced Analog Integrated Circuit Design
EE315A — VLSI Signal Conditioning Circuits EE315B — VLSI Data Conversion Circuits
B. Murmann
EE214 Winter 2010-11 – Chapter 1
2
The Evolution of a Circuit Designer…
EE101A,B
B. Murmann
EE114
EE214
EE314 EE315A,B
EE214 Winter 2010-11 – Chapter 1
3
Analog Design
EE 114 Bandwidth
Power Dissipation
EE 214
Electronic Noise
B. Murmann
EE214 Winter 2010-11 – Chapter 1
Distortion
4
Significance of Electronic Noise (1)
Signal-to-Noise g Ratio
SNR =
B. Murmann
Psignal Pnoise
EE214 Winter 2010-11 – Chapter 1
∝
2 Vsignal 2 Vnoise
5
Significance of Electronic Noise (2) Example: Noisy image
http://www.soe.ucsc.edu/~htakeda/kernelreg/kernelreg.htm p g g
B. Murmann
EE214 Winter 2010-11 – Chapter 1
6
Significance of Electronic Noise (3) Th The "fidelity" "fid lit " off electronic l t i systems t is i often ft determined d t i d by b their th i SNR – Examples • Audio systems • Imagers, Imagers cameras • Wireless and wireline transceivers
Electronic noise directly trades with power dissipation and speed – In I mostt circuits, i it low l noise i di dictates t t llarge capacitors it ((and/or d/ smallll R R, large gm), which means high power dissipation Noise has become increasingly important in modern technologies with reduced supply voltages – SNR ~ Vsignal2/Vnoise2 ~ (αVDD)2/Vnoise2 Designing a low-power, high-SNR circuit requires good understanding of electronic l t i noise i
B. Murmann
EE214 Winter 2010-11 – Chapter 1
7
Distortion vo
vi
Small-signal approximation
All electronic circuits exhibit some level of nonlinear behavior – The resulting waveform distortion is not captured in linearized smallsmall signal models The distortion analysis tools covered in EE214 will allow us to quantify the impact of nonlinearities on sinusoidal waveforms B. Murmann
EE214 Winter 2010-11 – Chapter 1
8
Significance of Distortion For a single tone input, the nonlinear terms in a circuit’s transfer function primarily result in signal harmonics
For a two-tone input, the nonlinear terms in a circuit’s transfer function result lt in i so-called ll d “i “intermodulation t d l ti products” d t ”
Example: Two interferer tones create an intermodulation product that corrupts the signal in a desired (radio-) channel
B. Murmann
EE214 Winter 2010-11 – Chapter 1
9
Noise and Distortion Analysis in EE214
Main objective – Acquire the basic tools and intuition needed to analyze noise and distortion in electronic circuits – Look at a few specific circuit examples to “get a feel” for situations where noise and/or distortion may matter Leave application-specific examples for later – EE314: Noise and distortion in LNAs,, mixers and power p amplifiers p – EE315A: Noise and distortion in filters and sensor interfaces – EE315B: Noise and distortion in samplers, A/D & D/A converters
B. Murmann
EE214 Winter 2010-11 – Chapter 1
10
Technology
MOSFET
Bipolar Junction Transistor (BJT)
EE114
EE214
B. Murmann
EE214 Winter 2010-11 – Chapter 1
11
Bipolar vs. CMOS (1) Advantages of bipolar transistors – Lower parametric variance – Higher Hi h supply l voltages l – Higher intrinsic gain (gmro) – Higher fT for a given feature size/lithography
Disadvantages of bipolar transistors – Lower integration density, larger features – Higher cost
B. Murmann
EE214 Winter 2010-11 – Chapter 1
12
Bipolar vs. CMOS (2)
A.J. Joseph, et al., "Status and Direction of Communication Technologies - SiGe BiCMOS and RFCMOS," Proceedings of the IEEE, vol.93, no.9, pp.1539-1558, September 2005.
•
CMOS tends to require finer lithography to achieve same speed as BiCMOS p process with advanced BJT B. Murmann
EE214 Winter 2010-11 – Chapter 1
13
Example that Leverages High-Speed BJTs: 40Gb/s Integrated Optical Transponder
B. Murmann
EE214 Winter 2010-11 – Chapter 1
14
Die Photo of 40Gb/s CDR Circuit *
• 120-GHz fT / 100GHz fmax 0.18μm SiGe BiCMOS • 144 pins • 3.5mm x 4.2mm • +1.8V and –5.2V supplies • 7.5W power dissipation
*A A. O Ong, ett al., l ISSCC 2003 B. Murmann
EE214 Winter 2010-11 – Chapter 1
15
Radar Sensor
R Ragonese ett al., l ISSCC 2009
B. Murmann
EE214 Winter 2010-11 – Chapter 1
16
Example that Leverages Densely Integrated CMOS: RF Transceiver System-on-a-Chip (SoC) In modern CMOS technology, millions of l i gates logic t can b be integrated on a chip – Together with moderate- to high moderate performance analog blocks
Mehta et al., "A 1.9GHz Single-Chip CMOS PHS Cellphone," ISSCC 2006.
B. Murmann
EE214 Winter 2010-11 – Chapter 1
17
45nm CMOS (Intel)
Steve Cowden THE OREGONIAN July 2007
B. Murmann
EE214 Winter 2010-11 – Chapter 1
18
Research in Device Technology Vdd A
Transport-enhanced FET
Molecular devices
B Out
Strained Si, Ge, SiGe, III-V A B
buried oxide
Gnd isolation
Silicon Substrate
Self-assembled device fabrication
Nanodevice array
Spintronics
top-gate channel
Nanotube 3D, heterogeneous i t integration ti
channel
Quantum cascade
back-gate isolation buried oxide
Multi-Gate / FinFET
Nanowire
Gate
Source
Drain
[Prof. P. Wong]
Embedded memory
Ferromagnetic domain wall
Time B. Murmann
EE214 Winter 2010-11 – Chapter 1
19
Thoughts on Device Technology
In the future, innovative circuit designers must embrace “whichever” technology is most suitable (in terms of performance, cost, reliability, etc. f their for th i specific ifi problem bl – Regardless of the respective I-V law and associated nonidealities In EE214, we will use bipolar and MOS technology to illustrate the similarities and differences between two advanced technologies The device parameters and simulation models of the “EE214 EE214 technology” correspond to a modern 0.18-μm SiGe BiCMOS technology – See e.g. S. Wada, et al., “A manufacturable 0.18-um SiGe BiCMOS technology for 40-Gb/s optical communication LSIs,” in Proc. 2002 Bipolar/BiCMOS Circuits and Technology Meeting, pp. 84–87.
B. Murmann
EE214 Winter 2010-11 – Chapter 1
20
Analysis of Feedback Circuits F Feedback db k circuits i it can b be studied t di d iin severall ways – Return ratio analysis (EE114) – Two-port analysis (EE214) Both methods have their own merits and demerits, and a good circuit designer should understand both approaches Two-port analysis nicely captures a number of practical scenarios in which the forward amplifier (“a”) and feedback network (“f”) can be intuitively identified and separated (while maintaining loading effects) – Shunt-shunt, shunt-series, series-shunt, series-series configurations
Example: Shunt series feedback circuit Shunt-series
B. Murmann
EE214 Winter 2010-11 – Chapter 1
21
Root Locus Techniques
Provides intuitive guidance on “where the poles move” when the loop gain is varied Valuable for stability analysis and frequency compensation
B. Murmann
EE214 Winter 2010-11 – Chapter 1
22
Course Outline
BJT & short channel MOS device models Review of elementaryy amplifier p stages g ((BJT focus)) Two-port feedback circuit analysis Root locus Wideband amplifiers Noise analysis Distortion analysis OpAmps and output stages
B. Murmann
EE214 Winter 2010-11 – Chapter 1
23
Summary of Learning Goals
Understand device behavior and models for transistors available in advanced integrated circuit technologies – SiGe BJT, short channel MOS Acquire the basic intuition and models for – Distortion analysis – Noise analysis – Two-port feedback circuit analysis – Root locus techniques and their application to broadband amplifiers Solidify the above topics in a hands-on project involving the design and optimization of a broadband amplifier circuit
B. Murmann
EE214 Winter 2010-11 – Chapter 1
24
Staff and Website
Instructors – Boris Murmann, Drew Hall Teaching assistants – Kamal Aggarwal, Pedram Lajevardi Administrative support – Ann Guerra, CIS 207 Lectures are televised – But please come to class to keep the discussion interactive! Web page: http://ccnet.stanford.edu/ee214 – Check regularly, especially bulletin board – Register for online access to grades and solutions
B. Murmann
EE214 Winter 2010-11 – Chapter 1
25
Text and Prerequisites EE214 C Course reader d – Hardcopies available at Stanford Bookstore (~1/3) Required textbook – Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley Reference text – B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2002 Course p prerequisite: q EE114 or equivalent q – Basic device physics and models – Frequency response, dominant pole approximation, ZVTC – Biasing, g, small-signal g models – Common source, common gate, and common drain stages – Port impedance calculations – Feedback basics B. Murmann
EE214 Winter 2010-11 – Chapter 1
26
Assignments
Homework (20%) – Handed out on Wed, due following Wed in class – Lowest L t HW score will ill b be d dropped d – Policy for off-campus students • Fax or email to SCPD before deadline stated on handout Midterm Midt E Exam (30%) Design Project (20%) – Design of an amplifier using HSpice (no layout) – Work W k in i tteams off two t – OK to discuss your work with other teams, but no file exchange! Final Exam (30%)
B. Murmann
EE214 Winter 2010-11 – Chapter 1
27
Honor Code
Please remember you are bound by the honor code – We will trust you not to cheat – We will try not to tempt you But if you are found cheating it is very serious – There is a formal hearing g – You can be thrown out of Stanford Save yourself a huge hassle and be honest For more info – http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/honorcode.pdf
B. Murmann
EE214 Winter 2010-11 – Chapter 1
28
Chapter 2 Bipolar p Junction Transistors B. Murmann Stanford University
Reading Material: Sections 1.1, 1.2, 1.3, 1.4, 2.5, 2.6, 2.7, 2.11, 2.12
History
Bardeen, Brattain, and Shockley, 1947
W. Brinkman, D. Haggan, and W. Troutman, “A history of the invention of the transistor and where it will lead us,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1858-1865, Dec. 1997.
W. Shockley, W Shockley M. M Sparks, Sparks and G G. K K. Teal Teal, “P P-N N junction transistors,” Phys. Rev. 83, pp. 151–162, Jul. 1951.
B. Murmann
EE214 Winter 2010-11 – Chapter 2
2
Conceptual View of an NPN Bipolar Transistor (Active Mode)
IC ∝ e
IB > NA, it follows that pn(0) ωβ
)
B. Murmann
EE214 Winter 2010-11 – Chapter 2
45
Transit Frequency Calculation (2)
|io/ii|
(
gm
ω Cπ + Cμ
)
(asymptote)
≅ βF
Note that rπ “matters” only for frequencies up to ωβ = ωT/βF
Text, p. 36
1=
ωT Cπ + Cμ
τT =
B. Murmann
(
gm
)
⇒ ωT =
gm Cπ + Cμ
C je Cμ C je Cμ C 1 = b+ + = τF + + gm gm ωT gm gm gm
EE214 Winter 2010-11 – Chapter 2
46
fT versus IC plot “peak fT”
Cje and Cμ dominate
High level injection, τF increases Text, p. 37
gm = IC/VT increases
The particular current value at which fT is maximized depends on the particular parameters of a technology and the emitter area of the BJT B. Murmann
EE214 Winter 2010-11 – Chapter 2
47
EE214 Technology Assumed to be similar to a 0 0.18 18-μm μm BiCMOS technology featuring a high-performance SiGe npn device – VCC = 2.5V (BJT), VDD=1.8V (MOS) See e e.g. g – Wada et al., BCTM 2002 – Joseph et al., BCTM 2001 – IBM 7HP documentation • https://www-01.ibm.com/chips/techlib/techlib.nsf/products/BiCMOS_7HP) NPN
PMOS/NMOS
Poly resistor
http://fuji.stanford.edu/events/spring01/slides/harameSlides.pdf
B. Murmann
EE214 Winter 2010-11 – Chapter 2
48
Cross Section of npn Device
B. Murmann
EE214 Winter 2010-11 – Chapter 2
49
EE214 npn Unit Device A technology typically comes with an optimized layout for a unit device of a certain size AE = 0.22μm x 3.2μm
Great care is then taken to extract a Spice model for this particular layout using measured data Spice model (usr/class/ee214/hspice/ee214_hspice.sp)
E .model npn214 npn + level=1 tref=25 is=.032f bf=300 br=2 vaf=90
B
+ cje=6.26f vje=.8 mje=.4 cjc=3.42f vjc=.6 mjc=.33 + re=2 re=2.5 5 rb=25 rc=60 tf=563f tr=10p
C
+ xtf=200 itf=80m ikf=12m ikr=10.5m nkf=0.9
Instantiation in a circuit netlist
B. Murmann
*
C
q1
n1 n2 n3
B
E npn214
EE214 Winter 2010-11 – Chapter 2
50
BJT Model Parameters
For more info consult the HSpice documentation under /afs/ir.stanford.edu/class/ee/synopsys/B-2008.09-SP1/hspice/docs_help PDF files: home.pdf hspice_cmdref.pdf hspice_integ.pdf hspice_relnote.pdf hspice_sa.pdf hspice_devmod.pdf hspice_mosmod.pdf hspice_rf.pdf hspice_si.pdf
B. Murmann
EE214 Winter 2010-11 – Chapter 2
51
Adding Multiple Devices in Parallel
For the unit device, there exists a practical upper bound for the collector current – Due D tto th the onsett off high hi h llevell iinjection j ti This means that the unit device can only deliver a certain maximum gm
E
E
E
B
B
B
If more gm is needed, “m” unit devices can be connected in parallel
C
C
C
Instantiation in a circuit netlist ((m=3))
B. Murmann
*
C
q1
n1 n2 n3
B
E
EE214 Winter 2010-11 – Chapter 2
npn214
3
52
npn Unit Device Characterization
* ee214 npn device characterization * q1 Vc ib
C c c 0
B E b 0 0 b
.op .dc ib .probe .probe .probe b .probe .probe .probe
npn214 1.25 1u
dec 10 10f 100u ib(q1) ic(q1) ie(q1) gm = par('gm(q1)') go = par('g0(q1)') (' 0( 1)') cpi = par('cap_be(q1)') cmu = par('cap_ibc(q1)') beta = par('beta(q1)')
CC
.options dccap post brief .inc '/usr/class/ee214/hspice/ee214_hspice.sp' .end
B. Murmann
EE214 Winter 2010-11 – Chapter 2
53
DC Operating Point Output **** bipolar junction transistors element 0:q1 model 0:npn214 ib 999.9996n ic 288.5105u vbe 803.4402m vce 1.2500 vbc -446.5598m vs -1.2327 power 361.4415u betad 288.5106 gm 10.2746m rpi 26 8737k 26.8737k rx 25.0000 ro 313.4350k cpi 14.6086f cmu 2 8621f 2.8621f cbx 0. ccs 0. betaac 276.1163 g ft 93.5999g
B. Murmann
EE214 Winter 2010-11 – Chapter 2
54
Gummel Plot
B. Murmann
EE214 Winter 2010-11 – Chapter 2
55
Transit Frequency
fT [GH Hz]
150
100
50
0 10
-4
10
-3
10
-2
IC [A]
B. Murmann
EE214 Winter 2010-11 – Chapter 2
56
Intrinsic Gain
ee215 npn
4000 3500
gm /go [GHz]]
3000 2500 2000 1500 1000 500 0 10
-8
10
-6
10
-4
10
-2
IC [A]
B. Murmann
EE214 Winter 2010-11 – Chapter 2
57
gm/IC
Important to realize that gm will not be exactly equal to IC/VT at high currents
B. Murmann
EE214 Winter 2010-11 – Chapter 2
58
I-V Curves
NPN (1x, AE=0.7μm2, I B=0.2, 0.4, ..., 1μA
300
800
NMOS 2/0.18, VGS=0.6, 0.8, ..., 1.4V
700
250
600 500 I D [μA]
I C [μA]
200 150
400 300
100
200 50 0 0
B. Murmann
100 0.5
1 1.5 VCE [V]
2
2.5
0 0
EE214 Winter 2010-11 – Chapter 2
0.5
1 VDS [V]
1.5
59
Passive Components (1)
Joseph et al., BCTM 2001
B. Murmann
EE214 Winter 2010-11 – Chapter 2
60
Passive Components (2)
Diffusion Resistor
MIM Capacitor
Text, p. 116
B. Murmann
EE214 Winter 2010-11 – Chapter 2
61
Chapter 3 MOS Transistor Modeling Gm/ID-based based Design B. Murmann Stanford University
Reading Material: Sections 1.5, 1.6, 1.7, 1.8
Basic MOSFET Operation (NMOS)
Text,, p.41 p
How to calculate drain current (ID) current as a function of VGS, VDS?
B. Murmann
EE214 Winter 2010-11 – Chapter 3
2
Simplifying Assumptions
1)) Current is controlled byy the mobile charge g in the channel. This is a very y good approximation. 2) "Gradual Channel Assumption" - The vertical field sets channel charge, so we can approximate the available mobile charge through the voltage diff difference b between t th the gate t and d th the channel h l 3) The last and worst assumption (we will fix it later) is that the carrier velocity is proportional to lateral field (ν = μE). This is equivalent to Ohm's law: velocity (current) is proportional to E-field E field (voltage) B. Murmann
EE214 Winter 2010-11 – Chapter 3
3
Derivation of First Order IV Characteristics (1)
Qn (y) = Cox [ VGS − V(y) − Vt ] ID = Qn ⋅ v ⋅ W
v = μ ⋅E ID = Cox [ VGS − V(y) − Vt ] ⋅ μ ⋅ E ⋅ W
ID = μCox
B. Murmann
VDS ⎤ W⎡ ⎢( VGS − Vt ) − ⎥ ⋅ VDS L ⎣ 2 ⎦
EE214 Winter 2010-11 – Chapter 3
4
Pinch-Off – VGS + + VDS –
N
Qn(y), V(y)
N
Voltage at the end of channel is fixed at VGS-V Vt
y y=0
y=L
Effective voltage across channel is VGS-Vt – At the point where channel charge goes to zero, there is a high lateral field that sweeps the carriers to the drain • Recall that electrons are minority carriers in the p-region of a pn j junction; ti th they are b being i sweptt ttoward d th the n-region i – The extra drain voltage drops across depletion region To first order, the current becomes independent of VDS
B. Murmann
EE214 Winter 2010-11 – Chapter 3
5
Plot of Output Characteristic Saturation Region
ID
Triode Region
VGS-V Vt VDS
Triode Region:
ID = μCox
VDS ⎤ W⎡ ⎢( VGS − Vt ) − ⎥ ⋅ VDS L ⎣ 2 ⎦
Saturation Region:
ID = μCox
(V − V ) W⎡ ( VGS − Vt ) − GS t ⎤⎥ ⋅ (VGS − Vt ) ⎢ L ⎣ 2 ⎦
=
B. Murmann
1 W (VGS − Vt )2 μCox 2 L EE214 Winter 2010-11 – Chapter 3
6
ID
Plot of Transfer Characteristic (in Saturation)
Vt VGS
VOV
gm =
dID W W = μCox ( VGS − Vt ) = μCox VOV dVGS L L
= 2IDμCox
B. Murmann
2I W = D L VOV
EE214 Winter 2010-11 – Chapter 3
7
Output Characteristic with “Channel Length Modulation”
Triode Region
Saturation Region
ID
go= dID/dVDS ≠ 0
VGS-Vt VDS
go = =
B. Murmann
dID d = dVDS dVDS
W ⎡1 ⎤ 2 ⎢ 2 μCox L (VGS − Vt ) (1 + λVds )⎥ ⎣ ⎦
λID 1 W μCox (VGS − Vt )2 ⋅ λ = ≅ λID 2 L 1 + λVDS
EE214 Winter 2010-11 – Chapter 3
8
Capacitances
Text, p. 54
B. Murmann
EE214 Winter 2010-11 – Chapter 3
9
Gate Capacitance Summary
B. Murmann
Subthreshold
Triode
Saturation
Cgs
Col
½ WLCox+ Col
Cgd
Col
½ WLCox+Col
Col
Cgb
⎛ 1 1 ⎞ + ⎜⎜ ⎟⎟ ⎝ C js WLCox ⎠
0
0
2/ 3
WLCox + Col
−1
EE214 Winter 2010-11 – Chapter 3
10
Capacitance Equations and Parameters
Parameter
Cdb =
ε Cox = ox t ox Col = WCol' AD ⋅ CJ MJ
VDB ⎞ ⎛ ⎜ 1 + PB ⎟ ⎝ ⎠
+
PD ⋅ CJSW MJSW
VDB ⎞ ⎛ ⎜ 1 + PB ⎟ ⎝ ⎠
AD = WL diff PD = W + 2L diff
NMOS
PMOS
Cox
8.42 fF/μm2
8.42 fF/μm2
C’ol C
0 491 fF/μm 0.491
0 657 fF/μm 0.657
CJ
0.965 fF/μm2
1.19 fF/μm2
CJSW
0 233 fF/μm 0.233
0 192 fF/μm 0.192
PB
0.8 V
0.8 V
MJ
0.38
0.40
MJSW
0.13
0.33
0.64 μm
0.64 μm
LDIF
B. Murmann
EE 214 Technology (0.18μm)
EE214 Winter 2010-11 – Chapter 3
11
Complete Small-Signal Model gd
gs
gs
gb
sb
m gs
o
db
2 bsub (Cj0 = 0.2 fF/μm , “dwell” model)
Cgg Cgs + Cgb + Cgd B. Murmann
Cdd Cdb + Cgd
EE214 Winter 2010-11 – Chapter 3
12
What are μCox (“KP”) and λ (“LAMBDA”) for our Technology? .MODEL MODEL nmos214 nmos +acm
hdif
= 0.32e-6
LEVEL
= 49
+VERSION = 3.1
TNOM
= 27
TOX
= 4.1E-9
+XJ
= 1E-7
= 3
NCH
= 2.3549E17
VTH0
= 0.3618397
+K1
= 0.5916053
K2
= 3.225139E-3
+K3B
= 2.3938862
W0
= 1E-7
NLX
= 1.776268E-7
+DVT0W
= 0
DVT1W
= 0
DVT2W
= 0
+DVT0
= 1.3127368
DVT1
= 0.3876801
DVT2
= 0.0238708
+U0
= 256.74093
UA
= -1.585658E-9
UB
= 2.528203E-18
+UC
= 5.182125E-11
VSAT
= 1.003268E5
A0
= 1.981392
+AGS
= 0.4347252
B0
= 4.989266E-7
B1
+KETA
= -9.888408E-3
A1
= 6.164533E-4
A2
= 0.9388917
+RDSW
= 128.705483
PRWG
= 0.5
PRWB
= -0.2
+WR
= 1
WINT
= 0
LINT
= 1.617316E-8
+XL
= 0
XW
= -1E-8
DWG
= -5.383413E-9
+DWB
= 9.111767E-9
VOFF
= -0.0854824
NFACTOR = 2.2420572
+CIT
= 0
CDSC
= 2.4E-4
CDSCD
= 0
+CDSCB
= 0
ETA0
= 2.981159E-3
ETAB
= 9.289544E-6
+DSUB
= 0.0159753
PCLM
= 0.7245546
PDIBLC1 = 0.1568183
K3
= 1E-3
= 5E-6
+PDIBLC2 = 2.543351E-3
PDIBLCB = -0.1
DROUT
+PSCBE1
= 8E10
PSCBE2
= 1.876443E-9
PVAG
= 7.200284E-3
+DELTA
= 0.01
RSH
= 6.6
MOBMOD
= 1
+PRT
= 0
UTE
= -1.5
KT1
= -0.11
+KT1L
= 0
KT2
= 0.022
UA1
= 4.31E-9
+UB1
= -7.61E-18
UC1
= -5.6E-11
AT
= 3.3E4
+WL
= 0
WLN
= 1
WW
= 0
+WWN
= 1
WWL
= 0
LL
= 0
+LLN
= 1
LW
= 0
LWN
= 1
+LWL
= 0
CAPMOD
= 2
XPART
= 1
+CGDO
= 4.91E-10
CGSO
= 4.91E-10
CGBO
= 1E-12
+CJ
= 9.652028E-4
PB
= 0.8
MJ
= 0.3836899
+CJSW
= 2.326465E-10
PBSW
= 0.8
MJSW
= 0.1253131
+CJSWG
= 3.3E-10
PBSWG
= 0.8
MJSWG
= 0.1253131
+CF
= 0
PVTH0
= -7.714081E-4
PRDSW
= -2.5827257
+PK2
= 9.619963E-4
WKETA
= -1.060423E-4
LKETA
= -5.373522E-3
+PU0
= 4.5760891 4 5760891
PUA
= 1.469028E 1 469028E-14 14
PUB
= 1.783193E 1 783193E-23 23
+PVSAT
= 1.19774E3
PETA0
= 9.968409E-5
PKETA
= -2.51194E-3
+nlev
= 3
kf
= 0.5e-25
B. Murmann
The HSpice p model for an NMOS device in our technology is shown to the left BSIM 3v3 model 110 parameters KP and LAMBDA nowhere to be found found…
= 0.7445011
EE214 Winter 2010-11 – Chapter 3
13
An Attempt to Extract μCox Bias MOSFET at constant VDS>VOV, sweep VGS and plot μCox estimate 300 NMOS 5/0.18 NMOS 20/0.72
μCox
2ID = W 2 V L OV
2 μnCox [μA/V ]
250 200 150 100 50 0 0
0.1
0.2 V
OV
0.3 [V]
0.4
0.5
The extracted μCox depends on L and VOV and cannot be viewed as a constant parameter
B. Murmann
EE214 Winter 2010-11 – Chapter 3
14
Questions
Which physical effects explain the large deviation from the basic square law model? How can we design with such a device? – Is there another “simple” equation that describes its behavior? We will approach the above two questions by performing a systematic, simulation-based device characterization – And discuss the relevant p physical y p phenomena that explain p the observed behavior As a basis for this characterization, we consider three basic figures of merit that relate directlyy to circuit design g
B. Murmann
EE214 Winter 2010-11 – Chapter 3
15
Figures of Merit for Device Characterization Square Law Transconductance efficiency – Want W t large l gm, for f as little littl currentt as possible
gm ID
=
2 VOV
Transit frequency – Want large g gm, without large g Cgg
gm Cgg
≅
3 μVOV 2 L2
Intrinsic gain – Want large gm, but no go
gm go
≅
2 λVOV
B. Murmann
EE214 Winter 2010-11 – Chapter 3
16
Device Characterization
* NMOS characterization .param .param vds vgs mn .op .dc gs .probe .probe b .probe .probe
gs=0.7 dd=1.8 d 0 g 0 d g 0 0
dc 'dd/2' dc 'gs' nmos214 L=0.18um
W=5um
DD
0.2V 1V 10mV ov = par('gs-vth(mn)') gm_id id = par('gmo(mn)/i(mn)') (' ( )/i( )') ft = par('1/6.28*gmo(mn)/cggbo(mn)') gm_gds = par('gmo(mn)/gdso(mn)')
.options options post brief dccap .inc /usr/class/ee214/hspice/ee214_hspice.sp .end
B. Murmann
EE214 Winter 2010-11 – Chapter 3
17
gm/ID Plot 40 35
0.18um NMOS 2/VOV
gm/I D [S/A A]
30
BJT (q/kT)
25 20 15 10 5 0 -0.2
B. Murmann
-0.1
0
0.1 0.2 VOV [V]
EE214 Winter 2010-11 – Chapter 3
0.3
0.4
0.5
18
Observations
Square law prediction is fairly close for VOV > 150mV Unfortunatelyy gm/ID does not approach pp infinity y for VOV → 0 It also seems that we cannot do better than a BJT, even though the square law equation would predict this for 0 < VOV < 2kT/q ≅ 52mV For further analysis, analysis it helps to identify three distinct operating regions – Strong inversion: VOV > 150mV • Deviations due to short channel effects – Subthreshold: VOV < 0 • Behavior similar to a BJT, gm/ID nearly constant – Moderate Inversion: 0 < VOV < 150mV • Transition region, region an interesting mi mix of the abo above e
B. Murmann
EE214 Winter 2010-11 – Chapter 3
19
Subthreshold Operation A plot of the device current in our previous simulation 1
10
0
0.8
10
-1
0.6
10
-2
10
-3
10
-4
I D [mA A]
I D [mA A]
0.4 0.2 0 -0.5
-5
0
0.5 V
1
10 -0.5
[V]
0
0.5 V
VOV [V]
1
[V]
VOV [V]
Questions – What determines the current when VOV< 0, i.e. VGS< Vt? – What Wh t iis th the d definition fi iti off Vt? B. Murmann
EE214 Winter 2010-11 – Chapter 3
20
Definition of Vt
Vt is defined as the VGS at which the number of electrons at the surface equals the number of doping atoms Seems somewhat arbitrary, but makes sense in terms of surface charge control
B. Murmann
EE214 Winter 2010-11 – Chapter 3
21
Mobile Charge versus VOV 6.E-07
Ch harge [C]
5.E-07
Fixed Charge Mobile Charge T t l Charge Total Ch
4.E-07 3.E-07 2.E-07 1.E-07 0.E+00 -1.0
-0.5
0.0
0.5
1.0
VOV [V]
Around VGS=Vt (VOV=0), the relationship between mobile charge in the channel and gate voltage becomes linear (Qn ~ CoxVOV) – Exactly what we assumed to derive the long channel model B. Murmann
EE214 Winter 2010-11 – Chapter 3
22
Mobile Charge on a Log Scale O On a log l scale, l we see th thatt there th are mobile bil charges h b f before we reach h the threshold voltage – Fundamental result of solid-state physics, not short channels 1.E-06 1.E-07
Mobile Charge [C]
1 E-08 1.E 08 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14 1.E-15 1.E-16 -1.00
-0.50
0.00
0.50
1.00
VOV [V]
B. Murmann
EE214 Winter 2010-11 – Chapter 3
23
BJT Similarity
We have – An NPN sandwich, sandwich mobile minority carriers in the P region This is a BJT! – Except that the base potential is here controlled through a capacitive divider,, and not directlyy byy an electrode B. Murmann
EE214 Winter 2010-11 – Chapter 3
24
Subthreshold Current
•
We know that for a BJT
•
kT q For the MOSFET in subthreshold we have
VBE
IC = IS ⋅ e VT
VT =
ID = I0 ⋅ e •
VGS − Vt nV VT
n is given by the capacitive divider
n=
C js + Cox Cox
= 1+
C js Cox
where Cjs is the depletion layer capacitance •
In the EE214 technology n ≅ 1.5
B. Murmann
EE214 Winter 2010-11 – Chapter 3
25
Comparison – NMOS versus NPN
Vt
B. Murmann
EE214 Winter 2010-11 – Chapter 3
26
Subthreshold Transconductance gm =
gm 1 = ID nVT
dID 1I = D dVGS n VT
Similar to BJT, but unfortunately n (≅1.5) times lower 40 35 30 gm/I D [S/A A]
0.18um NMOS 2/VOV
~1.5x
BJT (q/kT)
25 20 15 10 5 0 -0.2 02
-0.1 01
0
B. Murmann
0.1 0 1 02 0.2 VOV [V]
03 0.3
04 0.4
05 0.5
EE214 Winter 2010-11 – Chapter 3
27
Moderate Inversion IIn the th transition t iti region i between b t subthreshold bth h ld and d strong t inversion, i i we have two different current mechanisms
Drift (MOS)
ν = μE
Diffusion ((BJT))
ν = D
dn kT dn = μ dx q dx
Both current components are always present – Neither one clearly dominates in moderate inversion
Can show that ratio of drift/diffusion current ~(VGS-Vt)/(kT/q) – MOS equation becomes dominant at several kT/q
B. Murmann
EE214 Winter 2010-11 – Chapter 3
28
Re-cap
Subthreshold Operation
? Transition to Strong Inversion
What causes the discrepancy between 2/VOV and 0.18μm NMOS in strong inversion? B. Murmann
EE214 Winter 2010-11 – Chapter 3
29
Short Channel Effects
Velocity saturation due to high lateral field Mobility y degradation g due to high g vertical field Vt dependence on channel length and width Vt = f(VDS) ro = f(VDS) … We will limit the discussion in EE214 to the first two aspects of the above list, with a focus on qualitative understanding
B. Murmann
EE214 Winter 2010-11 – Chapter 3
30
Velocity Saturation (1) IIn the th derivation d i ti off the th square llaw model, d l it iis assumed d th thatt th the carrier i velocity is proportional to the lateral E-field, v=μE Unfortunately, the speed of carriers in silicon is limited (vscl ≅ 105 m/s) – At very high fields (high voltage drop across the conductive channel), the carrier velocity saturates
Text, p. 60
(approximation)
ν d (E) ≅
μE E 1+ Ec
≅ μEc = v scl
=
B. Murmann
EE214 Winter 2010-11 – Chapter 3
v scl 2
for E >> Ec
for E = Ec
31
Velocity Saturation (2) It is i important i t t to t distinguish di ti i h various i regions i iin th the above b plot l t – Low field, the long channel equations still hold – Moderate field, the long channel equations become somewhat inaccurate – Very high field across the conducting channel – the velocity saturates completely and becomes essentially constant (vscl) T To gett some feel f l for f latter l tt two t cases, let's l t' first fi t estimate ti t the th E field fi ld using i simple long channel physics In saturation, the lateral field across the channel is
E =
B. Murmann
VOV L
e.g.
200mV V = 1.11⋅ 106 0.18μm m
EE214 Winter 2010-11 – Chapter 3
32
Field Estimates In our 0.18μm technology, we have for an NMOS device v = scl μ
Ec
Therefore
m s = 6.7 ⋅ 106 V ≅ cm2 m 150 Vs 105
V 1.11⋅ 106 E m = ≅ 0.16 V Ec 6.7 ⋅ 106 m
This means that for VOV on the order of 0.2V, the carrier velocity is p is relatively y small somewhat reduced,, but the impairment The situation changes when much larger VOV are applied, e.g. as the case in digital circuits
B. Murmann
EE214 Winter 2010-11 – Chapter 3
33
Short Channel ID Equation A simple equation that captures the moderate deviation from the long channel drain current can be written as (see text, p. 62) ID ≅
≅
1 W 2 1 μCox VOV ⋅ 2 L ⎛ VOV ⎞ ⎜1+ ⎟ ⎝ Ec L ⎠ E L ⋅ VOV 1 W VOV ⋅ c μCox 2 L (EcL + VOV ) Think of this as a “parallel combination"
V ⋅0 0.18 18μm = 1 1.2V 2V m
Minimum-length Minimum length NMOS:
Ec L = 6 6.7 7 ⋅ 106
Minimum-length PMOS:
EcL = 16.75 ⋅ 106
B. Murmann
V ⋅ 0.18μm = 3V m
EE214 Winter 2010-11 – Chapter 3
34
Modified gm/ID Expression Assuming VOV 30 ro will be negligible in this design problem
B. Murmann
EE214 Winter 2010-11 – Chapter 3
62
Zero and Pole Expressions
High frequency zero (negligible)
ωz ≅
gm >> ωT Cgd
Dominant pole (see Chapter 4)
ωp1 ≅
1 Ri ⎡⎣Cgs + Cgbb + (1 + gmRL ) ⋅ Cgdd ⎤⎦
Nondominant pole (see Chapter 4)
ωpp2 ≅
1 1 ωp1 Ri RL ⎡Cgs + Cgb ⎤ CL + ⎡Cgs + Cgd ⎤ Cdb + CLCgd ⎣ ⎦ ⎣ ⎦
(
Calculation of capacitances from tabulated parameters:
Cgs + Cgb = Cgg − Cgd
B. Murmann
Cdb = Cdd − Cgd
EE214 Winter 2010-11 – Chapter 3
63
Determine Cgg via fT Look-up
L=0 18um L=0.18um 16.9 GHz
B. Murmann
EE214 Winter 2010-11 – Chapter 3
64
)
Find Capacitances and Plug in
Cgg = Cgd = Cdd =
1 gm 1 4mS = = 37.7fF 37 7fF 2π fT 2π 16.9GHz Cgd Cgg
Cgg = 0.24 ⋅ 37.7fF = 9.0fF
Cdd Cgg = 0.60 ⋅ 39.4fF = 23.6fF Cgg
∴ fp2 ≅ 6.0 GHz
∴ fp11 ≅ 196 MHz
B. Murmann
EE214 Winter 2010-11 – Chapter 3
65
Device Sizing
16.2 A/m
B. Murmann
EE214 Winter 2010-11 – Chapter 3
L=0.18um
66
Circuit For Spice Verification
Device width
W=
ID
ID W
=
300μA = 18.5μm 16.2A / m
Simulation circuit
o
B i
1F
B. Murmann
EE214 Winter 2010-11 – Chapter 3
67
Simulated DC Operating Point element region id vgs vds vdsat vod gm gds ... cdtot cgtot cgd ... gm/ID
B. Murmann
0:mn1 Saturati 326.8330u 624.9116m 873.1670m 113.7463m 138.5878m 138 5878m 4.1668m 108.2225u
Calculation 300 uA
4 mS
21.8712f 37.6938f 8.9163f
23.6 fF 37.7 fF 9.0 fF
12.8
13.3 S/A
EE214 Winter 2010-11 – Chapter 3
Good agreement!
68
HSpice .OP Capacitance Output Variables
Corresponding Small Signal Model Elements
HSpice (.OP)
cdtot cgtot cstot cbtot cgs cgd
B. Murmann
≡ Cgd + Cdb cgtot ≡ Cgs + Cgd + Cgb cstot ≡ Cgs + Csb bt t ≡ Cgb + Csb+ Cdb cbtot cgs ≡ Cgs cgd ≡ Cgd cdtot
21.8712f 37.6938f 44.2809f 34.9251f 26.7303f 8.9163f
EE214 Winter 2010-11 – Chapter 3
69
Simulated AC Response
213 MHz 11.5 dB (3.8)
5.0 GHz
Calculated values: |Av(0)|=12 dB (4.0), fp1=196 MHz, fp2=6.0 GHz
B. Murmann
EE214 Winter 2010-11 – Chapter 3
70
Using .pz Analysis Netlist statement .pz v(vo) vi
Output *************************************************** ****** pole/zero analysis input = 0:vi output = v(vo) poles (rad/sec) real imag -1.34190g 0. -31.4253g 0.
poles ( hertz) real imag -213.569x 0. -5.00149g 0.
zeros (rad/sec) ( d/ ) real imag 458.247g 0.
zeros ( h hertz) t ) real imag 72.9323g 0.
B. Murmann
EE214 Winter 2010-11 – Chapter 3
71
Observations
The design and pole calculations essentially right on target! – Typical discrepancies are on the order of 10-20%, mostly due to VDS dependencies, finite output resistance, etc. We accomplished this by using pre-computed spice data in the design process Even if discrepancies are more significant, there’s always the possibility to track down the root causes – Hand calculations are based on parameters that also exist in Spice, e.g. gm/ID, fT, etc. – Different from square law calculations using μCox, VOV, etc. • Based on artificial parameters that do not exist or have no significance i ifi iin th the spice i model d l
B. Murmann
EE214 Winter 2010-11 – Chapter 3
72
References
F. Silveira et al. "A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-oninsulator micropower OTA, OTA," IEEE J. Solid Solid-State State Circuits, Sep. 1996, pp. 1314-1319. D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id," Proc. Int. Conf. on El t i Electronics, Circuits Ci it and dS Systems t , pp. 1179-1182, 1179 1182 S Sep. 2002 2002. B. E. Boser, "Analog Circuit Design with Submicron Transistors," IEEE SSCS Meeting, Santa Clara Valley, May 19, 2005, http://www ewh ieee org/r6/scv/ssc/May1905 htm http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm P. Jespers, The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits, Springer, 2010. T. Konishi, K. Inazu, J.G. Lee, M. Natsu, S. Masui, and B. Murmann, “Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology,” IEICE Trans. Electronics, Vol. E94-C, E94 C, No.3, Mar. 2011. B. Murmann
EE214 Winter 2010-11 – Chapter 3
73
Chapter 4 Review of Elementary Circuit Configurations
B. Murmann Stanford University y Reading Material: Sections 3.3.1, 3.3.3, 3.3.6, 3.3.8, 3.5, 7.2.3, 7.2.4.1, 7.3.2, 7.3.4, 4.2.2, 4.2.3, 4.2.4
Basic Single-Stage Amplifier Configurations
MOS Common Source
Common Gate
Common Drain
Common Emitter
Common Base
Common Collector
Bipolar
Transconductance Stage B. Murmann
Current Buffer
EE214 Winter 2010-11 – Chapter 4
Voltage Buffer 2
Widely Used Two-Transistor Circuits
MOS
Cascode Stage
Current Mirror
Differential Pair
Bipolar p
B. Murmann
EE214 Winter 2010-11 – Chapter 4
3
Analysis Techniques (1) N Nodal d l analysis l i (KCL (KCL, KVL) – Write KCL for each node, solve for desired transfer function or port impedance – Most general method method, but conveys limited qualitative insight and often yields high-entropy expressions Miller theorem
http://paginas.fe.up.pt/~fff/eBook/MDA/Teo_Miller.html
Miller approximation pp − Approximate the gain across Z as frequency independent, i.e. K(s) ≅ K for the frequency range of interest − This approximation pp requires q a check ((or g good intuition)) B. Murmann
EE214 Winter 2010-11 – Chapter 4
4
Analysis Techniques (2) Dominant D i t pole l approximation i ti 1 1 1 = ≅ 2 s s s s s2 ⎛ s ⎞⎛ s⎞ 1− + ⎜1 − ⎟⎜ 1 − ⎟ 1 − p − p + p p p1 p1p2 1 2 1 2 ⎝ p1 ⎠⎝ p2 ⎠ b 1 1 ⇒ p1 ≅ − , p2 ≅ − 1 Given 2 1 + b1s + b2s b1 b2
Zero value time constant analysis − The coefficient b1 can be found by summing all zero value time constants in the circuit b1 = ∑ τi Generalized time constant analysis − Can also find higher order terms (e.g. b2) using a sum of time constant products − A. Hajimiri, “Generalized Time- and Transfer-Constant Circuit Analysis,” IEEE Trans. Circuits Syst. I, pp. 1105-1121, June 2010. B. Murmann
EE214 Winter 2010-11 – Chapter 4
5
Analysis Techniques (3)
Return ratio analysis – See text pp. 599-612 Blackman’s impedance formula – See text pp. 607-612 Two Two-port port feedback analysis – See text pp. 557-587 – More later in this course
B. Murmann
EE214 Winter 2010-11 – Chapter 4
6
Chapter Overview
BJT-centric review of elementary circuit configurations – Highlight differences to MOS circuits Single-stage amplifiers – Common emitter stage – Common emitter stage g with source degeneration g – Common collector stage – Common base stage – Common gate stage (discussion of bulk connection) BJT current mirrors BJT differential pair
B. Murmann
EE214 Winter 2010-11 – Chapter 4
7
Common-Emitter Stage VCC
Vo
RL RS vi
~
Q1
+ VO+vo –
IB
VCC
VI Vi
Vi
DC input bias voltage (VI) biases Q1 in the forward active region Typically, want VO ≅ VCC/2 Main differences to consider versus common-source stage (MOS) – Bias point sensitivity – Finite input resistance (due to rπ) – Base resistance (rb) often significant B. Murmann
EE214 Winter 2010-11 – Chapter 4
8
Bias Point Sensitivity IB
IC = βFIB
RS
VI
+ VBE –
+ R Vo L –
Is e qVBE IB ≅
VI − VBE(on)
VCC
kT
VO = VCC − ICRL = VCC − βFIBRL = VCC − βF
RS
RL ( VI − VBE(on) ) RS
The dependence on βF makes “direct voltage biasing” impractical How to generate VI so as to control Vo? Practical configurations are usually based on feedback, replica biasing, ac coupling or differential circuits
B. Murmann
EE214 Winter 2010-11 – Chapter 4
9
Small-Signal Equivalent Circuit for CE Stage RS vi
+ v1 –
~
Cμ
1
rb
rπ
Cπ
2 gmv1
ro
RL
+ CL vo –
For hand analysis, we will usually neglect rc and re If significant, rb can be included with RS, i.e. RS* = RS + rb Resulting R lti llow-frequency f gain i
A V (0)
vo vi
ω=0
⎛ r ⎞ = − ⎜ * π ⎟⋅ gmRLtot ⎝ RS + rπ ⎠
RLtot Lt t = ro || RL
=1 for MOS B. Murmann
EE214 Winter 2010-11 – Chapter 4
10
Gate Tunnel Conductance for MOSFETS MOSFET MOSFETs with ith extremely t l thin thi gate t oxide id draw d a gate t currentt due d to t direct tunneling This leads to a finite current gain and input resistance – Similar to BJT!
A Annema A. Annema, et al al., “Analog Analog circuits in ultra-deep-submicron ultra deep submicron CMOS CMOS,” IEEE J. J Solid Solid-State State Circuits, Circuits pp. pp 132-143 132 143, Jan. Jan 2005 2005.
B. Murmann
EE214 Winter 2010-11 – Chapter 4
11
Frequency Response Using nodal analysis, we find
⎛ s⎞ 1− ⎟ ⎜ ⎛ r ⎞ z1 ⎠ v o (s) = − ⎜ * π ⎟⋅ gmRLtot ⎝ v i (s) 1 + b1s + b2s2 ⎝ RS + rπ ⎠
b1 = RS* (Cπ + Cμ ) + RLtot (CL + Cμ ) + gmRS* RLtotCμ b2 = RS* RLtot (CπCL + CπCμ + CLCμ ) z1 = +
gm Cμ
z1 is a feedforward zero in the RHP. If Cπ >> Cμ, then
z1 = +
B. Murmann
gm gm >> = ωT Cμ Cπ + Cμ
EE214 Winter 2010-11 – Chapter 4
12
Dominant Pole Approximation If a dominant d i t pole l condition diti exists, i t we can write it
p1 ≅ −
1 1 =− * b1 RS (Cπ + Cμ ) + RLtot (CL + Cμ ) + gmRS* RLtotCμ =−
p2 ≅ −
RS*
1 ⎡⎣Cπ + (1 + gmRLtot ) Cμ ⎦⎤ + RLtot (CL + Cμ )
RS* (Cπ + Cμ ) + RLtot (CL + Cμ ) + gmRS* RLtotCμ b1 =− b2 RS* RLtot ((CπCL + CπCμ + CLCμ )
If Cμ 1/RS*
power dissipation p must be − Note,, however,, that gm ((and hence the p increased) to maintain the same Av(0) Consider another special case where gmRE>>1 and the time constant due to Cμ is negligible ⎛ R* ⎞ C τ ≅ ⎜1+ S ⎟ π ⎝ RE ⎠ gm
B. Murmann
⎛ C + Cμ ⎞ ⎛ RE ⎞ ω−3dB ≅ ωT ⎜ π ⎟⎜ * ⎟ ⎝ C π ⎠ ⎝ RE + R S ⎠
EE214 Winter 2010-11 – Chapter 4
20
Common-Collector Stage (Emitter Follower) VCC RS vi
Q1
~
VO+vo
VI
IB
RL
CL
Behavior is very similar to MOS common drain stage, except that – We do not need to worry about backgate effect – There is finite input resistance due to rπ – The output resistance depends on RS (in addition to 1/gm)
B. Murmann
EE214 Winter 2010-11 – Chapter 4
21
Input and Output Resistance Input I t resistance i t (by (b inspection) i ti ) Ri ≅ rπ (1 + gmRL )
Output O resistance i ((using i push-through h h h trick) i k)
RS* = RS + rb
Ro ≅
B. Murmann
R* 1 1 ⎛ RS* ⎞ + S ≅ ⎜1+ ⎟ gm β + 1 gm ⎝ rπ ⎠
EE214 Winter 2010-11 – Chapter 4
22
Low Frequency Voltage Gain
vi
RS*
vb vo
Ri ≅ rπ (1 + gmRL )
A v0 = ≅
rπ (1 + gmRL ) vo vb vo gmRL = ≅ vi v i v b rπ (1 + gmRL ) + Rs* 1 + gmRL gmRL 1 + gmRL
≅1
B. Murmann
RL
for rπ (1 + gmRL ) >> Rs* for
gmRL >> 1 and rπ (1 + gmRL ) >> R s*
EE214 Winter 2010-11 – Chapter 4
23
Frequency Response
Zi
vo vb vo v Zi = ⋅ = ⋅ o vi v i v b Zi + R S v b
Detailed analysis gives a very complex result for the general frequency response expression i Must typically apply approximations based on given component values
B. Murmann
EE214 Winter 2010-11 – Chapter 4
24
Frequency Response Assuming that RS is large (often the case, and the reason why the stage is used), we expect that the dominant pole is introduced at node vb For the frequency q y range g up p until the dominant p pole,, we can therefore approximate
vo gmRL ≅ =K v b 1 + gmRL
Zi ≅
ωp ≅
1 1 = s ( Cπ [1 − K ] + Cμ ) sCi
1 (Rs Rin ) Ci
See text, pp. 503 for a more detailed analysis, which also captures the feedforward zero introduced by Cπ
B. Murmann
EE214 Winter 2010-11 – Chapter 4
25
Common Collector Output Impedance Detailed analysis of the common-collector output impedance shows potentially inductive behavior for large RS The inductive behavior can lead to undesired “ringing” ringing (or oscillations) during circuit transients In other cases, the inductive behavior is utilized for bandwidth extension ((“inductive inductive peaking”) peaking ) The capacitance Cμ tends to reduce the inductive frequency range – Cμ appears in parallel with RS, and creates a low impedance termination for high frequencies – Makes it difficult to use the circuit as a “good inductor” For a discussion on common collector output impedance and a detailed KCL-based analysis, see EE114 or section 7.2.3
B. Murmann
EE214 Winter 2010-11 – Chapter 4
26
Common-Base Stage VCC Ai =
RL io Ri Ii + ii
Ro
VO+vo
io ii
Ai (0) =
iC β = iE β + 1
Neglecting rb, rc, re and rπ, we have Ro ≅ ro (1 + gmRS )
RS (large)
Ri ≅
1 ⎛ RL ⎜1 + gm ⎝ ro
⎞ 1 ⎟≅ ⎠ gm
Behavior is very similar to MOS common base stage stage, except that – We do not need to worry about backgate effect – The DC current gain is not exactly unity, due to finite β
B. Murmann
EE214 Winter 2010-11 – Chapter 4
27
Simplified Small-Signal Model for High-Frequency Analysis
vo RL = ii ⎛ s ⎞⎛ s ⎞ ⎜ 1 − ⎟⎜ 1 − ⎟ ⎝ p1 ⎠⎝ p2 ⎠
ωp2 =
gm Cπ + Cμ = ωT Cπ Cπ
ωp1 =
1 RL CL
The time constant associated with the load usually dominates the frequency response, i.e. ωp1 < ωp2 Note, however, that ωp2 can be important in feedback circuits (phase margin) B. Murmann
EE214 Winter 2010-11 – Chapter 4
28
Common Gate Stage – Bulk Connection Scenarios Cgb
Cgb Cdb
Cdb
Cbsub (DWELL)
Cbsub (DWELL)
VDD Csb
Cgs
VDD
ii
ωp2,a =
Csb
Cgs ii
gm Cggs + Cggb + Cbsub + Cdb [1 − K(s)]
ωp2,b =
gm + gmb Cggs + Csb
ωp2,a is always less than ωp2,b Æ Usually a bad idea to connect source to gate stage g bulk in a common g B. Murmann
EE214 Winter 2010-11 – Chapter 4
29
Backgate Effect in the EE214 Technology (1)
B. Murmann
EE214 Winter 2010-11 – Chapter 4
30
Backgate Effect in the EE214 Technology (2)
B. Murmann
EE214 Winter 2010-11 – Chapter 4
31
Basic BJT Current Mirror
IOUT = IC2
IIN Q1
+ VBE –
Q2
+ Vo = VCE2 –
IC2 = IC1
IS2e IS1e
VBE VT VBE VT
⎛ VCE2 ⎞ ⎜1+ ⎟ VA ⎠ IS2 ⎛ VCE2 VCE1 ⎞ ⎝ ≅ − ⎜1+ ⎟ I V VA ⎠ ⎝ S1 A ⎛ VCE1 ⎞ ⎜1+ ⎟ VA ⎠ ⎝
Error due to base current
IIN = IC1 + IB1 + IB2 = IC1 +
IC1 IC2 I ⎞ ⎛ + ≅ IC2 ⎜ 1 + 2 C2 ⎟ β β β ⎠ ⎝
for IS1 = IS2
IOUT 1 2 ≅ ≅ 1− IIN β ⎛ 2⎞ ⎜1+ β ⎟ ⎝ ⎠ B. Murmann
EE214 Winter 2010-11 – Chapter 4
32
BJT Current Mirror with “Beta Helper” VCC
IIN
IOUT
Q3
+
IE3
Q1
− IE3 =
Q2 VOUT
IC1 IC2 I + ≅ 2 C2 β β β
assumin g IS1 = IS2
–
IB3 = −
IE3 2IC2 ≅ β + 1 β(β + 1)
IIN = IC1 + IB3 ≅ IC1 +
IOUT ≅ IIN
B. Murmann
1 ⎛ 2 1+ ⎜ 2 ⎜β +β ⎝
⎞ ⎟⎟ ⎠
≅ 1−
2IC2 ⎡ 2 ⎤ ≅ IC2 ⎢1 + ⎥ β(β + 1) ⎣ β(β + 1) ⎦
2 β2
EE214 Winter 2010-11 – Chapter 4
33
BJT Current Mirror with Degeneration IIN
IOUT + Q1
Q2 R1
IC2 =
R2
VOUT
Neglecting base currents
VBE1 + IC1R1 = VBE2 + IC2R2
–
⎡⎛ IC1 ⎞ ⎛ IS2 ⎞ ⎤ ⎫⎪ R1 1 ⎧⎪ ⎨IC1R1 + VT ln ⎢⎜ ⎟ ⎜ ⎟ ⎥⎬ ≅ IC1 R2 ⎩⎪ R2 ⎣⎝ IC2 ⎠ ⎝ IS1 ⎠ ⎦ ⎭⎪
IOUT R1 ≅ IIN R2
Degeneration brings two benefits – Increased output resistance – Reduces sensitivity of mirror ratio to mismatches in IS Minimum VOUT for which Q2 remains forward active is increased B. Murmann
EE214 Winter 2010-11 – Chapter 4
34
Differential Circuits
Vi1
+ –
Vo1
Vi2
– +
Vo2
Enables straightforward biasing without AC coupling Information is carried in “differential” signals that are insensitive to “common-mode” perturbations, such as power supply noise Fully differential circuits are increasingly used for I/O and clock-and-data recovery (CDR) circuits to allow the use of small signals at high speeds
B. Murmann
EE214 Winter 2010-11 – Chapter 4
35
BJT Differential Pair VCC RC1 Vo1
Vi1
Differential Input Voltage
RC2
IC1 Q1
Vid Vi1 − Vi2 Vo2
IC2 Q2
Vi2
Differential Collector Current Icd Ic1− Ic2
Differential Output Voltage ITAIL
RTAIL
Vod Vo1 − Vo2
VEE
The following large signal analysis neglects rb, rc, re, finite REE and assumes that the circuit is perfectly symmetric
B. Murmann
EE214 Winter 2010-11 – Chapter 4
36
Large Signal Analysis IC1 ≅ IS1 e
Vi1 − Vbe1 + Vbe2 − Vi2 = 0 I ⇒ c1 = e Ic2 ITAIL = − (Ie1+ Ie2) =
Vbe1 − Vbe2 VT
1 (Ic1+ Ic2) α
=e
Vbe1 VT
Vi1 − Vi2 VT
IC2 ≅ IS2 e
=e
Vid VT
αITAIL
⇒ Ic1 =
1+ e
⎡ ⎢ 1 1 Icd = Ic1 − Ic2 = αFITAIL ⎢ − Vid V − + id ⎢ VT 1 + e VT ⎣1 + e
Vbe2 VT
V − id VT
Ic2 =
αITAIL 1+ e
V + id VT
⎤ ⎛ Vid ⎞ ⎥ ⎥ = αFITAIL tanh ⎜ 2V ⎟ ⎝ T⎠ ⎥ ⎦
⎛ V ⎞ Vod = IodRL = αITAILRL tanh ⎜ id ⎟ ⎝ 2VT ⎠ B. Murmann
EE214 Winter 2010-11 – Chapter 4
37
Plot of Transfer Characteristics
Text, p. 215
Text, p. 216
Linear region in Vod vs. vs Vid characteristic is narrow compared to MOS – Recall that full steering in a MOS pair occurs for Vid = 2VOV BJT differential pair is linear only for |Vid| < VT ≅ 26 mV
B. Murmann
EE214 Winter 2010-11 – Chapter 4
38
Emitter Degeneration C Can use emitter itt degeneration d ti resistors i t tto iincrease th the range off iinputt voltage over which the transfer characteristic of the pair is linear For large RE, linear range is approximately equal to ITAILRE VCC RC
RC
Text, p. 217
Vo2
Vo1 Q1
Vi1
Q2
RE
Vi2 RE
ITAIL VEE B. Murmann
EE214 Winter 2010-11 – Chapter 4
39
Voltage Decomposition
Common-Mode Voltages
VCC
1 Vic (Vi1 + Vi2 ) 2 1 Voc (Vo1 + Vo2 ) 2
RC1 Voc+Vod/2
Inputs Vi1 and Vi2 can be decomposed into a combination of differentialdifferential and common common-mode mode voltage sources 1 Vi1 = Vic + Vid 2 1 Vi2 = Vic − Vid 2
B. Murmann
RC2 Voc–Vod/2 Q1
Vid/2
Q2 –V Vid/2
ITAIL VEE
Vic
EE214 Winter 2010-11 – Chapter 4
40
Small Signal Model for vic = 0
Text, p. 224
Define differential mode gain as
B. Murmann
A dm
v od v id
vic = 0
EE214 Winter 2010-11 – Chapter 4
41
Differential Mode Half Circuit
Text, p. 225
v od v = −gmR id 2 2
B. Murmann
A dm =
v od = −gmR v id
EE214 Winter 2010-11 – Chapter 4
42
Small Signal Model for vid = 0
Text, p. 227
Define common mode gain as
B. Murmann
A cm
v od v id
vid = 0
EE214 Winter 2010-11 – Chapter 4
43
Common Mode Half Circuit
Text, p. 227
v oc = −GmRv ic
B. Murmann
A cm =
v oc gmR = −GmR = − v ic 1 + 2gmRTAIL
EE214 Winter 2010-11 – Chapter 4
44
Interaction of Common Mode and Differential Mode
A cdm
v od v ic i
A dcm
and vid = 0
v oc v id
vic = 0
In a perfectly balanced (symmetric) circuit, Acdm = Adcm = 0 In practice, Acdm and Adcm are not zero because of component mismatch Acdm is i iimportant t t because b it iindicates di t th the extent t t tto which hi h a commonmode input will corrupt the differential output (which contains the actual signal information) See S ttext, t section ti 3.5.6.9 3 5 6 9 ffor a d detailed t il d analysis l i
B. Murmann
EE214 Winter 2010-11 – Chapter 4
45
Common-Mode Rejecton For fully differential circuits, the common-mode rejection ratio (CMRR) is traditionally defined as CMRR
A dm A cdm
However, the text defines the ratio as CMRR Text T
A dm A cm
This latter definition is appropriate for circuits with a differential input and single-ended output, such as operational amplifiers.
B. Murmann
EE214 Winter 2010-11 – Chapter 4
46
Input-Referred DC Offsets In I a perfectly f tl symmetric t i circuit, i it Vid = 0 yields i ld Vod = 0 Imbalances can be modeled as input referred offsets VCC
VCC
RC1
Vo2
Vo1 IB1 Vi1
RC
RC2
Q1
Vo2
Vo1
Q2
–
Vi1
Vi2
Vos
+
Q1
Q2
Ios/2
Vi2 IB2
RC
IEE
IEE
OFFSETS
VEE PAIR W/ MISMATCH B. Murmann
VEE IDEAL PAIR
EE214 Winter 2010-11 – Chapter 4
47
Analysis Vos − VBE1 + VBE2 = 0 ⎛I ⎞ ⎛I ⎞ ∴ Vos = VT ln ⎜ C1 ⎟ − VT ln ⎜ C2 ⎟ ⎝ IS1 ⎠ ⎝ IS2 ⎠ ⎡⎛ I ⎞ ⎛ I ⎞ ⎤ = VT ln ⎢⎜ C1 ⎟ ⎜ S2 ⎟ ⎥ , ⎢⎣⎝ IC2 ⎠ ⎝ IS1 ⎠ ⎥⎦
where VT =
kT q
If Vod = 0, then IC1RC1 = IC2RC2 ∴
Thus
B. Murmann
IC1 IC2
=
RC2 RC1
⎡⎛ R ⎞ ⎛ I ⎞ ⎤ Vos = VT ln ⎢⎜ C2 ⎟ ⎜ S2 ⎟ ⎥ ⎢⎣⎝ RC1 ⎠ ⎝ IS1 ⎠ ⎥⎦ EE214 Winter 2010-11 – Chapter 4
48
Result For small mismatches ΔRC 1, then A≅
a 1 = T f
The feedback loop acts to minimize the error signal, Sε, thus forcing Sfb to t track t k Si. In I particular, ti l ⎛ a ⎞ ⎛ af ⎞ Sε = Si − f ⋅ So = Si − f ⋅ ⎜ Si = ⎜ 1 − ⋅S ⎟ ⎝ 1 + aff ⎠ ⎝ 1 + aff ⎟⎠ i ∴
B. Murmann
Sε Si
= 1−
T 1 = 1+ T 1+ T
and
⎛S ⎞ Sfb T = a⋅f⎜ ε ⎟ = Si ⎝ Si ⎠ 1+ T
EE214 Winter 2010-11 – Chapter 5
4
Gain Sensitivity Th The ffeedback db k network t k is i ttypically i ll a precision i i passive i network t k with ith an insensitive, well-defined transfer function f. The forward amplifier gain is generally large, but not well controlled. F Feedback db k acts t to t reduce d nott only l the th gain, i b butt also l th the relative, l ti or fractional, gain error by the factor 1+T
dA d ⎛ a ⎞ 1 d ⎛ 1 ⎞ = +a ⎜ = ⎜ ⎟ da da ⎝ 1+ af ⎠ 1+ af da ⎝ 1+ af ⎟⎠ =
(1+ af) − af (1+ af)
2
=
1 (1+ af)
2
=
1 (1+ T)2
For a change δa in a
δ = δa ∴ B. Murmann
dA δa δ = δa da (1+ T)2
δA δa ⎛ 1+ T ⎞ ⎛ 1 ⎞ δa = = A (1+ T)2 ⎜⎝ a ⎟⎠ ⎜⎝ 1+ T ⎟⎠ a EE214 Winter 2010-11 – Chapter 5
5
The Two-Port Approach to Feedback Amplifier Design A practical approach to feedback amplifier analysis and design is based on constructing two-port representations of the forward amplifier and feedback network The two two-port port approach relies on the following assumptions: – Loading effects can be incorporated in the two-port model for the forward amplifier – Transmission through the forward amplifier is nearly unilateral – Forward transmission through the feedback network is much less than that through the forward amplifier When the preceding assumptions break down, the two-port approach deviates from from, and is less accurate than than, the return ratio approach devised by Henrik Bode But, the two-port approach can provide better physical tuition, especially with respect p to what happens pp in the frequency q y domain when the feedback loop is “closed” – It is basically an effort to model feedback amplifiers in the way that Harold Black conceived them
B. Murmann
EE214 Winter 2010-11 – Chapter 5
6
Feedback Configurations IIn the th two-port t t approach h to t feedback f db k amplifier lifi analysis l i th there are ffour possible amplifier configurations, depending on whether the two-port networks are connected in SHUNT or in SERIES at the input and output p of the overall amplifier
At the OUTPUT – A shunt connection senses the output voltage – A series connection senses the output current
At the INPUT – A shunt connection feeds back a current in parallel with the input – A series connection feeds back a voltage in series with the input
The four possible configurations are referred to as SERIES-SHUNT, SERIES SHUNT, SHUNT-SHUNT, SHUNT-SERIES, and SERIES-SERIES feedback The following pages illustrate these configurations using ideal two-port networks B. Murmann
EE214 Winter 2010-11 – Chapter 5
7
Series-Shunt Feedback
+
+
a
vε –
+
vo –
vi –
+
+
–
–
vfb
f
a=
vo v , f = fb vε vo
A=
vo a a = = v i 1+ af 1+ T
In this case a, A and f are all voltage gains
B. Murmann
EE214 Winter 2010-11 – Chapter 5
8
Shunt-Shunt Feedback iε ii
+
vo
a
–
ifb f
a=
vo i , f = fb iε vo
A=
vo a a = = 1+ af 1+ T ii
a and A are transimpedances; f is a transadmittance
B. Murmann
EE214 Winter 2010-11 – Chapter 5
9
Shunt-Series Feedback iε ii
a
io
ifb f
a=
io i , f = fb iε io
A=
io a a = = ii 1+ af 1+ T
a, A, and f are current gains
B. Murmann
EE214 Winter 2010-11 – Chapter 5
10
Series-Series Feedback
+
+
a
vε
io
–
vi –
+
+
–
–
vfb
f
a=
io v , f = fb vε io
A=
io a a = = v i 1+ af 1+ T
a and A are transadmittances; f is transimpedance
Note: T = af is always y dimensionless B. Murmann
EE214 Winter 2010-11 – Chapter 5
11
Closed Loop Impedances T To illustrate ill t t the th influence i fl off feedback f db k on the th input i t and d output t t impedances i d off an amplifier, consider the following: – Include finite input and output impedances in a simple, idealized two-port model of the forward amplifier – Assume that the feedback network has ideal input and output impedances so as not to load the forward amplifier Consider two examples, series-shunt and shunt-series amplifiers SERIES-SHUNT io vε
B. Murmann
avε
EE214 Winter 2010-11 – Chapter 5
12
“Ideal” Series-Shunt Impedances Input Impedance
vi ii
Zi
O t t Impedance Output I d
Zo
io = 0
With io = 0
vi = 0
With vi = 0
v o = av ε
v ε + fv o = v i = 0
v i = v ε + fv o = (1+ af)v ε
io =
= (1+ T)v ε ii =
vo io
vε zi
Zi =
=
1⎛ 1 ⎞ v zi ⎜⎝ 1+ T ⎟⎠ i
=
vi = (1+ T)z i ii
v o − av ε zo
1 1+ af v o zo
(
)
1 (1+ T)v o zo
Zo =
B. Murmann
=
vo z = o io 1+ T
EE214 Winter 2010-11 – Chapter 5
13
“Ideal” Shunt-Series Impedances Basic amplifier p
iε
zi
ii
io +
aiε
zo vo
ifb f io
Input Impedance
Zi
vi ii
With vo = 0
–
v o =0
io = aiε i i= iε + fio = (1+ af) iε = (1+ T)iε
⇒
⎛ i ⎞ v i = iε zi = ⎜ i ⎟ zi ⎝ 1+ T ⎠ B. Murmann
EE214 Winter 2010-11 – Chapter 5
Zi =
vi zi = i i (1+ T)
14
O t t Impedance Output I d
Zo With ii = 0
vo io
i i= 0
iε + fio = 0 v o = (io + aiε )zo = (io + afio )zo
⇒
Zo =
= io (1+ T)zo
vo = (1+ T)zo io
In general: • Negative feedback connected in series increases the driving point impedance by (1+T) • Negative feedback connected in shunt reduces the driving point impedance by (1+T)
B. Murmann
EE214 Winter 2010-11 – Chapter 5
15
Loading Effects – Introductory Example Consider C id th the ffollowing ll i ffeedback db k circuit i it
Analysis methods
− Closed loop transfer function using nodal analysis − Return ratio analysis (see EE114) − Two-port feedback circuit analysis
B. Murmann
EE214 Winter 2010-11 – Chapter 5
16
Nodal Analysis Given v1 − vo
0
− ii
RF vo − v1
0
+ g m⋅ v 1 +
RF
vo RL
⎛⎜ RF⋅ ii + RL⋅ ii ⎞⎟ RL⋅ g m + 1 ⎜ ⎟ Find( v 1 , v o ) → ⎜ ⎟ ⎜ RL⋅ ii − RF⋅ RL⋅ g m⋅ ii ⎟ ⎜ ⎟ RL⋅ g m + 1 ⎝ ⎠
A
vo
RL − RF⋅ RL⋅ g m
ii
RL⋅ g m + 1
⎛1− ⎜ −RF⋅ ⎜ ⎜ ⎜1+ ⎝
⎞ ⎟ ⎟ 1 ⎟ g m⋅ RL ⎟ ⎠ 1
g m⋅ RF
No information about loop gain (which we need e.g. for stability analysis)
B. Murmann
EE214 Winter 2010-11 – Chapter 5
17
Return Ratio Analysis A
A
A inf ⋅
−RF
RR 1 + RR
+
g m⋅ RL 1 + g m⋅ RL
d
A inf
1 + RR
+
RL 1 + g m⋅ RL
−RF
d
RL
R ⎞ ⎛ ⎛1− ⎜ g m⋅ RL − L ⎟ ⎜ R ⎜ F⎟ −RF⎜ −RF⋅ ⎜ ⎜ 1 + g m⋅ RL ⎟ ⎝ ⎠ ⎜1+ ⎝
RR
g m⋅ RL
⎞ ⎟ ⎟ 1 ⎟ g m⋅ RL ⎟ ⎠ 1
g m⋅ RF
The result for the closed loop gain (A) matches the nodal analysis perfectly In addition, addition we have determined (along the way) the loop gain (RR) – This is useful for stability analysis The return ratio method is accurate and general The two-port method aims to sacrifice some of this accuracy and generality in exchange for better intuition and less computational effort – The involved approximations follow from the typical design intent for each of the four possible approximations B. Murmann
EE214 Winter 2010-11 – Chapter 5
18
Shunt-Shunt Feedback Model iε ii
+
vo
a
–
ifb f
RF feeds back a current that is proportional to the output voltage – The appropriate two-port model to use for this amplifier is therefore the “shunt-shunt” configuration We wish to identify proper “a” a and “ff “ blocks that model our circuit The key issue is that “a” and “f” are not perfectly separable without making any approximations – RF is responsible for feedback feedback, but also affects the behavior of “a” a B. Murmann
EE214 Winter 2010-11 – Chapter 5
19
y-Parameter Model for the Feedback Network (1)
B. Murmann
EE214 Winter 2010-11 – Chapter 5
20
y-Parameter Model for the Feedback Network (2)
y11f =
1 RF
y 21f = −
B. Murmann
1 RF
y12f = −
1 RF
y 22f =
1 RF
EE214 Winter 2010-11 – Chapter 5
21
y-Parameter Model for the Feedback Network (3)
Final steps – Absorb y11 and y22 into forward amplifier – Neglect feedforward through feedback network (y21) • This is justified by the usual design intent: we do not want the feedforward through the feedback network to be significant! B. Murmann
EE214 Winter 2010-11 – Chapter 5
22
Identification of “a” and “f”
iε ii
+
vo
a
–
ifb f
f
A
B. Murmann
−
1
a
RF
1 f
⋅
1 1+
1 aff
vo v1 ⋅ v 1 ie
−g m⋅
RL⋅ RF RL + RF
⋅ RF
af
g m⋅
RL⋅ RF RL + RF
1
RF 1+
1 RF + RL ⋅ g m RF⋅ RL EE214 Winter 2010-11 – Chapter 5
23
Comparison and Generalization
Note that for RL y21f in which case ⎛ −y21a ⎞ ⎜ yy ⎟ vo ⎝ i o ⎠ A= = iS ⎛ −y ⎞ 1+ ⎜ 21a ⎟ y12f ⎝ yiyo ⎠
B. Murmann
⇒
a=−
y21a yiyo
f = y12f
EE214 Winter 2010-11 – Chapter 5
29
For the simplified definitions, definitions it is possible to identif identify separate eq equivalent i alent circuits for a and f : yi
New forward amplifier
yo
iS
yi = yS + y11a + y11f yo = yL + y22a + y22f New feedback network
The admittances yS, y11a, y22f and yL have been “pulled” into the forward amplifier. Basically, the “loading” of the feedback network, as well as the source and load admittances, is absorbed in the equivalent forward amplifier. B. Murmann
EE214 Winter 2010-11 – Chapter 5
30
Example – Op Amp w/ Shunt-Shunt Feeback
iS
Small-signal equivalent circuit: Feedback network
ro iS
B. Murmann
ri
EE214 Winter 2010-11 – Chapter 5
31
I order In d to d determine i the h lloading di off the h ffeedback db k network k on the h fforward d amplifier, the y parameters of the feedback network are first determined using the following circuit :
y11f = y22f =
y12f =
i1 v1 i2 v2
i1 v2
=
1 RF
=
1 RF
v 2 =0
v1 =0
=− v1 =0
1 =f RF
Also, y21f = –1/RF, but it is neglected in comparison with y21a
B. Murmann
EE214 Winter 2010-11 – Chapter 5
32
Th overallll circuit The i i can now b be separated d iinto fforward d and d ffeedback db k paths, h with the loading of the feedback network included within the forward path Forward amplifier f
ro iS
ri
B. Murmann
EE214 Winter 2010-11 – Chapter 5
33
To determine the forward amplifier gain gain, a a, break the feedback loop at the “output” of the feedback network by setting ifb = 0. Then
⎛ r i RF ⎞ v1 = (r i PRF )iS = ⎜ ⎟ iS ⎝ r i + RF ⎠ ⎛ R ⎞ vo = − ⎜ ⎟ a v v1 ⎝ R + ro ⎠
Thus a=
vo iS
i fb = 0
where R
RF RL
⎛ r i RF ⎞ ⎛ R ⎞ = −a av ⎜ ⎟⎜ ⎟ ⎝ r i + RF ⎠ ⎝ R + ro ⎠
Since f = –1/RF, the loop p gain, g , T = af,, is
⎛ r i ⎞ ⎛ R PR ⎞ ⎛ ri ⎞ ⎛ ⎞ RLRF F L T = av ⎜ ⎟⎜ ⎟ = av ⎜ ⎟⎜ ⎟ ⎝ r i + RF ⎠ ⎝ RF PRL + ro ⎠ ⎝ r i + RF ⎠ ⎝ RLRF + roRF + roRL ⎠ B. Murmann
EE214 Winter 2010-11 – Chapter 5
34
The input and output impedances of the equivalent forward amplifier are zia = RF || ri zoa = ro || RF || RL Since the feedback network is connected in shunt at both the input and output of the forward amplifier, the closed-loop input and output impedances are RF || ri zia i = 1+ T 1+ T zoa ro || RF || RL Zo = = 1+ T 1+ T Zi =
B. Murmann
EE214 Winter 2010-11 – Chapter 5
35
Series-Series Feedback In a series-series feedback amplifier, p the forward amplifier p and feedback network share common currents at the input and output. Therefore, open circuit impedance parameters (z parameters) are used to characterize the two-port networks.
v1 = z11 i1 + z12 i2 v 2 = z 21 i1 + z 22 i2 where z11
v1 i1 i
z12
v2 i1
z22
2 =0
z21 B. Murmann
i2 = 0
v1 i2 i
1=0
v2 i2
EE214 Winter 2010-11 – Chapter 5
i1 = 0 36
Series-Series Feedback, cont’d The two-port representation of a series-series feedback amplifier is then Forward amplifier
io ii
vS
B. Murmann
EE214 Winter 2010-11 – Chapter 5
37
Series-Series Feedback, cont’d Summing voltages at the input and output v S = (z S + z11a + z11f )ii + (z12a + z12f )io 0 = (z ( 21a + z 21f )i i + (z ( L + z 22a + z 22f )io
Define
zi
zS + z11a + z11f
zo
zL + z22a + z22f
Again, g , neglect g reverse transmission through g the forward amplifier p and feedforward through the feedback network; that is, assume z12a > z 21f
B. Murmann
EE214 Winter 2010-11 – Chapter 5
38
Series-Series Feedback Equations Under the preceding assumptions, the series-series feedback amplifier can be represented by a two-port model with ⎛ −z ⎞ 21a ⎜ ⎟ io ⎝ z i zo ⎠ a A= = = vS ⎛ −z 1+ af z ⎞ 1+ ⎜ 21a ⎟ z12f ⎝ z i zo ⎠
where a=−
z 21a z i zo
f = z12f
B. Murmann
EE214 Winter 2010-11 – Chapter 5
39
Series-Series Feedback Equivalent Two-Port Networks Equivalent two two-port port networks can now be identified for a and f in which the loading of the feedback network is included in the forward amplifier New forward amplifier
vS
B. Murmann
EE214 Winter 2010-11 – Chapter 5
40
Series-Series Triple io
AC circuit : Q3 Q2
RS + vS ~ –
Q1
ii
RC1
iE1
RC2
RF
RE1
RL
iE3
RE2
Feedback Network
The forward amplifier in this circuit is NOT a two-port network because iE1 ≠ ii and iE3 ≠ io. However, However because iE1 and iE3 are closely related to ii and io, a two-port approach to feedback analysis can still be used. Begin g by y representing p g the feedback network as a two-port p network. B. Murmann
EE214 Winter 2010-11 – Chapter 5
41
io Q3 RS + vS ~ –
ii
Q2 Q1 iE1
RC2
RC1
z11f + ~ z12f iE3 –
RL
iE3
z22f + z21f iE1 ~ –
At the output, simply recognize that the feedback network “senses” iE3 rather than io, and that i iE3 = o α3 In effect, α3 is outside the feedback loop B. Murmann
EE214 Winter 2010-11 – Chapter 5
42
At the input, input consider the following small-signal equivalent circuit RS + vS –
ii
+ vπ1 –
gm1vπ1
rπ1 iE1
z11f + z12f iE3 –
v S = iiRS + v π1 + iE1z11f + z 12f iE3
∴ v S − z 12f ⋅
io = i R + v π1 + iE1z11f α3 i S
From this equation it is apparent that, although the z12f feedback voltage generator is in the emitter of Q1, it is still in series with, and subtracts from, the input voltage source, vS. Thus, the z12f generator can be moved f from the th emitter itt to t the th base b off Q1 B. Murmann
EE214 Winter 2010-11 – Chapter 5
43
Next, N t to t determine d t i the th z parameters t for f the th feedback f db k network, t k consider id the th following circuit RF + v1 –
i1
v z 12f = 1 i2
RE1
i1 =0
RE2
+ v2 –
⎛ ⎛ RE1 ⎞ v 2 ⎜ =⎜ ⎟ ⎝ RE1 + RF ⎠ ⎜ i 2 ⎝
z 11f = i2 z 22f =
v1 i1
= RE1 || (RF + RE2 ) i2 =0
v2 i2
= RE2 || (RF + RE1) i1 =0
⎞ ⎛ RE1 ⎞ ⎟= z ⎟ ⎜⎝ RE1 + RF ⎟⎠ 22f i1 =0 ⎠
⎛ RE1 ⎞ ⎡ RE2 (RE1 + RF ) ⎤ RE1 RE2 =⎜ ⎢ ⎥= ⎟ ⎝ RE1 + RF ⎠ ⎣ RE1 + RE2 + RF ⎦ RE1 + RE2 + RF z21f = z12f, but z21f is neglected in comparison with z21a B. Murmann
EE214 Winter 2010-11 – Chapter 5
44
Based B d on th the preceding di results, lt th the series-series i i ttriple i l can b be modeled d l d with the following equivalent circuit io Q3 Q2
RS
Q1
– ~ vfb=vf + + vS ~ –
RE1
RC2
RC1
RF
RF
RE2
+ vf –
RL
iE3
RE2 RE1
In this circuit we have managed to “break” the loop at the output of the feedback network. network Thus Thus, the circuit can be used to determine a a, f and T T. B. Murmann
EE214 Winter 2010-11 – Chapter 5
45
Note that a and f for the series-series triple can be defined in terms of either io or iE3. If A=
io i = α 3 E3 vS vS
and a and f are defined with respect to io, then f=
⎞ z12f RE1RE2 1 ⎛ = ⎜ α 3 ⎝ RE1 + RE2 + RF ⎟⎠ α3
As T = af becomes large A≅
⎛ R + R + RF ⎞ 1 = α3 ⎜ E1 E2 ⎟ f RE1RE2 ⎝ ⎠
Thus,, A is not desensitized to α3 by y the feedback loop p B. Murmann
EE214 Winter 2010-11 – Chapter 5
46
Series-Shunt Feedback In a series series-shunt shunt feedback amplifier, amplifier the forward amplifier and feedback network share the same input current and output voltage. Therefore a hybrid h-parameter representation is used for the two-port networks.
v1 = h11 i1 + h12 v 2 i2 = h21 i1 + h22 v 2 where h11
h21 B. Murmann
v1 i1 i2 i1
h12 v 2 =0
h22 v 2 =0
v1 v2
i1 = 0
i2 v2
i1 = 0
EE214 Winter 2010-11 – Chapter 5
47
Series-Shunt Feedback, cont’d Thus, the two-port model for a series-shunt feedback circuit is Forward amplifier
ii
vS
B. Murmann
EE214 Winter 2010-11 – Chapter 5
48
Series-Shunt Feedback, cont’d Summing voltages at the input and currents at the output,
v S = (zS + h11a + h11f )ii + (h12a + h12f ) v o 0 = (h21a + h21f )i i + (yL + h22a + h22f )io Define
zi
zS + h11a + h11f
yo
yL + h22a + h22f
and neglect reverse transmission through the forward amplifier and feedforward through the feedback network; that is, assume h12a > h21f B. Murmann
EE214 Winter 2010-11 – Chapter 5
49
Series-Shunt Feedback Equations With the simplifying assumptions, the series-series feedback amplifier can be represented by a two-port model with ⎛ −h ⎞ 21a ⎜ ⎟ z y vo ⎝ i o ⎠ a A= = = vS ⎛ −h 1+ af h ⎞ 1+ ⎜ 21a ⎟ h12f ⎝ z i yo ⎠
where a=−
h21a z i yo
f = h12f
B. Murmann
EE214 Winter 2010-11 – Chapter 5
50
Series-Shunt Feedback Equivalent Two-Port Networks Equivalent E i l t ttwo-portt circuits i it can now b be id identified tifi d for f a and d f in i which hi h th the loading of the feedback network is included in the forward amplifier New forward amplifier
ii
yo
zi
+ vo –
vS
B. Murmann
EE214 Winter 2010-11 – Chapter 5
51
Shunt-Series Feedback In a shunt-series feedback circuit, circuit the forward amplifier and feedback network share the same input voltage and output current. Thus, a hybrid gparameter representation is used for the two-port networks.
i1 = g11v1 + g12 i2 v 2 = g21v1 + g22 i2 where g11
i1 v1 i
g12
v2 v1
g22
2 =0
g21 B. Murmann
i2 =0
i1 i2
v1 = 0
v2 i2
EE214 Winter 2010-11 – Chapter 5
v1=0 52
Shunt-Series Feedback, cont’d The two-port model for a shunt-series feedback amplifier is thus Forward amplifier
iS
B. Murmann
EE214 Winter 2010-11 – Chapter 5
53
Shunt-Series Feedback, cont’d Summing currents at the input and voltages at the output, iS= (yS + g11a + g11f )v i + (g12a + g12f )io 0 = (g21a + g21f )v i + (zL + g22a + g22f )io Define
yi
y S + g11a + g11f
zo
zL + g22a + g22f
and neglect reverse transmission through the forward amplifier and feedforward through the feedback network; that is, assume g12a > g21f B. Murmann
EE214 Winter 2010-11 – Chapter 5
54
Shunt-Series Feedback Equations With the simplifying assumptions the shunt-series feedback circuit can described in the form of the ideal feedback equation ⎛ −g21a ⎞ ⎜ yz ⎟ i ⎝ i o ⎠ a A= o = = iS ⎛ −g 1+ af g ⎞ 1+ ⎜ 21a ⎟ g12f ⎝ yi zo ⎠
where a=−
g21a y i zo
f = g12f
B. Murmann
EE214 Winter 2010-11 – Chapter 5
55
Shunt-Series Feedback Equivalent Two-Port Networks Based on the above definitions and assumptions, equivalent two-port networks for a shunt-series amplifier can be defined as follows N New fforward d amplifier lifi
zo + iS
vi
io yi
–
B. Murmann
EE214 Winter 2010-11 – Chapter 5
56
Shunt-Series Feedback Pair io
AC circuit: Q2 iS
Q1
+ vi –
RS
RC1
RF
RL
iE2
RE
Feedback network
The forward amplifier in this circuit is not a two-port network b because io ≠ iE2. However, H th the circuit i it can b be analyzed l d iin a ffashion hi similar to the series-series triple. The feedback network can be represented by a two-port characterized by g parameters.
B. Murmann
EE214 Winter 2010-11 – Chapter 5
57
io Q2 iS
Q1
+ vi –
RS
g11f
RC1
RL
iE2 g22f + ~ g21f vi –
g12f iE2
The g parameters for the feedback network can be determined from the following circuit : i1
+ v1 –
B. Murmann
~
RF RE
+ v2 –
EE214 Winter 2010-11 – Chapter 5
i2
58
g11f =
i1 v1
g 22f =
g12f =
g21f =
= i2 = 0
v2 i2
= RE || RF v1 = 0
i1 i2
1 RE + RF
=− v1 = 0
v2 v1
RE RE + RF
= − g12f i2 = 0
g21f is neglected in comparison with g21a The shunt-series p pair can then be redrawn as follows : B. Murmann
EE214 Winter 2010-11 – Chapter 5
59
io Q2 iS
+ vi –
Q1 RF+RE
RC1
RS
iF
iE2 = –iiF
RF
RL
iE2
RE
A i we’ve Again, ’ managed d tto b break k th the lloop att th the output t t off th the ffeedback db k network. If a and f are defined in terms of io, then
B. Murmann
A=
io i = α 2 E2 iS iS
f=
iF g ifb 1 ⎛ RE ⎞ = − = 12f = − io io α2 α 2 ⎜⎝ RE + RF ⎟⎠ EE214 Winter 2010-11 – Chapter 5
60
Chapter 6 Frequency Response of Feedback Amplifiers B. Murmann Stanford University y Reading Material: Section 9.1, 9.2, 9.3, 9.4, 9.5
Gain and Bandwidth Consider a feedback amplifier with a single pole in the response of the forward-path amplifier and feedback that is frequency independent. vi
+
–
–
a(s)
vo
vfb f
a(s) =
a0 1− s p1
A(s)
v o (s) a(s) a(s) = = v i (s) 1+ a(s) ⋅ f 1+ T(s)
where T(s) B. Murmann
a(s) ⋅ f = "Loop Loop Gain Gain" EE214 Winter 2010-11 – Chapter 6
2
a0 a0 1− s p1 A(s) = = s a0 f 1− + a0 f 1+ p1 1− s p1 1 =
a0 ⋅ 1+ a0 f
= Ao ⋅
1 1−
s⎛ 1 ⎞ p1 ⎜⎝ 1+ a0 f ⎟⎠ 1
⎡ ⎤ s 1− ⎢1 ⎥ ⎣ p1(1+ T0 ) ⎦
where A 0 = A(0) =
a0 1+ a0 f
T0 = T(0) = a(0) ⋅ f = a0 f = "Low Frequency Loop Gain" B. Murmann
EE214 Winter 2010-11 – Chapter 6
3
Thus, feedback reduces the gain by (1+T0) and increases the –3dB bandwidth by (1+T0) for a “one-pole” forward-path amplifier. The Gain x Bandwidth (GBW) product remains constant.
20 log10 a0 20 log10 |a(jω)| 20 log10 (1+T0)
20 log10 A0
20 log10 |A(jω)|
|p1|
B. Murmann
(1+T0)|p1|
EE214 Winter 2010-11 – Chapter 6
4
Locus of the pole of A(s) in the s-plane: jω s plane s-plane
x
x
(1+T0)p1
p1
σ
Pole “moves” from p1 to (1+T0)p1 Note that ⎛a ⎞ 20 ⋅ log g10 a0 − 20 ⋅ log g10 A0 = 20 ⋅ log g10 ⎜ 0 ⎟ ⎝ A0 ⎠ = 20 ⋅ log10 (1+ T0 ) ≅ 20 ⋅ log g10 T0 B. Murmann
when T0 >> 1
EE214 Winter 2010-11 – Chapter 6
5
At the frequency ω0 = (1+T0)|p1| a(jω 0 ) = A0 and therefore T(jω 0 ) = a(jω 0 ) ⋅ f = A 0 f =
a0 f 1+ a0 f
≈1 Thus, ω0 is the unity-gain bandwidth of the loop gain, T(s).
B. Murmann
EE214 Winter 2010-11 – Chapter 6
6
Instability At a frequency where the phase shift around the loop of a feedback amplifier reaches ±180o the feedback becomes positive. In that case, pg gain is g greater than unity, y, the circuit is unstable. if the loop For a “single-pole” forward path amplifier stability is assured because the maximum phase shift is 90o. However, if a(s), or in general T(s), has multiple poles poles, the amount of loop gain that can be used is constrained. y of a feedback amplifier p can be assessed from: The stability – Nyquist diagram (polar plot of loop gain with frequency as a parameter) – Bode B d plot l t (plot ( l t off loop l gain i and d phase h as ffunctions ti off ffrequency)) – Locus of poles (root locus) of A(s) in the s-plane
B. Murmann
EE214 Winter 2010-11 – Chapter 6
7
Bode Stability Criterion
A feedback system is unstable when |T(jω)| > 1 at the frequency where Phase[T(jω)] = -180° Phase margin – Defined at the frequency where |T(jω)| =1 1 Æ ω0
PM = 180° + Phase ⎡⎣T ( jω0 ) ⎤⎦ Gain margin – Defined at the frequency where Phase[T(jω)] = -180° Æ ω180
GM =
B. Murmann
1 T ( jω180 )
EE214 Winter 2010-11 – Chapter 6
8
Example
20 log10 A0
Gain Margin
ω0
| p2 |
Phase Margin
B. Murmann
EE214 Winter 2010-11 – Chapter 6
9
Practical Phase Margins P Practical ti l circuits i it ttypically i ll use phase h margins i greater t 45° – For continuous time amplifiers, a common target is ~60° – For switched capacitor circuits, a phase margin of ~70° is desirable • See S EE315A In order to see the need for phase margin >45°, investigate the closedloop behavior of the circuit at ω = ω0
T( jω0 ) = a( jω0 ) ⋅ f = 1 A( jω0 ) = =
B. Murmann
⇒
a( jω0 ) =
1 f
(assuming f is real)
a( jω0 ) 1 + a( jω0 ) a( jω0 ) a( jω0 ) 1+ e
jφ[a( jω0 )]
=
a( jω0 ) 1 + e j(PM−180°)
EE214 Winter 2010-11 – Chapter 6
10
PM = 45o a(jω 0 )
A(jω (jω 0 ) =
=
− j135°
1+ e a(jω 0 ) = 0.3 − 0.7j
A(jω 0 ) =
∴
a(jω 0 )
=
0.76
a(jω 0 ) 1− 0.7 − 0.7j
1.3 ≅ 1.3A0 f
Thus, |A(jω0)| “peaks” at ω = ω0, it’s nominal –3dB bandwidth.
B. Murmann
EE214 Winter 2010-11 – Chapter 6
11
PM = 60o
A(jω 0 ) =
a(jω 0 ) − j120°
=
1+ e a(jω 0 ) = 0.5 − 0.87j
∴
A(jω 0 ) = a(jω 0 ) =
a(jω 0 ) 1− 0.5 − 0.87j
1 ≅ A0 f
PM = 90o
A(jω 0 ) =
∴
B. Murmann
A(jω 0 ) =
a(jω 0 ) 1+ e
− j90°
a(jω 0 ) 1.4
=
=
a(jω 0 ) 1− j
0.7 ≅ 0.7A0 f
EE214 Winter 2010-11 – Chapter 6
12
Closed-Loop Response for Various Phase Margins
Text, p. 632
B. Murmann
EE214 Winter 2010-11 – Chapter 6
13
Frequency Compensation (1) Frequency compensation refers f to the means by which the frequency f response of the loop gain in a feedback amplifier is altered so as to ensure adequate phase margin under the expected closed-loop conditions. Because operational amplifiers must often be compensated for use with a variety of feedback networks, compensation is usually accomplished by modifying only the forward path of the loop (i.e. the op-amp itself). In special i l purpose wideband id b d amplifier lifi d design, i th the response off th the feedback f db k network may also be altered. Several types yp of frequency q y compensation p are used in p practice,, e.g. g Narrowbanding (lag compensation) Feedforward (lead compensation) Pole splitting (Miller compensation, cascode compensation) Feedback (phantom) zero compensation
B. Murmann
EE214 Winter 2010-11 – Chapter 6
14
Narrowbanding (1) C Create t ad dominant i t pole l iin a(s) ( ) tto rollll off ff |T(j |T(jω)| )| att a frequency f low l enough to ensure adequate phase margin
(f=1)
Text, p. 634
B. Murmann
EE214 Winter 2010-11 – Chapter 6
15
Narrowbanding (2) N Note t th thatt in i the th example l off the th previous i slide lid ((with ith ff=1, 1 and d PM PM=45°), 45°) the th closed-loop bandwidth is limited to approximately ωp1, the frequency of the closest non-dominant pole Thi This can b be acceptable t bl if ωp1 is i sufficiently ffi i tl llarge, as th the e.g. case ffor th the pole introduced by a cascode Consider e.g. the amplifier below – Cp introduces i t d a non-dominant d i t pole l att hi high h ffrequencies i – CL is adjusted until the circuit achieves the desired phase margin • Therefore, this type of narrowbanding is called “load compensation”
B. Murmann
EE214 Winter 2010-11 – Chapter 6
16
Two-Stage Amplifier But, what if we would like to stabilize an amplifier that has two poles at relatively low frequencies? Consider e.g. the two-stage amplifier shown below, and assume that ωp1=1/R1C1 and ωp2=1/R2C2 are comparable
B. Murmann
EE214 Winter 2010-11 – Chapter 6
17
Pole Splitting (1)
R1
vi
gm1
Cc C1
R2 vo
gm2
C2
Purposely connect an additional capacitor between gate and drain of M2 (Cc = “compensation capacitor") Two interesting things happen – Low frequency input capacitance of second stage becomes large – exactly what we need for low ωp1 – At high frequencies, Cc turns M2 into a “diode connected device” – low impedance, p , i.e. large g ωp2 ! B. Murmann
EE214 Winter 2010-11 – Chapter 6
18
Pole Splitting (2) F From the th generall CS/CE stage t analysis l i off Ch Chapter t 4 4, we can approximate resulting poles and zeros as follows – See also text, section 9.4.2
p1 ≅ −
1 gm2R2 R1CC
p2 ≅ −
gm2CC C1C2 + CC (C1 + C2 )
z=+
gm2 CC
Increasing Cc reduces ωp1, and increases ωp2
− A very nice “knob” for adjusting the phase margin of the circuit The zero introduced due to Cc occurs at high frequencies and is not always troublesome In cases where the zero affects stability, y several options p exists to mitigate the problem
− Nulling resistor, cascode compensation, etc. − See EE114, EE315A B. Murmann
EE214 Winter 2010-11 – Chapter 6
19
Pole Splitting (3)
Text, p. 642
c c
c
B. Murmann
EE214 Winter 2010-11 – Chapter 6
20
Intuitive Derivation of Pole Split Using Shunt-Shunt Feedback
a(s) = −
gm2R2R1 (1 + sR1 [C1 + Cc ]) (1 + sR2 [C2 + Cc ])
Mag ( jω)
f(s) = −sCf
a(s) 1 f(s) ω
B. Murmann
EE214 Winter 2010-11 – Chapter 6
21
Nested Miller Compensation
Text,, p. p 655
Mag ( jω)
Cm2
Cm1 gm1, gm2
gm0, gm1, gm2
ω B. Murmann
EE214 Winter 2010-11 – Chapter 6
22
Feedforward Compensation
e.g. Thandri, JSSC 2/2003
|a(jω)|
Parallel path through gm3 dominates transfer function at high frequencies and returns the circuit behavior back to first order |pd|
ω
|p1| |z1|
φ(jω) ω
– π/2 –π
B. Murmann
The doublet p1, z1 can make it difficult to achieve a fast transient response – See Kamath, JSSC 12/1974
EE214 Winter 2010-11 – Chapter 6
23
Feedback Zero Compensation
Example:
Mag ( jω)
Due to the zero introduced in the feedback network network, T(j T(jω)) behaves like a first order system near unity crossover
a(s) ( ) 1 f(s) ω
B. Murmann
Closed-loop bandwidth is approximately equal to the frequency of the zero in the feedback network – Can be far beyond second pole
EE214 Winter 2010-11 – Chapter 6
24
Introduction to Root Locus Techniques: Three Pole Amplifier C Consider id a ffeedback db k network t k consisting i ti off a fforward d amplifier lifi with ith th three identical poles, and a feedback network with a constant transfer function f a0 3
a(s) =
⎛ s⎞ ⎜1− ⎟ p a0 a(s) 1⎠ ⎝ A(s) = = = 3 a0 1 + a(s)f ⎛ s⎞ 1+ a f 3 ⎜ 1 − ⎟ + T0 ⎛ s⎞ ⎝ p1 ⎠ − 1 ⎜ ⎟ p 1⎠ ⎝
a0 ⎛ s⎞ ⎜1− ⎟ ⎝ p1 ⎠
3
T0 = a0 f
The poles of A(s) are therefore the solution to 3
⎛ s⎞ ⎜ 1 − ⎟ + T0 = 0 ⎝ p1 ⎠
B. Murmann
EE214 Winter 2010-11 – Chapter 6
25
3
⎛ s⎞ ⎜ 1 − ⎟ = −T0 ⎝ p1 ⎠ ⎛ s⎞ ⎜ 1 − ⎟ = 3 −T0 = − 3 T0 ⎝ p1 ⎠
( = p (1 − = p (1 −
3
3
T0 e
(
3
T0 e j60°
s1 = p1 1 + 3 T0 s2 s3
1
1
0 = 1 − Re
)
T0 e j60°
)
− j60°
)
⎛ ⎛ s⎞ s⎞ or ⎜ 1 − ⎟ = 3 T0 e j60° or ⎜ 1 − ⎟ = 3 T0 e− j60° ⎝ p1 ⎠ ⎝ p1 ⎠
“root locus”
)
0 = 1 − 3 T0 cos(60°) ⇒ T0 = 8
B. Murmann
EE214 Winter 2010-11 – Chapter 6
26
Root-Locus Method We can generalize the above example to gain insight into the frequency response of any feedback amplifier by examining the “movement” of the closedloop poles in the s-plane as a function of the low-frequency loop gain, T0. Consider a generalized feedback amplifier with both a and f dependent on frequency.
+
vi
–
a(s)
–
vo
vfb f(s)
v o (s) a(s) a(s) = = v i (s) 1+ a(s)f(s) 1+ T(s)
A(s)
B. Murmann
EE214 Winter 2010-11 – Chapter 6
27
The poles of A(s) are the roots of 1 + T(s) = 0 0. In general,
a(s) = a0
1+ a1s + a 2s2 + ⋅ ⋅ ⋅ 2
1+ b1s + b 2s + ⋅ ⋅ ⋅
= a0
Na (s) Da (s)
and f(s) = f0
1+ c1s + c 2s2 + ⋅ ⋅ ⋅ 2
1+ d1s + d2s + ⋅ ⋅ ⋅
= f0
Nf (s) D f (s)
Thus, A(s) =
a0 Na (s)D f (s) Da (s)D f (s) + T0 Na (s)Nf (s)
where T0 = a0f0 .
B. Murmann
EE214 Winter 2010-11 – Chapter 6
28
The zeros of A(s) are the zeros of a(s) and the poles of f(s). Th poles The l off A(s) A( ) are the th roots t off : Da (s) D f (s) + T0 Na (s)Nf (s) = 0
As T0 increases from 0 to ∞, the poles of A(s) move in the s-plane from the poles of T(s) to the zeros of T(s).
The Root Locus is the paths the roots of 1 + T(s) = 0 trace in the s-plane s plane as T0 varies from 0 to ∞.
B. Murmann
EE214 Winter 2010-11 – Chapter 6
29
The root-locus construction rules follow from the equation 1+ T(s) = 1+ T0 ⋅ or equivalently q y T0 ⋅
Na (s) ⋅Nf (s) =0 Da (s) ⋅D f (s)
Na (s) ⋅Nf (s) = −1 Da (s) ⋅D f (s)
Thus T0 ⋅
(1− s za1)(1− s za2 ) ⋅ ⋅ ⋅ (1− s z f1)(1− s z f 2 ) ⋅ ⋅ ⋅ = −1 ((1− s pa1)(1− )( s pa2 ) ⋅ ⋅ ⋅ ((1− s p f1)(1− )( s p f 2 ) ⋅ ⋅ ⋅
where za1,za2 ,... = zeros of a(s) z f1,zf2 ,... = zeros of f(s) pa1,pa2 ,... = poles of a(s) pf1,pf2 ,... = poles l off f(s) f( ) B. Murmann
zeros of T(s)
poles of T(s)
EE214 Winter 2010-11 – Chapter 6
30
The above equation can be rewritten as ⎡ (−pa1)(−pa2 ) ⋅ ⋅ ⋅ (−p f1)(−p f 2 ) ⋅ ⋅ ⋅ ⎤ T0 ⋅ ⎢ ⎥ ⎣ (−za1)(−z a2 ) ⋅ ⋅ ⋅ (−z f1)(−z f 2 ) ⋅ ⋅ ⋅ ⎦
⎡(s − za1)(s − za2 ) ⋅⋅⋅ (s − zf1)(s − zf 2 ) ⋅⋅⋅⎤ ×⎢ ⎥ = −1 ⎣(s − pa1)(s − pa2 ) ⋅⋅⋅ (s − pf1)(s − pf 2 ) ⋅⋅⋅⎦
Expect all poles of T(s) to be in the left half plane (LHP). If all zeros of T(s) are in the LHP, or if there are an even number of zeros in the RHP RHP, then the first bracketed term in the above equation is positive, in which case ⎡ p p ⋅ ⋅ ⋅ p f1 p f 2 ⋅ ⋅ ⋅ ⎤ T0 ⋅ ⎢ a1 a2 ⎥ ⎢⎣ z a1 z a2 ⋅ ⋅ ⋅ z f1 z f 2 ⋅ ⋅ ⋅ ⎥⎦
⎡(s − za1)(s − za2 ) ⋅⋅⋅ (s − zf1)(s − zf 2 ) ⋅⋅⋅⎤ ×⎢ ⎥ = −1 ⎣(s − pa1)(s − pa2 ) ⋅⋅⋅ (s − pf1)(s − pf 2 ) ⋅⋅⋅⎦ B. Murmann
EE214 Winter 2010-11 – Chapter 6
31
Values of s satisfying the above equation are the poles of A(s) A(s). These values simultaneously fulfill both a phase condition and a magnitude condition, and these conditions define the points of the root locus. Phase Condition
⎡⎣ ∠(s − za1) + ∠(s − za2 ) + ⋅ ⋅ ⋅ + ∠(s − z f1) + ∠(s − z f 2 ) + ⋅ ⋅ ⋅⎤⎦ − ⎡⎣ ∠(s − pa1) + ∠(s − pa2 ) + ⋅ ⋅ ⋅ + ∠(s − p f1) + ∠(s − p f 2 ) + ⋅ ⋅ ⋅⎤⎦
= (2n − 1)π Magnitude Condition ⎡ p p ⋅ ⋅ ⋅ p f1 p f 2 ⋅ ⋅ ⋅ ⎤ ⎡ s − z a1 s − z a2 ⋅ ⋅ ⋅ s − z f1 s − z f 2 ⋅ ⋅ ⋅ ⎤ T0 ⋅ ⎢ a1 a2 ⎥ ⋅⎢ ⎥ = +1 ⎢⎣ z a1 z a2 ⋅ ⋅ ⋅ z f1 z f 2 ⋅ ⋅ ⋅ ⎥⎦ ⎢⎣ s − pa1 s − pa2 ⋅ ⋅ ⋅ s − p f1 s − p f 2 ⋅ ⋅ ⋅ ⎥⎦ B. Murmann
EE214 Winter 2010-11 – Chapter 6
32
For the case where there are an odd number of zeros in the RHP, the magnitude condition remains the same as above, but the phase condition is changed. Specifically, ⎡ p p ⋅ ⋅ ⋅ p f1 p f 2 ⋅ ⋅ ⋅ ⎤ ⎡ s − z a1 s − z a2 ⋅ ⋅ ⋅ s − z f1 s − z f 2 ⋅ ⋅ ⋅ ⎤ T0 ⋅ ⎢ a1 a2 ⎥ ⋅⎢ ⎥ = +1 ⎢⎣ z a1 z a2 ⋅ ⋅ ⋅ z f1 z f 2 ⋅ ⋅ ⋅ ⎥⎦ ⎣⎢ s − pa1 s − pa2 ⋅ ⋅ ⋅ s − p f1 s − p f 2 ⋅ ⋅ ⋅ ⎥⎦
and ⎡⎣ ∠(s − za1) + ∠(s − za2 ) + ⋅ ⋅ ⋅ + ∠(s − z f1) + ∠(s − z f 2 ) + ⋅ ⋅ ⋅⎤⎦ − ⎡⎣ ∠(s − pa1) + ∠(s − pa2 ) + ⋅ ⋅ ⋅ + ∠(s − p f1) + ∠(s − p f 2 ) + ⋅ ⋅ ⋅⎤⎦
= 2nπ
B. Murmann
EE214 Winter 2010-11 – Chapter 6
33
The rules for constructing the root locus are based on the phase condition. The magnitude condition determines where, for a given T0, the poles of A(s) actually lie on along the locus. To determine if a point X in the s-plane lies on the root locus, draw vectors from the poles and zeros of T(s) to the point X. The angles of these vectors are then used to check the phase condition.
B. Murmann
EE214 Winter 2010-11 – Chapter 6
34
Root-Locus Construction Rules Rule 1:
Branches of the root locus start at the poles of T(s), where T0 = 0, 0 and terminate on the zeros of T(s) T(s), where T0 = ∞. If T(s) has more poles than zeros, some branches terminate at infinity. Rule 2:
The root locus is located along the real axis whenever there is an odd number of poles and zeros of T(s) between that portion of the real axis and the origin of the s-plane.
Rule 3:
All segments of the locus on the real axis between pairs of poles, or pairs of zeros, must branch out from the real axis axis. B. Murmann
EE214 Winter 2010-11 – Chapter 6
35
Rule 4:
Locus is symmetric with respect to the real axis because complex roots occur only in conjugate pairs. Rule 5:
Branches leaving the real axis do so at right angles to it. Rule 6:
Branches break away from the real axis at points where the vector sum of reciprocals of distances to the poles of ( ) equals q the vector sum of reciprocals p of distances to T(s) the zeros of T(s). Rule 7:
Branches B h th thatt terminate t i t att infinity i fi it do d so asymptotically t ti ll tto straight lines with angles to the real axis of (2n –1)π/(Np – Nz), where Np = # of poles of T(s) and Nz = # of zeros of T(s) T(s). B. Murmann
EE214 Winter 2010-11 – Chapter 6
36
R l 8: Rule 8
The asymptotes of the branches terminating at infinity all intersect the real axis at a single point given by σa =
B. Murmann
[
] [
]
Σ poles of T(s) − Σ zeros of T(s) Np − Nz
EE214 Winter 2010-11 – Chapter 6
37
2-Pole Example
jω
p2
B. Murmann
p1
EE214 Winter 2010-11 – Chapter 6
σ
38
3-Pole Example Assume
T(s) =
T0 (1− s / p1)(1− s / p 2 )(1− s / p3 )
where p1 = −1× 106 sec−1 p2 = −2 × 106 sec−1 p3 = −4 × 106 sec−1
B. Murmann
EE214 Winter 2010-11 – Chapter 6
39
3-Pole Example, cont’d
σa
σi
B. Murmann
EE214 Winter 2010-11 – Chapter 6
40
Breakaway Point, σi
From Rule 6
1 1 1 + + =0 σi + 1 σi + 2 σi + 4 2
∴ 3σ 3 i + 14σ 14 i + 14 = 0 2
⎛ 7⎞ 7 14 1 σi = − ± ⎜ ⎟ − = − 7± 7 3 3 3 ⎝ 3⎠
(
)
= −3.22 or − 1.45
Since σi lies bet between een p1 and p2, σi = −1.45 × 106 sec−1
B. Murmann
EE214 Winter 2010-11 – Chapter 6
41
Asymptote Intercept, σa
From Rule 8 σa =
(−1− 2 − 4) − 0 = −2.33 2 33 × 106 sec−1 3
To find the loop gain, T0, at which the poles moving from p1 and p2 b become complex, l substitute b tit t th the b breakaway k point, i t s = σi = –1.45, 1 45 into the magnitude condition and solve for T0. T0
p1 p 2 p3 s − p1 s − p 2 s − p3
∴ T0 =
=1
−1 1.45 45 + 1 −1 1.45 45 + 2 −1 1.45 45 + 3
(1)(2)(4) (0.45)(0.55)(2.55) = = 0.08 8
B. Murmann
EE214 Winter 2010-11 – Chapter 6
42
The complex poles enter the RHP at approximately the points where their asymptotes cross the jω axis. At these points s = ± j(2.33) j(2 33) tan(60 ) = ±4j
Substituting into the magnitude condition and solving for T0 T0 = =
s − p1 s − p2 s − p3 p1 p2 p3 4j + 1 4j + 2 4j + 4
( = =
(1)(2)(4) 42 + 1
)(
4 2 + 22 8
)(
42 + 42
)=
17 ⋅ 20 ⋅ 32 8
(4.1)(4.5)(5.7) = 13.2 8
B. Murmann
EE214 Winter 2010-11 – Chapter 6
43
Plotting the Root Locus in Matlab % root locus example s = tf('s'); p1=-1; p2=-2; p3=-4; a = 1 / [(1-s/p1)*(1-s/p2)*(1-/p3)] rlocus(a) Root Locus 10 8 6
Imaginary A Axis
4 2 0 -2 -4 -6 -8 -10 -14 14
-12 12
-10 10
-8 8
-6 6
-4 4
-2 2
0
2
4
Real Axis
B. Murmann
EE214 Winter 2010-11 – Chapter 6
44
3 Poles and 1 Zero jω
p2
σ
p1
Introducing a zero in T(s) can be used to stabilize a feedback amplifier. The use of zeros in the feedback path is an important aspect of wideband amplifier design. B. Murmann
EE214 Winter 2010-11 – Chapter 6
45
Matlab Plot % root locus example s = tf('s'); z=-5; p1=-1; p2=-2; p3=-4; a = (1-s/z) / [(1-s/p1)*(1-s/p2)*(1-s/p3)] rlocus(a) ocus(a) Root Locus 15
10
Imaginary A Axis
5
0
-5
-10
-15 -6 6
-5 5
-4 4
-3 3
-2 2
-1 1
0
1
Real Axis
B. Murmann
EE214 Winter 2010-11 – Chapter 6
46
Chapter 7 Wideband Amplifiers B. Murmann Stanford University Reading Material: Section 9.5.3, 9.5.4
Overview
How to build amplifiers with large gain and bandwidth? Options we’ll look at – Cascade of first order amplifier stages – Multi-stage Multi stage amplifiers with global feedback – Multi-stage amplifiers with local feedback
B. Murmann
EE214 Winter 2010-11 – Chapter 7
2
Cascade of N First-Order Stages Consider a cascade of N identical stages, each with the singlepole response A(jω) =
A0 1+ jω ωB
GBW = A 0ωB
If there is no interaction among the stages, then the overall transfer function of the cascade is ⎛ ⎞ A0 AN (jω) = ⎜ ⎟ ⎝ 1+ jω ωB ⎠
N
In this case A 0N = AN0
B. Murmann
EE214 Winter 2010-11 – Chapter 7
3
Th –3dB The 3dB b bandwidth d idth off th the cascade d iis the th frequency, f ωBN, att which hi h AN (jωBN ) =
Thus,
A 0N 2
⎡ A0 ⎢ ⎢ 1+ (ω ω B )2 BN ⎣
N
⎤ N ⎥ = A0 ⎥ 2 ⎦
2
1+ (ωBN ωB ) = 21 N ωBN = ωB ⋅ 21 N − 1
B. Murmann
GBWN = A N0 ωB ⋅ 21 N − 1 < A N0 ωB
EE214 Winter 2010-11 – Chapter 7
4
Bandwidth Shrinkage
1
0.8
1 N 0.6 2 −1
0.4
0.2
0
2
4
6
8
10
N
B. Murmann
EE214 Winter 2010-11 – Chapter 7
5
Ideal Lowpass Response Suppose each stage in the cascade of N identical stages had an ideal lowpass response; that is, a magnitude response with an abrupt band edge transition between the passband and the stopband: |A(jω)| A0
⇒ GBWN = A N0 ωB
ωB
ω
In the design of wideband amplifiers it is therefore often desirable to h have a much h sharper h b band-edge d d ttransition iti than th iis obtained bt i d with ith a cascade of identical single-pole stages.
B. Murmann
EE214 Winter 2010-11 – Chapter 7
6
Maximally Flat Magnitude (MFM) Response
An approximation to the ideal lowpass response that is commonly used in broadband amplifier design is the Maximally Flat Magnitude (MFM), or Butterworth, response. response The MFM response provides a magnitude (gain) that is flat over as much of the passband as possible and decreases monotonically with frequency (i no peaking). (i.e. ki ) It iis obtained bt i d b by setting tti as many d derivatives i ti off th the magnitude with respect to frequency as possible to zero at ω = 0. For an nth-order MFM response,
dk H(jω) dω k
B. Murmann
=0
for 1 ≤ k ≤ 2n − 1
ω =0
EE214 Winter 2010-11 – Chapter 7
7
Th resulting The lti magnitude it d response iis H(jω) =
1 1+ (ω ( B)2n
where n is the order of the response, B is the bandwidth of the ideal p response, p , and the magnitude g has been normalized to unity y lowpass at ω = 0. |H(jω)| 1 n=2
n=1 n=3 B
B. Murmann
EE214 Winter 2010-11 – Chapter 7
ω
8
There is no peaking in the MFM response, and as n increases the band edge transition becomes sharper. In the limit as n t ∞, the MFM response approaches the ideal lowpass response. To determine the location of the poles of H(s), note that 2
H(jω) = H(jω) ⋅H(− jω) = H(s) ⋅H(−s)
s= jω
Thus,, for an MFM response p H(s) ⋅H(−s) = =
B. Murmann
1 1+ (s jB)2n
=
j2n j2n + (s B)2n
(−1)n (−1)n + (s B)2n
EE214 Winter 2010-11 – Chapter 7
9
The poles of H(s)×H(–s) are the 2n roots satisfying
⎛ s⎞ ⎜⎝ B ⎟⎠
2n
= −(−1)n = (−1)n+1
Th These roots t lie li equally ll spaced d on a circle i l in i th the s-plane l centered t d att the origin with radius B. The LHP roots are taken to be the poles of H(s), while those in the RHP are regarded d d as th the poles l off H( H(–s). )
B. Murmann
EE214 Winter 2010-11 – Chapter 7
10
MFM Pole Locations n=1
jω
p1 = − B
σ
–B
n=2
pi = Be j3π 4 , Be j5π
4
jω
B 45º
σ
B. Murmann
EE214 Winter 2010-11 – Chapter 7
11
n=3
pi = Be j2π 3 , Be jπ , Be j4π
3
jω
60º
σ
B. Murmann
EE214 Winter 2010-11 – Chapter 7
12
MFM Transient Response A potential disadvantage of the MFM response is that there is an overshoot in the step response when n ≥ 2. This may be an important consideration in applications such as pulse amplifiers. For a step input at t=0 n=3 3
Vo(t) n=1 n=2
t
n = 2 Æ 4% overshoot n = 3 Æ 8% overshoot
B. Murmann
EE214 Winter 2010-11 – Chapter 7
13
Comparison of 2-Pole Responses
Angle of Poles
–3dB BW
Overshoot
10-90% Rise Time
Coincident poles
0°
0.64B
0
3.4/B
MFM (Butterworth)
45°
B
4%
2.2/B
Chebyshev (1-dB ripple)
60°
1.3B
16%
1.6/B
Bessel
30° 30
0 8B 0.8B
0 4% 0.4%
2 7/B 2.7/B
B. Murmann
EE214 Winter 2010-11 – Chapter 7
More in EE315A
14
Wideband Amplification Using Multi-Stage Feedback At most three gain stages can be effectively used within a single feedback loop. Therefore, there are four basic configurations.
+
+ vi –
+ vo – ~
RF
RE
A V0 =
Series-Shunt Pair
B. Murmann
v o RF ≈ v i RE
EE214 Winter 2010-11 – Chapter 7
15
+ io
ii
AI0 = RF
i o RF ≈ ii RE
RE
Shunt-Series Pair
B. Murmann
EE214 Winter 2010-11 – Chapter 7
16
+ io
+ vi –
~
RF
RE1
A0 =
RE2
i o RF + RE1 + RE2 ≈ vi RE1 ⋅RE2
Series-Series Triple
B. Murmann
EE214 Winter 2010-11 – Chapter 7
17
+
+ vo –
ii RF A0 =
vo ≈ RF ii
Shunt-Shunt Triple
B. Murmann
EE214 Winter 2010-11 – Chapter 7
18
Analysis of Shunt-Series Pair
+ RC2
RC1
io Q2
Q1
ZL
ii RF
RE
Assume ZL ≈ 0 and RS ≈ ∞
B. Murmann
EE214 Winter 2010-11 – Chapter 7
19
Application Example: Optical Fiber Links (1)
K. Ohhata et al., “A Wide-Dynamic-Range, HighTransimpedance Si Bipolar Preamplifier IC for 10-Gb/s Optical Fiber Links,” JSSC 1/1999.
B. Murmann
EE214 Winter 2010-11 – Chapter 7
20
Circuit Implementation
Ohhata, JSSC 1/1999
B. Murmann
EE214 Winter 2010-11 – Chapter 7
21
Small-signal equivalent circuit for evaluating the open-loop response of the shunt-series pair:
io
RC1 Q2 Q1 ii
ifb
iE2
RF RE
B. Murmann
ifb RF
EE214 Winter 2010-11 – Chapter 7
RE
22
Note that in BJT amplifiers with a series output stage, the feedback network does not sample the output, io, directly, but rather the emitter current of Q2, iE2. Thus, a(s) and f(s) are defined as follows: a(s)
iE2 ii
f(s)
ifb iE2
For these definitions A(s)
io ⎛ a(s) ⎞ = −α 2 ⎜ ii ⎝ 1+ a(s)f(s) ⎟⎠
where α2 is the common-base current gain of Q2
B. Murmann
EE214 Winter 2010-11 – Chapter 7
23
The feedback response response, f(s) f(s), for the shunt-series pair (w/o compensation) is simply f(s) =
ifb RE =− iE2 RE + RF
To estimate the forward p path response, p a(s), ( ) begin g with the following small-signal equivalent circuit: Cμ1 ii
+ R1 v1 –
Cπ1
Cμ2 + RC1 v rπ2 2 gm1v1 –
+ vb –
R1 = (RF + RE ) || rπ1
Cπ2 RE*
io
gm2vb iE2
RE* = RE || RF B. Murmann
EE214 Winter 2010-11 – Chapter 7
24
First consider the transmission from the base to the emitter of the second stage iE2 = (v 2 − iE2RE* )(gm22 + Yπ 2 ) where Yπ22
gπ22 + sC π22
Thus, iE2 ⎡1+ 1 RE* (g ( m2 + Yπ 2 ) ⎤ = v 2 (g ( m2 + Yπ 2 ) ⎣ ⎦
∴
B. Murmann
gm2 + Yπ 2 iE2 = v 2 1+ RE* (gm2 + Yπ 2 )
EE214 Winter 2010-11 – Chapter 7
gm2 + Yπ 2 = gm2 +
25
gm2 + sC π 2 ≅ gm2 + sC π 2 β0
⎛ C ⎞ = gm2 ⎜ 1+ s π 2 ⎟ = gm2 1+ sτ T2 gm2 ⎠ ⎝
(
)
Therefore, Therefore gm2 (1+ sτ T2 ) iE2 = v 2 1+ gm2RE* + sRE* C π2 ⎡ ⎤ ⎡ ⎤ ⎢ ⎥ ⎢ ⎥ ⎛ g ⎞⎢ ⎛ g ⎞⎢ ⎥ 1+ sτ 1+ sτ ⎥ m2 T2 m2 T2 =⎜ ⎟⎢ ⎥= ⎜ ⎥ * ⎟ ⎢ * * * ⎛ R C ⎞ ⎥ ⎝ 1+ gm2RE ⎠ ⎢ ⎛ g R ⎞⎥ ⎝ 1+ gm2RE ⎠ ⎢ E π2 m2 E 1+ sτ T2 ⎜ * ⎟ ⎢ 1+ s ⎜ 1+ g R* ⎟ ⎥ ⎢ ⎝ 1+ gm2RE ⎠ ⎦⎥ ⎝ m2 E ⎠ ⎦ ⎣ ⎣
B. Murmann
EE214 Winter 2010-11 – Chapter 7
26
jω –ωT2 σ
⎛ 1+ g R* ⎞ m2 E −ω T2 ⎜ * ⎟ ⎝ gm2RE ⎠
Thus, the second stage is very broadband, and the pole-zero pair associated with it can usually be neglected. In that case, gm2 iE2 ≅ v 2 1+ gm2RE*
gm2eq
Also,, io = − α 2iE2 ≅ − iE2 B. Murmann
EE214 Winter 2010-11 – Chapter 7
27
The main influence of the series feedback stage on a(s) is the loading on Q1. We can model the loading using the following approximation for the input impedance of the series feedback stage:
+ v2 –
rπ2eq
Cμ2
Cπ2eq
where rπ2eq = rπ2 (1+ gm2RE* ) ≅ rπ2gm2RE* = β02RE* C π2eq =
B. Murmann
C π2
1+ gm2RE*
≅
C π2 ⎛ 1 ⎞ τ T2 ⎜ ⎟= gm2 ⎝ RE* ⎠ RE*
EE214 Winter 2010-11 – Chapter 7
28
Thus, the equivalent circuit for determining the open-loop response v2(s)/ii(s) is simply: Cμ1 ii
+ R1 v1 –
Cπ1
gm1v1
RL1
CL1
+ v2 –
where R1 = rπ1 || (RF + RE ) RL1 = RC1 || rπ2eq ≅ RC1 || β02RE*
CL1 = Ccs1 + Cμ 2 + C π 2eq ≅ Ccs1 + Cμ 2 +
B. Murmann
a(s)
we find
RE*
EE214 Winter 2010-11 – Chapter 7
Since
and
τ T2
29
iE2 ⎛ iE2 ⎞ ⎛ v 2 ⎞ =⎜ ⎟⎜ ⎟ ii ⎝ v 2 ⎠ ⎝ ii ⎠
gm2 iE2 1 ≅ gm2eq = ≅ * 2 * v2 1+ gm2RE RE
(
)
⎡ ⎛ R ⎞ ⎤ ⎡ 1− s z1 ⎤ ⎥⎢ a(s) = − ⎢gm1R1 ⎜ L1 ⎥ * ⎟ 2 ⎢⎣ ⎝ RE ⎠ ⎥⎦ ⎢⎣ 1+ b1s + b 2s ⎥⎦
Where (see Chapter 4) b1 = R1(Cπ1 + Cμ1) + RL1(CL1 + Cμ1) + gm1R1RL1Cμ1 b 2 = R1RL1(C π1CL1 + C π1Cμ1 + CL1Cμ1) z1 = + B. Murmann
gm1 C μ1 EE214 Winter 2010-11 – Chapter 7
30
If a dominant pole condition exists, with |p1| > |σi|, then for an MFM response B = 2 zF and the closed-loop pp pole p positions,, s1 and s2, are s1,s2 ≅ zF (−1± j) =
B. Murmann
B 2
EE214 Winter 2010-11 – Chapter 7
(−1± j)
36
The loop gain, T0, needed to place the closed-loop poles at these positions is
T0 = =
B. Murmann
s1 − p1 s2 − p 2 p1 p 2 2 zF
2
p1 p 2
=
=
B2 p1 p 2
2R1C π1RL1CL1 (RFCF )2
EE214 Winter 2010-11 – Chapter 7
37
Broadband Amplifier Design with Local Feedback
Rein & Moller, JSSC 8/1996
In a cascade of amplifier stages, the interaction (loading) between adjacent stages can be reduced by alternating local series and shunt feedback circuits.
B. Murmann
EE214 Winter 2010-11 – Chapter 7
38
Advantages & Disadvantages of Local Feedback Cascades
Advantages
• No N iinstability bili • Lower gain sensitivity to component and device parameter variations than amplifiers without local feedback
Disadvantages
• Hi Higher h gain i sensitivity iti it (less (l lloop gain) i ) th than multi-stage lti t feedback amplifiers (i.e. multi-stage amplifiers with global feedback) • Bandwidth obtainable is typically slightly less than that possible in multi-stage feedback amplifiers
B. Murmann
EE214 Winter 2010-11 – Chapter 7
39
Application Example (1)
Poulton, ISSCC 2003
B. Murmann
EE214 Winter 2010-11 – Chapter 7
40
Application Example (2) Poulton, ISSCC 2003
B. Murmann
EE214 Winter 2010-11 – Chapter 7
41
Application Example (3)
Poulton, ISSCC 2003
BW ~ 6 GHz B. Murmann
EE214 Winter 2010-11 – Chapter 7
42
Cherry-Hooper Amplifier
+ RF
RE Shunt F/B Series F/B Stage
Stage
E. Cherry and D. Hooper, Proc. IEE, Feb. 1963
B. Murmann
EE214 Winter 2010-11 – Chapter 7
43
Analysis
A(0) =
vo ⎛ 1 ⎞ RF ≅ ⎜− ⎟ ( −RF ) = v in ⎝ RE ⎠ RE
Thus, the low-frequency gain is approximately equal to the ratio of the p and two feedback resistors,, and is therefore insensitive to component device parameter values While the series feedback stage usually has a large bandwidth, there is p and output p nodes of the considerable interaction between the input shunt feedback stage. However this interaction can be controlled and can be used to position the poles to achieve a particular response, such as MFM. To see how the pole positions in a local feedback cascade can be controlled, we first consider the local feedback stages individually
B. Murmann
EE214 Winter 2010-11 – Chapter 7
44
Series Feedback Stage Small-signal equivalent circuit: RS vi
+ v1 –
~
io
Cμ rπ
gmv1
Cπ + vE –
ZL
RE
Include transistor rb in RS Neglect rμ, ro, re, and rc Assume that ZL ≈ 0; then there is no Milller effect and Cμ is just a (small) capacitance to ground which often has negligible impact.
B. Murmann
EE214 Winter 2010-11 – Chapter 7
45
Define Yπ
1 + sC π rπ
Then
v i − (v1 + vE ) = v1Yπ RS v1Yπ + gmv1 =
vE RE
Substituting for vE in the first of these two equations v i − v1 ⎡⎣1+ (gm + Yπ ) RE ⎤⎦ = v1YπRS ∴
B. Murmann
v1 1 = v i 1+ (gm + Yπ ) RE + YπRS EE214 Winter 2010-11 – Chapter 7
46
Since io = –gmv1 io gm =− vi 1+ gmRE + (RS + RE )Yπ ⎡ ⎤ ⎢ ⎥ ⎛ gm ⎞ ⎢ 1 ⎥ = −⎜ ⎟ ⎢ ⎛ R +R ⎞ ⎛ ⎥ 1+ g R ⎞ ⎝ 1 m E⎠ E ⎢ 1+ ⎜ S ⎥ + sC π⎟ ⎟⎜ ⎢⎣ ⎝ 1+ gmRE ⎠ ⎝ rπ ⎠ ⎥⎦ ⎡ ⎤ ⎥ ⎢ ⎛ gm ⎞ ⎢ 1 ⎥ = −⎜ ⎟ ⎢ ⎛ R + RE ⎞ ⎛ ⎞ ⎛ RS + RE ⎞ ⎥ ⎝ 1+ gmRE ⎠ 1 ⎢ 1+ + sC 1 ⎜ S C ⎟⎜ π⎜ ⎟ ⎟⎥ ⎢⎣ ⎝ rπ ⎠ ⎝ 1+ gmRE ⎠ ⎝ 1+ gmRE ⎠ ⎦⎥
B. Murmann
EE214 Winter 2010-11 – Chapter 7
47
Usually, Usually ⎛ RS + RE ⎞ ⎛ ⎞ gm (RS + RE ) ⎛ ⎞ 1 1 ⎜ r ⎟ ⎜ 1+ g R ⎟ = ⎜ ⎟ β0 ⎝ 1+ gmRE ⎠ ⎝ ⎠⎝ π m E⎠
> 1
gmeq ≅
1 RE
and p1 ≅ −
⎛ Cπ + Cμ ⎞⎛ RE ⎞ ⎛ RE ⎞ gm ⎛ RE ⎞ ⎜ ⎟ = − ωT ⎜ ⎟⎜ ⎟ ≅ − ωT ⎜ ⎟ Cπ ⎝ RE + RS ⎠ ⎝ Cπ ⎠⎝ RE + RS ⎠ ⎝ RE + RS ⎠
Note that this result corresponds to the dominant time constant found via ZVTC analysis in handout 7. Thus, for RE >> RS, p1 → – ωT. In some cases, the bandwidth may then be actually limited by Cμ (which was neglected in this analysis).
B. Murmann
EE214 Winter 2010-11 – Chapter 7
49
Emitter Peaking The bandwidth of the series feedback stage can be increased by introducing an “emitter peaking” capacitor in shunt with RE. io RS + vi –
Q1
~
RE
CE
N a large Not l b bypass capacitor
To analyze this circuit, substitute ZE for RE in the preceding analysis where analysis, ZE =
B. Murmann
RE 1 = YE 1+ sRECE
EE214 Winter 2010-11 – Chapter 7
50
Then, defining τE
RECE and assuming τ T ≅
io =− vi
gm 1+ gmZE + (RS + ZE )(
1 + sC π ) rπ
gm
=− 1+ −
Cπ gm
⎞ ⎛ RE ⎞ ⎛ RS 1 gm + + sC π ⎟ + sC πRS + ⎜ ⎜ ⎟ rπ rπ ⎝ 1+ sτE ⎠ ⎝ ⎠
gm ⎛ g R ⎞⎛ R C ⎞ 1+ S + sC πRS + ⎜ m E ⎟ ⎜ 1+ s π ⎟ rπ gm ⎠ ⎝ 1+ sτE ⎠ ⎝
since gm >>
B. Murmann
1 rπ EE214 Winter 2010-11 – Chapter 7
∴
io ≅− vi
51
gm
1+
⎛ 1+ sτ T ⎞ RS + sC πRS + gmRE ⎜ ⎟ rπ ⎝ 1+ sτE ⎠
If CE is chosen so that τE = τ T and it is true that gmRE >> Then
B. Murmann
RS gmRS = rπ β0
⎡ ⎤ ⎢ ⎥ ⎛ gm ⎞ ⎢ io 1 ⎥ ≅ −⎜ ⎟⎢ ⎥ vi 1+ g R ⎛ ⎞ RS ⎝ m E⎠ ⎢ 1+ sC π ⎜ ⎟⎥ ⎝ 1+ gmRE ⎠ ⎥⎦ ⎢⎣ EE214 Winter 2010-11 – Chapter 7
52
Th result The lt is i a single-pole i l l response with ith p1 = −
⎛R ⎞ 1+ gmRE ≅ −ω T ⎜ E ⎟ RSC π ⎝ RS ⎠
In this case, if RE > RS, then |p1| > ωT (!)
B. Murmann
EE214 Winter 2010-11 – Chapter 7
53
Note that τE > τT results in a pole-zero separation that can cause peaking in the frequency response jjω
p2
p1
σ
z1
|io/vi|
|z1| |p1| B. Murmann
|p2|
EE214 Winter 2010-11 – Chapter 7
ω
54
Shunt Feedback Stage Small-signal equivalent circuit CF
RF + v1 –
ii
rπ
Cπ
gmv1
RL
CL
+ vo –
Include transistor Cμ in CF Neglect RS or include it in rπ Neglect rb, rc, re, and rμ Include ro and Ccs in RL and CL
B. Murmann
EE214 Winter 2010-11 – Chapter 7
55
D fi Define τF
RFCF
τL
RLCL
and
B. Murmann
YF =
1 1 1 + sCF = (1+ sCFRF ) = (1+ sτF ) RF RF RF
YL =
1 1 + sCL = ((1+ sτL ) RL RL
Yπ =
1 + sC π rπ
EE214 Winter 2010-11 – Chapter 7
56
From the equivalent circuit: ii + (v o − v1)YF = v1Yπ
(1)
v o YL + gmv1 + (v o − v1)YF = 0
(2)
Then from (2) ⎛ Y + YF ⎞ v1 = −v o ⎜ L ⎟ ⎝ gm − YF ⎠
Substituting in (1) ⎤ ⎡ ⎛ Y + YF ⎞ ii + v o ⎢ YF + ⎜ L (Yπ + YF ) ⎥ = 0 ⎟ ⎝ gm − YF ⎠ ⎣⎢ ⎦⎥
∴
B. Murmann
vo gm − YF =− ii (gm − YF )YF + (YL + YF )(Yπ + YF )
EE214 Winter 2010-11 – Chapter 7
57
Assuming that gm >> 1/RF = GF gm − YF = gm − (GF + sCF ) ≅ gm − sCF
Then gm − sCF vo ≅− ii (gm − sCF )( )(GF + sCF ) + ⎡⎣((GL + GF ) + s(C ( L + CF ) ⎤⎦ ⎡⎣(gπ + GF ) + s(C ( π + CF ) ⎤⎦ Thus vo gm − sC CF ≅− ii a0 + a1s + a 2s2 where a0 = gmGF + (GL + GF )(gπ + GF ) a1 = (gm − GF )CF + (GL + GF )(C π + CF ) + (gπ + GF )(CL + CF ) a 2 = CLC π + CLCF + C π CF B. Murmann
EE214 Winter 2010-11 – Chapter 7
58
Further assuming g that gm >> GL, RF >> rπ, Cπ >> CF, and noting g that gm >> gπ a0 ≅ gm RF a1 ≅ gmCF + (GL + GF )C π + gπ (CL + CF ) a 2 ≅ C π (CL + CF ) Then vo R (1− s z1) ≅− F ii 1+ b1s + b 2s2 where
⎛ R + RL ⎞ R τ T + F (CL + CF ) b1 = a1 a0 ≅ RFCF + ⎜ F ⎟ β0 ⎝ RL ⎠
b 2 = a 2 a1 ≅ RF (CL + CF )τ T z1 = + gm CF
Often b1 ≅ RFCF B. Murmann
EE214 Winter 2010-11 – Chapter 7
59
z1 is a feedforward zero that is located in the RHP. RHP Since it was assumed that Cπ >> CF z1 >>
gm ≅ ωT Cπ
In these circumstances the feedforward zero can usually be neglected, and the shunt feedback stage has an approximate 2-pole response. vo RF =− ii (1 − s p1 )(1 − s p2 ) The poles p1 and p2 may be complex complex. CF can be used to alter the positions of the poles.
B. Murmann
EE214 Winter 2010-11 – Chapter 7
60
For example, CF can be chosen to provide a 2-pole MFM response: jω p1 45º
σ
–B p2
b2 =
B. Murmann
1 1 1 = = 2 2 p1p 2 p B 1
EE214 Winter 2010-11 – Chapter 7
61
Thus, ω−3dB =
If CF VCE(sat ) + VR1 VR1 < VBE − VCE(sat ) ≅ 0.8V 0 8V − 0 0.2V 2V = 0 0.6V 6V This limits the gain we can extract from this stage
gm1R1 =
IBIAS V 600mV R1 = R1 = = 23 2VT VT 26mV 26 V
Text, p. 449
B. Murmann
EE214 Winter 2010-11 – Chapter 10
5
PNP Folded Cascode Input Stage
Circuit still works for input common mode down to VEE (0V), as before But, the low frequency voltage gain is much larger g g
v od R3 R = gm1 1 o v id R3 + gm Ro ≅ ro6 (1 + gm6R6 ) ro3 (1 + gm3R3 )
B. Murmann
EE214 Winter 2010-11 – Chapter 10
6
NE5234 Input Stage
X
~0.9V
Provides rail-to rail common-mode input range by combining the currents from a PNP and NPN pair The NPN pair “steals” current from the PNP pair at node X whenever the input common mode is greater than |VBE| – Total Gm is approximately constant B. Murmann
EE214 Winter 2010-11 – Chapter 10
7
Second Stage
0.5V
0.5V
0.5V
~0.9V + 0.4V -
B. Murmann
EE214 Winter 2010-11 – Chapter 10
8
Common Mode Operating Point of Stage 1 Output
B. Murmann
EE214 Winter 2010-11 – Chapter 10
9
Basic Emitter Follower (“Class-A”) Output Stage
Issues – Output p voltage g cannot g go higher than VCC – VBE – Need large quiescent current IQ to provide good current sinking capability – IQ flows even if no signal is present, i.e. Io=0
B. Murmann
EE214 Winter 2010-11 – Chapter 10
10
Output Stage Nomenclature Cl Class-A A – Output devices conduct for entire cycle of output sine wave Class-B – Output devices conduct for ≅50% of sine wave cycle Class-AB – Output p devices conduct for >50%,, but
