Edi11 Ccopt Slides

INVENTIVE

EDI System 11 Training on Clock Concurrent Optimization (CCOpt) ICD Product Engineering

Design Infrastructure

What is CCOpt?

2

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CCOpt Overview Netlist Place

Up to 10% increase in frequency

Pre-CTS Optimization

CCOpt Post-CTS Optimization (optional)

Up to 30% less clock power

Route Post-Route Optimization

Accelerated timing closure

Final Layout

CCOpt combines useful skew CTS and post-CTS opt in one step

3

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Traditional CTS Timing Closure T

clock

L

C G logic

Ideal clocks

G < T – skew 4

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Skew balance L = C ± skew

Propagated Clocks

G < T – (L – C)

CCOpt Timing Closure clock

Pi-1

5

Pi

T

Pi+1

Gi

Gi+1

logic

logic

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CCOpt Timing Closure clock

Pi-1

Pi+1

Gi

Gi+1

logic

logic

Gi < T – (Pi-1 – Pi)

6

Pi

T

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Gi+1 < T – (Pi – Pi+1)

Logic Opt

CCOpt Timing Closure clock

Pi-1

Pi

Pi-1 + Gi – T

Gi

T

Pi+1 Gi+1 logic

logic

T + Pi+1 – Gi+1

Gi < T – (Pi-1 – Pi)

Pi-1 + Gi – T 7

<

Gi+1 < T – (Pi – Pi+1)

Pi

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< T + Pi+1 – Gi+1

Logic Opt

CTS

CCOpt Timing Closure clock

Pi-1

Pi

Pi-1 + Gi – T

Gi

T

Pi+1 Gi+1 logic

logic

T + Pi+1 – Gi+1

Gi < T – (Pi-1 – Pi)

Gi+1 < T – (Pi – Pi+1)

Logic Opt

Concurrent

Pi-1 + Gi – T 8

<

Pi

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< T + Pi+1 – Gi+1

CTS

Design Infrastructure

CCOpt Integration with EDI 11

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New ccoptDesign command • Basic User Support − Run export+CCOpt+import operation with one command − Supports MMMC and MSV − New setCCOptMode command for basic settings • Except clock NDRs which are picked up from setCTSMode

− No translation of clockTreeSpec settings (target USR1)

• Advanced User Support − Export design files and script: ccoptDesign -genScriptOnly script.tcl − Run CCOpt from a script: ccoptDesign -runScript script.tcl − Import post-CCOpt database: ccoptDesign -import mydesign.azdb 10

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Integration Architecture Verilog netlist

placeDesign optDesign -preCTS

ccoptDesign

routeDesign optDesign -postRoute GDSII

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Integration Architecture Verilog netlist

placeDesign optDesign -preCTS

ccoptDesign

routeDesign optDesign -postRoute GDSII

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Verilog netlist

Placed DEF

SDC

CCOpt

TCL

Verilog netlist

ECO DEF

SDC

CPF

Integration Architecture .lib

Verilog netlist

Cap Table

LEF

generateATF

placeDesign

ATF

optDesign -preCTS

ccoptDesign

routeDesign optDesign -postRoute GDSII

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Verilog netlist

Placed DEF

SDC

CCOpt

TCL

Verilog netlist

ECO DEF

SDC

CPF

Design Infrastructure

Logic Chains

14

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CCOpt Technology Traditional Physical Optimization

Clock Concurrent Optimization

clock

clock

T

L

T

C

skew

Gmax

Gmax

Gmax < T - skew variable

fixed

fixed

L+ Gmax < T + C variable

variable

fixed

More degrees of freedom

variable

CCOpt extends physical optimization into the clocks, optimizing both the datapath and the clock tree. 15

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Time Borrowing and Logic Chains clock

In CCOpt, slack can flow across register boundaries

?

? slack clock

CCOpt algorithms focus on optimizing the entire logic chain (not just the critical path)

clock

Logic chains can loop

16

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Critical Chains • Speed is not limited by critical path. • CCOpt can move slack. • Optimize “non-critical” paths on the critical chain to create spare slack. • Critical chain is focus in CCOpt. critical path

• Critical chain = max (delay / stage)

slack 13

11

9 Delay

19

11+9+19+8+13

=

Stage

8

• Contains longest delay (19) • Would traditionally be critical path • (delay / stage) = 12

= 12

5

traditional critical path CCOpt critical chain

11

15

Example Chain 1

Example Chain 2 • Individual delays all < 19 • But (delay / stage) = 14

16 Delay Stage 17

=

15+16+11

= 14

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• Therefore, of the two example chains, this chain is the critical chain.

Design Infrastructure

CCOpt Phases of Operation

18

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The Three Phases of CCOpt Goal: seed design for the main optimization loop

Preconditioning

• • •

Flip design into propagated mode Build initial balanced clock tree Basic "global" sizing only

Goal: search for the “best solution”

Optimization

• • • •

Combine clock scheduling and datapath optimization Schedules the clock tree using virtual delays Periodically improves placement, rebuilds clocks Later iterations make smaller placement and clock changes

Goal: legalize and polish design

Final Implementation

19

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• •

Clock buffered to meet timing windows Design fully legal and ERC fixed

Phase 1: Preconditioning CLK

CG

• Clock tree balanced with virtual delay • Datapath coarsely optimized for balanced clocks • Clock gates fully decloned 20

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Phase 2: Optimization CLK

CG

CG

• • • • 21

Virtual delay added and removed to aid timing Datapath optimized for skewed clocks Clock tree reclustered for efficiency Clock gates cloned for timing © 2012 Cadence Design Systems. All rights reserved. 

Phase 3: Final Implementation CLK

CG CG

• Buffering inserted in place of virtual delay • Flops and clock gates buffered to their timing windows

22

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CCOpt Log File (C-Ini)

Starting Rubix ccopt

(C-Pre)

ccopt Preconditioning...

(C-Opt)

ccopt Optimization...

“hyperspace” round full clock tree rebuilding

(C-L1H)

1H: At start of iteration

(C-L2N)

2N: At start of iteration

(C-L3L)

3L: At start of iteration

(C-Imp)

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Implementing clock schedule...

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“normal” round partial clock tree rebuilding “legalized” round Even less clock tree rebuilding + full datapath legalization

Design Infrastructure

CCOpt Commands

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CCOpt Commands • ccoptDesign − Run optimization. − Covered earlier in this presentation.

• setCCOptMode − Perform configuration (clock tree/CCOpt algorithm). − More details on later slide.

• getCCoptMode − Retrieve configuration settings. − Same options as setCCoptMode.

• generateCCOptRCFactor − Compute resistance and capacitance multipliers. 25

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Clock Tree Routing Configuration •

•

26

setNanoRouteMode In general…

Options affect how clocks are routed during CCOpt

–drouteUseMultiCutViaEffort

CCOpt uses this to predict whether NanoRoute will use double vias (high) or single (low)

setCTSMode –routeClkNet

Specifies whether clocks are routed during import

–routeGuide

Specifies whether route guides are used for clock routing

–routeNonDefaultRule –routeLeafNonDefaultRule

Specifies non-default rules used for clock nets

–routeShielding –routeLeafShielding

Specifies whether clock nets are shielded

–routeBottomPreferredLayer –routeTopPreferredLayer –routeLeafBottomPreferredLater –routeLeafTopPreferredLayer

Specifies preferred layers for clock routes

–routePreferredExtraSpace –routeLeafPreferredExtraSpace

Specifies whether additional space (beyond nondefault rule spacing) is used for clock routing

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The setCCOptMode Command setCCOptMode -cts_buffer_cells -cts_inverter_cells -cts_clock_gating_cells -cts_logic_cells -cts_target_slew -cts_target_nonleaf_slew -erc [ignore|respect*|fix] -placement [off|on*|advanced] -io_opt [off|secondary*|on] -dp_hold [ignore|manage*|fix] -effort [low|medium*|high]

Allowable CTS buffers Allowable CTS inverters Allowable CTS clock gating cells Allowable CTS logic cells (muxes etc.) Transition time target Transition time target for leaf nets Treatment of design rule violations. Timing driven placement effort IO path optimization effort Hold optimization effort Overall runtime vs. QoR control knob

− Defaults for switches have “*” − CCOPT will auto-pick appropriate defaults for other switches 27

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