SkyPHY II™ DVB-S2 Transceiver ASIC (ECC4100) High-Speed Satellite Communications Modem Chip
PRELIMINARY DATA SHEET
SkyPHY II AT-A-GLANCE •
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DVB-S2 Compliant “Transceiver-on-a “Transceiver-on-a-Chip -Chip”” Dual DVB-S2 Demodulators and Shared LDPC/ BCH Decoder QPSK, 8PSK, 16APSK, and 32APSK Modulation Constant (CCM), Variable (VCM) and Adaptive (ACM) Coding and Modulation Integrated L-Band Tuners and A/D Converters Demodulator Bypass, Decoder Bypass and Drop & Insert Features ASI, SPI and PCI-E Outputs DiSEqC DiSEqC Interfaces Interf aces Built-in DVB-S2 DVB- S2 Transmitter Transmitter Single DVB-S Compliant Receiver Mobile Enhancements
TYPICAL APPLICATIONS Next Generation Set Top Boxes for Satellite Broadcast and Interactive TV DVB-S2 Compliant SCPC Modems with Adaptive Links Broadband VSATs with ACM Capabilities Mobile Terminals for COTM (Communicationson-the-Move) Networks Secure Ultra-High Ultra- High Bandwidth Video and/or and/or Data Links and Relays •
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Te SkyPHY II DVB-S2 transceiver chip by Efficient Channel Coding (“ECC”) is the world’s first DVB-S2 compliant satellite transceiveron-a-chip implemented in an Application Specific Integrated Circuit (ASIC). Integrating many of a broadband terminal’s components into a single chip, it significantly reduces size, weight, power consumption and manufacturing manufactu ring cost in contrast with solutions that require require separate tuners, A/D converters, c onverters, demodulators, modulators, encoders, decoders and various other discrete components. Te chip leverages the exceptional power and bandwidth efficiencies of the DVB-S2 standard. ECC’s unique design experience synthesizes Adaptive Coding and Modulation (ACM), Forward Error Correction (FEC), and Application Specific Integrated Circuit (ASIC) technology to create the premier solution for next generation satellite communication systems. Te SkyPHY II DVB-S2 transceiver chip covers a wide range of symbol rates and data formats, including MPEG transport streams, generic data streams a nd GSE packets. It may be embedded in fixed and mobile broadband via satellite equipment such as SCPC modems, VSAs, IRDs and hybrid terminals.
SkyPHY II™ DVB-S2 Transceiver ASIC (ECC4100)
BLOCK DIAGRAM
TUNER BYPASS
DECODER BYPASS (DROP)
DEMODULATOR BYPASS (INSERT) JTAG
I 2C
PCI-E
BERT
I DUAL A/D CONVERTER
L-BAND TUNER
Q
DVB-S2 DEMODULATOR TRANSPORT STREAM PROCESSOR
MODE ADAPTER
ASI
DiSEqC
DiSEqC
L-BAND TUNER
FRAME SYNC
PL HEADER DECODER
FRAME SYNC
PL HEADER DECODER
DECODER, DESCRAMBLER AND CHANNEL ARBITER
PL HEADER DECODER
SPI
PL HEADER DECODER
TUNER BYPASS I DUAL A/D CONVERTER
Q
TRANSPORT STREAM PROCESSOR
MODE ADAPTER
ASI
DVB-S2 DEMODULATOR
DVB-S RECEIVER PROGRAMABLE TRANSMITTER
Te SkyPHY II DVB-S2 transceiver chip is compliant with interactive services modes defined in the DVB-S2 standard that allow network operators to offer the benefits of ACM to their subscribers. Its distinctive architecture enables vendors of interactive, broadcast and mobile satellite communications equipment to deliver cost-effective, high-performance products to the consumer, enterprise and government markets. Modulation, demodulation, decoding and transport stream processing functions are integrated into a single chip along with two L-band tuners and four A/D converters. Te chip is a complete front-end product for Digital Video Recorder (DVR) equipped satellite receivers and interactive Home Media Centers. It is also backwards compatible such that one channel receives a DVB-S signal while the other channel simultaneously receives a DVB-S2 waveform. Te chip processes MPEG transport streams, generic data streams or encapsulated GSE packets. Data may be multiplexed and filtered according to a stream identifier in the DVB-S2 baseband header or a set of PIDs. Extracted, filtered and demultiplexed data are then output via ASI, SPI or PCI-E interfaces.
PLL EXTERNAL CLOCK
PCR SAMPLE CLOCK
Te A/D converters operate at rates up to 200 MHz and generate 8-bit digital I-Q samples. Te maximum receive symbol rate is equal to 0.5 times the sample clock rate (e.g. 100MSps for a 200MHz clock). Te SkyPHY II DVB-S2 transceiver chip reduces the timeto-market for vendors who design and manufacture oneway and two-way terminals. It is fabricated using the latest 65nm process technology and is delivered in a highly reliable BGA package. Te ratio of bits per symbol is equal to the total number of bits, including DVB-S2 frame overhead, divided by the total number of modulated symbols. Required Es/ No measures the implementation losses for the DVB-S2 modulator, frequency upconverter and SkyPHY II DVBS2 transceiver chip in L-band loopback. Te SkyPHY II DVB-S2 transceiver chip evaluation board has an intuitive web based graphical user interface and facilitates the integration and testing of the device in customer’s platforms.
SkyPHY II™ DVB-S2 Transceiver ASIC (ECC4100)
KEY BENEFITS Reduces Size, Weight, Power and Cost High degree of integration Reduction in size, weight and power consumption versus multi-component solutions Significant savings in terms of bill-of-material costs • • •
Improves Link Budget Performance Low Implementation Loss Achieves Near Shannon-Limit Performance Improved Link Performance (Relative to Legacy DVB-S Systems) 35% more throughput or equivalently 25% less bandwidth Smaller receive antenna or lower downlink EIRP required ACM doubles system capacity under typical conditions 2.8 dB more link margin on average • •
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Boosts Link Availability Dynamic SNR range greater than 14 dB ACM counters rain fades with 28 modulation and coding choices Maximum likelihood phase tracking provides excellent phase noise performance Usable satellite transponder footprint extended to geographic edge-of- coverage • • • •
Reduces Time-to-Design and Time-to-Market Complete System-on-a-Chip architecture facilitates rapid, low-cost terminal development Flexible evaluation platform, easy-to- configure software and technical support Significant savings on bill-of-material costs as compared to multi-component solutions • • •
Targets Professional Satcom Applications Interoperable with commercial-off-the-shelf DVB-S2 modulators Open standard implementation suitable for multi-vendor environment • •
DVB-S2 PERFORMANCE CURVES 4 3.8
16APSK THEORETICAL
3.6 3.4
K P S 6 A 1 2 B - S V D
3.2
) l o b m y s / s t i b ( Y C N E I C I F F E L A R T C E P S
M Q A 1 6 G 8PSK S N D THEORETICAL B D V
3 2.8 2.6 2.4
S 2 V B D
2.2
K 8 P S
P S K G 8 N S D V B D
2 1.8
QPSK THEORETICAL
1.6 1.4 1.2
- S 2 D V B
1
P S K S Q B D V
K Q P S
0.8 0.6 0.4 -2
-1
0
1
2
3
4
5
6
7
8
SIGNAL TO NOISE RATIO (Es/No) (dB)
9
10
11
12
13
14
15
SkyPHY II™ DVB-S2 Transceiver ASIC (ECC4100) PRELIMINARY TECHNICAL SPECIFICATIONS DVB-S2 Receivers Input Frequency Range: 950 – 2150 MHz L-band Tuners (2) (950 to 2150MHz) A/D Converters (4) (200M samples per second) (8 bits per sample) Receive Channel Rates: 100 kSps - 100 MSps Code Rates: 1/4, 1/3 2/5, 1/2, 3/5, 2/3, 3/4, 5/6, 8/9, 9/10 (28 MODCODES) Modes: CCM, VCM and ACM ASI Outputs (2) / SPI Output (1) DiSEqC Interfaces (2) •
SkyPHY II DVB-S2 RECEIVER PERFORMANCE
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(64,800b Frames Measured at 30MSps)
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MOD
LDPC CODE IDENTIFIER
BW EFFICIENCY
ES/NO [dB] (QEF)
EB/NO [dB] (QEF)
QPSK
1/4
0.49
-1.60
1.50
QPSK
1/3
0.66
-0.90
0.90
QPSK
2/5
0.70
0.10
1.10
DVB-S2 Transmitter Output Frequency Range: 950 – 1450 MHz (10 kHz steps) D/A Convert ers (2) Transmit Channel Rates: 100 kSps – 100 MSps Modulation Types: QPSK, 8PSK, 16APSK, 32APSK Code Rates: 1/4, 1/3 2/5, 1/2, 3/5, 2/3, 3/4, 5/6, 8/9, 9/10 (28 MODCODES) Modes: CCM, VCM and ACM ASI Input (1)
QPSK
1/2
0.99
1.30
1.30
QPSK
3/5
1.19
2.70
2.00
QPSK
2/3
1.32
3.30
2.10
QPSK
3/4
1.49
4.20
2.50
QPSK
4/5
1.59
4.90
2.90
QPSK
5/6
1.65
5.40
3.20
DVB-S2 Configuration Matched Filtering with 0.20, 0.25 or 0.35 Roll-off Factor Normal Frames (64,800 bits) or Short Frames (16,800 bits) Pilot Tone Insertion PCR Reconstruction Null Packet Insertion Fast Carrier Acquisition Automatic Carrier Search Automatic Spectrum Inversion Power Conversation Modes
QPSK
8/9
1.77
6.40
3.90
QPSK
9/10
1.79
6.60
4.10
8PSK
3/5
1.78
5.90
3.40
8PSK
2/3
1.98
6.90
3.90
8PSK
3/4
2.23
8.20
4.70
8PSK
5/6
2.48
9.60
5.70
8PSK
8/9
2.65
10.90
6.70
8PSK
9/10
2.68
11.20
6.90
16APSK
2/3
2.64
9.30
5.10
16APSK
3/4
2.97
10.50
5.80
16APSK
4/5
3.17
11.40
6.40
16APSK
5/6
3.30
11.90
6.70
16APSK
8/9
3.52
13.10
7.60
16APSK
9/10
3.57
13.30
7.80
32APSK
3/4
3.70
13.20
7.50
32APSK
4/5
3.95
14.10
8.10
32APSK
5/6
4.12
14.70
8.60
32APSK
8/9
4.39
16.10
9.70
32APSK
9/10
4.45
16.40
10.00
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Packet & Stream Processing MPEG Transport Streams, Generic Data Streams or GSE Packets Transport Stream Multiplexing Stream Identifier Filtering of DVB- S2 Baseband Headers PID Filtering of MPEG Transport Streams Transport Layer Bypass (Outputs Full Baseband Frames) GSE Packet Extraction 400 Mbps Maximum Transport Stream Rate • • • • • • •
Diagnostic & Clock Interfaces PCI Express I2C Interface BERT Interface JTAG Boundary Scan External Clock Reference Input PCR Reconstructed from DVB-S2 Carrier Signal • • • • • •
Efficient Channel Coding 4830 East 49th Street Cuyahoga Heights, OH 44125
216.706.7800 216.706.7801 Fax: Email:
[email protected] www.viasat.com/ecc Tel:
This data sheet is intended solely to provide advance information about products under development. ECC reserves the right to make changes and corrections to this data sheet and these products at any time and without notice. ECC assumes no liability for these products in accordance with the standard terms and conditions of sale. Purchasers are solely responsible for the selection and application of these products. No license, express or implied, by estoppel or other wise, to any intellectual property rights is granted by this data sheet. Copyright © 2009 ViaSat, Inc. All rights reser ved. Printed in the USA. SkyPHY is a trademark of Efficient Channel Coding, Inc. All other trademarks mentioned are the sole property of their respective companies. Specifications and product availability are subject to change without notice.
