EC6601 VLSI Design Model Qb

October 27, 2017 | Author: xperiaash | Category: Cmos, Mosfet, Field Effect Transistor, Logic Gate, Field Programmable Gate Array
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EC6601 VLSI Design

Department of Electronics and Communication Engineering


AUTHORS 1. Mr. M. Yuvaraj, Assistant Professor, Dept. of ECE, Agni College of Technology.

2. Mrs. A Shifana Parween, Assistant Professor, Dept. of ECE, Agni College of Technology.

3. Mr. G. Laxmanaa , Assistant Professor, Dept. of ECE, Agni College of Technology.


Department of ECE, Agni College of Technology

EC6601 VLSI Design

1. What are the different operating regions foe an MOS transistor? _ Cutoff region _ Non- Saturated Region _ Saturated Region

2. What is Channel-length modulation? The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.

3. Define Threshold voltage in CMOS? The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

4. What is Body effect? The threshold volatge VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.

5. What is Scaling? Proportional adjustment of the dimensions of an electronic device while maintaining the electrical properties of the device, results in a device either larger or smaller than the unscaled device

6. What is Elmore’s Constant. In general, most circuits of interest can be represented as an RC tree, i.e., an RC circuit with no loops. The root of the tree is the voltage source and the leaves are the capacitors at the ends of the branches. The Elmore delay model [Elmore48] estimates the delay from a source switching to one of the leaf nodes changing as the sum over each node I of the capacitance Cion the node, multiplied by the effective resistance Rison the shared path from the source to the node and the leaf. Application of Elmore delay is best illustrated through examples.


Department of ECE, Agni College of Technology

EC6601 VLSI Design

7. Define Static CMOS logic. The principle of static CMOS logic is that the output is connected to ground through an n-block and to VDD through a dual p-block. Without changes of the inputs this gate consumes only the leakage currents of some transistors. When it is switching it draws an additional current which is needed to charge and discharge the internal capacitances. and the load. Although the gate's logic function is ideally independent of the transistor channel widths, they determine the dynamic behavior essentially: wider transistors will switch a capacitive load faster, but they will also cause a larger input capacitance of the gate. Unless otherwise noted, minimum-width and, of course, minimum-channel-length transistors are assumed. For given capacitances the transistors' on-state current Ion will limit the switching speed of the gate and, consequently, the maximum clock frequency of a synchronous circuit.

8. Define Dynamic CMOS logic. Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed.


Department of ECE, Agni College of Technology

EC6601 VLSI Design

9. What is meant by transmission gate? A transmission gate, or analog switch, is defined as an electronic element that will selectively block or pass a signal level from the input to the output. This solid-state switch is comprised of a pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner so that both transistors are either on or off.A transmission gate consists of an n-channel transistor and p-channel transistor with separate gates and common source and drain.

10.What are the different types of power dissipation? There are three types of power dissipation. They are 

Static power dissipation. Ps= leakage power * supply voltage.

Dynamic power dissipation. Pd = CLV2dd fclk

Short circuit power dissipation Psc = Imean * Vdd

11.What are synchronizers? A synchronizer is a circuit that accepts an input that can change at arbitrary times and produces an output aligned to the synchronizer’s clock. Because the input can change dur- ing the synchronizer’s aperture, the synchronizer has a nonzero probability of producing a metastable output


Department of ECE, Agni College of Technology

EC6601 VLSI Design

12. State bistability principle A bistable circuit has two stable states. In absence of any triggering, the circuit remains in a single state (assuming that the power supply remains applied to the circuit), and hence remembers a value. A trigger pulse must be applied to change the state of the circuit. Another common name for a bistable circuit is flip-flop (unfortunately, an edgetriggered register is also referred to as a flip-flop).

13. Explain about C2MOS latch. The dynamic latch of Figure 10.17(d) can also be drawn as a clocked tristate. Such a form is sometimes called clocked CMOS (C2MOS) the output is driven through the nMOS and pMOS working in parallel. C2MOS is slightly smaller because it eliminates two contacts.

14. What is meant by true single phase clocked register? The True Single-Phase Clocked Register (TSPCR) uses a single clock (without an inverse clock). The basic single-phase positive and negative latches are shown in Figure 7.30. For the positive latch, when CLK is high, the latch is in the transparent mode and corresponds to two cascaded inverters; the latch is noninverting, and propagates the input to the output. On the other hand, whenC LK = 0, both inverters are disabled, and the latch is in hold-mode. Only the pull-up networks are still active, while the pull-down circuits are deactivated. As a result of the dual-stage approach, no signal can ever propagate from the input of the latch to the output in thism ode. A register can be constructed by cascading positive and negative latches.


Define pipelining. Pipelining is a popular design technique often used to accelerate the operation of the datapaths in digital processors. The idea is easily explained with the example of Figure 7.40a. The goal of the presented circuit is to computelog(|a - b|), where both a and


Department of ECE, Agni College of Technology

EC6601 VLSI Design

b represent streams of numbers, that is, the computation must be performed on a large set of input values.

16.What is meant by Datapath circuits? A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations, registers, and buses.[1] Along with the control unit it composes the central processing unit (CPU).

17.How CLA differ from RCA. CLA


The carry lookahead adder (CLA) solves the carry delay problem by calculating the carry signals in advance, based on the input signals. It is based on the fact that a carry signal will be generated in two cases: (1) when both bits ai and bi are 1, or (2) when one of the two bits is and the carry-in is 1

In the ripple carry adder, the output is known after the carry generated by the previous stage is produced. Thus, the sum of the most significant bit is only available after the carry signal has rippled through the adder from the least significant stage to the most significant stage. As a result, the final sum and carry bits will be valid after a considerable delay.

18.List out different high speed adders.     

Carry look ahead adder Carry skip adder Carry save adder Carry select adder Carry bypass adder

19.Define Accumulator. An accumulator is a register for short-term, intermediate storage of arithmetic and logic data in a computer's CPU (central processing unit). The term "accumulator" is rarely used in reference to contemporary CPUs, having been replaced around the turn of the millennium by the term "register." In a modern computers, any register can function as an accumulator.


Department of ECE, Agni College of Technology

EC6601 VLSI Design

20.Draw the generic block diagram of digital processor?

21. Write the design style classification? The IC design style can be classified as  

Full custom Design ASICs Semi custom Design ASICs o Standard Cell Design o Gate Array Design  Channeled Gate Array  Channel less Gate Array Programmable ASICs o PLDs o FPGA

22.Differentiate between channeled & channel less gate array. The channeled gate array 


The channeled gate array was the first

channel less gate array •

This channel less gate-array

to be developed . In a channeled gate

architecture is now more widely used .

array space is left between the rows of

The routing on a channelless gate array

transistors for wiring.

uses rows of unused transistors.

A channeled gate array is similar to a

The key difference between a channel

CBIC. Both use the rows of cells

less gate array and channeled gate array

separated by channels used for

is that there are no predefined areas set

interconnect. One difference is that the

aside for routing between cells on a

space for interconnect between rows of

channel less gate array. Instead we

cells are fixed in height in a channeled

route over the top of the gate-array

Department of ECE, Agni College of Technology

EC6601 VLSI Design

gate array, whereas the space between

devices. We can do this because we

rows of cells may be adjusted in a

customize the contact layer that defines


the connections between metal 1, the first layer of metal, and the transistors.

23. What is a FPGA? A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000 equivalent gates.

24.What is an antifuse? An antifuse is normally high resistance (>). On application of appropriate 100M

programming voltages, the antifuse is changed permanently to a low-resistance structure (200-500).


Department of ECE, Agni College of Technology

EC6601 VLSI Design

1. A. Discuss DC transfer characteristics of the CMOS.


DC transfer characteristics Digital circuits are merely analog circuits used over a special portion of their range. The DC transfer characteristics of a circuit relate the output voltage to the input voltage, assuming the input changes slowly enough that capacitances have plenty of time to charge or discharge. Specific ranges of input and output voltages are defined as valid 0 and 1 logic levels. This section explores the DC transfer characteristics of CMOS gates and pass transistors. Static CMOS Inverter DC Characteristics Let us derive the DC transfer function (Vout vs. Vin) for the static CMOS inverter shownin Figure 2.25. We begin with Table 2.2, which outlines various regions of operation forthe n- and p-transistors. In this table, Vtnis the threshold voltage of the n-channel device, and Vtpis the threshold voltage of the p-channel device. Note that Vtpis negative. The equations are given both in terms of Vgs/Vdsand Vin /Vout. As the source of the nMOS transistor is grounded, Vgsn= Vin and Vdsn= Vout. As the source of the pMOS transistoristied to VDD, Vgsp= Vin – VDD and Vdsp= Vout – VDD.The objective is to find the variation in output voltage (Vout) as a function of the inputvoltage (Vin). This may be done graphically, analytically (see Exercise 2.16), or through simulation [Carr72]. Given Vin, we must find Vout subject to the constraint that Idsn=|Idsp|. For simplicity, we assume Vtp= –Vtnand that the pMOS transistor is 2–3 times as wide as the nMOS transistor so �n = �p. We relax this assumption in Section 2.5.2.We comnce with the graphical representation of the simple algebraic equations described by EQ (2.10) for the two transistors shown in Figure 2.26(a). The plot shows Idsn and Idspin terms of Vdsnand Vdspfor various values of Vgsn and Vgsp. Figure 2.26(b)shows the same plot of Idsnand |Idsp| now in terms of Vout for various values of Vin. The possible operating points of the inverter, marked with dots, are the values of Vout where Idsn= |Idsp| for a given value of Vin. These operating points are plotted on Vout vs. Vin axes in Figure 2.26(c) to show the inverter DC transfer characteristics. The supply current IDD= Idsn= |Idsp| is also plotted against Vin in Figure 2.26(d) showing that both transistors are momentarily ON as Vin passes through voltages between GND and VDD, resulting ina pulse of current drawn from the power supply. The operation of the CMOS inverter can be divided into five regions indicated on Figure2.26(c). The state of each transistor in each region is shown in Table 2.3. In region A, then MOS transistor is OFF so the pMOS transistor pulls the output to VDD. In region B, then MOS transistor starts to turn ON, pulling the output down. In region C, both transistors are in saturation. Notice that ideal transistors are only in region C for Vin = VDD/2 and that the slope of the transfer curve in this example is – in this region, corresponding to infinite gain. Real transistors have finite output resistances on account of channel length modulation, described in Section 2.4.2, and thus have finite slopes over a broader region C. In region D, the pMOS transistor is partially ON and in region E, it is completely Region Condition p-device n-device Output A 0
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