easa - Module 5

PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS

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MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS (DCAM PART 66 CATEGORY B1.1/B2)

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WARNING

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This document is intended for the purposes of training only. The information contained herein is as accurate as possible at the time of issue, and is subject to ongoing amendments where necessary according to any regulatory journals and documents. Where the information contained in this document is in variation with other official journals and/or documents, the latter must be taken as the overriding document. The contents herein shall not be reproduced in any form without the expressed permission of ETD

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TABLE OF CONTENT 5.1 ELECTRONICS INSTRUMENT SYSTEM (DCAM Ref 5.1) Level 3……………………………………………………………………………….……….. 1

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5.1.1 Introduction………………………………………………………………………………………………………………………………………………………. 1 5.1.2 Integrated Digital Avionics System…………………………………………………………………………………………………………………………….. 4 5.1.3 Electronics Flight Instruments System (EFIS)………………………………………………………………………………………………………………… 6 5.1.4 Electronic Centralized Aircraft Monitoring (ECAM)……………………………………………………………………………………………………………14 5.1.5 Engine Indicating and Crew Alerting System (EICAS)………………………………………………………………………………………………………. 16 5.1.6 Flight Management System (FMS)…………………………………………………………………………………………………………………………….. 18 5.1.7 Cockpit Layouts…………………………………………………………………………………………………………………………………………………...20

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5.2 NUMBERING SYSTEMS (DCAM Ref 5.2) Level 2………………………………………………………………………………………….…..……………. 24 5.2.1 Decimal System………………………………………………………………………………………………………………………………………………….. 24 5.2.2 The Binary System………………………………………………………………………………………………………………………………………………. 26 5.2.3 The Octal System…………………………………………………………………………………………………………………………………………………38 5.2.4 Hexadecimal System……………………………………………………………………………………………………………………………………………..44 5.2.5 Binary Coded Decimal……………………………………………………………………………………………………………………………………………49 5.2.6 Adding……………………………………………………………………………………………………………………………………………………………...52 5.2.7 Subtraction………………………………………………………………………………………………………………………………………………………... 52 5.3 DATA CONVERSION (DCAM Ref 5.3) Level 2…………………………………………………………………………….…………………………………..56 5.3.1 Digital and Analogue Computers………………………………………………………………………………………………………………………………. 56 5.3.2 Digital Bus………………………………………………………………………………………………………………………………………………………… 59 5.3.3 Typical Digital System Inputs…………………………………………………………………………………………………………………………………… 60 5.3.4 Typical Digital Systems Outputs………………………………………………………………………………………………………………………………...62 5.3.5 Digital to Analogue / Analogue to Digital Conversion………………………………………………………………………………………………………... 64

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5.4 DATA BUSES (DCAM Ref 5.4) Level 2…………………………………………………………………………………………………………………………90 5.4.1 What is Data Bus?.................................................................................................................................................................................................... 91 5.4.2 About ARINC……………………………………………………………………………………………………………………………………………………... 93 5.4.3 Data Encoding……………………………………………………………………………………………………………………………………………………. 93 5.4.4 ARINC 429………………………………………………………………………………………………………………………………………………………... 97 5.4.5 MIL-STD-1553B………………………………………………………………………………………………………………………………………………….. 104 5.4.6 ARINC 629………………………………………………………………………………………………………………………………………………………... 106 5.4.7 Ethernet…………………………………………………………………………………………………………………………………………………………… 122

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5.5 LOGIC CIRCUITS (DCAM Ref 5.5) Level 2……………………………………………………………………………………………………………………..128 5.5.1 Logic Gates……………………………………………………………………………………………………………………………………………………….. 128 5.5.2 Electronic Gates in Circuit……………………………………………………………………………………………………………………………………… 138 5.5.3 Gate Application in Aircraft Systems……………………………………………………………………………………………………………………………150 5.5.4 Tri-state Devices…………………………………………………………………………………………………………………………………………………. 154 5.6 BASIC COMPUTER STRUCTURE (DCAM Ref 5.6) Level 2…………………………………………………………………………………………………156 5.6.1 Central Processing Unit…………………………………………………………………………………………………………………………………………. 157 5.6.2 Memories…………………………………………………………………………………………………………………………………………………………. 160 5.6.3 Magnetic Memory Types…………………………………………………………………………………………………………………………………………162 5.6.4 Solid State Memories……………………………………………………………………………………………………………………………………………. 172 5.6.5 Storage Capacity………………………………………………………………………………………………………………………………………………….179 5.6.6 Highway Structure……………………………………………………………………………………………………………………………………………….. 179 5.6.7 Instruction Words………………………………………………………………………………………………………………………………………………… 180 5.7 MICROPROCESSORS (DCAM Ref 5.7) Level 2………………………………………………………………………………………………………………181 5.7.1 Microprocessor (CPU) Structure and Operation……………………………………………………………………………………………………………… 181

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5.8 INTEGRATED CIRCUITS (DCAM Ref 5.8) Level 2…………………………………………………………………………………………………..……….184 5.8.1 Adders…………………………………………………………………………………………………………………………………………………………….. 184 5.8.2 Flip-Flops…………………………………………………………………………………………………………………………………………………………. 192 5.8.3 Counters…………………………………………………………………………………………………………………………………………………………... 197 5.8.4 Decoders………………………………………………………………………………………………………………………………………………………….. 200 5.8.5 Encoders………………………………………………………………………………………………………………………………………………………….. 210

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5.9 MULTIPLEXING (DCAM Ref 5.9) Level 2…………………………………………………………………………………………………………………..…..216

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5.9.1 Multiplexers……………………………………………………………………………………………………………………………………………………….. 216 5.9.2 De-multiplexer……………………………………………………………………………………………………………………………………………………. 220 5.10 FIBRE OPTICS (DCAM Ref.5.10) Level 2…………………………………………………………………………………………………………………….224 5.10.1 Definition of Fibre Optics………………………………………………………………………………………………………………………………………. 224 5.10.2 Fibre Optic Data Links…………………………………………………………………………………………………………………………………………. 224 5.10.3 Fibre Optic Systems……………………………………………………………………………………………………………………………………………. 226 5.10.4 Advantages and Disadvantages of Fibre Optics……………………………………………………………………………………………………………. 228 5.10.5 Frequency and Bandwidth…………………………………………………………………………………………………………………………………….. 230 5.10.6 Fibre Optic Concepts……………………………………………………………………………………………………………………………………………232 5.10.7 Transmission of Light Through Optical Fibres………………………………………………………………………………………………………………. 236 5.10.8 Basic Structure of an Optical Fibre…………………………………………………………………………………………………………………………… 242 5.10.9 Propagation of Light along a Fibre…………………………………………………………………………………………………………………………… 244 5.10.10 Fibre Types……………………………………………………………………………………………………………………………………………………. 253 5.10.11 Properties of Optical Fibre Transmission……………………………………………………………………………………………………………………260 5.10.12 Choice of Fibres………………………………………………………………………………………………………………………………………………..274 5.10.13 Joining Optical Fibre………………………………………………………………………………………………………………………………………….. 275 5.10.14 Aircraft Fibre Optic Networks………………………………………………………………………………………………………………………………… 279 5.10.15 Applications in Aircraft Systems……………………………………………………………………………………………………………………………...284 5.10.16 Fibre Optic Testing……………………………………………………………………………………………………………………………………………. 287

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5.11 ELECTRONIC DISPLAYS (DCAM Ref.5.11) Level 2……………………………………….………………………………………….……………………288 5.11.1 Light Emitting Diodes (LEDs)…………………………………………………………………………………………………………………………………..288 5.11.2 Liquid Crystal Displays (LCDs)………………………………………………………………………………………………………………………………...290 5.11.3 Cathode Ray Tube (CRT)………………………………………………………………………………………………………………………………………294 5.11.4 Principle of the Colour CRT…………………………………………………………………………………………………………………………………… 302

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5.12 ELECTROSTATIC SENSITIVE DEVICES (DCAM Ref.5.12) Level 2………………………………….…………….…………………………………….304 5.12.1 What is an Electrostatic Discharge?....................................................................................................................................................................... 304 5.12.2 Typical Electrostatic Voltages…………………………………………………………………………………………………………………………………. 306 5.12.3 ESDS Equipment and Material Handling……………………………………………………………………………………………………………………. 310

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5.13 SOFTWARE MANAGEMENT (DCAM Ref.5.13) Level 2……………………………..……………………………………………………………..………316 5.13.1 Introduction……………………………………………………………………………………………………………………………………………………… 316 5.13.2 Requirements…………………………………………………………………………………………………………………………………………………… 317 5.14 ELECTROMAGNETIC ENVIRONMENT (DCAM Ref.5.14) Level 2………………………………………………………………………………………..320 5.14.1 General…………………………………………………………………………………………………………………………………………………………...320 5.14.2 Lightning versus Static Discharge………………………………………………………………………………………………………………………….… 322 5.14.3 Electromagnetic Interference (HIRF)………………………………………………………………………………………………………………………… 324 5.14.4 Lightning Strikes……………………………………………………………………………………………………………………………………………….. 325 5.14.5 Protection………………………………………………………………………………………………………………………………………………………... 326 5.14.6 Maintenance…………………………………………………………………………………………………………………………………………………….. 326 5.14.7 Static……………………………………………………………………………………………………………………………………………………………... 327 5.15 TYPICAL ELECTRONIC/DIGITAL AIRCRAFT SYSTEMS (DCAM Ref.5.15) Level 2……………………………………………………..……………334 5.15.1 On Board Maintenance and BITE……………………………………………………….……………………………………………………………………. 334 5.15.2 ARINC Communication Addressing and Reporting System (ACARS)…………………………………………………………………………………… 342 5.15.3 Electronic Centralised Aircraft Monitors (ECAM)…………………………………………………………………………………………………………….344 For Training Purposes Only

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5.15.4 Electronic Flight Instrument Systems (EFIS)…………………………………………………………………………………………………………………354 5.15.5 Engine Indicating and Crew Alerting System (EICAS)……………………………………………………………………………………………………. 372 5.15.6 Fly-By-Wire……………………………………………………………………………………………………………………………………………………… 396 5.15.7 Flight Management Systems (FMS)………………………………………………………………………………………………………………………….. 416 5.15.8 Global Positioning Systems (GPS)…………………………………………………………………………………………………………………………… 422 5.15.9 Inertial Reference Systems (IRS)…………………………………………………………………………………………………………………………….. 438 5.15.10 Traffic Alert Collision Avoidance System (TCAS)…………………………………………………………………………………………………………. 464 5.15.11 Integrated Modular Avionics (IMA)………………………………………………………………………………………………………………………….. 476 5.15.12 Cabin Systems………………………………………………………………………………………………………………………………………………… 480 5.15.13 Information Systems………………………………………………………………………………………………………………………………………….. 496

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1 ELECTRONIC INSTRUMENT SYSTEM (EIS) 5.1.1 Introduction In a modern aircraft, the cockpit crew is provided with many different information. To handle this amount of data with a minimum of manpower and ’in time’; it is necessary to reduce the number of indicators in the cockpit, i.e. no longer using a separate indicator for each system/sensor.

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Figure 1.1 Cockpit of Conventional Design (Separate indicator for each system/sensor)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) This is achieved by displaying all data from the various systems on some few ‘multi-purpose indicators’. A system which handles the flow and display of data of many or all aircraft systems is called an ’integrated digital avionic system’. The advantages of such a system are - it provides a better overview over the actual condition of each connected system - it reduces the flight crew’s workload - less time (and money) is required for maintenance - it saves electrical power consumption - the weight is reduced (wiring, units).

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Figure 1.2 Cockpit with EFIS (Multi-purpose Indicators)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) A digital avionic system replaces the former instrumentation by an electronic flight instrument system (EFIS) and/or an engine indication and crew alerting system (EICAS). This includes the change from old analogue equipment to modern systems, because digital outputs are required.

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Figure 1.3 ‘Fully Integrated’ Cockpit Design with EFIS and EICAS

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.2 Integrated Digital Avionics System The new generation of aircraft avionics is highly integrated. It saves electrical power and weight. It provides high accuracy and reliability. The level of integration varies (whether only the main avionic systems are combined or all), depending on the type of aircraft.

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An essential function of an integrated digital avionic system is the exchange of information between subsystems and/or between line replaceable units (LRU) within a subsystem. Note: A line--replaceable unit (LRU) (also called ’black box’) is a unit, which can be replaced at flight--line level in a short time.

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To incorporate a fully integrated digital avionic system and to ensure the required information exchange, a digital data bus is required. This bus is used to provide a 2-way interface between various computers, sensors and indicators. The interface between computers and/or external devices (e.g. transceivers, receivers) is accomplished via the digital data bus. Data may travel ’one way’ or in 2 directions, depending on the system design.

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Figure 1.4 Conventional and Integrated Designs

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) Typically, the data bus is a serial bus on which the data are transmitted sequentially, i.e. one word after the other. A serial bus is commonly used for longdistance data transmissions (more than 50 m) as required in large aircraft. The bus is made up of a twisted pair of wires which are shielded and jacketed. The shielding is grounded at all terminal ends and breakouts to keep bit distortion at a low level. Shield grounding and high voltage spike protection within the individual data--receiving components ensure accurate transmissions.

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Transmission of data within micro-computers, between micro-computers and external devices as well as between other components can be accomplished with 8-, 16-, 32- and 64-bit digital data words, depending on the system layout.

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Some of these information are in the form of discrete data. Typically, these data are formed by switching between +28 V DC and open (or between ground and open). Discrete data are carried on a single wire.

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This type of information is used for annunciators, warnings and wherever simple ‘condition information’ is sufficient. This is a small portion of the total information interchange.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.3 Electronics Flight Instruments System (EFIS) A basic EFIS system is more than an Electronic Flight Director with Electronics Attitude and Direction Indicators (EADIs) or Primary Flight Displays (PFDs) and Electronic Horizontal Situation Indicators (EHSIs) or Navigation Displays (NDs) as display units. A typical EFIS system consists of two or more display units and their associated drive and control units. 5.1.3.1 Electronic Attitude and Direction Indicator The electronic attitude direction indicator (EADI - see Fig. 1.5) is normally comprises: • • • • • • • •

an attitude indicator a fixed aircraft symbol pitch and bank command bars a glide slope indicator a localizer deviation indicator a slip indicator flight mode anunciator various warning flags

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The aircraft' s attitude relative to the horizon is indicated by the fixed aircraft symbol and the flight command bars. The pilot can adjust the symbol to one of three flight modes. To fly the aircraft with the command bars armed, the pilot simply inserts the aircraft symbol between the command bars. The command bars move up for a climb or down for descent, roll left or right to provide lateral guidance. They display the computed angle of bank for standard-rate turns to enable the pilot to reach and fly a selected heading or track. The bars also show pitch commands that allow the pilot to capture and fly an ILS glide slope, a pre-selected pitch attitude, or maintain a selected barometric altitude. To comply with the directions indicated by the command bars, the pilot manoeuvres the aircraft to align the fixed symbol with the command bars. When not using the bars, the pilot can move them out of view. The glide slope deviation pointer represents the centre of the instrument landing system (ILS) glide slope and displays vertical deviation of the aircraft from the glide slope centre. The glide slope scale centreline shows aircraft position in relation to the glide slope.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) The localizer deviation pointer, a symbolic runway, represents the centre of the ILS localizer, and comes into view when the pilot has acquired the glide slope. The expanded scale movement shows lateral deviation from the localizer and is approximately twice as sensitive as the lateral deviation bar in the horizontal situation indicator. The selected flight mode is displayed in the lower left of the EADI for pitch modes, and lower right for lateral modes. The slip indicator provides an indication of slip or skid indications.

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Figure 1.5 A typical EADI display

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.3.2 Electronic Horizontal Situation Indicator The electronic horizontal situation indicator (EHSI) assists pilots with the interpretation of information provided by a number of different navigations aids. There are various types of EHSI but essentially they all perform the same function. An EHSI display (see Fig. 1.6) can be configured to display a variety of information (combined in various different ways) including: • • • • • •

heading indication radio magnetic indication (RMI) track indication range indication wind speed and direction VOR, DME, ILS or ADF information.

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Figure 1.6 A typical EHSI display

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.3.3 Flight Director Systems The major components of a flight director system (FDS) are the electronic attitude and direction indicator (EADI) and electronic horizontal situation indicator (EHSI) working together with a mode selector and a flight director computer.

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The FDS combines the outputs of the electronic flight instruments to provide an easily interpreted display of the aircraft' s flight path. By comparing this information with the pre-programmed flight path, the system can automatically compute the necessary flight control commands to obtain and hold the desired path. The flight director system receives information from the: • • • • •

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attitude gyro VOR/localizer/glide slope receiver radio altimeter compass system barometric sensors

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The flight director computer uses this data to provide flight control command information that enables the aircraft to: • • • • •

fly a selected heading fly a predetermined pitch attitude maintain altitude intercept a selected VOR track and maintain that track fly an ILS glide slope/localizer

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) The flight director control panel comprises a mode selector switch and control panel that provides the input information used by the FDS. The pitch command control pre-sets the desired pitch angle of the aircraft for climb or descent. The command bars on the FDS then display the computed attitude to maintain the pre-selected pitch angle. The pilot may choose from among many modes including the HDG (heading) mode, the VOR/LOC (localizer tracking) mode, or the AUTO APP or G/S (automatic capture and tracking of ILS and glide path) mode. The auto mode has a fully automatic pitch selection computer that takes into account aircraft performance and wind conditions, and operates once the pilot has reached the ILS glide slope. Flight director systems have become increasingly more sophisticated in recent years.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.3.4 Primary Flight Display (PFD) The typical EFIS PFD is a multicolour cathode ray tube (CRT) or liquid crystal display (LCD) display unit that presents a display of aircraft attitude and flight control system commands including VOR, localizer, TACAN (Tactical Air Navigation), or RNAV (Area Navigation) deviation together with glide slope or preselected altitude deviation. Various other information can be displayed including mode annunciation, radar altitude, decision height and excessive ILS deviation.

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Figure 1.7 EFIS primary flight display

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.3.5 Navigation Display (ND) Like the EFIS PFD, a typical EFIS ND takes the form of a multicolour CRT or LCD display unit. However, in this case the display shows the aircraft' s horizontal situation information which, according to the display mode selected, can include compass heading, selected heading, selected VOR, localizer, or RNAV course and deviation (including annunciation or deviation type), navigation source annunciation, digital selected course/desired track readout, excessive ELS deviation, to/from information, distance to station/waypoint, glide slope, or VNAV deviation, ground speed, time-to-go, elapsed time or wind, course information and source annunciation from a second navigation source, weather radar target alert, waypoint alert when RNAV is the navigation source, and a bearing pointer that can be driven by VOR, RNAV or ADF sources as selected on the display select panel. The display mode can also be set to approach format or en-route format with or without weather radar information included in the display.

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Figure 1.8 EFIS navigation display

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.3.6 Display Select Panel (DSP) The display select panel provides navigation sensor selection, bearing pointer selection, format selection, navigation data selection (ground speed, time-togo, time, and wind direction/speed), and the selection of VNAV (if the aircraft has this system), weather, or second navigation source on the ND. A DH SET control that allows decision height to be set on the PFD is also provided. Additionally, course, course direct to, and heading are selected from the DSP. 5.1.3.7 Display Processor Unit (DPU)

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The display processor unit provides sensor input processing and switching, the necessary deflection and video signals, and power for the electronic flight displays. The DPU is capable of driving two electronic flight displays with different deflection and video signals. For example, a PFD on one display and an ND on the other.

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5.1.3.8 Weather Radar Panel (WXP)

The weather radar panel provides MODE control (OFF, STBY, TEST, NORM, WX, and MAP), RANGE selection (10, 25, 50, 100, 200 and 300 nm), and system operating Controls for the display of weather radar information on the MFD and the ND when RDR is selected on the MFD and/or the DSP. 5.1.3.9 Multifunction Display (MFD)

The multifunction display takes the form of another multicolour CRT or active-matrix LCD display unit. The display is normally mounted on the instrument panel in the space provided for the weather radar (WXR) indicator. Standard functions displayed by the unit include weather radar, pictorial navigation map, and in some systems, check list and other operating data. Additionally, the MFD can display flight data or navigation data in case of a PFD or ND failure. 5.1.3.10 Multifunction Processor Unit (MPU)

The multifunction processor unit provides sensor input processing and switching and the necessary deflection and video signals for the multifunction display. The MPU can provide the deflection and video signals to the PFD and ND displays in the event of failures in either or both display processor units.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.4 Electronic Centralized Aircraft Monitoring (ECAM) Technical information concerning the state of an Airbus aircraft is displayed using the aircraft' s electronic centralized aircraft monitor (ECAM— see Fig. 1.9). This normally takes the form of two CRT or LCD displays that are vertically arranged in the centre of the instrument panel. The upper (primary) display shows the primary engine parameters (N1/fan speed, EGT, N2/high pressure turbine speed), as well as the fuel flow, the status of lift augmentation devices (flap and slat positions), along with other information. The lower (secondary) ECAM display presents additional information including that relating to any system malfunction and its consequences.

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Figure 1.9 A320 ECAM displays located above the centre console between the captain and first officer

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) Test your understanding Figure 1.10 shows a flight deck display.

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Figure 1.10

(a) (b) (c) (d) (e)

Identify the display. What information is currently displayed? Where is the display usually found? What fan speed is indicated? What temperature is indicated?

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.5 Engine Indicating and Crew Alerting System (EICAS) In Boeing aircraft the equivalent integrated electronic aircraft monitoring system is known as the engine indicating and crew alerting system (EICAS). This system provides graphical monitoring of the engines of later Boeing aircraft, replacing a large number of individual panel-mounted instruments. In common with the Airbus ECAM system, EICAS uses two vertically mounted centrally located displays (see Fig. 1.11).

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The upper (primary) EICAS display shows the engine parameters and alert messages whilst the lower (secondary) display provides supplementary data (including advisory and warning information).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3)

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Figure 1.11 EICAS display

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.6 Flight Management System (FMS) The flight management system (FMS) fitted to a modern passenger aircraft brings together data and information gathered from the electronic flight instruments, aircraft monitoring and navigation systems, and provides outputs that can be used for automatic control of the aircraft from immediately after take-off to final approach and landing. The key elements of an FMS include a flight management computer (FMC), control and display unit (CDU), IRS, AFCS, and a system of data buses that facilitates the interchange of data with the other digital and computerized systems and instruments fitted to the aircraft.

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Two FMS are fitted, one for the captain and one for the first officer. During normal operation the two systems share the incoming data. However, each system can be made to operate independently in the event of failure. By automatically comparing (on a continuous basis) the indications and outputs provided by the two systems it is possible to detect faults within the system and avoid erroneous indications. The inputs to the FMC are derived from several other systems including IRS, EICAS, engine thrust management computer, and the air data computer. Figures 1.12 and 1.13 shows the FMC control and display units fitted to an A320 aircraft.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3)

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 1.12 Captain’s FMS CDU

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Figure 1.13 A320 cockpit layout

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) 5.1.7 Cockpit Layouts Major developments in display technology and the introduction of increasingly sophisticated aircraft computer systems have meant that cockpit layouts have been subject to continuous change over the past few decades. At the same time, aircraft designers have had to respond to the need to ensure that the flight crew are not overburdened with information and that relevant data is presented in an appropriate form and at the time that it is needed.

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Figure 1.14 shows how the modern EFIS layouts have evolved progressively from the basic-T instrument configuration found in non-EFIS aircraft. Maintaining the relative position of the instruments has been important in allowing pilots to adapt from one aircraft type to another. At the same time, the large size of modern CRT and LCD displays, coupled with the ability of these instruments to display combined data (for example, heading, airspeed and altitude) has led to a less-cluttered instrument panel (see Fig. 1.15). Lastly, a number of standby (or secondary) instruments are made available in order to provide the flight crew with reference information which may become invaluable in the case of a malfunction in the computer system.

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Basic T'flight instrument configuration

Basic EFIS flight instrument configuration

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Enhanced EFIS flight instrument configuration

Figure 1.14 Evolution of instrument layouts

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3)

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Figure 1.15 Captain' s flight instrument and display layout on the A320

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) Test your understanding 1. Identify each of the Boeing 767 flight instruments and displays shown in Fig. 1.16. 2. Classify the flight instruments in Question 1 as either primary or standby.

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Figure 1.16

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS ELECTRONIC INSTRUMENT SYSTEM (DCAM 5.1 L3) NOTES

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2 NUMBERING SYSTEMS Most digital transmission in today' s modern aircraft uses various types of number systems. Typically these would be decimal, binary, octal and hexadecimal, or various forms of these systems. 5.2.1 Decimal System

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This is the system in everyday use, there are 10 digits (0 to 9 inclusive), so it has a ‘base’ or ‘radix'(number of digits used in the system) of 10. Taking the number 72306 can be written as:

(7 × 10,000) + (2 × 1000) + (3 × 100) + (0 × 10) + (6 × 1)

(

) (

) (

) (

) (

= 7 × 10 4 + 2 × 10 3 + 3 × 10 2 + 0 × 101 + 6 × 10 0 = 72306

)

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Each digit is effectively multiplied by a power of 10.

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Note that to write 19.526 in powers of 10 then:

(1× 10 ) + (9 × 10 ) + (5 × 10 ) + (2 × 10 ) + (6 × 10 ) 1

0

−1

−2

−3

1 1 1 = .006 = .02 + 6 × = .5 + 2 × 10 100 1000 = 10 + 9 + .5 + .02 + .006 = 10 + 9 + 5 × = 19.526

Note that 100 = 1, in fact any number to the power of nought = 1. Proof, using the number 3 i.e. 30 = 1

1=

9 32 = 2 = 3 2 × 3 − 2 = 3 2+ ( − 2 ) = 3 0 9 3

3 was used because it is an easy number to show you that any number to the power of nought is equal to 1. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) It can be seen that the decimal system is based on successive powers of 10, the number with the smallest value (100) is known as the least significant digit (LSD) and the number with the highest value is known as the most significant digit (MSD). The disadvantage of the decimal system for use in a digital computer is that the circuits which would be used, e.g. transistors, would have to have 10 discrete levels at collector current. For example 0mA (milliamps) = 0, 1mA = 1, 2mA - 2, 3mA = 3 etc. Such a system would be extremely difficult to operate because: a) Any variation of power supply would cause errors. b) Component tolerance would have to be virtually zero, and be unaffected by temperature variations. c) Component values will change with age.

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Any errors from the above may cause an error increment of one or two, giving an incorrect output (e.g. instead of 8 [correct reading] it might be 7 or 9).

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Precision is important, and to expect a circuit to be infallible in distinguishing between 10 different magnitudes of current is a bit much.

Where accuracy and speed are important it would be better to use a system which has just two states. Reliance is high because the circuit is either HIGH (voltage level) or LOW (voltage level) or ON and OFF and component characteristics variations are unimportant. The system that is the basis of today' s digital processing is the "two states" BINARY SYSTEM.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.2 The Binary System This has a base or radix of 2. As in the decimal system, we can represent any number in successive powers of 2. For example:

27 = 2 4 + 2 3 + 21 + 2 0 = 16 + 8 + 2 + 1 further expanded

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= 1 × 2 4 + 1 × 2 3 + 0 × 2 2 + 1 × 21 + 1 × 2 0 ↓ 1

↓ 1

↓ 0

↓ 1

↓ 1

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means the binary number for 27 = 110112

To avoid confusion between systems with different radix this would be written as 110112 to identify it as a binary number. What about the fraction expressed as powers of 2?

1 = 0.5 2 1 .012 = 2 − 2 = 2 = 0.25 2 1 .0012 = 2 −3 = 3 = 0.125 2 1 .00012 = 2 − 4 = 4 = 0.0625 2 .12 = 2 −1 =

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Example Change 17.75 decimal to binary.

17.75 = 2 4 + 2 0 + 2 −1 + 2 −2 expanded gives

= 1 × 2 4 + 0 × 2 3 + 0 × 2 2 + 0 × 21 + 1 × 2 0 + 1 × 2 −1 + 1 × 2 −2 ↓ ↓ ↓ 1 0 0 17.75 = 10001.112

↓ 0

↓ 1

↓ ⋅ 1

↓ 1

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Note a binary digit is termed a bit.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.2.1 Binary/Decimal Equivalents The table below shows the relationship between Binary and Decimal numbers up to Decimal 21, but it could obviously be continued for larger numbers. Decimal Number 0 1 2 3 4 5 6 7 8 9 10

24 0 0 0 0 0 0 0 0 0 0 0

5-bit binary number (Word) Decimal Number 23 22 21 20 0 0 0 0 11 0 0 0 1 12 0 0 1 0 13 0 0 1 1 14 0 1 0 0 15 0 1 0 1 16 0 1 1 0 17 0 1 1 1 18 1 0 0 0 19 1 0 0 1 20 1 0 1 0 21 BINARY/DECIMAL EQUIVALENTS

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24 0 0 0 0 0 1 1 1 1 1 1

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5-bit binary number (Word) 23 22 21 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0

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20 1 0 1 0 1 0 1 0 1 0 1

From the table it can be seen that the binary number is longer than the decimal number but because of the very fast switching speeds of modern circuits this does not present a problem. Also because of the reliability of the two-state system, the practical advantages gained by using binary numbers are considerable.

ACTIVITY: Write the successive powers of 2 for the following decimal numbers and then expand to finally give the binary number. a) 19 b) 29 c) 15.125 d) 22.0625 This method is OK but when you get larger numbers it becomes much more difficult, to convert from decimal to binary, the successive division by two may be employed, the ' remainder'of any division (which must be either 0 or 1) is then recorded successively in a separate column. The following examples show the method used. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2)

Example 1 Convert 796 to binary 2 2 2 2 2 2 2 2 2 2

796 398 199 99 49 24 12 6 3 1 0

remainder remainder remainder remainder remainder remainder remainder remainder remainder remainder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Example 2 Convert 217 in binary form 2 2 2 2 2 2 2 2 2

217 108 54 27 13 6 3 1 0

remainder remainder remainder remainder remainder remainder remainder remainder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2)

NOTES

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) CONVERSION OF DECIMAL TO BINARY ACTIVITY: Convert the following decimal numbers to binary a) 846 b) 317 c) 147 You should practice converting the smaller number using powers of 2 and perhaps speed it up a bit. Example

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Convert 4510 to binary

Write down the successive powers of 2

(2 ) (2 ) (2 ) (2 ) (2 ) (2 ) 5

32

4

16

3

2

1

0

8

4

2

1

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Then make up the number, i.e.

(1 × 32) + (1 × 8) + (1 × 4) + (1× 1) = 45 So

32 16 8 4 2 1 1 0 1 1 0 1

The binary number is 1011012

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) ACTIVITY:

So the idea is to write down the powers of 2 and put 1' s in the powers you need to make up the number. Try these: a) 47 b) 32 c) 21

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) The following example shows you how to convert decimal fractions to binary. You use successive multiplication by two, recording the carries and then reading DOWN the carries column. Convert 0.615 to binary form

READ DOWN And write from left to right to give binary fraction: 0.1001112

0.615 x 2 1 230 x 0 460 x 0 920 x 1 840 x 1 680 x

2 2 2 2 2 2 ----- until required 1 360 x accuracy is obtained

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.2.2 Conversion of a Mixed Decimal to a Binary The next example shows how to convert a mixed decimal number to binary. Note that it must be treated in two parts as shown. Example Convert 14.625 to binary Separate into whole and fraction parts – i.e.: 14.625 = 14.000 + 0.625 (WHOLE) (FRACTION)

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Recombine the whole fraction parts to give: 14.62510 = 1110.1012

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Conversion of Binary to Decimal

Assume we have a binary number e.g., 1011012

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The easy way to convert this is to write the powers of 2 above each bit position starting from left and working towards the right e.g.:

32 16 8 4 2 1 the powers added 1 0 1 1 0 1

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So it can be seen that the number is: 32+8+4+1=4510

(there are no 16s and no 2s but one of each of the other values – 32, 8, 4 & 1)

Examples: 1.

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Convert 1101101 binary to decimal

Again, write the powers of 2 above each bit position.

64 32 16 8 4 2 1 1 1 0 1 1 0 1 So 64+32+8+4+1=10910

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 2.

Convert 1101.1 binary to decimal

Again, write the powers of 2 above each bit position.

8 4 2 1 .5 1 1 0 1 .1 So 8+4+1+.5=13.510 3.

Convert 1001110.112 to decimal

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64 32 16 8 4 2 1 .5 .25 1 0 0 1 1 1 0 .1 1 =64+8+4+2+.5+.25 =78.7510

ACTIVITY:

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Convert to decimal

a) 110011 b) 1110011 c) 1011.1 d) 1100.001

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.3 The Octal System In the binary system the number of bits in a word can be quite lengthy and problems can occur such as the high possibility of an error in manipulating so many digits. The octal system helps lessen these difficulties, being more compact and easily converted back to decimal or binary.

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The system uses the base or radix 8, this means of course, to convert from decimal to octal we divide by 8 then record the remainders as before and read upwards to get the octal number.

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To convert this number to binary split each octal number into it' s three figure binary number and join together.

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Example 1

Convert 796 to octal and then convert octal to binary

To convert from binary to octal, start from the right and group into threes, if the final group does not have three bits then add noughts to make up to the three.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Example 2 Convert 10101002 to octal

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Example 3

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) To convert from octal to binary (just a recap) the reverse procedure is used. Example - convert 12638 to binary

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) ACTIVITY: Convert the following binary numbers to octal: a) 101010100 b) 1110100000 c) 111010001 Convert the following octal numbers to binary: a) 426 b) 5625 c) 65217

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Fractions in decimal to octal are dealt with in a similar manner to decimal to binary except multiplication by 8 is used. Example Convert .9062510 to binary then octal.

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to convert to octal

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or we could have used the binary number split into threes 0.11101 starting after the decimal point going left to right

The reverse procedure is used to obtain a binary fraction from an octal fraction. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) ACTIVITY:

Convert the following binary numbers to octal. a) 111.111 b) 101.1 c) 110.0111 Convert the following octal numbers to binary a) .64 b) .77 c) .43

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.4 Hexadecimal System This system has a base or radix of 16 and is used again where large binary numbers are handled to cut down possible errors. Since we have only ten different digit symbols (0 to 9 inclusive) six other symbols have to be used these are the letters A to F inclusive. The table below shows the three numbering systems already considered and the hexadecimal system.

Decimal Octal Binary Hexadecimal 0 0 0000 0 1 1 0001 1 2 2 0010 2 3 3 0011 3 4 4 0100 4 5 5 0101 5 6 6 0110 6 7 7 0111 7 8 10 1000 8 9 11 1001 9 10 12 1010 A 11 13 1011 B 12 14 1100 C 13 15 1101 D 14 16 1110 E 15 17 1111 F 16 20 10000 10

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COMPARISON OF NUMBERING SYSTEMS

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Conversion from Decimal to Hexadecimal Convert 76210 to Hexadecimal

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Conversion from Hexadecimal to Binary Convert 2BC16 to Binary

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2BC16 is equal to 10101111002

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) ACTIVITY:

Convert the following Binary numbers to Hexadecimal a) 11100010 b) 1111111 c) 111001 Convert the following Hexadecimal codes to Decimal a) 2D b) 1AF c) 21A

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Convert the following Decimal numbers to Hexadecimal a) 1632 b) 494 c) 5174

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Convert 17816 to Decimal, Binary and Octal Convert EF16 to Decimal, Binary and Octal

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Fractions in Hexadecimal Convert 0.9062510 to Hexadecimal

to convert to Binary 0.E816

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Group into four digits

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Convert the following Hexadecimal numbers to Binary a) 0.A8 b) 0.F6

Just comparing the length of a binary number to Octal or Hexadecimal 111100001111101100011.00010011012 =7417543.04648 =1E1F63.13416

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) ACTIVITY: Convert the following decimal fractions to Hexadecimal a) 0.6250 b) 0.81250

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.5 Binary Coded Decimal BCD There are several forms of this system but we shall concentrate on the 8421 code. It is used in display read-out systems, decoders and counters.

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It is called an 8421 code as each digit is weighted from left to right 8421 in powers of 2.

You might be thinking that this is the same as the binary code, however, with numbers from 10 upwards each number is represented by the 4 bit code. Example 1110 to BCD Is 0001 0001 leaving a space between each group of four digits.

Converting from BCD to Decimal is again quite easy For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 10000101 Split into groups of four

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By way of a summary and to enable a comparison to be made between a number representation in the various systems and codes, consider the decimal number 347.

OCTAL HEXADECIMAL

533 15B

When a number such as decimal 347 is converted into any binary form the corresponding group of binary digits is known as a WORD. Each word is formed of a number of BITS (BINARY DIGITS) and this represents the word length.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) ACTIVITY: Convert the following decimal numbers to BCD a) 94 b) 529 c) 2947 Convert the following BCD numbers to decimal a) 011100001001 b) 001101100100

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) 5.2.6 Adding The rules are similar to those when adding decimal numbers, e.g. 5+5 = 0 and carry 1 to the next higher ' power'column, and 1+1 in binary results in 0 carry 1. Rules 0+0=0 0+1=1 1+0=1 1+1=0 with 1 to carry Example: add 1011 and 1110

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5.2.7 Subtraction

Again similar to rules for decimal subtraction except 0-1 = 1 borrow 1 Rules

0-0=0 1-0=1 1-1=0 0-1=1 borrow 1

Example: subtract 10101 from 11011

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Multiplication Rules 0x0=0 0x1=0 1x0=0 1x1=1 Example: multiply 1100 x 11

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Multiplication in a computer is achieved by repeated addition (e.g. in decimal 2 x 4 is computed as 2+2+2+2=8). Division

Example: divide 111100 by 110

Check this by converting binary 1010 to see if the answer is correct.

Computers cannot divide; they carry out division by repeated subtraction, which is in itself done by an addition process.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Positive and Negative Numbers The computer needs to distinguish between positive and negative numbers. For storage purposes only there is usually an additional bit added which identifies whether the number is positive or negative, e.g.: ‘0'for positive numbers ‘1’ for negative numbers Example - using an 8 bit binary word the sign bit is added on the front. Decimal - 4.5

binary 100100.100

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As mentioned, this is a convenient method for storing numbers but does not allow direct subtraction of one number from another. By inverting the number and adding 1 we get the negative of the number. This process is called TWO' s COMPLEMENT. The Twos Complement process involves inverting each bit in a word and adding 1.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS NUMBERING SYSTEMS (DCAM 5.2 L2) Example: Find the negative binary number of +5 decimal minus +7 decimal Note negative numbers have a 1 in the most significant bit position whilst the positive number has a 0. When numbers are represented as negative, subtraction is achieved by addition (adding a negative number being the same as subtracting a positive number) e.g.

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This means that both addition and subtraction can be done by the same circuits in a computer which considerably reduces the hardware involved.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3 DATA CONVERSION

5.3.1 Digital and Analogue Computers

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With new technological advances in computer development, an ever increasing number of digital computers are being used in the aviation industry. In addition to performing the traditional avionics functions, the digital computers are being used in new areas, such as thrust management and engine

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controls. With the use of these digital Systems, the flight crew’s workload is reduced. Other important considerations in the use of digital computers are the reduction of system weight and size; increase in data handling speed, and improved system reliability. This contributes to an increase in overall aeroplane

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efficiency.

5.3.1.1 Analogue Computers

Analogue computers are characterized by the processing of analogue signals. An analogue signal is an electrical signal whose amplitude varies continuously with time. Transducers, such as temperature and fuel sensors, provide voltage and current outputs proportional to the quantity being monitored. An analogue computer operates on a principle of creating a physical or electrical analogy using mathematical formulas. Variables, such as temperature or fuel flow, are represented by the magnitude of a physical phenomenon, such as voltage or current. The computing process is accomplished by designing hardware to perform prescribed functions. To change algorithm most often requires redesign of the circuit. Hence, analogue computers are not easily used in more than one operating environment. An analogue computer designed for the 727 aeroplane would not be easily converted for use in 777 aeroplanes

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3.1.2 Digital Computers

Digital is defined as incremental or stepped. A digital computer processes information and outputs an incremented or stepped output. This output can be used to control an on-off type device or to communicate with another digital device. The mathematical formulas used to process the information and

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develop an output are stored in a program in the computer’s memory. Should it become necessary to change these formulas, the computer program is simply modified. The ability to change a program, within a digital computer allows one computer to be used in many applications or on many airframe types

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3.2 Digital Bus

Digital devices usually need to communicate with each other. One device will send information to another which will process this data and possibly send it to another device. The path or circuit over which these devices communicate is called a Digital Bus. This Digital Bus may be used to connect several

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sources to any of several destinations. For example, airspeed information is transmitted from the Air Data Computer to several destinations over a Digital Bus called an ARINC 429 Bus.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3.3 Typical Digital System Inputs

One type of input used by digital systems is the discrete input. This is a high/low or on/off input used by the digital computer to indicate certain conditions taking place within the aeroplane. An example of a discrete input would be an input from the air/ground switch indicating whether the aircraft is on ground

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or in the air. The digital computer would use this indication within its calculations. A fire detection input would be Digital inputs send digitally encoded data using a rapid series of pulses encoded in one several forms. For example, the Air Data Computer sends a digital output representing airspeed to the

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computer on a Digital Bus. This digital input, called ARINC 429 information in this case, is a series of high and low levels or pulses which the computer uses for calculation using airspeed.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3.4 Typical Digital Systems Outputs

Digital computer also utilize discrete as outputs and may use these discrete outputs to turn on and off other devices. For example, the computer controlled stall warning light in the cockpit is illuminated by a high level output from the computer. Other examples may include illuminating the fire light with a high kevel output and turning on the fire bell circuit with a low level output.

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Digital outputs are generated from a computer in the form of a high and low levels and pulses. The series pulses can represent, for example, barometric altitude and is sent from the Air Data Computer to the cabin pressurization system on a Digital Bus. This digital information is a type of ARINC information.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3.5 Digital to Analogue / Analogue to Digital Conversion

While digital computers process information faster and more efficiently than analogue computers, they do have somewhat of a disadvantage in that they only understand 1’s and 0’s. The real world is a analogue in nature. Temperature, for example, does not change in discrete steps. It is a continuously

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varying quantity. In order for digital computers to use temperature information, the analogue quantity must be converted to a digital representation of temperature. Aeroplane control surfaces do not move in discrete steps but rather in continuous motion. A digital computer may be able to determine where

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a control surface must be positioned, but the signal to the surface must be in analogue form to drive the surface. The circuits used to interface digital computers to the analogue world are referred to as Digital to Analogue Converters (DAC) and Analogue to Digital Converters (ADC).

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DAC converters change the digital data words of a digital computer to an equivalent analogue signal as either a voltage or current source. There are many different types of DAC converters but each one has this same basic description.

ADC converters change the analogue signals received from sensors to digital data understood by the digital computer. Many different types of ADC converters exist. The type used depends on the type of analogue signal and what the digital computers need to know about the signal.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) 5.3.5.1 Digital to Analogue Converters (DACs)

Principle

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Each DAC circuit has a specific purpose based on its use within the system but the general purpose of all DACs is to provide an analogue signal output based on the digital value represented in the digital computer. This analogue signal is either a voltage or current output but the principles involved are essentially the same.

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The basic principle of a DAC converter is to divide the analogue output into a series of small steps. The number of steps depends on the number of bits used in the data to be converted. If the data consists of 8 bits then the output is divided into 256

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steps. The size of each step would be 0.0195 volts

(5v/256 steps). If an 8 bit, 5 volt converter is driven by a simple counter then the output of the converter would be a series of 256 steps of 0.0195 volts. As the counter progress from 0 to 255, the converter output increases from 0 volts to 4.98v then drops to zero when the counter rolls over. Also, note that the maximum output voltage is not 5 volts.

This is due a fact that each digital input bit is weighted according to its position within the binary input. The least significant bit (LSB) has a weight of 5v/256 = 0.0195 volts, the next most significant bit has a weight of 5v/128 = 0.039 volts, the next has a weight of 5v/64 = 0.078 volts, and so on, with the most significant bit (MSB) having a weight of 5v/2 = 2.5 volts. If you add all the individual bit weights, you get a 4.98 volt maximum output when the DAC input is 1111 1111.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Binary Weighted Ladder Starting from V1 and going through V3, this would give each input voltage exactly half the effect on the output as the voltage before it. In other words, input voltage V1 has a 1:1 effect on the output voltage (gain of 1), while input voltage V2 has half that much effect on the output (a gain of 1/2), and V3 half of that (a gain of 1/4). These ratios are the same ratios corresponding to position weights in the binary system. The op-amp is used as a summation device, to sum the weighted inputs of the digital information.

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If we drive the inputs of this circuit with digital gates so that each input is either 0 volts or full supply voltage, the output voltage will be an analogue representation of the binary value of these three bits.

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The disadvantage of this circuit is that a high precision is required of the resistors, especially the higher values (± 0.5%). This makes it difficult to mass produce.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) R-2R Ladder The R-2R ladder network is another type of DAC. Each bit of the binary input controls a solid state switch which connects either a reference voltage or a ground to the resistors. The ladder is constructed of resistors of only two values, R or 2R rather than binary weighted. In this type of network the actual resistor values are not as critical as in the binary weighted ladder. Also since the resistance values can be small; it is much easier to implement this in a solid state device.

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The inverting input of the op-amp is at virtual earth. Current flowing in the elements of the ladder network is therefore unaffected by switch positions. The selected resistor values ensure that the relationship:

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The current ITOTAL, is the sum of the currents switched to the inverting input of the op-amp from the R-2R ladder by the digitally controlled switches Do - D3. ITOTAL is given by the relationship:

The output voltage VOUT is the voltage across the op-amp feedback resistor which is by Ohms law:

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Some uses of DACs

Waveform Generators

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The analogue output required from a digital computer which is not always a steady output level. Sometimes a particular wave form is required, such as a sawtooth or ramp. A ramp or sawtooth wave can be easily implemented by using simple R-2R ladder and a counter.

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A binary counter used to drive a R-2R ladder causes the ladder to output a sequence of steps of different voltage levels. As the counter reaches its

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maximum value, it returns to zero or is said to "roll over' . When the input word rolls over to zero the output also returns to zero. While this output is not a pure ramp due to the fact that the binary words generate steps, most analogue systems are slow enough in their reaction times that they react the same as if the signal was continuous. High quality R-2R ladders have relatively short response times (2 microseconds typical). For an 8 bit device this makes the rise time from 0 to 10 volts in the order of 0.5 microseconds or a frequency of 2 MHz.

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Programmable Gain Amplifiers

DACs can also be used to provide gain control of an analogue signal. This arrangement may be required, for example, to control the speed of an AC motor by varying the input voltage level to the motor. This can be accomplished quite simply by applying an AC voltage as VR to a ladder network.

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A simple-motor controller is shown. A 5 volt AC reference signal is applied as VR to an 8-bit DAC. The data word is generated by the computer

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to select the desired motor speed by setting the output level. Remember for an 8-bit device this output can be divided into 256 steps, so very fine control can be established with this simple method. One minor problem with this simple motor control is the fact that the computer does not know if the motor speed is correct. To check this, there must be a feedback from the motor. This feedback would be analogue so we need an analogue to digital converter.

Almost all "real world" applications are analogue in nature. Therefore, analogue to digital converters (ADCs) are quite common in computer systems, and especially in those systems dedicated to monitoring or controlling "real world" events. An ADC converts a continuous voltage signal, or analogue signal into a multi-bit digital word.

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5.3.5.2 Analogue to Digital Converters (ADCs) Principle

There are seven techniques normally used for the conversion process. They are: •

Flash

•

Pipeline

•

ramp generation,

•

successive approximation

• • •

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charge balancing sigma delta

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Successive approximation and integration are the most common in use. Both the ramp generation and successive approximation type converters require DACs as part of the circuit but these are usually built into the ADC chip.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Flash ADC

Illustrated in figure 3.23 is a 3-bit flash ADC with resolution 1 volt. The resistor network and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest

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type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.). Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output.

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The flash converter requires 2n - 1 comparators, where n is the number of bits. So a 4 bit flash ADC will require 15 comparators. The flash converter is sometimes called a parallel converter because the conversion takes place in a single cycle. For this reason also, it is the fastest type of ADC, but it does have the most complicated architecture.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Pipeline ADC

The ADC pipeline architecture effectively overcomes the limitations of the flash architecture. A pipelined converter divides the conversion task into several consecutive stages. Each of these stages consists of a sample and hold circuit, an m-bit ADC (e.g., a flash converter), and an m-bit DAC. First the sample

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and hold circuit of the first stage acquires the signal. The m-bit flash converter then converts the sampled signal to digital data. The conversion result forms the most significant bits of the digital output. This same digital output is fed into an m-bit digital-to-analog converter, and its output is subtracted from the

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original sampled signal. The residual analog signal is then amplified and sent on to the next stage in the pipeline to be sampled and converted as it was in the first stage. This process is repeated through as many stages as are necessary to achieve the desired resolution. Pipelined converters achieve higher

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resolutions than flash converters containing a similar number of comparators. This comes at the price of increasing the total conversion time from one cycle to p cycles.

Ramp Generation ADC

A ramp generation ADC, sometimes called a counter ADC, compares the unknown input voltage to a DAC connected as a ramp generator. As long as the unknown input is greater than the ramp signal the counter continues. As soon as the ramp exceeds the unknown voltage input the counter stops and the ramp is held at the fixed level. The count is then read by the computer. The clear line clears the binary counter, setting its output to zero. The counter counts up with each clock pulse as long as the comparator output is high. The comparator output is high as long as the output of the DAC (Vo) is less than the analogue input (VI). When Vo exceeds VI, the comparator output goes low. This in turn stops the counter and Vo remains greater than VI. The digital output word now represents the input voltage. The fact that Vo is slightly greater than VI is of little consequence since the step size is 1/256 times the full range. The circuit will hold this digital value until the binary counter is cleared or until VI is greater than Vo again. The ramp generation ADC converter is really working as a peak detector. This can pose some problems if the computer needs to sense variations of VI over short time periods. Therefore, the ramp generation ADC works best in applications where the analogue signal level varies at a slow rate, such as a temperature sensor.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) An improvement of the ramp generation ADC converter is to use an up-down counter (sometimes called a Tracking ADC). The up-down counter eliminates the need for the clear line and the AND gate. The computer output is used to control the counter either up or down as required to track the input signal. This is sometimes called a tracking or servo counting ADC.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Successive Approximation Register (SAR) ADC

The successive approximation ADC (also known as a Bit-Weighted converter) is similar to the ramp generation ADC except that a programmer is used to control the DAC ladder network. A successive approximation converter provides a fast conversion (second only to the Flash converter) of a momentary

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value of the input signal. It works by first comparing the input with a voltage which is half the input range. If the input is over this level it compares it with three-quarters of the range, and so on. Twelve such steps give 12-bit resolution. While these comparisons are taking place the signal is frozen in a sample

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and hold circuit. After A-D conversion the resulting bytes are placed into either a pipeline or buffer store. A pipeline store enables the ADC to do another conversion while the previous data is transferred to the computer. Buffered ADCs place the data into a queue held in buffer memory. The computer can

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read the converted value immediately, or can allow values to accumulate in the buffer and read them when it is convenient. This frees the computer from having to deal with the samples in real time, allowing them to be processed in convenient batches without losing any data.

The successive approximation method is much faster than the counting type methods. For an 8bit word, the successive approximation takes 8 clock cycles while the counting type method could take up to 256 (28) clock cycles.

The Successive-Approximations Register (SAR) architecture can be thought of as being at the other end of the spectrum from the flash architecture. While a flash converter uses many comparators to convert in a single cycle, a SAR converter conceptually uses a single comparator over many cycles to make its conversion. An unknown input voltage, VI, is applied to the comparator. The output of the comparator controls the operation of the programmer. The digital word representing VI is determined as follows: T1 - bit 7 is set, VD greater than VI

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) T5 - bit 3 is set, Vo greater than VI T6 - bit 3 is reset, bit 2 is set, Vo greater than VI T7 - bit 2 is reset, bit 1 is set, Vo greater than VI T8 - bit 1 is reset, bit 0 is set, Vo less than VI

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The final digital word is 00110001. After this word is stored by the processor, the programmer is instructed to start the sequence over again.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Integration Type ADC

There are various forms of integration type ADC: single slope and dual-slope. The dual-slope method is by far the most common. Basically, dual-slope converters allow a capacitor to charge from the unknown analogue input voltage for a fixed period of time. The charge on the capacitor at the end of this

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time depends only on the input voltage level. At the end of the fixed charge time, a known reference voltage of opposite polarity is gated to the capacitor such that it will discharge back to zero. The time required for discharge is counted. The final count is the digital equivalent of the analogue input level.

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The advantages of the integration methods are accuracy and noise immunity. However, the conversion process usually takes between 10 and 50

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milliseconds. This is quite a long time in the computer world. It is ideal however for use in a digital multimeter which requires a fine resolution but can sacrifice high speeds.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Initial conditions on the circuit are that both Clear and Timer lines are high. This condition causes an open on the input to the integrator, clears the integrator by discharging the capacitor through S3, and clears the counter (sets all output bits to 0). The processor starts the conversion by setting both Timer and Clear lines low. This results in the input voltage (VI) being applied to the integrator. S3 is now open so VI is integrated and the integrator output goes negative as the capacitor charges. The negative integrator output causes the comparator output to be high which allows the counter to count the clock pulses.

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When the signal to be measured fluctuates slowly, as in the case of a temperature monitored by a thermocouple, an integrating converter is best. By averaging the signal the converter helps reduce unwanted signal contamination (noise).

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This converter reduces noise but is slower than the successive approximation type. It lets the input signal charge a capacitor for a fixed period and then measures the time for the capacitor to fully discharge at a fixed rate. This time is a measure of the integrated input voltage, which reduces the effects of noise.

Since the counter was set to zero at clear, the counter starts counting from zero to 256 (all 1' s). When the counter counts one more pulse it goes to zero. This transition from all 1' s to all 0' s is sensed by the processor which in turn causes the timer pulse to be set high. S2 then switches the integrator input from V, to VR. VR is the opposite polarity of V, so the capacitor starts to discharge. As the capacitor discharges the integrator output returns to zero. When this occurs the comparator output goes low which stops the counter. The time required to discharge the capacitor is proportional to the input voltage since VR is a constant and the charge time is a constant (256 counts). The processor starts the sequence over again by setting the clear pulse once every 512 clock pulses.

The major disadvantage of the single-slope integrating ADC is that it becomes inaccurate as the circuit drifts (an inevitable result of age and temperature). This is irradiated in the dual-slope version.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) Charge Balancing ADC

In a Charge Balancing Converter the input signal again charges a capacitor for a fixed period, but in this case the capacitor is simultaneously discharged in units of charge packets. (Meaning that if the capacitor is charged to more than the packet size it will release a packet, if not a packet cannot be released.)

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This creates a pulse train. By counting the pulses coming out of the capacitor, the system determines the input voltage. (A charge balancing converter is also known as a voltage to frequency converter.)

Sigma-delta ADC

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This converter digitizes the signal with very low resolution (1-bit) and a very high sampling rate (MHz). By over sampling, and using digital filters, the resolution can be increased to as many as 20 or more bits. Sigma-delta converters are especially useful for high resolution conversion of low-frequency signals as well as low-distortion conversion of signals containing audio frequencies. They have good linearity and high accuracy.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA CONVERSION (DCAM 5.3 L2) NOTES

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4 DATA BUSES

From the computers within the aircraft, systems information has to be transmitted to the components, this may be in the form of electrical or fibre optic signals and are known as data buses. Aeronautical Radio Incorporated (ARINC) is a corporation made up of scheduled airlines, transport companies, aircraft manufactures and foreign flag airlines.

One primary activity of ARINC is to produce specifications and reports for the purpose of: 1. Indicating to manufacturers the group opinion concerning requisites of new equipment.

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2. To channel new equipment designs in a direction which will result in maximum standardisation.

There are many ARINC specifications in existence for example: o

ARINC 573 - Specification for digital flight data recording systems

o

ARINC 561 - Specification for the Inertial Navigation System

o

ARINC 429 - Specification for transfer of digital data between avionic Components

o

ARINC 629 - An improvement on the ARINC 429 system

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4.1 What is Data Bus?

A bus is a collection of wires through which data is transmitted from one part of a computer to another. You can think of a bus as a highway on which data

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travels within a computer. When used in reference to personal computer components, the terms bus usually refers to internal bus. This is a bus that connects all the internal components to the CPU and main memory.

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However when used in reference to aircraft, it is the data highway which links one computer to another within the aircraft for example, the Flight

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Management Computer and the Air Data Computer.

All buses consists of 2 parts •

An address bus

•

A data bus

The data bus transfers actual data whereas the address bus transfers information about where the data should go. On aircraft bus, the two parts are incorporated within a single data ‘word’. A bus can be either serial or parallel. A serial bus requires less wiring, but is slower. A parallel bus required one wire for each bit within the data word, but is much faster.

A bus can enable communication between a single computer to a single LRU only, known as single source-single sink; or a single computer to multiple LRUs, known as single source-multiple sinks, or multiple computers to multiple LRUs known as multiple sources-multiple sinks. The latest databus systems are multiple sources-multiple sink (ARINC 629 and MIL-STD-1553B).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Data Bus Systems On aircraft in general, there are unidirectional and bidirectional data bus architectures. The accompanying communications protocols will then support one or the other system. The simpler and to this day the most prevalent architecture on-board commercial airplanes is the unidirectional (simplex) data bus represented by ARINC 429. The system consists of a single transmitter and a number of receivers, each monitoring the line and listening for messages relevant for them. Communication back to the transmitter, if needed, is performed by a separate transmitter, receiver(s), and wires. Due to its simplicity, the system is robust, fault-tolerant, and extremely simple to design and implement. The disadvantage is a lot of labor-intensive wiring, which is also expensive and heavy, requires higher power consumption and leads to high operational costs of the aircraft.

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More advanced data bus architectures such as ARINC 629 are bidirectional (duplex). ARINC 629 is applied on Boeing 777 and some Boeing 737 models. Here, any member or user of the system can transmit, receive, or both on a common, shared data bus. As the implementation of the physical layer is comparatively expensive, market penetration did not happen. More than 30 years ago, especially military avionic systems, which previously used discrete wiring, were upgraded to interface with the MIL-STD-1553B bidirectional data bus. This led to a significant weight saving, and the labor to run wiring harnesses could be reduced by thousands of hours. However, the bus control became more complex, and the engineering effort to integrate the system was no small task.

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Bus Traffic Control

Every non-100% time-triggered, Time Division Multiple Access (TDMA) based databus must be able to arbitrate data bus transmissions to ensure that only one transmitter is operational at a time and that the receivers are waiting for messages. And, unlike the unidirectional bus, a lot of thought has to go into the system design and integration. There are two approaches commonly used for traffic control of bidirectional buses: central control and distributed control. The advantage of the central control or command/respond approach is that only one bus component has control of the bus traffic (master). All users are directed by the bus controller (master). If the data bus architecture has to change, only the bus controller (master) has to be modified to support the new configuration. But the most significant weakness of such architecture in an aircraft environment, where the bus controller or network failure could have catastrophic repercussions, is that the bus controller (master) represents a single point failure. When it fails, the entire system fails. Therefore, many systems based on MIL-STD-1553B are equipped with redundant bus controllers (distributed control), only one having control of the network at a time. In a fully distributed control system, all members of the network are in charge of their own access. Single fault tolerance can be achieved when appropriate fault handling mechanisms are implemented as well as true partitioning is in place (both within and between Line Replaceable Units, LRUs) to prevent fault propagation. So if any member fails or happens to operate erratically, the rest of the system will not be affected and will continue operating correctly. The weakness of the distributed control is exactly the opposite of the central control strength. It generates higher complexity in bus access sharing, and a change to the system configuration may require a change to every user of the system.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4.2 About ARINC

Aeronautical Radio Incorporated (ARINC) is a major company that develops and operates systems and services to ensure the efficiency, operation, and performance of the aviation and travel industries. It was set-up in 1929 by four major airlines to provide a single licensee and coordinator of radio

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communications outside the government. Only airlines and aviation-related companies can be shareholders, although all airlines and aircraft can use ARINC' s services.

5.4.3 Data Encoding

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Parity Checking

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In communications, parity checking refers to the use of parity bits to check that data has been transmitted accurately. The parity bit is added to every data unit (typically seven or eight bits) that are transmitted. The parity bit for each unit is set so that all bytes have either an odd number or an even number of set bits. Assume, for example, that two devices are communicating with even parity (the most common form of parity checking). As the transmitting device sends data, it counts the number of set bits in each group of seven bits. If the number of set bits is even, it sets the parity bit to 0; if the number of set bits is odd, it sets the parity bit to 1. In this way, every byte has an even number of set bits. On the receiving side, the device checks each byte to make sure that it has an even number of set bits. If it finds an odd number of set bits, the receiver knows there was an error during transmission. The sender and receiver must both agree to use parity checking and to agree on whether parity is to be odd or even. If the two sides are not configured with the same parity sense, communication will be impossible. Parity checking is the most basic form of error detection in communications. Although it detects many errors, it is not foolproof, because it cannot detect situations in which an even number of bits in the same data unit are changed due to electrical noise.

Parity checking is used not only in communications but also to test memory storage devices. Many PCs, for example, perform a parity check on memory every time a byte of data is read. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Binary Encoding Formats

There are several ways in which binary 1 and 0 can be represented by voltage levels on a pair of wires. The few which are used on aircraft data bus types will be shown here:

Bipolar Return to Zero (BPRZ)

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In Bipolar Return to Zero encoding, a Hi level (logic 1) is given by a positive voltage on one wire followed by a return to null (zero). A Lo level (logic 0) is

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given by a negative voltage on the other wire followed by a return to null.

BPRZ requires a clock to maintain the bit cell period.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Harvard Bi-Phase Harvard Bi-Phase uses a two phase voltage level to represent a high (logic 1) and a single phase voltage to represent a low (logic 0). If two lows occur sequentially, the voltage level will toggle from high to low or low to high, but remain in that state for the time period of the bit cell. Harvard Bi-Phase requires a clock to maintain the bit cell period.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Manchester II / Non Return to Zero (NRZ)

Manchester II NRZ uses the change from a high to a low voltage to represent a high (logic 1) and a change from low to high to represent a low (logic 0). Manchester II NRZ requires a clock to maintain the bit cell period.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4.4 ARINC 429

ARINC 429 is the most commonly used data bus for commercial and transport aircraft. ARINC 429 employs unidirectional transmission of 32 bits word over two wires (twisted pairs) using bipolar RZ format. The protocol has five fields in each word which enables it to transmit the data and the address

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information within the same bus transmission. Messages are repeated at specified intervals with typical applications sending groups or frames of messages.

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The commonly used word formats such as BNR, BCD, Discrete data, and other formats. ARINC 429 is a specification, which defines how avionics

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equipment and systems should communicate with each other. They are interconnected by wires in twisted pairs. The specification defines the electrical and data characteristics and protocols, which are used.

ARINC 429 employs a unidirectional (simplex) data bus standard, sometimes known as Mark 33 Digital Information Transfer System (DITS). Messages are transmitted at a bit rate of either 12.5 kilobits per second or 100 kilobits per second to other system elements, which are monitoring the bus messages. Transmission and reception is on separate ports so that many wires may be needed on aircraft, which use a large number of avionics systems.

ARINC 429 Usage

ARINC 429 has been installed on most commercial transport aircraft including; Airbus A310/A320 and A330/A340; Bell Helicopters; Boeing 727, 737, 747, 757, and 767; and McDonnell Douglas MD-11. Boeing has installed a newer system specified as ARINC 629 on the 777, and some aircraft are using alternate systems in an attempt to reduce the weight of wire needed and to exchange data at a higher rate than is possible with ARINC 429. The unidirectional ARINC 429 system provides high reliability at the cost of wire weight and limited data rates. Military aircraft generally use a high-speed, bidirectional protocol specified in Military Specifications MIL-STD-1553.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

The ARINC 429 System First of all we are going to consider the ARINC 429 Specification for data transfer. As an example let us consider the Air Data Computer which will have on its output side an ARINC 429 transmitter (TX). One of its outputs (among many) on the data bus will be altitude information which will be picked up by the ARINC 429 Receiver (RX) in the Digital Altimeter.

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Figure 4.4 SIMPLIFIED ARINC 429 SYSTEM

Figure 4.5 DITS DATA BUS

The data bus is a pair of twisted wires with shielding. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) The ARINC 429 Digital Information Transfer System (DITS) is a self-clocking, self-synchronising system called "bipolar return to zero". The data is transmitted in binary bit form. The ' 1' s and ‘0' s are represented by high voltage levels (+10v) and low voltage levels (-10v) respectively for one half of the clock cycle i.e., each pulse returns to zero in the middle of a clock pulse.

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Figure 4.6 shows the principle of this transmission. The data is transmitted in groups of 32 bits in serial fashion i.e., one bit at a time. Some data buses are designated as LOW SPEED (12.5k-14k bits/sec) or HIGH SPEED (100k bits/sec). Signals only flow in one direction on the bus.

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Figure 4.6 DITS TRANSMISSION CHARACTERISTIC

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Word Format This 32 bits word has five basic parts:

1. LABEL 2. SOURCE/DESTINATION IDENTIFIER (SDI) 3. DATA FIELD 4. SIGN STATUS MATRIX (SSM) 5. PARITY BIT (P)

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Figure 4.7 ARINC 429 DIGITAL DATA WORD

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) The LABEL. The first eight bits of the word (octal coded), identifies the information contained in the data e.g., airspeed, exhaust gas temperature etc. There are a large number of words being transmitted on the bus and the receiver decodes the labels and selects only those words it requires.

The SOURCE/DESTINATION IDENTIFIER.

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This is used to identify the source or destination of a word and are bits 9 and 10 in the word i.e., which of a number of installations the word is coming from or needs to be directed to.

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The DATA FIELD

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Contains the specific data related to the label e.g., how many knots for airspeed, value of exhaust gas temperature etc. For a binary word BNR this is contained in bits 11-28; and for a binary coded decimal (BCD) word it is in bits 11-29. Any bits not used are filled with logic ‘0' s these are known as pad bits and have no data significance.

The SIGN STATUS MATRIX,

Bits 29, 30, 31 for a binary word BNR and 30, 31 for a BCD word identifies the characteristics of the word e.g., north or south, positive or negative, east or west and its status e.g., no computed data, failure warning or functional test or normal operation.

The PARITY BIT.

ARINC 429 uses odd parity i.e. the total number of logic ' 1’s in the word must be an odd number, if it is not an odd number, the parity bit is set to 1. This is used in the system to check for errors, if on receiving a signal it does not contain an odd number of ' 1' s then there is something wrong with the transmission and a fault signal would be generated.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) To enable the receiver to identify the beginning of a transmission, the data word is synchronised by a minimum 4 bits time gap. Figure 4.8 and Figure 4.9 shows two examples of an ARINC 429 transmission, one using binary BNR and the other BCD.

Binary Word Example

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BCD Word Example

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Figure 4.8

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Figure 4.9

The transmitters of the system, which are embedded in the system equipment, are capable of interfacing with up to 20 receivers.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4.5 MIL-STD- 1553B This is a United States Military Standard and has been adopted as a NATO standard (STANAG 3838). It is a multiple source data transmission system in that transmission can from more than one source. It is a half duplex system in that data transfer can take place in either direction on a single line but not in both directions on that line simultaneously. The basic configuration is shown in the following diagrams. The data bus may be a twisted pair or fibre optic cable with a maximum length of 100m.

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Control of the bus is effected by a Bus Controller (BC) which is connected to a number of Remote Terminals {RT), up to a maximum of 31, via the data bus (central control). These remote terminals are connected to the aircraft subsystems. Data is transferred at a rate of 1MHz using the Manchester bi-

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phase digital format (see ARINC 629). The data word size is 20 bits, with an actual word size of 16 bits, with SYNCH waveform and parity taking up four bits. Between the Bus Controller (BC) and Remote Terminals (RT) there are various transfer formats.

However, we shall look at transfer of data from RT to BC. 1. BC sends a transmit signal to RT.

2. RT replies after a short time with a status word, this is followed immediately with one or more data words up to a maximum of 32. 3. Transmission of one word takes 70µs.

Transfer from one RT to another RT:

1. BC sends command to one RT.

2. Transit command sent to other RT.

3. The sending RT sends a status word followed by the data word up to a maximum of 32 words. 4. The receiving RT sends a status word to the BC.

ARINC 629 has been developed from the MIL-STD-1553B the BC being replaced by the Data Autonomous Transmission and Communication (DATAC) where each LRU has a serial interface module which controls the timing of the LRU data onto the bus when the LRU' s are not transmitting. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 4.10 1553B DATA BUS LAYOUT

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Figure 4.11 1553B WORD FORMATS

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Figure 4.12 1553B TYPICAL DATA TRANSACTION

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4.6 ARINC 629 In the ARINC 429 system data only flows in one direction so if we wish to send data back to the receiving element another data bus is required. Also with the advent of more digital systems on aircraft another data transmission system was required which was faster and bidirectional. The ARINC 629 fulfils these requirements and is used, as well as ARINC 429, on the Boeing 777.

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The ARINC 629 data bus is an unshielded, twisted pair of wires bonded and terminated at both ends. Data is sent and received at a rate of 2 megabits per second. The system has three parts:

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a) Data bus cable

b) Current mode coupler c) Stub cable

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

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Figure 4.13 AR1NC 629 - TYPICAL ARRANGEMENTS

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Data Bus Cable

Up to 120 terminals can be connected to the bus which can be up to 100 metres long. The bus operates a 2MHz which allows 100,000 20 bit words to be transmitted each second, The cable is 20 AWG (American Wire Gauge) twisted pair of wires bonded together continuously along their length, at the end of each bus cable are 130 ohm impedance matched resistors.

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Many LRU' s receive data at the same time. Communication is bidirectional and on B777, the maximum number of LRU' s on one bus is 46. All the data on the bus is available to all LRU' s on the bus. Each LRU has a serial interface module and a terminal controller which controls the timing of its LRU data onto

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the bus when other LRU' s are not transmitting (distributed control).

Current Mode Coupler

This connects the data bus cable to the stub cable. These are found in panels in the electronics compartment arranged in rows so that the bus cable can run through them.

Figure 4.14 and Figure 4.15 shows a coupler, which uses the inductive principle ie, transformer coupling, as can be seen the coupler has two parts, the lower part in which the data bus cable is carefully positioned through the wire guides to give controlled routing and protection. The upper part has the electronics for putting data on and taking data off the bus and sending via the receptacle to the LRU stub cable. The housing is waterproof. The diagram shows a typical current mode coupler panel.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 4.14 CURRENT MODE COUPLER

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Figure 4.15 CURRENT MODE COUPLER PANEL

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Stub Cables

The stub cables are for bidirectional data movement between LRU and current mode coupler. The stub cables also supply power from the LRU' s to the current mode couplers. The stub cable has four wires, two to transmit and two to receive. These cables are in the normal aircraft wiring bundles.

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Figure 4.16 shows the arrangement and layout of a stub cable. These cables can be up to 40 metres long. All the data bus cables on the 777 are inside the current mode coupler panels except the left and right bus cables. The diagrams show the basic layout.

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These long runs of cables will have production break splices done at the factory, and you can see the coupler connector to the coupler panel.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

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Figure 4.16 ARINC 629 STUB CABLE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Data Structure The data is transmitted in groups called messages. Messages are comprised of word strings and up to 31 word strings can be in a message. Word strings begin with a label followed by up to 256 data words. Each label and data word is 20 bits. Figure 4.17 shows the complete structure of the ARINC 629 message.

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GENERAL - ARINC 629 DATA BUS CABLE

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BUS CABLE

Figure 4.17 (A)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

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COMPLETE ARINC 629 MESSAGE STRUCTURE

Figure 4.17 (B)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) A particular parameter is defined by its position in the labelled word string and it is the responsibility of the system designer to define labels and parameters. The table below compares the ARINC 429 to the ARINC 629 data word. ARINC 429 requires a different word for each type of information it sends. ARINC 629 uses a word string that has a label followed by information that can have up to 256 types of data i.e., more information on the bus hence faster transmission. ARINC 629 deals with standards for this bus and it is also referred to as the Digital Autonomous Terminal Access Communication (DATAC) bus.

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To keep the data bus to a twisted pair of cables it was necessary for the databus to be self-clocking. Manchester II bi-phase is the form of self-clocking used in ARINC 629. See Figure 4.18.

f o g y n r i r a t e e e i n r i p g o n r P SE A M ARINC 429 LABEL PARAMETER 230 231 233 234 235 323 330 331 332 333 362 364 363

DATAC LABEL WORD POSITION PARAMETER AIR DATA TRUE AIRSPEED 230 1 TRUE AIRSPEED TOTAL AIR TEMP 2 TOTAL AIR TEMP STATIC AIR TEMP 3 STATIC AIR TEMP BARO CORRECTION (mB) #1 4 BARO CORRECTION (mB) #1 BARO CORRECTION (in of Hg) #1 5 BARO CORRECTION (in of Hg) #1 AIR DATA FLIGHT PATH ACCEL 330 1 FLIGHT PATH ACCEL BODY WAY RATE 2 BODY WAY RATE BODY LONGITUDINAL ACCEL 3 BODY LONGITUDINAL ACCEL BODY LATERAL ACCEL 4 BODY LATERAL ACCEL BODY NORMAL ACCEL 5 BODY NORMAL ACCEL ALONG TRACK HRZ ACCEL 6 ALONG TRACK HRZ ACCEL VERTICAL ACCEL 7 VERTICAL ACCEL CROSS TRACK HRZ ACCEL 8 CROSS TRACK HRZ ACCEL DATA IDENTIFICATION/ RECOGNITION COMPARISON TABLE – EXAMPLE

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Figure 4.18 MANCHESTER II BIPHASE ENCODING PRINCIPLE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) The data buses between LRU' s and LRM' s (line replacement modules) may be of different types and data maybe transferred at different speeds. For example: ARINC 629 ARINC 429 ARINC 453 ARINC 717

sends and receives data at 2 megabits per second. one way buses data sends and receives data at low speed (12 kilobits per second and 14 kilobits per second) and high speed (100 kilobits per second) is a one way bus that sends data at 1 megabit per second. is a one way bus that sends and receives data at 128 words per second. is a one way bus that sends and receives data at 128 words per second. is a one way bus that sends and receives data at 9600 bits per second is a one way bus that sends and receives data on a casual wire at 20 kilobits per second. two way bus that sends and receives signals at 10 megabits per second. two way bus that sends and receives signals at 10 megabits per second. two way bus that sends and receives signals at 10 megabits per second. fibre optic data bus sends and receives signals at 100 megabits per second.

f o g y n r i r a t e e e i n r i p g o n r P SE A M ARINC 618 RS-422 RS-232

10 base T RS-485

10 base 2

ARINC 636

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As you can see there is a considerable amount of data being sent and received at varying speeds and using a variety of data bus systems. You do not need to remember all these data bus systems but you should appreciate the layout of a bus system on a modem aircraft.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Protocol

This is the formal code of behaviour of a computer/ data bus system. It governs the sequence which computers/terminals write data onto the data bus. In basic terms it means that when one computer/terminal is writing data onto the bus the rest are quiet and, if necessary, reading that data off the bus. It can

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be either Basic Protocol (BP) or Combined Protocol. The BP can be operated in periodic mode or aperiodic mode. We shall consider the BP modes.

Timing

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All operations on a data system are governed by a timing signal. On the ARINC 629 system the timing of messages is such as to ensure that the required repetition rate is maintained and there are no collisions between messages. Three timers are used to ensure periodicity, collision free access and equal access opportunity, these are: •

Transmit Interval (TI). This is common to all terminals and can be set in the range of 0.5 to 64 milliseconds. TI controls the minimum interval between periodic transmissions.

•

Terminal Gap (TG). Each terminal has a unique time value assigned to it. This is in the range from 4 to 128 microseconds. The TG is the parameter which ensures clash free access.

•

Synch Gap (SG). This is common to all terminals and is set to a value larger than the largest TG. SG is the basic parameter which ensures that all the terminals have equal access opportunity.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) ‘Periodic’ Mode

Figure 4.19 shows the operation in periodic mode. This is used when there is a sufficient bus data rate to allow all messages to be transmitted at the same rate (the highest rate). The TI is set to the inverse of the TG to allow collision free access. There is spare time on the TI and the terminals generally transmit in a set order (power-up order). The SG does not feature in this mode.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

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Figure 4.19 BUS ACTIVITY - PERIODIC MODE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) ‘Aperiodic’ Mode

If there is insufficient bus capacity for all the messages to be transmitted at the maximum rate then the aperiodic mode is used. Each terminal is given an equal opportunity to transmit one message on the bus during a defined period. This is achieved by assigning to each terminal a unique terminal gap (TG) value and by determining a Synchronisation Gap (SG) that is longer than the longest TG.

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Figure 4.20 shows the operation of a simple three terminal system. The terminal with the shortest TG starts to transmit (terminal 1). All other terminals reset their timers. When the first terminal has finished transmitting it will have to wait until the bus has been quiet for the duration of the SG before it is given the

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opportunity to transmit again. So effectively now the terminal with the shortest TG that has not transmitted it' s information is terminal 3 (looking at figure 4.20, terminal 3' s TG is shorter than terminal 2' s TG so terminal 3 will transmit.) This process will repeat itself until all the terminals have transmitted in order of their shortest TG.

When all terminals have transmitted the bus goes quiet while SG timers operate, and the cycle will start again with the shortest TG terminal transmitting first. This cycle time is called a Minor Frame (MIF) and the shortest MIF possible (equal to the synchronization gap, and the sum of the messages and their terminal gaps) is the Minimum Frame Time (MFT).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2)

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 4.20 BUS ACTIVITY – TIMING

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Figure 4.21 DATA BUSES

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) 5.4.7 Ethernet History of Ethernet Engineers Bob Metcalfe and D.R. Boggs developed Ethernet beginning in 1972. Industry standards based on their work were established in 1980 under the IEEE 802.3 set of specifications. Generally speaking, Ethernet specifications define low-level data transmission protocols and the technical details manufacturers need to know to built Ethernet products like cards and cables.

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Ethernet technology has evolved and matured over a long time period. The average consumer can generally rely on the off-the-shelf Ethernet products to work as designed and to work with each other. Ethernet Technologies

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Traditional Ethernet supports data transfer at the rate of 10 Megabits per second (Mbps). Over time, as the performance needs of LAN have increased, the industry created additional Ethernet specifications for Fast Ethernet and Gigabit Ethernet. Fast Ethernet extends traditional Ethernet performance up to 100 Mbps and Gigabit Ethernet up to 1000 Mbps speeds. Ethernet cables likewise are manufactured to any of several standard specifications. The most popular Ethernet cable in current use, Category 5 or CAT5, supports both traditional and Fast Ethernet. The Category 5e (CAT5e) cable supports Gigabit Ethernet. Quad cables are used in modern commercial aircraft to transport data of the high speed Ethernet. Ethernet data communication is used on the Airbus A380 in the Network Server System (NSS) and in the Avionics Data Communication Network (ADCN). In the Ethernet Network the quad cable guarantee failure free data transmission with up to 100 Mbps over a distance of up to 100 meters between a very high number of users. Quad cables are usually delivered as complete harnesses. One harness is composed of a shielded quad cable with four internal copper wires and a contact (pin or socket) on each end.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Types of Ethernet Often referred to as Thicknet, 10Base5 was the first incarnation of Ethernet technology. The industry used Thicknet in the 1980s until 10Base2 Thinnet appeared. Thicknet and Thinnet used coaxial cable but Thinnet is thinner and more flexible cabling. The most common form of traditional Ethernet, however, is 10Base-T. 10Base-T offers better electrical properties than Thicknet or Thinnet, because 10Base-T cables utilize unshielded twisted pair (UTP) wiring rather than coaxial. (Note: The number shows the data transport rate in Mbps and the letter defines the cable type used as the physical transport medium) Fast Ethernet

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In the mid-1990s, Fast Ethernet technology matured and met its design goals of (i) increasing the performance of traditional Ethernet while (ii) avoiding the need to completely re-cable existing Ethernet networks. Fast Ethernet comes in two major varieties: • •

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100Base-T (using unshielded twisted pair cable) 100Base-FX (using fiber optic cable)

By far the most popular of these is 100Base-T, a standard that includes 100Base-TX (full duplex), 100Base-T2 and 100Base-T4.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Ethernet Topology, Protocol and Devices Traditional Ethernet employs a bus topology, meaning that all devices or hosts on the network use the same shared communication line. Each device possesses an Ethernet address. Sending devices use Ethernet address to specify the intended recipient of massages.

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Data sent over the Ethernet exists in the form of frames. An Ethernet frame contains a header, a data section, and a footer having a combined length of no more than 1518 bytes. The Ethernet header contains the addresses of both the intended recipient and the sender. Data sent over the Ethernet is automatically broadcast to all devices on the network. By comparing their Ethernet address against the address in the frame header, each Ethernet device tests each frame to determine if it was intended for them and reads or discard the frame as appropriate.

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Devices wanting to transmit on the Ethernet first perform a preliminary check to determine whether the medium is available or whether a transmission is currently in progress. If the Ethernet is available, the sending device transmits onto the wire. It’s possible, however, that two devices will perform this test at approximately the same time and both transmit simultaneously. By design, the Ethernet standard does not prevent multiple simultaneously transmission. These so-called collisions, when they occur, cause both transmissions to fail and require both sending devices to re-transmit. Ethernet uses an algorithm based on random delay times to determine the proper waiting period between re-transmissions. In traditional Ethernet, this protocol for broadcasting, listening and detecting collisions is known as CSMA/CD (Carrier Sense Multiple Access / Collision Detection).

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Some newer forms of Ethernet do not use CSMA/CD. Instead, they use the so-called full duplex Ethernet protocol, which supports point-to-point simultaneously sends and receives with no listening required.

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Figure 4.22 TRADITIONAL ETHERNET

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) Avionics Full Duplex Switched Ethernet (AFDX) A problem with the standard ethernet is, that if you have many computers you may get long waiting times to detect a silent medium that allows you to transmit the information. Therefore if you have time critical data transmissions like in the avionics system, you need to divide the ethernet network by switches. In the Avionics world this is called the AFDX switch. Now all computers can transmit data at any time and the switch transfers the data only to the receiver who needs the information. Here for example from computer 1 to computer 3. At the same time computer 5 could send data to computer 6. A collision is not possible, because the switch always buffers the data until the specific line is free. If for example Computer 1 and computer 5 want to send data at the same time to computer 3, than the AFDX switch buffers both data and transmit the data after each other.

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Figure 4.23 FAST ETHERNET

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES & ELECTRONIC INSTRUMENT SYSTEMS DATA BUSES (DCAM 5.4 L2) NOTES

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) 5.5 LOGIC CIRCUITS 5.5.1 Logic gates

Introduction

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Devices used in logic networks control the flow of information through the system and are therefore known as logic gates since the ' gates'are opened and closed by the binary inputs in order to perform a logical function.

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Logic gates are the basic building blocks from which many different kinds of logical outputs can be obtained. The gates we shall consider are the AND, NOT, OR, NAND, NOR and XOR gates. They are made up of electronic components and the output can be represented by Boolean algebra (named after George Boole (1815 -1864).

Logic gates have binary inputs of 1 or 0 and they may represent (in a circuit) ON, CLOSED (logic 1) or OFF, OPEN (logic 0). We shall be using the American symbols for the gates (there are British Standard symbols but are not in common use in the aircraft industry).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) AND Gate

This gate can have two or more inputs and only one output. It will give an output if all inputs are on. If any one input is not available the output will be zero. The symbol for a 2 input AND gate is shown below. The AND gate can be made up electrically by two switches in series. The lamp will only light when

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switches A AND B are both made. If any one switch is open the lamp will not light. The operation of the logic gate can be described by means of a TRUTH TABLE.

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•

When switch A is open (logic 0) and switch B is open (logic 0) there is no output the lamp (logic 0).

•

When switch A is made (logic 1) and switch B is open (logic 0) there is still no output to lamp (logic 0).

•

When switch A is open (logic 0) and switch B is made (logic 1) - still no output to lamp (logic 0).

•

When switch A is made (logic 1) and switch B is made (logic 1) there is an output to the lamp (logic 1).

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Where A and B are the inputs and S is the output. Only 2 inputs are shown but there may be more A, B, C, D etc. You must remember the symbols and the truth table.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) ACTIVITY:

Sketch a circuit for a three input AND gate and draw it' s symbol and derive it' s truth table. The Boolean expression for this gate is written A.B = S. The dot means AND, and the expression is read as "A AND B equals S" (in some books the output is called z).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) OR Gate

This can have two or more inputs and will give an output if any one input is logic 1.

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An OR gate circuit can be made up by two switches in parallel. The lamp will light if switch A OR B is closed.

So the truth table will be:

The Boolean expression is:

A + B = S The + means OR and the expression is read as "A OR B equals S". For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) NOT Gate

This gate has one input and one output.

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This gate produces an inversion of the input signal, so when the input is A the output is NOT A, which is symbolised by a bar on top of the A = A. So the output of this gate is the opposite to it' s input.

So input logic 1; output logic 0. Input logic 0; output logic 1. The truth table:

The Boolean expression is:

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) NAND Gate

This is short for NOT AND and works similar to a NOT gate except that it has more than one input.

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The bubble on the end of what is an AND gate has the same function as in the NOT gate - it inverts the signal, except that in this case more than one input is involved. In this gate when A is 0 AND B is 0 then the output is 1. In the AND gate this would be 0. So the NAND gate is an inverted AND gate.

The truth table is:

The Boolean expression is:

A⋅ B = S

The bar over A.B gives NOT AND and is read as “NOT (A AND B) EQUALS S”

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) NOR GATE

This is short for NOT OR and is simply a negated OR gate.

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Again an input A = 0 and B = 0 would, for a OR gate, give 0 as an output, but for the NOR gate it would give a 1 as an output.

The truth table is:

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The Boolean expression is:

A+ B = S

The bar over A+B gives NOT OR and is read as “NOT (A OR B) equals S”.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) XOR Gate

You may have noticed that the OR gate gives an output when A OR B = 1 and when A AND B = 1. The XOR gate only gives an output when A OR B are 1 not when A and B are 1, so it is exclusively an OR gate and will not work under the AND function. It is read as a two syllable word x then or.

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The truth table is:

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The Boolean expression is

AB + AB = S Which is read as "NOT A AND B OR A AND NOT B EQUALS S".

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) It should be appreciated that for all the gates so far discussed we have assumed logic 1 is positive (+5 volts) and logic 0 is zero (0 volts). This is called POSITIVE LOGIC and is the notation most frequently used.

However, NEGATIVE LOGIC may be used, and this means that logic 0 is positive (+5 volts) and logic 1 is zero (0 volts). We shall use positive logic throughout this book. To consolidate your knowledge of logic gates we shall put a few together to make up some simple logic circuits.

Note: Bubbles on inputs to gates negates or inverts the signal.

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With reference to logic circuit 1, what is the output logic level S if A = logic 1 B = logic 0 and C = logic 1?

With A = 1 and B = 0 (remember this 0 is changed to 1 by the bubble) the output of the first gate = 1. The input to the second gate is 0 (the 1 from gate 1 inverted, and input C = 0) so the output is 0.

What would be the Boolean expression for this circuit? The output of gate 1 is A.B (read as "A AND NOT B"). The output of gate 2 is A. B. C (read as "NOT [A AND NOT B] AND C").

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2)

ACTIVITY:

Study the following circuits and determine the logic level of the output from each.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) 5.5.2 Electronic Gates in Circuit

The earliest examples of logic mechanisms were those using mechanical levers (the key in a lock for example - AND logic}, gear wheels etc. Other systems used low-pressure highly filtered air in accurately engineered logic gates to control machines. These devices were slow, heavy and prone to failure due to their moving parts.

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Electrics have played a part in logic circuits as shown in the drawings above on AND and OR circuits. Micro switches, suitably wired are still used on many aircraft to perform logic functions. With the introduction of electronics, solid state circuitry can perform the most complex logic functions with the advantages

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of minimal size and weight; very low power consumption, and extremely fast operation.

The simplest logic using discrete components was the diode-resistor logic, the diagram below shows an AND gate.

When A or B = 0 then current will flow through the resistor and the diodes. This means that all the voltage is dropped across the resistor and no voltage is on the output line, so the output is 0V (logic state 0). When A and B are logic 1 (+5 volts), no current flows, voltage is the same both sides of resistor R and output is +5v (logic state 1).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) The diagram below shows an OR gate.

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When A or B are logic 1 current will flow and S will be high logic 1.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) The next advance was resistor transistor logic and diode transistor logic. The diagrams below show some typical circuits.

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Today since the integrated circuit (IC) became possible the logic gates work by transistor-transistor logic (TTL), metal oxide semiconductors (MOS) and complementary metal oxide semiconductor (CMOS) group of families.

The integrated circuit is a complete electronic circuit, transistors, diodes, resistors, capacitors, all made from and on one ' chip'of silicon, typically 5mm square and 0-5mm thick.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) The following diagram shows a typical IC with it' s plastic case partly cutaway to show the ' chip' .

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Note the metal pins - for inserting into a suitable IC socket or to be soldered into a PCB (Printed Circuit Board). Note also the metal connections from the chip to the pins. The reason for this form of construction is so as to allow the chip to be connected to other circuits. It is too small, in it' s original form, to be handled and/or to be connected to anything.

The scales of integration refer to the number of gates contained in a single IC package: •

Small scale integration (SSI) - containing not more than 11 gates.

•

Medium scale integration (MSI) - containing up to 100 gates.

•

Large scale integration (LSI) - containing between 100 to 1000 gates.

•

Very large scale integration (VLSI) - containing over 1000 gates.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) The diagrams below show the some TTL and CMOS sates.

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CMOS NOR GATE

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TTL NAND GATE

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CMOS NAND GATE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) Properties of TTL and CMOS

TTL uses bi-polar transistors along with diodes and transistors formed to microscopic dimensions on a slice of silicon (chip). TTL must have a steady 5V dc supply, while CMOS will work on dc voltages between 3V and 15V and usually requires much less power. CMOS uses unipolar Field Effect Transistors

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(FET) with metal-oxide-silicon technology; this lends itself to VLSI as they take up less room on a chip, compared to the TTL. CMOS has much higher input impedance. One important point with CMOS is that if static electric charges are allowed to build up on it' s input pins, these voltages can break down the

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thin layer of silicon oxide insulation between the gate and the other electrodes of MOSFET' S and this will destroy the IC. Anti-static protection is important.

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Gate operating parameters include:

a. Speed of operation - the time that elapses between the application of a signal to an input terminal and the resulting change in the logical state at the output terminals.

b. Fan in - number of inputs coming from similar circuits that can be connected to the gate without adversely affecting it' s performance. c. Fan out - the maximum number of similar circuits that can be connected to it' s output terminals without the output falling outside the limits at which logic levels 1 and 0 are specified.

d. Noise margin - this is maximum noise voltage (unwanted voltage) that can appear at it' s input terminals without producing a change in output state.

e. Power dissipation - as in any circuit, supply voltage multiplied by the current (Power = V x I) gives the power in the circuit and this heat must be dissipated.

f.

Speed of operation - the time that elapses between the application of a signal to an input terminal and the resulting change in the logical state at the output terminals.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) Typical figures for TTL and CMOS are shown below. Speed of Operation Fan in Fan out Noise Margin Power Dissipation Standard TTL

9nS

8

10

0.4V

40mW

CMOS

30nS

8

50

1.5V

0.001mW

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If you look back at the diagrams for the TTL AND gate and the TTL NAND gate you will see that the NAND gate uses fewer components and is therefore cheaper to produce.

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This also applies to the NOR gate, i.e. it is cheaper to produce than the OR gate.

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NOT GATE (INVERTING)

AND GATE

OR GATE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) NAND gates can be connected together to form any of the other basic gates -thus reducing production costs by manufacturing one gate only. The following drawings show how these gates can be formed.

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NAND GATE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) The following drawings show the pin connections of ICs for different gate configurations. There is no need to remember them but it does give a good idea of how the chip (with the gates in) is connected - although the chip itself is so small that it looks like a piece of silver metal 4 or 5 mm square.

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PIN CONNECTIONS TTL AND GATE

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PIN CONNECTIONS CMOS NOR GATE

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PIN CONNECTIONS CMOS AND GATE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) It is sometimes useful to know other logic gate representations. The drawings below show some alternative logic gate symbols.

AND GATE

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NAND GATE

NOR GATE

NOT OR INVERTING GATE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) At first sight it might appear that they are not equivalent by looking at the Boolean expressions. However using De Morgans rules we can prove they are the same.

De Morgans rules state:

A + B = A⋅ B A⋅ B = A + B

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Taking rule 1; NOT A OR B - NOT A AND NOT B. To apply the rule - split the bar and change the sign.

A + B split the bar A + B and change the sign A ⋅ B

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Taking the first AND gate output A.B output of equivalent circuit A ⋅ B = split the bar A + B change the sign A ⋅ B . Double bar over a letter removes the bar, i.e. second bar negates the single bar so the output is A.B, same as the AND gate. This procedure can be used with all the equivalent circuits. However, much more importantly, to convert the AND gate into it' s OR gate equivalent, remove bubbles where there are any, add bubbles where there are none. No bubbles on AND gate so add bubbles on all three connections.

Look at the NAND gate and shown that the OR gate has two bubbles on the input (none on the NAND) and none on the output (none on the NAND). So WHERE THERE ARE BUBBLES REMOVE THEM, WHERE THER ARE NO BUBBLES PUT SOME IN, this will give the equivalent circuit.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) ACTIVITY:

Draw the equivalent circuit of these gates.

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We now need to look at how these gates are used in aircraft circuits. You will need to be able to interpret these diagrams and explain how an output is arrived at.

You should be able to describe the operation of a logic circuit if an unexpected logic input is present. Logic gate circuitry is extensively used in aircraft schematic diagrams for all aircraft systems including airframe systems, engine systems, and all avionic systems.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) 5.5.3 Gate Application in Aircraft Systems Take-Off Warning System

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It can be seen that it consists of two OR gates and an AND gate, with logic states sent from 7 parameters. When throttle lever is pushed forward, the switch at that position is made (advance) and there is logic state 1 to OR gate 1.

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Five other parameters are sensed and logic states sent to OR gate 2. If all the other parameters are in the take-off position, i.e.

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1.

Slats not fully extended.

2.

Flaps in take-off position ie less than 25°.

3.

Spoiler handle in retract position.

4.

Horizontal stabiliser in the green band (correct angle of incidence for take-off).

Then the inputs to OR gate 2 are all logic 0 and it' s output to the AND gate is logic state 0.

The aircraft on the ground (weight switch) gives another logic 1 to the AND gate, which has at this time 2 logic 1' s and a logic 0.

If either of the four inputs go out of the take-off position e.g. flaps greater than 25°, then the flap input signal to logic gate 2 is logic 1 which makes the input to the AND gate logic 1. The AND gate now has three logic 1' s which now gives an output to the warning circuits (CONFIG light and aural warning).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) The following schematic diagram shows a take-off warning circuit

f o g y n r i r a t e e e i n r i p g o n r P SE A M For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) Landing Gear Lever “Disagree” Circuit The below diagram is of an undercarriage "gear disagree" indication circuit. Systems 1 and 2 sense any disagreement between the landing gear position and the landing gear selector lever position. So if a disagreement is detected then the ' gear'light illuminates.

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LANDING GEAR LEVER "DISAGREE" CIRCUIT

ACTIVITY:

Explain the operation of the circuit.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) ACTIVITY: To further enhance your ability to interpret logic diagrams, study the next drawing. It is a take-off warning circuit to warn the pilot if the aircraft is in the incorrect configuration for takeoff. Draw the logic circuit for the diagram.

It is important that you look at the logic schematic diagrams for your aircraft and work out how the gates are used.

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TAKE-OFF WARNING CIRCUIT

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) 5.5.4 Tri-state Devices

A tri-state device is a modification of the NOT gate. It includes an extra input called the Control Gate. The NOT gate actually has three output possibilities: •

If the control line is ON and the input is 1, the output is 1.

•

If the control line is ON and the input is 0, the output is O.

•

If the control line is OFF, the output should have no effect on the bus.

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This is not the same as either a 0 or a 1. It is "disconnected", like a loose wire. We call such a thing a "tri-state device".

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS LOGIC CIRCUITS (DCAM 5.5 L2) Another version of a tri-state device is shown in fig 5.33 (b):

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(Different models of tri-state devices differ in whether the data, or control, or both, or neither, is inverted.)

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Tri-state devices are connected to the output of logic circuits, just before the logic circuit connects to a bus. In this way, several logic circuits can be connected to the same bus. Thus, when the control line is off, the output does not interfere with other outputs all tied together on the bus. So at all times we will have exactly one item outputting to the bus, by switching the control line on for that item' s tri-state device and switching the control line off for all other items'tri-state.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) 5.6 BASIC COMPUTER STRUCTURE

A basic computer consists of the following: Central Processing Unit (CPU), Memory, Address Bus, Control Bus, Data Bus, Input/Output ports and power connections. Figure 6.1 shows the basic layout.

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Figure 6.1 BASIC COMPUTER LAYOUT

These elements are known as the hardware elements of a computer.

The computer' s function is to execute the instructions in the program. The program, it' s procedures, and documentation is known as the software. On aircraft this will be mainly in the form of pre-loaded programs but in some systems the program is on disc, which can be changed e.g., Flight Management System Navigational Data Base.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) 5.6.1 Central Processing Unit (CPU) This executes the individual instructions that are in the program and may also be called a microprocessor. This is a single integrated circuit on a chip. Its components include: •

The Register section

•

Arithmetic Logic Unit (ALU)

•

Control and Timing section

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The Register Section

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The register section consists of a number of storage locations (shift registers) where a piece of data is kept, or one of the registers used by the microprocessor in carrying out the different operations.

These storage elements or temporary memory store a single byte or word; a byte is typically an 8 bit (binary digit) word e.g., 10011101. Arithmetic Logic Unit (ALU)

This unit performs the arithmetic and logical operations. All calculations are performed in binary, including addition, subtraction, multiplication and division. Adders can be made using a number of logic gates where the basic principles of addition apply i.e., 0+0=0 1+0=1 0+1=1

1+1=1 carry 1

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) For subtraction the following method using "two' s complement" may be used. To obtain the two' s complement of a number (in binary form): i.

invert the binary number i.e., change all the ' 0' s to ‘1’s and all the ' 1' s to ‘0’s

ii.

then add 1

Example: Subtract 5 from 9 using a word length of 4 bits.

STEP 1: Write down in binary form the equivalent of binary 510 and 910.

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510=0101

910=1001

STEP 2: Subtract binary 5 from binary 9. Binary 5 is

0101

Invert gives

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1010

Add 1

1

1011 this is the two’s complement

Gives

STEP 3: Now we ADD the two’s complement of 5 to binary 9 9

1001

-5

1011

(1)0100

Using a word length of four bits [the carry one (1) is ignored], the answer is 0100 which is decimal 4.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Multiplication can be achieved by repetitive adding:

A x B = A + A + A + ……. (B times)

Division is achieved by repetitive subtractions: A ÷ B = A - B - B - B - …… Until the remainder is zero or a smaller number than B.

Timing and Control Section

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This co-ordinates the internal operation of the microprocessor and controls the operation of the ALU and registers to the desired action specified when an instruction is performed. The clock in this section is a crystal controlled oscillator producing pulses typically 120MHz to 200MHz (200,000,000 pulses per second). The program counter within the section counts the pulses and initiates the next step in the program and points to the address of the next instruction.

The microprocessor communicates with the memory to access, store and transfer data to the data highway or bus.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) 5.6.2 Memories

The purpose of the memory is to store the program instructions and data. These are recalled at appropriate times by the CPU while it is performing its functions. Memory can be basically divided into two types: a. Magnetic. b. Solid state.

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Magnetic memory is typically used where bulk-data is maintained on a long-term basis. In this type of memory, the data can be stored as a presence (or

f o g y n r i r a t e e e i n r i p g o n r P SE A M

absence) of a magnetized area in the storage medium.

Solid state memory can be used for transient or permanent data storage. In this type of memory, the data is stored as a voltage level. Access to the memory elements is directed by the address bus. Information transfer is accomplished using the bi-directional data bus.

Memory devices are the individual elements of the computer memory which can store Logic "1" and Logic "0" bits, in such a manner, that a single bit or group of bits (words) can be stored and retrieved. The memory can be physically part of the computer. For example, the computer-on-a chip has built-in memory. Although this memory is usually small, it does provide the computer with the necessary storage for instructions and data.

Memory devices may be on the same circuit card as the computer, in the same line replaceable unit (LRU), or in a separate LRU. In the case of aircraft computer systems, the memory is usually within the same LRU. There are many memory devices in use. The most common are the magnetic tape, magnetic disc and solid state memory.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) General Characteristics

Many devices have been used for storage of data in computers. Some of these devices have found wide usage while others have seen only limited application. Because of the diversity between the various memory types, it is difficult to define a set of standard characteristics which apply to all. There are some characteristics, however, which are generally applied to memory devices.

Volatile vs Non-Volatile Memories

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The selection of a memory type for a given computer system can be based upon the need for memory retention when system power is removed. If the memory is of a type that loses its data when power is removed, it is termed volatile memory; memory that retains data when power is removed is termed non-volatile memory. Volatile memory is made temporarily non-volatile by using a dedicated battery to provide enough power to the device to hold its memory.

Magnetic vs Solid State Memories

In general, most memory devices are either classified as magnetic or solid state. Memory devices using magnetic storage of data are typically employed where bulk data is maintained on a long-term basis. In this type of device, a binary "1" is noted by the presence of a small magnetized area in the storage medium. A binary "0" has no magnetized area or a magnetized area of opposite flux.

Solid state memories are used for transient storage of data and for permanent storage of data/instructions. Binary data is stored in these devices as a voltage level on a capacitor or at the output of a latch circuit.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Destructive vs Non Destructive Readouts

In configuring a computer system, the designer must provide additional circuitry for memories whose data is lost upon readout. These types of memories are referred to as having destructive readouts. Their use requires that the system temporarily store the data readout then write that data back into the

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memory before processing it. Memory devices which do not lose data upon readout are referred to as having nondestructive readouts.

5.6.3 Magnetic Memory Types

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Magnetic Tape

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The magnetic tape is a flexible plastic tape, with a uniform coating of magnetic material on one surface. The tape is usually stored on a plastic or metal reel, and when the tape is used, it is unwound off the supply reel past a read/write head and is wound onto a take-up reel. As the tape passes the read/write head, the computer controls the reading and writing of the magnetic bits from parallel tracks on the tape. These tracks extend from one end of the tape to the other. The read/write head is divided into the same number of sections as there are tracks on the tape being used. One track on the tape is usually reserved for the clock or timing pulses to allow synchronization of the tape with the computer operation.

Magnetic tapes can be used to store the computer program instructions and data. By means of a bi-directional tape drive, the computer may access the stored information anywhere on the length of the tape. Depending upon the length of the tape and the speed of the drive mechanism, memory access times can be very long.

Magnetic tapes can also be used as a storage medium for permanent record or backup. If a program is on a magnetic disc, for example, a copy of the program can be recorded onto the magnetic tape for backup. This is stored in a library. If anything should happen to the disc, the copy tape can be used to reprogram another disc. As revisions to the program are made, revisions are also made to the stored backup tape. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2)

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Figure 6.2 The Magnetic Tape Head

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) In a typical digital flight data recorder, aeroplane operating parameters are recorded for later use during performance evaluation or during accident investigation. The flight data recorder uses a magnetic tape. The magnetic tape is made of Kapton (similar to Mylar, except for higher thermal properties). The width is 1/4 inch, the length is 388 ft. The tape is self-lubricating. The tape format is 8 track bi-directional. The tape has a recording capacity of 25 hours. Beginning-of-tape (BOT) and end-of-tape (EOT) sensors are provided to reverse direction of motion and to switch to the next track.

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Figure 6.3 Magnetic Tape Used in Digital Flight Data Recorder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Magnetic Floppy Disc

The magnetic floppy disc is a flat magnetically coated disc. Digital information is stored on the disc in magnetic tracks. Generally, there are 40 to 80 tracks on a disc. The tracks are concentric about the disc center and each track is divided into pie-shaped sectors. Each sector can store between 128 and 512

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bytes of information and is accessible by using read/write heads. The disc is rotated to allow the read/write heads to store or to read the information on any of the sectors. There are several sizes of magnetic discs, ranging from 3 1/2 inches to 14 inches in diameter. Memory capacity on these discs varies,

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depending on disc size and formatting. The most common floppy disc is the 3 1/2 inch floppy. Usually it is formatted to hold 1440K bytes of information. Discs can be flexible (floppy discs) or rigid (hard discs). Rigid or hard discs can be stacked in such a manner that one head or multiple heads on an access

f o g y n r i r a t e e e i n r i p g o n r P SE A M

arm can extend between pairs of discs to read or write on disc surfaces above and below the arm.

The flexible disc is usually packaged inside a more rigid plastic envelope or jacket. Head access to the disc is provided through a slot in the envelope. A sliding guard protects the magnetic disc when not in use. A drive spindle makes contact with the disc through a hole in the center of the envelope. This allows the spindle to spin the disc at high speeds inside the envelope. A typical 3 1/2 inch disc spins at around 300 rpm when data is read or written. The advantage of magnetic discs is their rapid access time. The access for magnetic tape is in seconds (or minutes) while disc access time is in milliseconds. Size is a disadvantage due to the mechanical components needed to drive and read the discs.

Figure 6.4 A Magnetic Floppy Disk (diskette)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Magnetic Hard Disk Drive (HDD) A hard disk is a sealed unit containing a number of platters in a stack. Hard disks may be mounted in a horizontal or a vertical position. In this description, the hard drive is mounted horizontally. Electromagnetic read/write heads are positioned above and below each platter. As the platters spin, the drive heads

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move in toward the center surface and out toward the edge. In this way, the drive heads can reach the entire surface of each platter.

On a hard disk, data is stored in thin, concentric bands. A drive head, while in one position can read or write a circular ring, or band called a track. There

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can be more than a thousand tracks on a 3.5-inch hard disk. Sections within each track are called sectors. A sector is the smallest physical storage unit on a disk, and is almost always 512 bytes (0.5 kB) in size.

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The structure of older hard drives (i.e. prior to Windows 95) will refer to a cylinder/head/ sector notation. A cylinder is formed while all drive heads are in the same position on the disk. The tracks, stacked on top of each other form a cylinder. This scheme is slowly being eliminated with modern hard drives. All new disks use a translation factor to make their actual hardware layout appear continuous, as this is the way that operating systems from Windows 95 onward like to work.

To the operating system of a computer, tracks are logical rather than physical in structure, and are established when the disk is low-level formatted. Tracks are numbered, starting at 0 (the outermost edge of the disk), and going up to the highest numbered track, typically 1023, (close to the center). Similarly, there are 1,024 cylinders (numbered from 0 to 1023) on a hard disk. The stack of platters rotates at a constant speed. The drive head, while positioned close to the center of the disk reads from a surface that is passing by more slowly than the surface at the outer edges of the disk. To compensate for this physical difference, tracks near the outside of the disk are less-densely populated with data than the tracks near the center of the disk. The result of the different data density is that the same amount of data can be read over the same period of time, from any drive head position.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2)

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 6.5 The Internal Working of an HDD

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Figure 6.6 Parts of a Hard Drive ( with Two Platters)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) The disk space is filled with data according to a standard plan. One side of one platter contains space reserved for hardware track-positioning information and is not available to the operating system. Thus, a disk assembly containing two platters has three sides available for data. Track positioning data is written to the disk during assembly at the factory. The system disk controller reads this data to place the drive heads in the correct sector position. A sector, being the smallest physical storage unit on the disk, is almost always 512 bytes in size because 512 is a power of 29 (2 to the power of 9). The number 2 is

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used because there are two states in the most basic of computer languages - on and off. Each disk sector is labeled using the factory track-positioning data. Sector identification data is written to the area immediately before the contents of the sector and identifies the starting address of the sector.

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The optimal method of storing a file on a disk is in a contiguous series, i.e. all data in a stream stored end-to-end in a single line. As many files are larger

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than 512 bytes, it is up to the file system to allocate sectors to store the file' s data. For example, if the file size is 800 bytes, two 512 k sectors are allocated for the file. A cluster is typically the same size as a sector. These two sectors with 800 bytes of data are called two clusters. They are called clusters because the space is reserved for the data contents. This process protects the stored data from being over-written. Later, if data is appended to the file and its size grows to 1600 bytes, another two clusters are allocated, storing the entire file within four clusters.

If contiguous clusters are not available (clusters that are adjacent to each other on the disk), the second two clusters may be written elsewhere on the same disk or within the same cylinder or on a different cylinder - wherever the file system finds two sectors available. A file stored in this non-contiguous manner is considered to be fragmented. Fragmentation can slow down system performance if the file system must direct the drive heads to several different addresses to find all the data in the file you want to read. The extra time for the heads to travel to a number of addresses causes a delay before the entire file is retrieved.

Cluster size can be changed to optimize file storage. A larger cluster size reduces the potential for fragmentation, but increases the likelihood that clusters will have unused space. Using clusters larger than one sector reduces fragmentation, and reduces the amount of disk space needed to store the information about the used and unused areas on the disk. Most disks used in personal computers today rotate at a constant angular velocity. The tracks

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) near the outside of the disk are less densely populated with data than the tracks near the center of the disk. Thus, a fixed amount of data can be read in a constant period of time, even though the speed of the disk surface is faster on the tracks located further away from the center of the disk.

Modern disks reserve one side of one platter for track positioning information, which is written to the disk at the factory during disk assembly. It is not

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available to the operating system. The disk controller uses this information to fine tune the head locations when the heads move to another location on the disk. When a side contains the track position information, that side cannot be used for data. Thus, a disk assembly containing two platters has three sides that are available for data.

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Figure 6.7 Sectors and Clusters

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Optical Laser Disc

One of the developments in memory storage is the optical laser disc or Compact Disc (CD). This method of storage uses a technique which allows a large volume of information to be stored in a much smaller area. The 12 centimeter disc currently stores over 600 megabytes (600MB or 600 000 000 bytes).

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This is enough data for an average 24 volume encyclopedia. This small compact size is used in the smaller computers (or home computers). Other laser disc systems will be used with large mainframe computers. For instance, one manufacturer produces a system which stores one trillion bytes of information on four 14-inch laser discs. This is approximately equivalent to 400 billion-typed pages.

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There are several configurations for optical laser disc. One configuration is called CD-ROM (Compact Disc, Read Only Memory). This performs a similar function as a Read Only Memory microcircuit. A second configuration is called WORM (Write-Once, Read Many times) often referred to as CD-R. This optical disc can be written onto only once but read many times. Once data has been written onto the disc it can not be erased or written over. Currently, the capacity for a WORM is up to 650 Meg. A third configuration is the rewritable CD-RW. These discs allow the user to write, read, erase and rewrite up to 650MB of information on the disc. There are two methods currently used to organize an optical disc. The first method is called Constant Linear Velocity. In this method the disc is organized much like an old vinyl record played on a stereo. The second is called Linear Angular Velocity where the data is arranged on the disc in concentric rings, much like the tracks on a floppy disc. Information is stored on the disc as "pits" or "bumps" which are only 0.83 to 3.04 microns long and 0.50 microns (0.002 inches) wide. Each "track" is 1.6 microns apart. The Digital Versatile Disc (DVD) is the same size as a standard CD but by using different data encoding techniques, has a capacity of up to 4.7 Gigabytes (4.7GB or 4 700 000 000 bytes) . Like the CD they are available in both DVD-R and DVD-RW versions but due to the variety of encoding methods compatibility can be a problem. Both CDs and DVDs are available as double sided discs, with double the capacity, for specialist applications.

In all configurations a laser disc has a special Dye-polymer coating which responds to the wavelength of the recording laser to create either "bumps" or "pits". When reading the disc, the absence or presence of these pits is detected by a photodetector. The photodetector compares a beam of light being sent from the recording laser to a beam being returned from the disc. This is done by using a beam splitter in the laser disc system. The beam splitter For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) sends part of the light to the detector. The other part of the light is sent to the laser disc, reflected back to the beamsplitter and reflected onto the photodetector. The photodetector can now compare the two beams of light. An erasable Laser disc system uses a second laser to heat the dyepolymer layer and remove the bump or pit created by the recording laser.

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Figure 6.8 The Optical Laser Disc

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) 5.6.4 Solid State Memories Semiconductor or solid state memory chips have been used for small capacity memories. However, the development of high capacity semiconductor memory chips, with the ability to store millions of bits within a single integrated circuit (IC), has greatly modified the whole technology of building computer

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memories. Semiconductor memories have made possible the building of faster, more compact, lower power consumption memories for computers.

The two principal types of solid state memory devices are the: •

Read Only Memory (ROM).

•

Random Access Memory (RAM)

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Classifications of Solid State Memory

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Up to this point, you have learned some of the general functions of the CPU, the physical characteristics of memory, and how data is stored in the internal storage section. Now, we will explain yet another way to classify internal (primary or main) storage. This is by the different kinds of memories solid state memory: read-only memory, random-access memory, programmable read-only memory, and erasable programmable read-only memory.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Read-Only Memory (ROM)

In most computers, it is useful to have often used instructions, such as those used to bootstrap (initial system load) the computer or other specialized programs, permanently stored inside the computer. Memory that enables us to do this without the programs and data being lost (even when the computer

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is powered down) is called read-only memory. Only the computer manufacturer can provide these programs in ROM and once done, they cannot be changed. Consequently, you cannot put any of your own data or programs in ROM. Many complex functions such as routines to extract square roots,

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translators for programming languages, and operating systems can be placed in ROM memory. Since these instructions are hard wired (permanent), they can be performed quickly and accurately. Another advantage of ROM is that your computer facility can order programs tailored for its needs and have them

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permanently installed in ROM by the manufacturer. Such programs are called microprograms or firmware.

Programmable Read-Only Memory (PROM)

An alternative to ROM is programmable read only memory (PROM) that can be purchased already programmed by the manufacturer or in a blank state. To implant programs, or data, into a PROM a programming machine (called a PROM programmer) is used to apply the correct voltage for the proper time to the appropriate addresses selected by the programmer. As the PROM is simply an array of fusible links the programming machine essentially blows the various unwanted links within the PROM leaving the correct data patterns, a process which clearly cannot be reversed.

By using a blank PROM, you can enter any program into the memory. However, once the PROM has been written into, it can never be altered or changed. Thus you have the advantage of ROM with the additional flexibility to program the memory to meet a unique need. The main disadvantage of PROM is that if a mistake is made and entered into PROM, it cannot be corrected or erased. Also, a special device is needed to "burn" the program into PROM.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Erasable Programmable Read-Only Memory (EPROM)

The erasable programmable read-only memory (EPROM) was developed to overcome the drawback of PROM. EPROMs can also be purchased blank from the manufacturer and programmed locally at your command/activity. Again, this requires special equipment. The big difference with EPROM is that it

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can be erased if and when the need arises. Data and programs can be retrieved over and over again without destroying the contents of the EPROM. They will stay there quite safely until you want to reprogram it by first erasing the EPROM with a burst of ultra-violet light. This is to your advantage, because if a

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mistake is made while programming the EPROM, it is not considered fatal. The EPROM can be erased and corrected. Also, it allows you the flexibility to change programs to include improvements or modifications in the future.

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EPROM is re-usable by exposing the EPROM to ultraviolet (UV) light. The EPROM has to be removed from the microprocessor board and usually requires 15 to 20 minutes of exposure. A quartz window is installed on the top side of an EPROM to facilitate access to the UV light. Electrically Erasable Programmable Read Only Memory (EEPROM) was developed to replace the difficulty of reprogramming EPROM. This type of ROM is electrically alterable and the programming circuitry is included as part of the system.

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f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 6.9 An EPROM Package

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Electrically Erasable Programmable Read-Only Memory (EEPROM)

EEPROM is a special type of PROM that can be erased by exposing it to an electrical charge. Like other types of PROM, EEPROM retains its contents even when the power is turned off. Also like other types of ROM, EEPROM is not as fast as RAM.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Random-Access Memory (RAM)

Another kind of memory used inside computers is called random-access memory (RAM) or read/write memory. RAM memory is rather like a blackboard on which you can scribble down notes, read them, and rub them out when you are finished with them. In the computer, RAM is the working memory. Data can

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be read (retrieved) from or written (stored) into RAM just by giving the computer the address of the location where the data is stored or is to be stored. When the data is no longer needed, you can simply write over it. This allows you to use the storage again for something else. Ferrite cores, semiconductor, and bubble storage all have random access capabilities.

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Most modern RAM is of the integrated circuit (IC) or ' chip'form, containing flip flops, or MOSFETS, each flip-flop being switched to the 1 or 0 position, corresponding to a ' bit'of information.

Figure 6.10 A RAM Stick

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) Static Random Access Memory (SRAM) - SRAM' s store bits (1' s or 0' s) in memory cells that are basically flip flops. In a logic diagram, an SRAM memory cell looks like two cross connected NAND or NOR gates - that is, the output of each NAND or NOR gate is connected to one input of the other NAND or NOR gate. This is a "flip flop", which can store a 1 or a zero for as long as you apply power - but not very much power. Very little power consumption is required except during transitions - writing into the memory cell. Static power consumption (without transitions) is very low because the flip

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flop is based on CMOS NAND or NOR gates where either a P-channel or an N-channel transistor conducts, but not both - and the P and N channel transistors are connected in such a way that there is no conduction path from the power supply to ground so power is not consumed in the static state

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(except through leakage). The advantages of SRAM' s are their very high speed and very low power consumption – but SRAM memory cells generally require 6 transistors.

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Static Random Access Memories are the fastest type of memory.

Dynamic Random Access Memory (DRAM) - DRAM' s store bits in memory cells that are basically capacitors under transistors. The transistor is used as a relay to the capacitor, and the capacitor stores a bit (a "1" or a "0") as either storing charge on the capacitor or not storing charge. However, the charge on a capacitor gradually leaks out over time - so, periodically (generally several thousand times per second), the contents of a DRAM need to read out and then rewritten back in - this is called a "refresh cycle", or a "refresh". As you might expect, the refresh consumes a lot of power. DRAM' s consume more power, and are slower than SRAM' s - but because a DRAM cell uses just one transistor (with a capacitor) compared to 6 transistors for an SRAM cell, a DRAM memory is much cheaper than an SRAM memory.

SDRAM - Short for Synchronous DRAM, a type of DRAM that can run at much higher clock speeds than conventional memory. SDRAM actually synchronizes itself with the CPU' s bus. SDRAM is the new memory standard for modern PCs.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) DDR SDRAM - Double Data Rate - Short for Double Data Rate-Synchronous DRAM, a type of SDRAM that supports data transfers on both edges of each clock cycle (the rising and falling edges), effectively doubling the memory chip' s data throughput. DDR-SDRAM also consumes less power, which makes it well-suited to notebook computers. DDR-SDRAM is also called SDRAM II and DDRAM. DDR-SDRAM and RDRAM are the two technologies expected to replace SDRAM.

Bubble Memory (Old RAM)

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This is a magnetic solid state memory in which data is stored as microscopic cylindrical regions (the bubbles), that can drift in a thin film of garnet. These

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bubbles are generated by pulses through an aluminium loop over an insulating film on top of the garnet. Presence of a bubble is logic 1, no bubble is logic 0. These ‘bubbles’ can move around in the material in a controlled manner to form a shift register type memory. This is a non-volatile memory.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) 5.6.5 Storage Capacity An eight bit word is called a BYTE. The symbol K (capital K) is used to represent 1024 bits (210). The number of addressable locations in a memory is dependant on its number of input/output lines. A memory with 8 input lines has 28 or 256 locations; one with 16 input lines has 216 or 65,536 locations. The memory capacity in the second case assuming 8 bits (byte) per location is then a 64K memory (64 kilobytes). 5.6.6 Highway Structure

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Figure 6.11 shows the highway structure, there are three buses, the address bus, the data bus and the control bus. As we have already seen the memory consists of a number of locations, each individually identified by an ADDRESS. The address bus is therefore used to specify the memory location or

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input/output port involved in the transfer. It is a one way bus and may have anything from 4 to 32 lines depending on the number of memory addresses 8

there are, 8 lines give 2 =256 addresses. The data bus is a bi-directional bus and is used to carry the data being transferred to and from the memory or input and output transfer. The control bus comprises input and output lines which synchronise the microprocessor' s operation with that of the external circuitry e.g., read/write controls, timing signals, input/output selection. This is also a bi-directional bus.

Figure 6.11 HIGHWAY STRUCTURE

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS BASIC COMPUTER STRUCTURE (DCAM 5.6 L2) 5.5.7 Instruction Words

Each microprocessor has its own unique set of instructions. These instruction words normally consist of one, two or three bytes. The first byte is referred to as the operation code (opcode), this tells the microprocessor the type of operation to be performed. The remaining bytes can be data or an address indicating where the data is stored, this is known as the operand.

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An example of a single byte instruction would be to move the contents of register B to register A so the instruction would be an eight bit word which would indicate to the microprocessor that this is required ie, the opcode. A two-byte instruction will have an opcode (8 bits) and an operand, telling the

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microprocessor what the data is, or the address in the memory where it can be found. So this instruction will tell the microprocessor to do something with the data e.g., move it into a particular register.

A three-byte instruction would again make byte 1 the opcode and bytes 2 and 3 the operands, the second and third bytes each of 8 bits contain either data or an address of a 16 bit word. The second byte may hold the least significant bits and byte three the most significant bits. It should be noted in some microprocessors this may be the other way round. So the instruction here might be, "the content of the memory location whose address is specified by byte 2 and 3 is moved to a register".

Fetch-Execute Cycle

The microprocessor operates in a two phase mode, during the first phase, the fetch cycle, the next instruction is fetched from the memory and then in the second phase or execution cycle the microprocessor performs (executes) the action specified by the instruction (opcode). The program counter points to the next sequential instruction to be fetched and executed. Thus during a typical instruction cycle, the next instruction to be executed is read from the memory location indicated by the contents of the program counter. While this instruction is being executed, the contents of the program counter are incremented to point to the next instruction. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MICROPROCESSORS (DCAM 5.7 L2) 5.7 MICROPROCESSORS 5.7.1 Microprocessor (CPU) Structure and Operation Figure 7.1 shows a block diagram of a microprocessor used in an aircraft system. The function of the components is as follows: •

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Arithmetic and Logic Unit (ALU) - The arithmetic-logic section performs all arithmetic operations-adding, subtracting, multiplying, and dividing.

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Through its logic capability, it tests various conditions encountered during processing and takes action based on the result, data flows between the arithmetic-logic section and the internal registers during processing. Specifically, data is transferred as needed from the internal register section to

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the arithmetic-logic section, processed, and returned to the internal register section. At no time does processing take place in the memory section. Data may be transferred back and forth between these two sections several times before processing is completed. The result of a data operation is stored in either memory or an internal register. •

Registers - Perform a wide variety of functions, e.g. temporary storage information and specific programming operations. Accumulator - This is a general purpose register which contains one of the operands and the result of most ALU operations. Instruction Register - This register holds in binary form the opcode byte of the current instruction which the microprocessor is executing. Program Counter - This register/counter holds the address of the location in the memory where the next instruction in the program sequence is to be found. The contents of the counter can be incremented or decremented by special control pulses.

Buffer Register - Temporarily stores data.

Status Register - This is normally made up of single bit indicators (called flags). Typically the flags would include: ZERO flag – is the result zero?

CARRY flag - did a carry occur?

SIGN flag – is the number plus or minus?

PARITY flag - check whether the total number of bits is odd or even

Stack Pointer – Is used to indicate the next available location in the stack memory area. It serves as the effective address in stack addressing modes as well as subroutine and interrupts processing.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MICROPROCESSORS (DCAM 5.7 L2) Index Register – A general purpose register that is frequently used as an index value for calculation of an effective address. When executing an instruction with indexed addressing, the CPU fetches the opcode and the base address, and then modifies the address by adding an Index Register contents to the address prior to performing the desired operation.

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Figure 7.1 MICROPROCESSOR BLOCK DIAGRAM

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MICROPROCESSORS (DCAM 5.7 L2) •

Instruction Decoder - The binary word held in the instruction register is identified by the decoder, thus enabling the control unit to send out correct timing and control pulses.

•

Timing and Control - Contains the clock for timing pulses and also carries out a large number of functions e.g.:

Providing read/write pulses for registers, memories and input/output devices via a control bus. Incrementing and decrementing the program counter.

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CPU Clock - Also called clock rate, this is the speed at which a CPU executes instructions. Every computer contains an internal clock that regulates the rate at which instructions are executed and synchronizes all the various computer components. The CPU requires a fixed number of clock ticks (or clock cycles) to execute each instruction. The faster the clock, the more instructions the CPU can execute per second. The clock cycle is the smallest operation any computer makes. Clock speeds are expressed in megahertz (MHz) or gigahertz (GHz).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) 5.8 INTEGRATED CIRCUITS

5.8.1 Adders Adders are combinations of logic gates that combine binary values to obtain a sum. They are classified according to their ability to accept and combine the digits. In this section we will discuss quarter adders, half adders, and full adders.

Quarter Adder

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A quarter adder is a circuit that can add two binary digits but will not produce a carry. This circuit will produce the following results:

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0 plus 1 = 1 1 plus 0 = 1

1 plus 1 = 0 (no carry)

You will notice that the output produced is the same as the output for the Truth Table of an XOR. Therefore, an X-OR gate can be used as a quarter adder. The combination of gates in Figure 8.1 will also produce the desired results. When A and Bare both LOW (0), the output of each AND gate is LOW (0); therefore, the output of the OR gate is LOW (0). When A is HIGH and B is LOW, then B is HIGH and AND gate 1 produces a HIGH output, resulting in a sum of 1 at gate 3. With A LOW and B HIGH, gate 2 output is HIGH, and the sum is 1. When both A and B are HIGH, neither AND gate has an output, and the output of gate 3 is LOW (0); no carry is produced.

Figure 8.1 Quarter Adder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) Half Adder

A half adder is designed to combine two binary digits and produce a carry. Figure 8.2 shows two ways of constructing a half adder. An AND gate is added in parallel to the quarter adder to generate the carry. The SUM column of the Truth Table represents the output of the quarter adder, and the CARRY column represents the output of the AND gate.

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We have seen that the output of the quarter adder is HIGH when either input, but not both, is HIGH. It is only when both inputs are HIGH that the AND gate is activated and a carry is produced. The largest sum that can be obtained from a half adder is 102 (12 plus 12).

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.2 Half Adders and Truth Table

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2)

Full Adder The full adder becomes necessary when a carry input must be added to the two binary digits to obtain the correct sum. A half adder has no input for carries from previous circuits.

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One method of constructing a full adder is to use two half adders and an OR gate as shown in Figure 8.3. The inputs A and B are applied to gates 1 and 2. These make up one half adder. The sum output of this half adder and the carry-from a previous circuit become the inputs to the second half adder. The

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carry from each half adder is applied to gate 5 to produce the carry-out for the circuit. Now let' s add a series of numbers and see how the circuit operates.

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First, let' s add 1 and O. When either A or B is HIGH, gate 1 has an output. This output is applied to gates 3 and 4. Since the carry-in is 0, only gate 3 will produce an output. The sum of 12 and 0 is 12. Now let' s add 12 and 12. If A and B are both HIGH, the output of gate 1 is LOW. When the carry IN is 0 (LOW), the output of gate 3 is LOW. Gate 2 produces an output that is applied to gate 5, which produces the carry-out. The sum of 12 and 12 is 102, just as it was for the half adder. When A and B are both LOW and the carry-in is 1, only gate 3 has an output and produces a sum of 12 with no carry-out. Now, let' s add A or B and a carry-in. For example, let' s assume that A is HIGH, B is LOW and carry-in is HIGH. With these conditions, gate 1 will have an output. This output (HIGH) and the carry-in (HIGH) applied to gates 3 and 4 will produce a sum out of 0 and a carry of 1. This carry from gate 4 will cause gate 5 to produce a carry-out. The sum of A and a carry (12 plus 12) is 102.

When A, B, and the carry-in are all HIGH, a sum of 1 and a carry-out are produced. First, consider A and B. When both are HIGH, the output of gate 1 is LOW, and the output of gate 2 is HIGH, giving us a carry-out at gate 5. The carry-in produces a 1 output at gate 3, giving us a sum out f 1. The output of the full adder is 112. The sum of 12 plus 12 plus 12 is 112.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2)

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Figure 8.3 Full Adder and Truth Table

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) Parallel Adders

The adders discussed in the previous section have been limited to adding single-digit binary numbers and carries. The largest sum that can be obtained using a full adder is 112. Parallel adders let us add multiple-digit numbers. If we place full adders in parallel, we can add two- or four-digit numbers or any

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other size desired. Figure 8.4 uses STANDARD SYMBOLS to show a parallel adder capable of adding two, two-digit binary numbers. In previous discussions we have depicted circuits with individual logic gates shown. Standard symbols (blocks) allow us to analyze circuits with inputs and outputs

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only. One standard symbol may actually contain many and various types of gates and circuits. The addend would be input on the A inputs (A2 = MSB, A1= LSB), and the augend input on the B inputs (B2 = MSB, B1= LSB). For this explanation we will assume there is no input to C0 (carry from a previous circuit).

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Now let' s add some two-digit numbers. To add 102 (addend) and 012 (augend), assume there are numbers at the appropriate inputs. The addend inputs will be 1 on A2 and 0 on A1. The augend inputs will be 0 on B2and 1 on B1. Working from right to left, as we do in normal addition, let' s calculate the outputs of each full adder. With A1 at 0 and B1at 1, the output of adder 1 will be a sum (S1) of 1 with no carry (C1). Since A2 is 1 and B2 is 0, we have a sum (S2) of 1 with no carry (C2) from adder 1. To determine the sum, read the outputs (C2, S2, and S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1. The sum, then, of 102 and 012 is 0112 or 112.

To add 112 and 012, assume one number is applied to A1 and A2, and the other to B1 and B2, as shown in Figure 8.5. Adder 1 produces a sum (S1) of 0 and a carry (C1) of 1. Adder 2 gives us a sum (S2) of 0 and a carry (C2) of 1. By reading the outputs (C2, S2, and S1), we see that the sum of 112 and 012 is 1002. As you know, the highest binary number with two digits is 112. Using the parallel adder, let' s add 112 and 112. First, apply the addend and augend to the A and B inputs. Calculate the output of each full adder beginning with full adder 1. With A1and B1 at 1, S1 is 0 and C1 is 1. Since all three inputs (A2, B2, and C1) to full adder FA2 are 1, the output will be 1 at S2 and 1 at C2. The output of the circuit, as you read left to right, is 1102, the sum of 112 and 112. Parallel adders may be expanded by combining more full adders to accommodate the number of digits in the numbers to be added. There must be one full adder for each digit.

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f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.4 Parallel Binary Adder

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Figure 8.5 Parallel Addition

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) Subtraction Subtraction is accomplished in computers by the R' s complement and add method. R' s complement subtraction allows us to use fewer circuits than would be required for separate add and subtract functions. Adding X-OR gates to full adders, as shown in Figure 8.6, enables the circuit to perform R' s complement subtraction as well as addition.

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To add two numbers using this circuit, the addend and augend are applied to the A and B inputs. The B inputs are applied to one input of the X-OR gates.

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A control signal is applied to the other input of the X-OR gates. When the control signal is LOW, the circuit will add; and when it is HIGH, the circuit will subtract. In the add mode, the outputs of the X-OR gates will be the same as the B inputs. Addition takes place in the same manner as described in

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parallel addition. Before we attempt to show subtraction, let' s review R' s complement subtraction. To subtract 102 from 112, write down the minuend (112). Perform the R' s complement on the subtrahend. Now add the minuend and the complemented subtrahend.

Disregard the most significant 1, and the difference between 112 and 102 is 012. The most significant 1 will not be used in the example shown in the following paragraph. Now let' s subtract 102 from 112 using the adder/subtracter circuit. The minuend (112) is input on the A terminals, and the subtrahend (102) is input on the terminals. In the subtract mode, a 1 from the control circuit is input to each of the X-OR gates and to the Co carry input. By applying a 1 to each of the X-OR gates, you find the output will be the complement of the subtrahend input at B1and B2. Since B1 is a 0, the output of X-OR 1 will be 1. The input B2 to X-OR 2 will be inverted to a 0. The HIGH input to Co acts as a carry from a previous circuit. The combination of the X-OR gates and the HIGH at Co produces the R' s complement of the subtrahend. The full adders add the minuend and the R' s complement of the subtrahend and produce the difference. The output of C2 is not used. The outputs of S2 and S1 are 0 and 1, respectively, indicating a difference of 012. Therefore, 112 minus 102 equal 012.

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Figure 8.6 R’s Complement Adder/Substracter

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) 5.8.2 FLIP-FLOPS

Memory type circuits use ' flip-flops'as their main components. There are many types but we shall look at three, the SR or RS, D and JK flip-flops. These are so called because on the application of a suitable pulse at the input it causes it to flip'into one of it' s two stable states and stay in that state until a second input will ' flop'it into its previous state.

SR Flip-flop

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The SR flip-flop has two output terminals Q and Q . The diagram shows the SR flip-flop using NAND gates.

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SR FLIP-FLOP

When S=1, R=0; Q=1, Q =0 the flip flop is SET

When S=0, R=1; Q=0, Q =1 the flip flop is RESET

When S=0, R=0 then no change occurs Q and Q will be what they were before.

When S=1 and R=1 then Q=1 and Q equals 1. The circuit is stable while S=R=1, but if they are changed simultaneously from 1 to 0 then due to different switching times of the gates we cannot predict whether Q or Q will be 1. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) The output state is said to be indeterminate so S=R=1 should not be allowed to occur. The truth table is shown below.

S

R

Q

Q

1

0

1

0

0

1

0

1

0

0

Depends on state before inputs applied

1

1

Indeterminate

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So basically the flip-flop can exist in two stable states: Q = 1 ( Q = 0) or

Q = 0 ( Q = 1)

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) Clocks In sequential logic circuits where there may be a large number of flip-flops, it is important they all act at the same time, so no circuit operates out of sequence.

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This is achieved by a CLOCK pulse from a high frequency pulse generator. The circuits may be triggered when the clock pulse changes from 1 to 0 or when it changes from 0 to 1 (edge triggered) or when the level is 1 or 0. Figures 8.7 and Figure 8.8 shows a clocked SR flip-flop and it’s truth table.

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Figure 8.7 CLOCKED SR FLIP-FLOP

INPUTS

S 0 0 1 1 0 0 1 1

DURING CLOCK PULSE

OUTPUTS BEFORE CLOCK PULSE

OUTPUTS AFTER CLOCK PULSE

R

A

B

Q

Q

Q

Q

0 0 0 0 1 1 1 1

1 1 0 0 1 1 0 0

1 1 1 1 0 0 0 0

1 0 1 0 1 0 1 0

0 1 0 1 0 1 0 1

1 0 1 1 0 0 1 1

0 1 0 0 1 1 1 1

COMMENTS

NO CHANGE IN OUTPUTS FLIP-FLOP SETS WITH Q = 1 & FLIP-FLOP RESETS WITH

Q =0

Q =1&Q=0

THIS INPUT IS NOT ALLOWED

Figure 8.8 TH TABLE - CLOCKED SR FLIP-FLOP

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) D Type SR Flip-flop This is a modified SR flip-flop. The D stands for Delay. If you look at the truth table, when the clock pulse changes (rises), whatever is at D is transferred to Q, when clock pulse falls Q stays at that level. NO MATTER WHAT IS APPLIED TO D, Q will only change state at the next clock pulse. The truth table shows that the output equals the input one clock pulse earlier, i.e. the data is held back until the clock pulse = 1.

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.9 CLOCKED D TYPE FLIP-FLOP

OUTPUTS

INPUT

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BEFORE OUTPUTS

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AFTER

CLOCK PULSE

CLOCK PULSE

D

S

R

Q

Q

Q

Q

0

0

1

1

0

0

1

0

0

1

0

1

0

1

1

1

0

1

0

1

0

1

1

0

0

1

1

0

Figure 8.10 TRUTH TABLE CLOCKED D TYPE FLIP-FLOP

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) JK Flip-flop The next diagram shows the layout and truth table of the JK flip-flop using NAND gates. The two inputs are called J and K, the operation is fully described in the truth table and J=K=1 is allowed (unlike S=R=1 in a SR flip flop) and toggles (changes state) when this input is applied. These flip-flops are used in counters and shift registers and a wide variety of logic circuits.

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.11 JK FLIP-FLOP

INPUTS J 0 0 1 1 0 0 1 1

OUTPUTS

BEFORE DURING

CLOCK OUTPUTS

AFTER

CLOCK PULSE

PULSE

CLOCK PULSE

K

Q

Q

A

B

Q

Q

0

1

0

1

1

1

0

0

0

1

1

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

1

0

1

1

0

1

0

0

1

1

0

1

1

1

0

1

1

1

0

1

0

0

1

1

0

1

0

1

1

0

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COMMENTS

NO CHANGE IN OUTPUTS

STAYS AT OR SET TO Q = 1 & Q = 0

STAYS AT OR SET TO Q = 1 & Q = 0

TOGGLES

Figure 8.12 TRUTH TABLE JK FLIP-FLOP

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) 5.8.3 Counters

A counter is simply a device that counts. Counters may be used to count operations, quantities, or periods of time. They may also be used for dividing frequencies, for addressing information in storage, or for temporary storage. Counters are a series of flip-flops wired together to perform the type of

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counting desired. They will count up or down by ones, twos, or more. The total number of counts or stable states a counter can indicate is called

MODULUS. For instance, the modulus of a four-stage counter would be 1610, (24 ) since it is capable of indicating 00002 to 11112 . The term modulo is

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used to describe the count capability of counters; that is, modulo-16 for a four-stage binary counter, modulo-11 for a decade counter, modulo-8 for a threestage binary counter, and so forth.

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A counter can also be used as a frequency divider. Thus, each stage of the counter reduces the frequency of a square wave input by 2. A four-stage counter will therefore reduce the input frequency 16 times (24 ) and a 3 stage counter 8 times (23 ) etc.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) Ripple Counters

Ripple counters are so named because the count is like a chain reaction that ripples through the counter because of the time involved. This effect will become more evident with the explanation of the following circuit. Figure 8.13, view A, shows a basic four-stage, or moduIo-16, ripple counter. The inputs

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and outputs are shown in view B. The four J-K flip-flops are connected to perform a toggle function; which, you will recall, divides the input by 2. The HIGHs on the J and K inputs enable the flip-flops to toggle. The inverters on the clock inputs indicate that the flip-flops change state on the negative-going pulse.

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Assume that A, B, C, and D are lamps and that all the flip-flops are reset. The lamps will all be out, and the count indicated will be 00002. The negative-

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going pulse of clock pulse 1 causes flip-flop 1 to set. This lights lamp A, and we have a count of 00012. The negative-going pulse of clock pulse 2 toggles flip-flop 1, causing it to reset. This negative-going input to flip-flop 2 causes it to set and causes B to light. The count after two clock pulses is 00102, or 210. Clock pulse 3 causes flip-flop 1 to set and lights lamp A. The setting of flip-flop 1 does not affect flip-flop 2, and lamp B stays lit. After three clock pulses, the indicated count is 00112.

Clock pulse 4 causes flip-flop 1 to reset, which causes flip-flop 2 to reset, which causes flip-flop 3 to set, giving us a count of 01002. This step shows the ripple effect. This setting and resetting of the flip-flops will continue until all the flip-flops are set and all the lamps are lit. At that time the count will be 11112 or 1510. Clock pulse 16 will cause flip-flop 1 to reset and lamp A to go out. This will cause flip-flop 2 through flip-flop 4 to reset, in order, and will extinguish lamps B, C, and D. The counter would then start at 00012 on clock pulse 17. To display a count of 1610 or 100002, we would need to add another flip-flop. The ripple counter is also called an asynchronous counter. Asynchronous means that the events (setting and resetting of flip-flops) occur one after the other rather than all at once. Because the ripple count is asynchronous, it can produce erroneous indications when the clock speed is high. A high-speed clock can cause the lower stage flip-flops to change state before the upper stages have reacted to the previous clock pulse. The errors are produced by the flip-flops inability to keep up with the clock.

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Figure 8.13 Four Stage Ripple Counter A. Logic Diagram

B. Timing Diagram

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) 5.8.4 Decoders

Introduction

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The basic function of a decoder is to detect the presence of a specified combination of bits (code) on its inputs and to indicate that presence by a specified output level. In its general form a decoder has ‘n’ input lines to handle ‘n’ bits and from one to 2n output lines to indicate the presence of one or more n-bit combinations.

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The Basic Binary Decoder

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Suppose we wish to determine when a binary 1001 occurs on the inputs of a digital circuit. An AND gate can be used as the basic decoding element because it produces a HIGH output only when all of its inputs are HIGH. Therefore we must make sure that all of the inputs to the AND gate are HIGH when the binary number 1001 occurs; this can be done by inverting the two middle bits (the Os).

The logic equation for the decoder of Figure 8.14 (a) is developed as illustrated in Figure 8.14 (b). Ao is the LSB, and A3 is the MSB. In the representation of a binary number or other weighted code, the LSB is always the right-most bit in a horizontal arrangement and the topmost bit in a vertical arrangement, unless specified otherwise.

If a NAND gate is used in place of the AND gate, as shown in Figure 8.15, a LOW output will indicate the presence of the proper binary code.

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f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.14 A Basic Binary Decoder

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Figure 8.15 A Basic Binary Decoder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) The Four-Bit Binary Decoder In order to decode all possible combination of four bits, sixteen decoding gates are required (24 = 16). This type of decoder is commonly called a 4-line-to16-line decoder because there are four inputs and sixteen outputs. A list of sixteen binary code words and their corresponding decoding functions is shown

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below. Rather than reproducing the complex logic diagram for the decoder each time it is required in a schematic, a simpler representation is normally used. A logic symbol for a 4-line-to-16-line decoder is shown in Figure 8.16. The BIN/DEC label indicates that a binary input makes the corresponding decimal output active. The input labels 1, 2, 4, and 8 represent the weights of the input bits.

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Decoding Functions and Truth Table for a 4-line to 16 line Decoder

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Figure 8.16 4-line to 16-line Decoder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) The BCD to Decimal Decoder

The BCD-to-Decimal decoder converts each BCD code word (8421) into one of ten possible digit indications. It is frequently referred to as a 4-line-to-10line decoder, although other types of decoder also fall into this category (such as Excess 3 decoder). The method of implementation is essentially the same

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as for the 4-line-to-16-line decoder previously discussed, except that only 10 decoding gates are required because the BCD code represents only the ten decimal digits 0 through 9. A list of the ten BCD code words and their corresponding decoding functions is given in the table below. The logic is identical to that of the first ten decoding gates in the 4-line-to-16-line decoder.

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BCD to Decimal Converter Truth Table

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) The BCD-to-Seven-Segment Decoder/Driver

This type of decoder accepts the BCD code on its inputs and provides outputs to energize seven-segment display devices to produce a decimal readout. Before proceeding with a discussion of this decoder, let us examine the basics of a seven-segment display device. Figure 8.17 shows a common display

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format composed of seven elements or segments. Energizing certain combinations of these segments can cause each of the ten decimal digits to be produced. Figure 8.18 illustrates this method of digital display for each of the ten digits by using a darker segment to represent one that is energized. To

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produce a 1, segments b and c are energized; to produce a 2, segments a, b, g, e, and d are used; and so on.

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.17 7 Segment LED DIsplay

Figure 8.18 10 Digits – 7 Segment Display

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) LED Displays

One common type of seven-segment display consists of light-emitting diodes (LEDs) arranged as shown in Figure 8.19. Each segment is an LED that emits light when there is current through it. In Figure 8.19 (a) the common-anode arrangement requires the driving circuit to provide a LOW level voltage in

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order to activate a given segment. When a LOW is applied to a segment input, the LED is turned on, and there is current through it. In Figure 8.19(b) the common-cathode arrangement requires the driver to provide a HIGH level voltage to activate a segment. When a HIGH is applied to a segment input, the

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LED is turned on and there is current through it. The activated segments for each of the ten decimal digits are listed in the table overleaf. We will now examine the decoding logic required to produce the format for a seven-segment display with a BCD input. Notice that segment la'is activated for digits 0, 2,

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3, 5,6, 7, 8, and 9; segment ‘b'is activated for digits 0, 1, 2, 3,4,7, 8, and 9; and so on. If we let the BCD inputs to the decoder be represented by the general form A3 A2 A1 Ao, a Boolean expression can be found for each segment in the display, and this will tell us the logic circuitry required to drive or activate each segment. For example, the equation for segment la'is as follows:

This equation says that segment ' a'is activated, or "true," if the BCD code is "0 OR 2 OR 3 OR 5 OR 6 OR 7 OR 8 OR 9." The table 8.1 below lists the logic function for each of the seven segments.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2)

f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.19 7 Segment LED Display

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Table 8.1 LED Controller Segment

Activation

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) From the expressions in the table below, the logic for the BCD-to-seven-segment decoder can be implemented. Each of the ten BCD codes is decoded, and then the decoding gates are ORed as dictated by the logic expression for each segment. For instance, segment ' a'requires that the decoded BCD digits 0, 2, 3, 5, 6, 7, 8, and 9 be ORed.

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BCD-to-7 Segment Decoder Logic

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) NOTES

f o g y n r i r a t e e e i n r i p g o n r P SE A M For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) 5.8.5 Encoders

An encoder is a combinational logic circuit that essentially performs a "reverse" decoder function. An encoder accepts an active level on one of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded output, such as binary or BCD. Encoders can also be devised to encode

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various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a coded format is called encoding.

The Decimal-to-BCD Encoder

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This type of encoder has ten inputs - one for each decimal digit - and four outputs corresponding to the BCD code, as shown in Figure 8.20. This is a basic 10-line-to-4-line encoder. For instance, the most significant bit of the BCD code, A3, is a 1 for decimal digit 8 or 9. The OR expression for bit A3 in terms of the decimal digits can therefore be written.

Bit A2 is a 1 for decimal digit 4, 5, 6, or 7 and can be expressed as an OR functions as follows: A2 = 4 + 5 + 6 + 7

Bit A1 is a 1 for decimal digit 2, 3, 6, or 7 and can be expressed as A1 = 2 + 3 + 6 + 7

Finally, Ao is a 1 for digit 1, 3, 5, 7, or 9. The expression for A0 is

Ao= 1 +3+5+7+9

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f o g y n r i r a t e e e i n r i p g o n r P SE A M Figure 8.20 DEC to BCD Encoder

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BCD Truth Table

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) Now we can implement the logic circuitry required for encoding each decimal digit to a BCD code by using the logic expressions just developed. It is simply a matter of ORing the appropriate decimal digit input lines to form each BCD output. The basic encoder logic resulting from these expressions is shown in Figure 8.21. Basic logic diagram of a decimal-to-BCD encoder. A O-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.

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The basic operation is as follows: When a HIGH appears on one of the decimal digit input lines, the appropriate levels occur on the four BCD output lines.

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For instance, if input line 9 is HIGH (assuming all other input lines are LOW), this condition will produce a HIGH on outputs A0 and A3 and LOWs on outputs A1 and A2, which is the BCD code (1001) for decimal 9.

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Figure 8.21 Decimal to BCD Encoder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS INTEGRATED CIRCUITS (DCAM 5.8 L2) An Encoder Application

A classic application example is a keyboard encoder. The ten decimal digits on the keyboard of a calculator, for example, must be encoded for processing by the logic circuitry. When one of the keypads is pressed, the decimal digit is encoded to the corresponding BCD code. Figure 8.22 shows a simple keyboard encoder arrangement using a 74147 priority encoder.

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Notice that there are ten push-button switches, each with a pull-up resistor to + V. The pull-up resistor ensures that the line is HIGH when a switch is not depressed. When a switch is depressed, the line is connected to ground, and a LOW is applied to the corresponding encoder input. The zero key is not

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connected because the BCD output represents zero when none of the other keys are depressed.

The BCD output of the encoder goes into a storage device, and each successive BCD code is stored until the entire number has been entered.

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Figure 8.22 Keyboard Encoder

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) 5.9 MULTIPLEXING 5.9.1 Multiplexers

Introduction

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The idea-of multiplexing/ de-multiplexing is to send data from several sources down the one data transmission line - thus saving weight. A multiplexer is a device which selects data from one of many inputs and connects this data to a common single output. Some practical examples are in Flight Data

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Recording (FDR) where the Digital Flight Data Acquisition Unit (DFDAU) receives a large number of inputs from the various aircraft parameters which have to be sampled and eventually fed to the FDR.

Another example is in passenger entertainment systems where the passenger can select one audio/visual channel from amongst many channels supplied to the seat. These channels (inputs) are "multiplexed" in that each input is sampled and passed in serial fashion along a data line. When the passenger selects the required service e.g. the film channel, then only the information on that line relevant to the film channel is selected by a ' de-multiplexer'and fed to the passenger.

A multiplexer/ de-multiplixer system can be likened to a train service with several trains waiting at the platforms of say a major London station. They are all destined to go to the same town - say Manchester - with the same number of platforms, but only one main line between the two cities. Each train leaves it' s platform it turn and is caused to go onto the main line by a set of points (multiplexer). It travels on the main line until it reaches its destination station where it is caused to go to it' s own platform by another set of points (de-multiplexer).

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) Each-train is sent down the same main line in this fashion. Data can be transmitted like this, but at much greater speeds of course. The multiplexer unit can be likened to a mechanical rotary switch (see drawing below), with separate units of data waiting in temporary store to be transmitted down the data output line. In reality it is electronic with no moving parts and is very fast.

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SIMPLE REPRESENTATION OF A MULTIPLEXER

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) The next diagram shows the basic principle of a multiplexer showing the data to be transmitted. Just check, first of all you are satisfied that with the inputs on X and Y = 0. These are the ' command signals' .

So with command input of X=0 Y=0 logic 1 goes out through the OR gate. Now work through the multiplexer action when X = 1 Y = 0. You should see the

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AND gate 2 gives logic 1. Now try X=0 Y=1 and you will see the AND gate 3 gives an output of 1 and finally when X=1 Y=1 then AND gate 4 will give an output of 1. So the OR gate will have passed the input 1111 down to data highway.

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This data has to be transferred along a data highway usually by Time Division Multiplexing (TDM). In TDM the data channels each occupy the same

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frequency band but divide the channel into time slots into which bits of signal are transmitted.

MULTIPLEXER LOGIC CIRCUIT

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) The next diagram shows four data channels operating at 200bits/sec. The buffer store is a holding store until access to the data highway is signalled. The duration of each bit is 1/200s or 5ms (5 milli seconds) so an 8 bit word occupies 40ms. The common line is operated at input channel speed times the number of channels i.e., 4 x 200 = 800 bits/sec. So each bit will have a time slot of 1.25mS. Data from the systems connected to Channels 1, 2, 3 and 4 are fed into a Buffer Store, until each store is signalled by the clock pulse to output its data onto the common line in sequence.

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As you can see from the diagram there must be some way of converting these signals to the appropriate receiving channel, i.e. channel 1 input signal data

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to be picked up by channel 1 receiving channel. This will be by a de-multiplexer, a device with a single input but with multiple outputs. There obviously has to be synchronisation between the input and output channels to ensure each data go to the correct channel. Thus all the system works on the command of

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the clock (electronic).

TIME DIVISION MULTIPLEXER

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) 5.9.2 De-multiplexer These are similar to a multiplexer but work "the other way round". They take sequential input data from a common data line and output each piece of data to its appropriate channel. The drawing below shows the mechanical equivalent of the electronic device.

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SIMPLE REPRESENTATION OF A DE-MULTIPLEXER

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The next diagram shows a 1 line to 8 line de-multiplexer. It has 8 AND gates, three NOT gates, and input line and 8 output lines. As the name implies it has 1 input line and 8 output lines, with the single data input line is connected to all eight gates. Each gate will be enabled by the signals on the select lines S2 S1 S0.

Assuming 000 input on the select lines only GATE 0 will open and the data will appear at its output. The truth table shows the logic states of the de-multiplexer.

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TRUTH TABLE FOR THE ONE LINE TO 8 MULTIPLEXER

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) The next diagram shows the basic principles of a passenger entertainment system.

The multiplexer selects all the inputs in turn, (12 channels of recorded music, passenger address messages and tape signals) digitises them (analogue to digital converter) into one serial data signal stream. This stream of data is fed to the seats via the sidewall disconnects. The data is received by the

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electronic boxes. Depending on the selection made by the passenger, the signal is de-multiplexed and decoded (digital to analogue) to output the required signal.

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A PASSENGER ENTERTAINMENT SYSTEM - GENERAL ARRANGEMENT

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS MULTIPLEXING (DCAM 5.9 L2) Some Definition

Simplex

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Data in Simplex channel is always one way. Simplex channels are not often used because it is not possible to send back error or control signals to the transmit end.

Half Duplex

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A half-duplex channel can send and receive, but not at the same time. It’s like one-lane bridge where two way traffic must give way in order to cross. Only one end transmits at a time, the other end receives.

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Data can travel in both directions simultaneously. There is no need to switch from transmit to receive mode like in half duplex. It is like a two lane bridge on a two lane highway.

The term “Full Duplex” is somewhat redundant, as “Duplex” alone will suffice. However, “Full Duplex” is still sometimes used to differentiate it from Half Duplex.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.FIBRE OPTICS

5.10.1 Definition of Fibre Optics

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In the other modules, you learn the basic concepts used in electrical systems. Electrical systems include telephone, radio, cable television (CATV), radar, and satellite links. In the past 30 years, researchers have developed a new technology that offers greater data rates over longer distances at costs lower than copper wire systems. This new technology is fibre optics.

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Fibre optics uses light to send information (data). More formally, fibre optics is the branch of optical technology concerned with the transmission of radiant power (light energy) through fibres.

5.10.2 Fibre Optic Data Links

A fibre optic data link sends input data through fibre optic components and provides this data as output information. It has the following three basic functions: •

To convert an electrical input signal to an optical signal

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To send the optical signal over an optical fibre

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To convert the optical signal back to an electrical signal

A fibre optic data link consists of three parts - transmitter, optical fibre, and receiver. Figure 10.1 is an illustration of a fibre optic data-link connection. The transmitter, optical fibre, and receiver perform the basic functions of the fibre optic data link. Each part of the data link is responsible for the successful transfer of the data signal.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) A fibre optic data link needs a transmitter that can effectively convert an electrical input signal to an optical signal and launch the data-containing light down the optical fibre. A fibre optic data link also needs a receiver that can effectively transform this optical signal back into its original form. This means that the electrical signal provided as data output should exactly match the electrical signal provided as data input.

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The transmitter converts the input signal to an optical signal suitable for transmission. The transmitter consists of two parts, an interface circuit and a source drive circuit. The transmitter' s drive circuit converts the electrical signals to an optical signal. It does this by varying the current flow through the light

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source. The two types of optical sources are light-emitting diodes (LEDs) and laser diodes. The optical source launches the optical signal into the fibre. The optical signal will become progressively weakened and distorted because of scattering, absorption, and dispersion mechanisms in the fibre waveguides.

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The receiver converts the optical signal exiting the fibre back into an electrical signal. The receiver consists of two parts, the optical detector and the signalconditioning circuits. An optical detector detects the optical signal. The signal-conditioning circuit conditions the detector output so that the receiver output matches the original input to the transmitter. The receiver should amplify and process the optical signal without introducing noise or signal distortion. Noise is any disturbance that obscures or reduces the quality of the signal. Noise effects and limitations of the signal-conditioning circuits cause the distortion of the receiver' s electrical output signal.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.3 Fibre Optic Systems

System design has centred on long-haul communications and the subscriber-loop plant. The subscriber-loop plant is the part of a system that connects a subscriber to the nearest switching centre. Cable television is an example. Limited work has also been done on short-distance applications and some aircraft systems.

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Initially, central office trunking required multimode optical fibres with moderate to good performance. Fibre performance depends on the amount of loss and signal distortion introduced by the fibre when it is operating at a specific wavelength. Long-haul systems require single mode optical fibres with very high

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performance. Single mode fibres tend to have lower loss and produce less signal distortion. In contrast, short-distance and aircraft systems tend to use only multimode technology. Examples of short-distance systems include process control and local area networks (LANs).

Short-distance and aircraft systems have many connections. The larger fibre core and higher fibre numerical aperture (NA) of multimode fibres reduce losses at these connections. In aircraft and subscriber-loop applications, system design and parts selection are related.

Designers consider trade-offs in the following areas: •

Fibre properties

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Types of connections

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Optical sources

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Detector types

Designers develop systems to meet stringent working requirements, while trying to maintain economic performance. It is quite difficult to identify a standard system design approach. This module identifies the types of components chosen by the aircraft manufacturers for aircraft applications. Future system design improvements depend on continued research. Researchers expect fibre optic product improvements to upgrade performance and lower costs for short-distance applications.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) NOTES

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.4 Advantages and Disadvantages of Fibre Optics

Fibre optic systems have many attractive features that are superior to electrical systems. These include improved system performance, immunity to electrical noise, signal security, and improved safety and electrical isolation. Other advantages include reduced size and weight, environmental protection, and overall system economy. The following list details the main advantages of fibre optic systems.

Advantages of Fibre Optics

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System Performance

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Greatly increased bandwidth and capacity

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Lower signal attenuation (loss)

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Immunity to Electrical Noise

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Immune to noise (electromagnetic interference [EMI] and radio-frequency interference [RFI])

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No crosstalk

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Lower bit error rates

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Signal Security

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difficult to tap

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Nonconductive (does not radiate signals) - Electrical Isolation

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No common ground required

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Freedom from short circuit and sparks

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Reduced size and weight cables

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Environmental Protection

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Resistant to radiation and corrosion

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Resistant to temperature variations

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Improved ruggedness and flexibility

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Less restrictive in harsh environments

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Silica is the principal, abundant, and inexpensive material (source is sand) Despite the many advantages of fibre optic systems, there are some

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disadvantages. Because of the relative newness of the technology, fibre optic components are expensive. Fibre optic transmitters and receivers are still relatively expensive compared to electrical interfaces.

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The lack of standardization in the industry has also limited the acceptance of fibre optics. Many industries are more comfortable with the use of electrical systems and are reluctant to switch to fibre optics. However, industry researchers are eliminating these disadvantages. Standards committees are addressing fibre optic part and test standardization.

The cost to install fibre optic systems is falling because of an increase in the use of fibre optic technology. Published articles, conferences, and lectures on fibre optics have begun to educate managers and technicians. As the technology matures, the use of fibre optics will increase because of its many advantages over electrical systems.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.5 Frequency and Bandwidth

Bandwidth is defined as the amount of information that can be transmitted at one time. In the early days of radio transmission when the information transmitted was mostly restricted to Morse code and speech, low frequencies were (long waves) were used. The range of frequencies available to be transmitted (which determines the bandwidth) was very low. This inevitably restricted us to low speed data transmission.

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As time went by, we required a wider bandwidth to send more complex information and to improve the speed of transmission. To do this, we had to increase the frequency of the radio signal used. The usable bandwidth is limited by the frequency used - the higher the frequency, the greater the

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bandwidth.

When television was developed we again had the requirement of a wider bandwidth and we responded in the same way - by increasing the frequency. And so it went on. More bandwidth needed? Use higher frequency. For something like sixty years this became an established response - we had found the answer! Until fibre optics blew it all away.

The early experiments showed that visible light transmission was possible and we explored the visible spectrum for the best light frequency to use. The promise of fibre optics was the possibility of increased transmission rates. The old solution pointed to the use of the highest frequency but here we met a real problem. We found that the transmission losses were increasing very quickly. In fact the losses increased by the fourth power. This means that if the light frequency doubled, the losses would increase by a factor of 24 or 16 times.

We quickly appreciated that it was not worth pursuing higher and higher frequencies in order to obtain higher bandwidths if it meant that we could only transmit the data over a very short distance. The bandwidth of a light based system was so high that a relatively low frequency could be tolerated in order to get lower losses and hence more transmission range. So we explored the lower frequency or the red end of the visible spectrum and then even further

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) down into the infrared. And that is where we are at the present time. Infrared light covers a fairly wide range of wavelengths and is generally used for all fibre optic communications. Visible light is normally used for very short range transmissions using plastic fibre.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.6 Fibre Optic Concepts

Fibre Optic Light Transmission

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Fibre optics deals with the transmission of light energy through transparent fibres. How an optical fibre guides light depends on the nature of the light and the structure of the optical fibre.A light wave is a form of energy that is moved by wave motion. Wave motion can be defined as a recurring disturbance

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advancing through space with or without the use of a physical medium. In fibre optics, wave motion is the movement of light energy through an optical fibre.

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Velocity of light

For all practical purposes the velocity of light through free space is 3 × 108m/s (186,000 miles per second). The velocity of light changes as it passes from one medium to another. When light travels through these other mediums its velocity is reduced. Because of this slowing down, the light ray bends at the surface of the new medium. In optics a medium is any substance that transmits light.

Propagation of Light

The exact nature of light is not fully understood, although people have been studying the subject for many centuries. In the 1700s and before, experiments seemed to indicate that light was composed of particles. In the early 1800s, a physicist Thomas Young showed that light exhibited wave characteristics. Further experiments by other physicists culminated in James Clerk (pronounced Clark) Maxwell collecting the four fundamental equations that completely describe the behaviour of the electromagnetic fields. James Maxwell deduced that light was simply a component of the electromagnetic spectrum. This seems to firmly establish that light is a wave. Yet, in the early 1900s, the interaction of light with semiconductor materials, called the photoelectric effect, could not be explained with electromagnetic-wave theory. The advent of quantum physics successfully explained the photoelectric effect in terms of fundamental particles of energy called quanta. Quanta are known as photons when referring to light energy. For Training Purposes Only

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) The electromagnetic energy of light is a form of electromagnetic radiation. Light and similar forms of radiation are made up of moving electric and magnetic forces. A simple example of motion similar to these radiation waves can be made by dropping a pebble into a pool of water. In this example, the water is not actually being moved by the outward motion of the wave, but rather by the up-and-down motion of the water. The up-and-down motion is transverse, or at right angles, to the outward motion of the waves. This type of wave motion is called transverse-wave motion. The transverse waves spread out in

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expanding circles until they reach the edge of the pool, in much the same manner as the transverse waves of light spread from the sun. However, the waves in the pool are very slow and clumsy in comparison with light, which travels approximately 186,000 miles per second (3 x 108 m/s).

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Light radiates from its source in all directions until it is absorbed or diverted by some substance (fig. 10-3). The lines drawn from the light source (a light

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bulb in this instance) to any point on one of the transverse waves indicate the direction that the wavefronts are moving. These lines are called light rays. Although single rays of light typically do not exist, light rays shown in illustrations are a convenient method used to show the direction in which light is traveling at any point. A ray of light can be illustrated as a straight line.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Properties of Light

When light waves, which travel in straight lines, encounter any substance, they are either reflected, absorbed, transmitted, or refracted. This is illustrated in Figure 10.4. Those substances that transmit almost all the light waves falling upon them are said to be transparent. A transparent substance is one

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through which you can see clearly. Clear glass is transparent because it transmits light rays without diffusing them (view A of Figure 10.5). There is no substance known that is perfectly transparent, but many substances are nearly so. Substances through which some light rays can pass, but through which

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objects cannot be seen clearly because the rays are diffused, are called translucent (view B of Figure 10.5). The frosted glass of a light bulb and a piece of oiled paper are examples of translucent materials. Those substances that are unable to transmit any light rays are called opaque (view C of Figure

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10.5). Opaque substances either reflect or absorb all the light rays that fall upon them.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.7 Transmission of Light Through Optical Fibres

The transmission of light along optical fibres depends not only on the nature of light, but also on the structure of the optical fibre. Two methods are used to describe how light is transmitted along the optical fibre. The first method, ray theory, uses the concepts of light reflection and refraction. The second

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method, mode theory, treats light as electromagnetic waves. You must first understand the basic optical properties of the materials used to make optical fibres. These properties affect how light is transmitted through the fibre.

Basic Optical-Material Properties

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The basic optical property of a material, relevant to optical fibres, is the index of refraction. The index of refraction (n) measures the speed of light in an optical medium. The index of refraction of a material is the ratio of the speed of light in a vacuum to the speed of light in the material itself. The speed of 8

light (c) in free space (vacuum) is 3 X 10 meters per second (m/s). The speed of light is the frequency (f) of light multiplied by the wavelength of light (A). When light enters the fibre material (an optically dense medium), the light travels slower at a speed (v). Light will always travel slower in the fibre material than in air. The index of refraction is given by:

A light ray is reflected and refracted when it encounters the boundary between two different transparent mediums. For example, Figure 10.9 shows what happens to the light ray when it encounters the interface between glass and air. The index of refraction for glass (n1) is 1.50. The index of refraction for air (n2) is almost 1.00.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Let' s assume the light ray or incident ray is traveling through the glass. When the light ray encounters the glass-air boundary, there are two results. The first result is that part of the ray is reflected back into the glass. The second result is that part of the ray is refracted (bent) as it enters the air. The bending of the light at the glass-air interface is the result of the difference between the index of refractions. Since n1 is greater than n2, the angle of refraction (θ2) will be s law of refraction is used to describe the relationship between the incident and the refracted rays at the greater than the angle of incidence (θ1). Snell' boundary. Snell' s Law is given by:

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As the angle of incidence (θ1) becomes larger, the angle of refraction (θ2) approaches 90 degrees. At this point, no refraction is possible. The light ray is totally reflected back into the glass medium. No light escapes into the air. This condition is called total internal reflection. The angle at which total internal reflection occurs is called the critical angle of incidence. The critical angle of incidence (θc) is shown in Figure 10.10. At any angle of incidence (θ1) greater than the critical angle, light is totally reflected back into the glass medium. The critical angle of incidence is determined by using Snell' s Law. The critical angle is given by:

The condition of total internal reflection is an ideal situation. However, in reality, there is always some light energy that penetrates the boundary. This situation is explained by the mode theory, or the electromagnetic wave theory, of light.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Total Internal Reflection As already stated, on refraction at a denser medium, a beam of light is bent towards the normal and, vice versa. In the diagram below, the ray APB is

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refracted away from the normal. For any rarer medium the angle of refraction is always greater than the angle of incidence. By increasing the angle of incidence, the angle of refraction will eventually become 90°, as in the case of the ray AP’D. A further increase in the angle of incidence should give an

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angle of refraction greater than 90°, but this is impossible and the ray is reflection at the boundary, remaining within the denser medium, this is ‘total internal reflection’, with none of the light passing through the boundary.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Dispersion Although it has not been stated it has been assumed that the light ray consisted of only one wavelength. Such light is called monochromatic, and is not

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naturally encountered. Most light beams are complex waves that contain a mixture of wavelengths and are thus called polychromatic. As shown in the diagram below, white light can be separated into individual wavelengths by a glass prism through the process of ‘dispersion’. Dispersion is based on the fact that different wavelengths of light travel at different velocities in the same medium. Because different wavelengths have different indexes of refraction, some will be refracted more than others.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.8 Basic Structure of an Optical Fibre

The basic structure of an optical fibre consists of three parts; the core, the cladding, and the coating or buffer. The basic structure of an optical fibre is shown in Figure 10.11. The core is a cylindrical rod of dielectric material. Dielectric material conducts no electricity. Light propagates mainly along the core

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of the fibre. The core is generally made of glass. The core is described as having a radius of (a) and an index of refraction n1. The core is surrounded by a layer of material called the cladding. Even though light will propagate along the fibre core without the layer of cladding material, the cladding does perform some necessary functions.

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The cladding layer is made of a dielectric material with an index of refraction n2. The index of refraction of the cladding material is less than that of the core material. The cladding is generally made of glass or plastic. The cladding performs the following functions: •

Reduces loss of light from the core into the surrounding air

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Reduces scattering loss at the surface of the core

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Protects the fibre from absorbing surface contaminants

•

Adds mechanical strength

For extra protection, the cladding is enclosed in an additional layer called the coating or buffer. The coating or buffer is a layer of material used to protect an optical fibre from physical damage. The material used for a buffer is a type of plastic. The buffer is elastic in nature and prevents abrasions. The buffer also prevents the optical fibre from scattering losses caused by microbends. Microbends occur when an optical fibre is placed on a rough and distorted surface. Microbends are discussed later in this chapter.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.9 Propagation of Light along a Fibre

The concept of light propagation, the transmission of light along an optical fibre, can be described by two theories. According to the first theory, light is described as a simple ray. This theory is the ray theory, or geometrical optics, approach. The advantage of the ray approach is that you get a clearer

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picture of the propagation of light along a fibre. The ray theory is used to approximate the light acceptance and guiding properties of optical fibres. According to the second theory, light is described as an electromagnetic wave. This theory is the mode theory, or wave representation, approach. The

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mode theory describes the behaviour of light within an optical fibre. The mode theory is useful in describing the optical fibre properties of absorption, attenuation, and dispersion. These fibre properties are discussed later in this chapter.

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5.10.9.1 Ray Theory

Two types of rays can propagate along an optical fibre. The first type is called meridional rays. Meridional rays are rays that pass through the axis of the optical fibre. Meridional rays are used to illustrate the basic transmission properties of optical fibres. The second type is called skew rays. Skew rays are rays that travel through an optical fibre without passing through its axis.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Meridional Rays

Meridional rays can be classified as bound or unbound rays. Bound rays remain in the core and propagate along the axis of the fibre. Bound rays propagate through the fibre by total internal reflection. Unbound rays are refracted out of the fibre core. The core of the step-index fibre has an index of

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refraction n1. The cladding of a step-index has an index of refraction n2 that is lower than n1. Figure 10.12 assumes the core-cladding interface is perfect. However, imperfections at the core-cladding interface will cause part of the bound rays to be refracted out of the core into the cladding. The light rays

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refracted into the cladding will eventually escape from the fibre. In general, meridional rays follow the laws of reflection and refraction

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It is known that bound rays propagate in fibres due to total internal reflection, but how do these light rays enter the fibre? Rays that enter the fibre must intersect the core-cladding interface at an angle greater than the critical angle (θc). Only those rays that enter the fibre and strike the interface at these angles will propagate along the fibre.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) How a light ray is launched into a fibre is shown in Figure 10.13. The incident ray I1 enters the fibre at the angle θa. I1 is refracted upon entering the fibre and is transmitted to the corecladding interface. The ray then strikes the core-cladding interface at the critical angle (θc). I1 is totally reflected back into the core and continues to propagate along the fibre. The incident ray I2 enters the fibre at an angle greater than θa. Again, I2 is refracted upon entering the fibre and is transmitted to the core-cladding interface. I2 strikes the core-cladding interface at an angle less than the critical angle (θc). I2 is refracted into the

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cladding and is eventually lost. The light ray incident on the fibre core must be within the cone of acceptance defined by the angle θa shown in figure 10.13.

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Angle θa is defined as the acceptance angle. The acceptance angle (θa) is the maximum angle to the axis of the fibre that light entering the fibre is propagated. The value of the angle of acceptance (θa) depends on fibre properties and transmission conditions.

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The acceptance angle is related to the refractive indices of the core, cladding, and medium surrounding the fibre. This relationship is called the numerical aperture of the fibre. The numerical aperture (NA) is a measurement of the ability of an optical fibre to capture light. The NA is also used to define the cone of acceptance of an optical fibre. Figure 10.14 illustrates the relationship between the acceptance angle and the refractive indices. The index of refraction of the fibre core is n1. The index of refraction of the fibre cladding is n2. The index of refraction of the surrounding medium is no. By using Snell' s law and basic trigonometric relationships, the NA of the fibre is given by:

Since the medium next to the fibre at the launching point is normally air, no is equal to 1.00. The NA is then simply equal to sin θa. The NA is a convenient way to measure the light-gathering ability of an optical fibre. It is used to measure source-to-fibre power-coupling efficiencies. A high NA indicates a high source-to-fibre coupling efficiency. Typical values of NA range from 0.20 to 0.29 for glass fibres. Plastic fibres generally have a higher NA. An NA for plastic fibres can be higher than 0.50. In addition, the NA is commonly used to specify multimode fibres.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) However, for small core diameters, such as in single mode fibres, the ray theory breaks down. Ray theory describes only the direction a plane wave takes in a fibre. Ray theory eliminates any properties of the plane wave that interfere with the transmission of light along a fibre. In reality, plane waves interfere with each other. Therefore, only certain types of rays are able to propagate in an optical fibre. Optical fibres can support only a specific number of guided modes. In small core fibres, the number of modes supported is one or only a few modes. Mode theory is used to describe the types of plane waves able to propagate along an optical fibre.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Skew Rays

A possible path of propagation of skew rays is shown in Figure 10.15, view A, provides an angled view and view B provides a front view. Skew rays propagate without passing through the centre axis of the fibre. The acceptance angle for skew rays is larger than the acceptance angle of meridional rays.

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This condition explains why skew rays outnumber meridional rays. Skew rays are often used in the calculation of light acceptance in an optical fibre. The addition of skew rays increases the amount of light capacity of a fibre. In large NA fibres, the increase may be significant.

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The addition of skew rays also increases the amount of loss in a fibre. Skew rays tend to propagate near the edge of the fibre core. Large portions of the

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number of skew rays that are trapped in the fibre core are considered to be leaky rays. Leaky rays are predicted to be totally reflected at the core-cladding boundary. However, these rays are partially refracted because of the curved nature of the fibre boundary. Mode theory is also used to describe this type of leaky ray loss.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.9.2 Mode Theory

The mode theory, along with the ray theory, is used to describe the propagation of light along an optical fibre. The mode theory is used to describe the properties of light that ray theory is unable to explain. The mode theory uses electromagnetic wave behaviour to describe the propagation of light along a fibre. A set of guided electromagnetic waves is called the modes of the fibre.

Plane Waves

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The mode theory suggests that a light wave can be represented as a plane wave. A plane wave is described by its direction, amplitude, and wavelength of propagation. A plane wave is a wave whose surfaces of constant phase are infinite parallel planes normal to the direction of propagation. The planes having the same phase are called the wavefronts. The wavelength ( ) of the plane wave is given by:

where c is the speed of light in a vacuum, f is the frequency of the light, and n is the index of refraction of the plane-wave medium.

Figure 10.16 shows the direction and wavefronts of plane-wave propagation. Plane waves, or wavefronts, propagate along the fibre similar to light rays. However, not all wavefronts incident on the fibre at angles less than or equal to the critical angle of light acceptance propagate along the fibre. Wavefronts may undergo a change in phase that prevents the successful transfer of light along the fibre.

Wavefronts are required to remain in phase for light to be transmitted along the fibre. Consider the wavefronts incident on the core of an optical fibre as shown in Figure 10.16. Only those wavefronts incident on the fibre at angles less than or equal to the critical angle may propagate along the fibre.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) The wavefront undergoes a gradual phase change as it travels down the fibre. Phase changes also occur when the wavefront is reflected. The wavefront must remain in phase after the wavefront transverses the fibre twice and is reflected twice. The distance transversed is shown between point A and point B on Figure 10.17. The reflected waves at point A and point B are in phase if the total amount of phase collected is an integer multiple of 2

radian. If

propagating wavefronts are not in phase, they eventually disappear. Wavefronts disappear because of destructive interference. The wavefronts that are

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in phase interfere with the wavefronts that are out of phase. This interference is the reason why only a finite number of modes can propagate along the fibre.

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The plane waves repeat as they travel along the fibre axis. The direction the plane waves travel is assumed to be the z direction as shown in Figure 10.17.

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The plane waves repeat at a distance equal to

/ sin θ. Plane waves also repeat at a periodic frequency:

=2 sin θ /

The quantity

defined as the propagation constant along the fibre axis. As the wavelength ( ) changes, the value of the propagation constant must also

change. For a given mode, a change in wavelength can prevent the mode from propagating along the fibre. The mode is no longer bound to the fibre. The mode is said to be cut off. Modes that are bound at one wavelength may not exist at longer wavelengths. The wavelength at which a mode ceases to be bound is called the cut-off wavelength for that mode. However, an optical fibre is always able to propagate at least one mode. This mode is referred to as the fundamental mode of the fibre. The fundamental mode can never be cut off.

The wavelength that prevents the next higher mode from propagating is called the cut-off wavelength of the fibre. An optical fibre that operates above the cut-off wavelength (at a longer wavelength) is called a single mode fibre. An optical fibre that operates below the cut-off wavelength is called a multimode fibre. Single mode and multimode optical fibres are discussed later in this chapter. In a fibre, the propagation constant of a plane wave is a function of the wave' s wavelength and mode. The change in the propagation constant for different waves is called dispersion. The change in the propagation constant for different wavelengths is called chromatic dispersion. The change in propagation constant for different modes is called modal dispersion.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) These dispersions cause the light pulse to spread as it goes down the fibre (fig. 10-18). Some dispersion occurs in all types of fibres. Dispersion is discussed later in this chapter.

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) 5.10.10 Fibre Types There are two main fibre types: •

Step index (multimode, single mode)

•

Graded index (multimode)

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5.10.10.1 Step Index Fibre

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Step index fibre is so called because the refractive index of the fibre ‘steps’ up as we move from the cladding to the core of the fibre. Within the cladding the refractive index is constant, and within the core of the refractive index is constant.

Figure 19

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PART 66 CAT B1.1/B2 MODULE 5 DIGITAL TECHNIQUES ELECTRONIC INSTRUMENT SYSTEMS FIBRE OPTICS (DCAM 5.10 L2) Single Mode Fibres

The core size of single mode fibres is small. The core size (diameter) is typically around 8 to 10 micrometers (µm). A fibre core of this size allows only the fundamental or lowest order mode to propagate around a 1300 nanometer (nm) wavelength. Single mode fibres propagate only one mode, because the

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core size approaches the operational wavelength ( ). The value of the normalized frequency parameter (V) relates core size with mode propagation.

In single mode fibres, V is less than or equal to 2.405. When V < 2.405, single mode fibres propagate the fundamental mode down the fibre core, while

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high-order modes are lost in the cladding. For low V values (