E6430_QAL81 la-7782p
March 31, 2017 | Author: Vincent Ton | Category: N/A
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Description
A
B
C
D
E
COMPAL CONFIDENTIAL 1
MODEL NAME : QAL81 LA-7782P (DAA00002J00) PCB NO : BOM P/N : TBD
1
GPIO MAP: E4_VC_GPIO_map_rev_0.8
Dalmore 14 DSC
2
2
Ivy Bridge + Panther POINT
m o c . x i f n a ub
2011-05-12
h z . w w w / / : p
REV : 0.1 (X00) @ : Nopop Component CONN@ : Connector Component
htt
3
MB Type
3
BOM P/N
TPM
1@
3@
TCM
2@
4@
TPM DIS/TCM DIS
2@
3@
4
4
MB PCB Part Number
Description
DAA00002J00
PCB 0LE LA-7782P REV0 M/B DSC
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
www.vinafix.vn C
Title
Cover Sheet Size
Rev 0.1
LA-7782 Date:
D
Document Number Tuesday, May 24, 2011
Sheet E
1
of
66
A
B
C
D
E
Block Diagram Compal confidential Memory BUS (DDR3) 1
iLVDS
LVDS Switch MAX14979
LVDS CONN PAGE 23
Ivy Bridge
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 PAGE 12-13 1
PAGE 22
rPGA CPU
dLVDS
HDMI CONN PAGE 26
DDRIII-DIMM X2
1333/1600 MHz
Touch Screen
Nvidia N13M
DPE
PS8171 PAGE 26
PAGE 23
988 pins
PEG Gen3
BT 4.0
PAGE 41
PAGE 6-11
DPC DPD VGA
DOCKING PORT PAGE 38
PAGE 44-51
USB2.0 [3,8]
DMI2
Lane x 8
Lane x 4
dVGA iVGA
Video Switch MAX14885E
DAI
CRT CONN
Camera
FDI
INTEL
SATA Repeater PS8513B
SATA
USB
Trough LVDS Cable
E-SATA
PAGE 37
PAGE 24
SATA5
USB 2.0 Port
Panther Point-M
DOCK LAN USB3.0 [4]
PAGE 37
On IO board
USB3.0
iLVDS
USB3.0/2.0
BGA
PAGE 36
2
PI5USB1457A USB Power Share PAGE 36
PAGE 14-21
EXPRESS Card
PCIE2
m o c . x i f n a ub PCI Express BUS 100MHz
1/2 Mini Card PP
PAGE 35
PAGE 34
USB10
USB6
PAGE 34
USB4
3
CPU XDP Port PCH XDP Port
RFID
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
LPC BUS
China TCM1.2 SSX44B
PAGE 34
33MHz
PAGE 29
PAGE 29 3
HeadPhone & MIC Jack
MDC
HDD
PAGE 14
32M 4K sector
on IO board DAI
Fingerprint CONN
FP_USB
PCIE4
USH Module
E-Module
Dig. MIC
RJ11 on IO board
SMSC SIO ECE5048
Trough LVDS Cable
BC BUS FFS LNG3DM PAGE 27
PAGE 39
SMSC KBC MEC5055
4
Thermal
PWM FAN
GUARDIAN III EMC4022
4
PAGE 40
PAGE 22
Discrete TPM AT97SC3204
DELL CONFIDENTIAL/PROPRIETARY PAGE 32
Compal Electronics, Inc.
PAGE 22
TP CONN B
KB CONN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn PAGE 41
A
To Docking side
USB7
PAGE 28
Power On/Off SW & LED
RJ45
PAGE 27
WiFi ON/OFF DC/DC Interface
INT.Speaker
PAGE 27
W25Q32BVSSIG
USH BCM5882
TDA8034HN
LAN SWITCH PI3L720 PAGE 31
PAGE 14
64M 4K sector
USB5
PAGE 31
DOCK LAN
HDA Codec 92HD93
SATA Repeater PS8520B
W25Q64CVSSIG
PAGE 32
htt
Smart Card
SPI
h z . w w w / / : p
1/2 Mini Card Full Mini Card WLAN WWAN
Intel Lewisville 82579LM
HD Audio I/F
Option
PCIE1
on IO board
USB Port
PAGE 33
PCI Express BUS 100MHz PCIE5
PAGE 36
PCIE x1
OZ600FJ0
PAGE 33
PCIE3
USB3.0/2.0+PS
Card Reader
SDXC/MMC
2
USB3.0
PAGE 41
C
Title
DIS Block Diagram Size
Rev 0.1
LA-7782 Date:
D
Document Number Monday, May 30, 2011
Sheet E
2
of
66
5
4
3
2
1
POWER STATES USB PORT# Signal
SLP S3#
SLP S4#
SLP S5#
SLP A#
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
S4 (Suspend to DISK) / M3
LOW
LOW
S5 (SOFT OFF) / M3
LOW
S3 (Suspend to RAM) / M-OFF
LOW
State
D
ALWAYS PLANE
M PLANE
SUS PLANE
RUN PLANE
ON
ON
ON
ON
HIGH
ON
ON
ON
HIGH
HIGH
ON
ON
LOW
LOW
HIGH
ON
HIGH
HIGH
LOW
ON
DESTINATION
CLOCKS
0
JUSB1 (Right side Top)
ON
1
JUSB2 (Right side Bottom)
OFF
OFF
2
JESA1 (Right side ESATA)
OFF
OFF
OFF
3
MLK DOCK
ON
OFF
OFF
OFF
4
WLAN
OFF
ON
OFF
OFF
5
WWAN
6
JMINI3(Flash)
7
USH->BIO
8
DOCKING
9
JUSB (Left side)
10
Express card
11
Bluetooth
12
Camera
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
PCH
D
PM TABLE C
power plane
+15V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+5V_ALW
+1.5V_MEM
+3.3V_RUN
+1.05V_M +1.05V_M
+3.3V_ALW_PCH
+1.8V_RUN
+3.3V_RTC_LDO
+1.5V_RUN
+3.3V_M (M-OFF)
+0.75V_DDR_VTT
SATA
DESTINATION
SATA 0
HDD
SATA 1
ODD/ E3 Module Bay
SATA 2
NA
SATA 3
NA
SATA 4
ESATA
+VCC_CORE +1.05V_RUN_VTT
S0
B
m o c . x i f n a ub
+1.05V_RUN
State
ON
ON
ON
ON
ON
h z . w w w / / : p
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
htt
OFF
SATA 5
Dock
need to update Power Status and PM Table
USH
13
LCD Touch
0
BIO
1
NA
PCI EXPRESS
DESTINATION
B
Lane 1
MINI CARD-1 WWAN
Lane 2
MINI CARD-2 WLAN
Lane 3
Express card
Lane 4
E3 Module Bay (USB3)
Connetion
Lane 5
1/2vMINI CARD-3 PCIE
Port C
Dock DP port 2
Lane 6
MMI
Port D
Dock DP port 1
Lane 7
10/100/1G LOM
Port E
MB HDMI Conn
Lane 8
None
DSC DP/HDMI Port
A
C
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
Title
Index and Config. Size
Rev 0.1
LA-7782 Date:
2
Document Number Friday, May 20, 2011
Sheet 1
3
of
66
3
EN_INVPWR
FDC654P (Q21)
+BL_PWR_SRC
ISL62883 (PU1000)
+GPU_CORE
2
1
MODC_EN
4
HDDC_EN
5
SI3456BDV (Q27)
SI3456BDV (Q30)
+5V_HDD
+5V_MOD
MCARD_MISC_PWREN
DGPU_PWR_EN
+PWR_SRC BATTERY
+VCC_CORE 1.05V_0.8V_PWROK
MCARD_WWAN_PWREN
ADAPTER D
SI3456 (Q42)
VT1318M (PU700)
D
SI3456 (Q40)
+VCC_GFXCORE ALWON
CHARGER
+3.3V_FLASH RT8205 (PU100)
C
+3.3V_WWAN
+5V_ALW
C
CPU1.5V_S3_GATE
AO4728 (QC3)
SIO_SLP_S3#
SIO_SLP_A#
+1.05V_M
NTGS4141N (Q59)
+1.8V_RUN
TPS51461 (PU600)
+VCC_SA
SI3456 (Q38)
+3.3V_WLAN
SI3456 (Q49)
S13456 (Q54)
+1.5V_CPU_VDDQ
+1.5V_RUN
SIO_SLP_A#
SIO_SLP_S3#
SIO_SLP_S3#
SI3456 (Q34)
TPS22966 (U78)
SI3456 (Q58) B
+3.3V_ALW_PCH
+3.3V_SUS
+3.3V_LAN
+3.3V_M
Pop option Pop option
+1.0V_LAN
+3.3V_M
SI4164 (Q63)
A
AUX_ON
SUS_ON
PCH_ALW_ON
h z . w w w / / : p SY8033 (PU300)
htt
+1.05V_RUN_VTT
m o c . x i f n a ub AUX_EN_WOWL
(PU400)
1.05V_VTTPWRGD
(PU500)
SIO_SLP_S3#
+1.5V_MEM
TPS51212
CPU_VTT_ON
B
0.75V_DDR_VTT_ON
DDR_ON
RT8207 (PU200)
TPS51212
SIO_SLP_S3#
+3.3V_ALW
+3.3V_RUN
+5V_RUN
+0.75V_DDR_VTT
A
DELL CONFIDENTIAL/PROPRIETARY
+1.05V_RUN
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
Title
Power Rail Size
Rev 0.1
LA-7782 Date:
2
Document Number Friday, May 20, 2011
Sheet 1
4
of
66
5
4
3
2
1
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K H14
MEM_SMBCLK
C9
MEM_SMBDATA
202
2N7002
200
DIMMA
SMBUS Address [A0]
DIMMB
SMBUS Address [A4]
2N7002 2.2K
202
PCH D
+3.3V_LAN
2.2K C8 G12 M16
28
LAN_SMBDATA
31
200
53
SML1_SMBCLK A5
D
SMBUS Address [C8]
LOM
E14 SML1_SMBDATA
3A
LAN_SMBCLK
2.2K
53
3A
2.2K B4
DOCK_SMB_CLK
A3
DOCK_SMB_DAT
+3.3V_ALW
SMBUS Address 127 129
DOCKING
2.2K C
2.2K
XDP2
51
2.2K
1A
SMBUS Address [TBD]
+3.3V_ALW_PCH
B6
1A
XDP1
51
2.2K
SMBUS Address [TBD]
10K
APR_EC: 0x48 SPR_EC: 0x70 MSLICE_EC: 0x72 USB: 0x59 AUDIO: 0x34 SLICE_BATTERY: 0x17 SLICE_CHARGER: 0x13
+3.3V_RUN
10K 4
G Sensor
6
SMBUS Address [0x3B] C
+3.3V_ALW 30
1B 1B
B5
LCD_SMBCLK
A4
LCD_SMDATA
WWAN
32
SMBUS Address [TBD]
2.2K
KBC
2.2K 1C 1C
A56 B59
PBAT_SMBCLK PBAT_SMBDAT
100 ohm
7
100 ohm
6
BATTERY CONN
SMBUS Address [0x16]
2.2K
h z . w w w / / : p 2.2K
USH_SMBCLK
1E
B53
USH_SMBDAT
htt
B
MEC 5065
+3.3V_ALW
M9
1E
A50
2B
A49
CARD_SMBCLK
2B
B52
CARD_SMBDAT
m o c . x i f n a ub
+3.3V_ALW
L9
USH
SMBUS Address [0xa4]
B
2.2K
2.2K
+3.3V_SUS
7 8
Express card
SMBUS Address [TBD]
2.2K 2.2K CHARGER_SMBCLK
9
A47
CHARGER_SMBDAT
8
1G 1G
+3.3V_ALW
B50
Charger
SMBUS Address [0x12]
2.2K 2.2K
A
2D
B7
BAY_SMBDAT
2D
A7
BAY_SMBCLK
+3.3V_ALW 29 30
E3 Module Bay
SMBUS Address [0xd2]
A
2.2K 2.2K 2A 2A
5
+3.3V_RUN
B49
GPU_SMBCLK
T4
B48
GPU_SMBDAT
T3
4
Compal Electronics, Inc. GPU
www.vinafix.vn 3
Title
SMBUS Address [0xXX]
SMBUS TOPOLOGY Size
Document Number
Rev 0.1
LA-7782 Date: 2
Friday, May 20, 2011
Sheet 1
5
of
66
5
4
3
2
1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. (2)PEG_ICOMPO use 12mil connect to RC2
JCPU1I
1
+1.05V_RUN_VTT
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
B28 B26 A24 B23
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
G21 E22 F21 D21
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
G22 D22 F20 C21
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
A21 H19 E19 F18 B21 C20 D18 E17
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
A22 G19 E20 G18 B20 C19 D19 F17
FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]
FDI_FSYNC0 FDI_FSYNC1
J18 J17
FDI0_FSYNC FDI1_FSYNC
FDI_INT
H20
FDI_LSYNC0 FDI_LSYNC1
J19 H17
FDI0_LSYNC FDI1_LSYNC
A18 A17 B16
eDP_COMPIO eDP_ICOMPO eDP_HPD#
FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1
FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]
PCI EXPRESS* - GRAPHICS
B27 B25 A25 B24
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
FDI_INT
(1) EDP_COMPIO use 4mil trace to RC1 (2) EDP_ICOMPO use 12mil to RC1 EDP_COMP
C15 D15
C18 E16 D16 F15
PEG_COMP
K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32
PEG_CRX_GTX_N0 PEG_CRX_GTX_N1 PEG_CRX_GTX_N2 PEG_CRX_GTX_N3 PEG_CRX_GTX_N4 PEG_CRX_GTX_N5 PEG_CRX_GTX_N6 PEG_CRX_GTX_N7 PEG_CRX_GTX_N8 PEG_CRX_GTX_N9 PEG_CRX_GTX_N10 PEG_CRX_GTX_N11 PEG_CRX_GTX_N12 PEG_CRX_GTX_N13 PEG_CRX_GTX_N14 PEG_CRX_GTX_N15
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32
PEG_CRX_GTX_P0 PEG_CRX_GTX_P1 PEG_CRX_GTX_P2 PEG_CRX_GTX_P3 PEG_CRX_GTX_P4 PEG_CRX_GTX_P5 PEG_CRX_GTX_P6 PEG_CRX_GTX_P7 PEG_CRX_GTX_P8 PEG_CRX_GTX_P9 PEG_CRX_GTX_P10 PEG_CRX_GTX_P11 PEG_CRX_GTX_P12 PEG_CRX_GTX_P13 PEG_CRX_GTX_P14 PEG_CRX_GTX_P15
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25
PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_N9 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_N12 PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_N15
M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25
PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_P11 PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_P13 PEG_CTX_GRX_C_P14 PEG_CTX_GRX_C_P15
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
PEG_CRX_GTX_N[0..15]
PEG_CRX_GTX_P[0..15]
eDP
eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_N0
CC1 CC2
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P0 PEG_CTX_GRX_N0
PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N1
CC3 CC4
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P1 PEG_CTX_GRX_N1
PEG_CTX_GRX_C_P2 PEG_CTX_GRX_C_N2
CC5 CC6
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P2 PEG_CTX_GRX_N2
PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_N3
CC7 CC8
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P3 PEG_CTX_GRX_N3
PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N4
CC9 2 CC10 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P4 PEG_CTX_GRX_N4
PEG_CTX_GRX_C_P5 PEG_CTX_GRX_C_N5
CC11 2 CC12 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P5 PEG_CTX_GRX_N5
PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_N6
CC13 2 CC14 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P6 PEG_CTX_GRX_N6
PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N7
CC15 2 CC16 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CTX_GRX_P7 PEG_CTX_GRX_N7
PEG_CTX_GRX_C_P8 PEG_CTX_GRX_C_N8
CC17 1 CC18 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P8 PEG_CTX_GRX_N8
PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_N9
VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233
VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285
VSS
m o c . x i f n a ub
h z . w w
w / / : p htt
eDP_AUX eDP_AUX#
B
C17 F16 C16 G15
J22 J21 H22
PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO
Intel(R) FDI
C
JCPU1A
2
RC2 24.9_0402_1%~D D
T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29
CC19 1 CC20 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P9 PEG_CTX_GRX_N9
PEG_CTX_GRX_C_P10 CC21 1 PEG_CTX_GRX_C_N10 CC22 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P10 PEG_CTX_GRX_N10
PEG_CTX_GRX_C_P11 CC23 1 PEG_CTX_GRX_C_N11 CC24 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P11 PEG_CTX_GRX_N11
PEG_CTX_GRX_C_P12 CC25 1 PEG_CTX_GRX_C_N12 CC26 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P12 PEG_CTX_GRX_N12
PEG_CTX_GRX_C_P13 CC27 1 PEG_CTX_GRX_C_N13 CC28 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P13 PEG_CTX_GRX_N13
PEG_CTX_GRX_C_P14 CC29 1 PEG_CTX_GRX_C_N14 CC30 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P14 PEG_CTX_GRX_N14
PEG_CTX_GRX_C_P15 CC31 1 PEG_CTX_GRX_C_N15 CC32 1
2 0.22U_0402_16V7K~D 2 0.22U_0402_16V7K~D
PEG_CTX_GRX_P15 PEG_CTX_GRX_N15
F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3
D
C
B
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
DP Compensation
1
+1.05V_RUN_VTT
RC1 24.9_0402_1%~D A
2
A
EDP_COMP
DELL CONFIDENTIAL/PROPRIETARY
eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance GPU
Channel B --> PCH
1
MAX14885E
GPU_CRT_RED PCH_CRT_RED
7 17
GPU_CRT_GRN PCH_CRT_GRN
8 18
GPU_CRT_BLU PCH_CRT_BLU
9 19
BLUA BLUB
GPU_CRT_CLK_DDC PCH_CRT_DDC_CLK
5 15
SCLA SCLB
GPU_CRT_DAT_DDC PCH_CRT_DDC_DAT
6 16
+3.3V_RUN
1 R416
2 CRT_EN 100K_0402_5%~D
GRNA GRNB
VL
RED1 RED2 GRN1 GRN2
SDAA SDAB
21
33 24
SCL1 SCL2 SDA1 SDA2
34 25
1 40 39 38
S00 S01 S10 S11
SH1 SH2
37 28
30 20 10
GND GND GND
41
SV1 SV2 NC
RED_CRT RED_DOCK
32 23
SVA SVB
4 14
EN
2
2
C1181 1U_0402_6.3V6K~D
B
11
SHA SHB
GPU_CRT_VSYNC PCH_CRT_VSYNC
CRT_SWITCH
VCC
1 C1182 1U_0603_10V7K~D
29
35 26
GPU_CRT_HSYNC PCH_CRT_HSYNC
CRT_SWITCH
VCC
31 22
3 13
EDID_SELECT# CRT_SWITCH DGPU_SELECT#
REDA REDB
BLU1 BLU2
2
+3.3V_RUN
GREEN_CRT GREEN_DOCK BLUE_CRT BLUE_DOCK
Port 1 --> MB Port RGB
CLK_DDC2_CRT CLK_DDC2_DOCK
Port 2 --> Docking Port RGB
DAT_DDC2_CRT DAT_DDC2_DOCK HSYNC_BUF HSYNC_DOCK
36 27
VSYNC_BUF VSYNC_DOCK
12
GPAD MAX14885EETL+T_TQFN40_5X5~D
CRT_SWITCH
0
0
1
1
DGPU_SELECT#
0
1
0
1
EDID_SELECT#
0
1
0
1
A --> Port 1
B --> Port 1
A --> Port 2
B --> Port 2
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
www.vinafix.vn
CRT/Video switch Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 1
Sheet
25
of
66
2
1
1
NC
2 3
+5V_RUN
D4 BAT1000-7-F_SOT23-3~D +5V_RUN_HDMI
R475 1
+3.3V_RUN_HDMI
2 4.7K_0402_5%~D
HDMI_APD HDMI_EMI0 HDMI_EMI1
+3.3V_RUN_HDMI
HDMI_PEQ 1
1
2
2 1 3
HDMI_OE# D
S
HDMI_HPD_SINK 2 G
1
2
C358 2.2U_0603_6.3V6K~D
R467 499_0402_1%~D
R443 4.7K_0402_5%~D
HDMI_PRE
25
29 28 4 1 12 11 27 33 6 3 10 35
2 15 21 26 40 46 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6
22 23 19 20 16 17 13 14
HPDX
7
2 1
2 1
2 2 1.5K_0402_5%~D HDMI_SDA_SINK 2 1.5K_0402_5%~D HDMI_SCL_SINK HDMI_PIO
R460 1 R461 1
+5V_HDMI_DDC
32 34
OUT1p OUT1n OUT2p OUT2n OUT3p OUT3n OUT4p OUT4n
2
@
2
HDMI_HPD_SINK
R1164 10K_0402_5%~D 1 2 HDMI_HPD_SINK_R HDMI_SDA_SINK HDMI_SCL_SINK HDMI_CEC TMDSE_CON_CLK# TMDSE_CON_CLK TMDSE_CON_N0 TMDSE_CON_P0 TMDSE_CON_N1
TMDSE_RP_P2 TMDSE_RP_N2 TMDSE_RP_P1 TMDSE_RP_N1 TMDSE_RP_P0 TMDSE_RP_N0 TMDSE_RP_CLK TMDSE_RP_CLK#
TMDSE_CON_P1 TMDSE_CON_N2 TMDSE_CON_P2
OE#
SDA SCL
SDA_SINK SCL_SINK PIO ASQ0 ASQ1 APD EMI0 EMI1 REXT PEQ CEXT PRE
8 9
1 @ R451 L19
DPE_GPU_HPD
TMDS_E_GPU_DDC# TMDS_E_GPU_DDC
@ R476
4
4
3
3
TMDSE_CON_CLK#
TMDSE_RP_CLK
1
1
2
2
TMDSE_CON_CLK
1 @ R462 L20
PS8171QFN48G_QFN48_7X7
TMDSE_RP_N0
4
TMDSE_RP_P0
1
+3.3V_RUN_HDMI
1
2
1
2
@ R478
2 4.7K_0402_5%~D
HDMI_APD 4.7K_0402_5%~D @R479 @ R479 1
A
+3.3V_RUN_HDMI
@ R480
2 4.7K_0402_5%~D
HDMI_EMI0 4.7K_0402_5%~D @R481 @ R481 1
1
HDMI_EMI1
2
@ R482
2 4.7K_0402_5%~D
4.7K_0402_5%~D @R483 @ R483 1
TMDSE_RP_N1
4
TMDSE_RP_P1
HIGH DDCBUF (Active Buffer) Setting1 PIO (HPD setting) HPD=HPD_SINK# APD (Auto power down) Enable PEQ (level of EQ) High level PRE (pre-emphasis) Low level
LOW No HPD=HPD_SINK Disable Mid level No
MID Setting2
1
4
3
1
2
1
TMDSE_RP_N2
2 4.7K_0402_5%~D
4.7K_0402_5%~D @R485 @ R485 1
+3.3V_RUN_HDMI
1 @ R486
TMDSE_CON_N0
2
TMDSE_CON_P0
2 0_0402_5%~D
4
3
1
2
3
TMDSE_CON_N1
2
TMDSE_CON_P1
A
Low level High level
HDMI_PEQ
2
@ R484
3
DLW21SN900HQ2L_0805_4P~D 1 2 @ R469 0_0402_5%~D
TMDSE_RP_P2 +3.3V_RUN_HDMI
2 0_0402_5%~D
DLW21SN900HQ2L_0805_4P~D 1 2 @ R466 0_0402_5%~D
4.7K_0402_5%~D @R477 @ R477 1
20 21 22 23
2 0_0402_5%~D
TMDSE_RP_CLK#
1 @ R468 L21 +3.3V_RUN_HDMI
B
DLW21SN900HQ2L_0805_4P~D 1 2 @ R459 0_0402_5%~D
HDMI_PIO
2
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ GND D2GND D2_shield GND D2+ GND
DDC_EN DDCBUF
Q25 SSM3K7002FU_SC70-3~D
1
JHDMI1 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TYCO_2041270-1 CONN@
HPD_SINK
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
2 4.7K_0402_5%~D 2 4.7K_0402_5%~D 1 4.7K_0402_5%~D HDMI_OE#
30
IN1p IN1n IN2p IN2n IN3p IN3n IN4p IN4n
1
5 18 24 31 36 37 43 49
2
R472 1 @ R473 1 @ R474 2
+3.3V_RUN_HDMI +3.3V_RUN_HDMI
@
1
1 2
HDMI_HPD_SINK
39 38 42 41 45 44 48 47
2
@
2
1
C338 10U_0805_10V6K~D
TMDSE_GPU_C_P2 TMDSE_GPU_C_N2 TMDSE_GPU_C_P1 TMDSE_GPU_C_N1 TMDSE_GPU_C_P0 TMDSE_GPU_C_N0 TMDSE_GPU_C_CLK TMDSE_GPU_C_CLK#
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
1
C344 0.1U_0402_25V6K~D
1 1 1 1 1 1 1 1
2
@
C342 0.1U_0402_25V6K~D
R1168 0_0402_5%~D
D70 RB751V-40GTE-17_SOD323-2~D
+5V_RUN
TMDSE_GPU_P2 TMDSE_GPU_N2 TMDSE_GPU_P1 TMDSE_GPU_N1 TMDSE_GPU_P0 TMDSE_GPU_N0 TMDSE_GPU_CLK TMDSE_GPU_CLK#
2 2 2 2 2 2 2 2
2
1
C340 0.1U_0402_25V6K~D
C346 C347 C348 C349 C350 C351 C352 C353
2
1
C355 0.1U_0402_25V6K~D
U19 B
C354 0.01U_0402_25V7K~D
1
1
C337 0.1U_0402_10V7K~D
+3.3V_RUN_HDMI
Close to U19 VCC pins
+VDISPLAY_VCC @ R5 0_1206_5%~D
PJP54@ PAD-OPEN1x1m
F2 0.5A_15V_SMD1812P050TF
1
+3.3V_RUN
1 @ R470 L22 4 4 1
1
2 0_0402_5%~D 3 2
3
TMDSE_CON_N2
2
TMDSE_CON_P2
DLW21SN900HQ2L_0805_4P~D 1 2 @ R471 0_0402_5%~D
2 4.7K_0402_5%~D
HDMI_PRE
2 4.7K_0402_5%~D
@R487 @ R487 1
2 4.7K_0402_5%~D
+3.3V_RUN_HDMI
HDMI_CEC
2 R1165
DPE_GPU_HPD
1 R1128
DELL CONFIDENTIAL/PROPRIETARY
1 10K_0402_5%~D
Compal Electronics, Inc.
2 100K_0402_5%~D
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
www.vinafix.vn
HDMI port Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 1
Sheet
26
of
66
5
4
3
2
1
+3.3V_RUN
AUX/DDC GPU for DPC to E-DOCK
1
+3.3V_RUN
AUX/DDC GPU for DPD to E-DOCK
2
1
C356 0.1U_0402_25V6K~D
D
DPC_GPU_AUX/DDC
C357 0.1U_0402_10V7K~D DPC_GPU_AUX/DDC 2 1 DPC_GPU_AUX_C
DPC_GPU_AUX#/DDC
U20 1 2
DPC_DOCK_AUX
DPC_DOCK_AUX DPC_GPU_AUX#/DDC 2 C360
3
1 DPC_GPU_AUX#_C 0.1U_0402_10V7K~D DPC_DOCK_AUX#
DPC_DOCK_AUX#
2 C366 0.1U_0402_25V6K~D
BE0 A0 B0
A3
4 5
BE1 A1
6
B1
7
VCC BE3
B3 BE2
GND
C367 0.1U_0402_10V7K~D DPD_GPU_AUX/DDC 2 1 DPD_GPU_AUX_C
14 13 DPD_GPU_AUX/DDC
DPC_GPU_AUX/DDC
12
A2
9
B2
8
DPD_DOCK_AUX
DPD_DOCK_AUX
11 10
DPD_GPU_AUX#/DDC 2 C368
DPD_GPU_AUX#/DDC
DPC_GPU_AUX#/DDC
BE0 A0
3
VCC BE3
B0
4 5
1 DPD_GPU_AUX#_C 0.1U_0402_10V7K~D DPD_DOCK_AUX#
DPD_DOCK_AUX#
D
U23 1 2
A3
BE1 A1
6 7
PI3C3125LEX_TSSOP14~D
B3 BE2
B1
A2
GND
B2
14 13 DPD_GPU_AUX/DDC
12 11 10
DPD_GPU_AUX#/DDC
9 8
PI3C3125LEX_TSSOP14~D
+5V_RUN +5V_RUN 1
DPC_CA_DET# DPD_CA_DET
DPD_CA_DET
U21 NC7SZ04P5X-G_SC70-5~D
2
1
A 3
3
5
C369 0.1U_0402_25V6K~D 4
Y
P
A
1
G
5 P
2
G
DPC_CA_DET
NC
C365 0.1U_0402_25V6K~D DPC_CA_DET
1
2
NC
2
Y
4
DPD_CA_DET#
U24 NC7SZ04P5X-G_SC70-5~D
C
C
There is a new die for PI3C3125. Sample availabe on May.
+3.3V_RUN
R1539 2.2K_0402_5%~D
2
1
6 1 1
2 0_0402_5%~D
B
DPD_DOCK_AUX
2
3 4
5 4
4
2
1 @ R1064
R1066 2.2K_0402_5%~D
DPC_DOCK_AUX#
1 @ R1067
Q111B DMN66D0LDW-7_SOT363-6~D
Q113B DMN66D0LDW-7_SOT363-6~D
5
2 0_0402_5%~D
2
+3.3V_RUN
3
1
1
2
DPD_CA_DET
1 @R1523 @ R1523
2
1 2
1 1
5
R1530 2.2K_0402_5%~D
3
3 4
2 R1065 100K_0402_5%~D DPC_DOCK_AUX
6
6
2
1 2 6
R1063 100K_0402_5%~D
C1175 0.01U_0402_16V7K~D
1
+3.3V_ALW2
DMN66D0LDW-7_SOT363-6~D Q109B
+3.3V_RUN
2 0_0402_5%~D
DMN66D0LDW-7_SOT363-6~D Q109A
2
DMN66D0LDW-7_SOT363-6~D Q110A
2
C1174 0.01U_0402_16V7K~D
DPC_CA_DET 1
DMN66D0LDW-7_SOT363-6~D Q110B
5
1 @ R1538
Q111A DMN66D0LDW-7_SOT363-6~D
2
B
R1062 2.2K_0402_5%~D Q113A DMN66D0LDW-7_SOT363-6~D
R1537 100K_0402_5%~D
R1532 100K_0402_5%~D
+5V_RUN
2
1
+3.3V_ALW2
1
1
+3.3V_RUN +5V_RUN
2 0_0402_5%~D
DPD_DOCK_AUX#
A
A
DELL CONFIDENTIAL/PROPRIETARY 1 R491 1 R492
5
DPD_CA_DET 2 1M_0402_5%~D DPC_CA_DET 2 1M_0402_5%~D
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
www.vinafix.vn 3
Title
DP AUX SW Size
Rev 0.1
LA-7782 Date:
2
Document Number Friday, June 10, 2011
Sheet 1
27
of
66
5
4
3
2
1
D
D
1
+3.3V_RUN
PJP53 PAD-OPEN1x1m
2
Free Fall Sensor +3.3V_RUN_FFS
1
2
C388 0.1U_0402_25V6K~D
2
C387 10U_0603_6.3V6M~D
1 C
U88
LNG3DM 1 14
HDD_FALL_INT
HDD_FALL_INT FFS_INT2
11 9
INT 1 INT 2
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK
5 12
GND GND SDO/SA0 SDA / SDI / SDO SCL/SPC NC CS NC
7 6 4 8
C
10 13 15 16
RES RES RES RES
VDD_IO VDD
2 3
HDD PWR
LNG3DMTR_LGA16_3X3~D +5V_ALW
+PWR_SRC_S
JSATA1
@ R506 100K_0402_5%~D
3
2
1 2
4
6
1
2
1
2
C396 0.1U_0402_25V6K~D
1
FFS_INT2_Q C395 1000P_0402_50V7K~D
2
RUN_ON SIO_SLP_S3#
GND1 GND2
1 @ R1621 1 R1624
2 0_0402_5%~D 2 0_0402_5%~D @ R505 100K_0402_5%~D
23 24
2
1 2 5 6
1
2
1
2
+5V_RUN @ PJP3 1 1 2
1
4
3
2
5
+5V_HDD 2
JUMP_43X79
SHORT DEFAULT
B
R504 100K_0402_5%~D 2
3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND Reserved GND 12V 12V 12V
6
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
@ Q27 SI3456DDV-T1-GE3_TSOP6~D
3
+5V_HDD Source
JAE_SP100421-HDD CONN@
Main SATA +5V Default
Pleace near HDD CONN +3.3V_RUN_HDD
2
1
2
C399 0.1U_0402_25V6K~D
1
C402 0.1U_0402_25V6K~D
A
Q29A DMN66D0LDW-7_SOT363-6~D
2
FFS_INT2_Q Q29B DMN66D0LDW-7_SOT363-6~D
5
FFS_INT2
HDD_DET# +5V_HDD
+5V_HDD R508 100K_0402_5%~D
FFS_INT2
+3.3V_RUN_HDD
PAD-OPEN1x1m HDD_DET#
1 +3.3V_RUN
2
4
+5V_HDD
1
PJP64 B
D G HDD_EN_5V
S
1
SATA_PRX_DTX_N0 SATA_PRX_DTX_P0
GND RX+ RXGND TXTX+ GND
2
1
SATA_PTX_DRX_P0 SATA_PTX_DRX_N0
C394 10U_0805_10V6K~D
+3.3V_RUN
1 1 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 1 1 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D
Q28A DMN66D0LDW-7_SOT363-6~D
PSATA_PRX_DTX_N0_C PSATA_PRX_DTX_P0_C
2 C383 2 C384 2 C385 2 C386
PSATA_PTX_DRX_P0_C PSATA_PTX_DRX_N0_C
C393 0.1U_0603_50V7K~D
2 DDR_XDP_WAN_SMBDAT 10K_0402_5%~D 2 DDR_XDP_WAN_SMBCLK 10K_0402_5%~D 2 HDD_FALL_INT 100K_0402_5%~D
R500 100K_0402_5%~D
Q28B DMN66D0LDW-7_SOT363-6~D
1 R501 1 R502 1 R503
1 2 3 4 5 6 7
R499 100K_0402_5%~D
1
+3.3V_RUN
1
+3.3V_ALW2
For HDD Temp.
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
Pleace near HDD CONN
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn 3
2
HDD CONNECTOR Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
28
of
66
5
4
3
2
1
+3.3V_ALW
1 R510
2 ZODD_WAKE# 10K_0402_5%~D
1 R513
2 MOD_MD 10K_0402_5%~D
1 R514
2 USB30_SMI# 100K_0402_5%~D
For ODD
+3.3V_ALW_PCH D
D
+5VMOD Source
0.1U_0402_10V7K~D 2 0.1U_0402_10V7K~D 2
PCIE_PTX_EMBRX_P4 PCIE_PTX_EMBRX_N4
EMBCLK_REQ# PCIE_WAKE# PLTRST_EMB# BAY_SMBDAT BAY_SMBCLK
EMBCLK_REQ# PCIE_WAKE# PLTRST_EMB# BAY_SMBDAT BAY_SMBCLK MOD_SATA_PCIE#_DET
+3.3V_ALW
1 R1183
1 C409 PCIE_PTX_EMBRX_P4_C 1 C408 PCIE_PTX_EMBRX_N4_C
+5V_MOD
2 10K_0402_5%~D
+5V CLKREQ# WAKE# PERST# SMB_DATA SMB_CLK HPD
R512 100K_0402_5%~D
GND1 GND2
2
1 2 5 6 +5V_MOD
1
2
+5V_RUN
1
@ PJP4 1 1 2
2
JUMP_43X79 R511 100K_0402_5%~D
C
+3.3V_ALW B
D
S
3
1
TYCO_2-2129116-3 CONN@
1
SSM3K7002FU_SC70-3~D MOD_MD
S
32 33
Q76
B
SI3456DDV-T1-GE3_TSOP6~D
3
2
25 26 27 28 29 30 31
2
MODC_EN
1
GND REFCLK+ REFCLKGND PETX+ PETXGND GND PERX+ PERXGND
1
14 15 16 17 18 19 20 21 22 23 24
2
PCIE_PRX_EMBTX_P4 PCIE_PRX_EMBTX_N4
1 2
6
MODC_EN# 5
MOD_EN
C401 10U_0805_10V6K~D
Pleace near ODD CONN
CLK_PCIE_EMB CLK_PCIE_EMB#
D Q30 G 2
DP +5V +5V MD GND GND
Q31A DMN66D0LDW-7_SOT363-6~D
2
C398 0.1U_0402_25V6K~D
C
C397 1000P_0402_50V7K~D
2
1
R507 100K_0402_5%~D R509 100K_0402_5%~D
C400 0.1U_0603_50V7K~D
MOD_MD 1
+5V_ALW
Q31B DMN66D0LDW-7_SOT363-6~D
+5V_MOD
8 9 10 11 12 13
+3.3V_ALW2
3
DEVICE_DET#
+5V_MOD
+PWR_SRC_S
GND A+ AGND BB+ GND
4
SATA_ODD_PRX_DTX_N1 SATA_ODD_PRX_DTX_P1
1 2 3 4 5 6 7
1
SATA_ODD_PRX_DTX_N1_C SATA_ODD_PRX_DTX_P1_C
SATA_ODD_PTX_DRX_P1 SATA_ODD_PTX_DRX_N1
2
SATA_ODD_PTX_DRX_P1_C SATA_ODD_PTX_DRX_N1_C
1 1 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 1 1 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D
4
JSATA2
2 C407 2 C406 2 C405 2 C404
ZODD_WAKE#
1
R515 100K_0402_5%~D
ZODD_WAKE# 2
2
G
MODC_EN#
USB30_EN
4
DMN66D0LDW-7_SOT363-6~D USB30_SMI# 3
6
Q123B USB30_SMI#
USB30_EN
Q123A DMN66D0LDW-7_SOT363-6~D
2 1
5
MOD_SATA_PCIE#_DET
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
ODD CONNECTOR Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
29
of
66
2
1
1
2 1
2
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_SYNC
3
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_BITCLK
6
PCH_AZ_CODEC_SDOUT
5 10
PCH_AZ_SDIN0_R 2 33_0402_5%~D PCH_AZ_CODEC_RST#
1 R1096
8 11
DVDD_CORE
AVDD1 AVDD2
DVDD_IO
PVDD PVDD
DVDD
SENSE_A SENSE_B PORTA_L PORTA_R VrefOut_A
BITCLK SDATA_OUT
PORTB_L PORTB_R
SYNC SDATA_IN
PORTD_+L PORTD_-L
RESET# PORTD_+R PORTD_-R
I2S_MCLK
15
I2S_BCLK
16
I2S_DO
1 R1097
2 33_0402_5%~D
17
I2S_LRCLK I2S_DI#
18
Place R1097 close to codec
24
Close to U72 pin6
I2S_MCLK
MONO_OUT
I2S_SCLK
PC_BEEP
I2S_DOUT DMIC_CLK/GPIO 1 DMIC_0/GPIO 2 DMIC1/GPIO0/SPDIFOUT1 SPDIFOUT0//GPIO3/Aux_Out
I2S_LRCLK I2S_DIN
CAP+ PCH_AZ_CODEC_BITCLK
20
AUD_NB_MUTE#
47
2 10K_0402_5%~D
42
MIC_IN_L MIC_IN_R +VREFOUT
31 32
AUD_HP_OUT_L AUD_HP_OUT_R
40 41
INT_SPK_L+ INT_SPK_L-
44 43
INT_SPK_R+ INT_SPK_R-
EAPD
VREFFILT CAP2 VVreg
DVSS PVSS
AVSS1 AVSS AVSS
GND
C1163
2 1U_0402_6.3V6K~D +VREFOUT 1 R1143
+VDDA_AVDD
AUD_PC_BEEP
2 4 46 48
DMIC_CLK_L 1 LE3
1
35
2
1
2
1 +3.3V_RUN
PORT E
20K
PORT B
PORT F
10K
NA
DMIC0
5.11K R1082 100K_0402_5%~D
PORT A
SPDIFOUT0
14 EN_I2S_NB_CODEC#
EN_I2S_NB_CODEC# 1 2 1 15 R1540 1K_0402_1%~D
1Y#
2A
2Y#
3A
3Y#
4A
4Y#
5A
5Y#
6A
6Y#
OE1# OE2#
2
3 1
2
3 1
2
3
GND
DAI_BCLK#
5
DAI_LRCK#
7
DAI_DO#
9
DAI_12MHZ#
DAI_BCLK#
DAI_LRCK#
DAI_DO#
A
11 +3.3V_RUN I2S_DI# 1 @ R166
13
DAI_DI 2 0_0402_5%~D
8 @ D58 DA204U_SOT323-3~D
CD74HC366M96_SO16~D
SPDIFOUT1 (DMIC1)
DAI_DI
2.49K
DAI_12MHZ#
2
6 10
1A
1
39.2K
1
1
4
VCC
DAI_DI
Pull-up to AVDD
2
3
2
2
3
DAI_12MHZ#
3
2
SENSE_B
U73
16
1
1 2 4
1 1
2
+3.3V_RUN
12
R1078 2.49K_0402_1%~D 2 1 C979 1000P_0402_50V7K~D
2
2 10K_0402_5%~D 2 10K_0402_5%~D
@ D57 DA204U_SOT323-3~D
SENSE_A
1 @ R162 1 @ R163 1 @ R164 1 @ R165
2 I2S_BCLK 22_0402_5%~D 2 I2S_LRCLK 0_0402_5%~D 2 I2S_DO 0_0402_5%~D 2 I2S_MCLK 22_0402_5%~D
+VDDA_AVDD
6
2
1
@ D56 DA204U_SOT323-3~D
Place closely to Pin 14
1
2
1
@ D55 DA204U_SOT323-3~D
1 R162, R163, R164, R165,R166 CO-lay with U73
DAI_DO#
2
1
@ D54 DA204U_SOT323-3~D
2
Resistor
R1081 100K_0402_5%~D
1 @ R1141 1 @ R1142
Place C962 close to Codec
26 30 33
A
2
Place C963~C966 close to Codec
@ C967 0.1U_0402_25V6K~D
DAI_LRCK#
R1080 20K_0402_1%~D
BEEP
C962 4.7U_0603_6.3V6K~D
+3.3V_RUN
Add for solve pop noise and detect issue
R1079 39.2K_0402_1%~D
SPKR
2
DAI_BCLK#
1
2 100K_0402_5%~D 2 100K_0402_5%~D
2 0_0402_5%~D PAD~D
21 22 34 37
C983 100P_0402_50V8J~D
AUD_HP_NB_SENSE
1
2
+3.3V_RUN
1 R1119 1 R1120
Place LE3 close to codec
1 @ R169 @ T90
36
C1103 0.1U_0402_10V7K~D
5
AUD_SENSE_B
2
PAD-OPEN1x1m R1087 100K_0402_5%~D
Q107B DMN66D0LDW-7_SOT363-6~D
AUD_HP_OUT_L AUD_HP_OUT_R
2 1 C1105 0.1U_0402_25V6K~D 2 1 C1106 0.1U_0402_25V6K~D 2 DMIC_CLK BLM18BB221SN1D_2P~D DMIC0
12
@
2 Q107A DMN66D0LDW-7_SOT363-6~D
+VREFOUT
place at Codec bottom side @ PJP62 1 2
2
C982 100P_0402_50V8J~D
1
2
25
3
2
1
+3.3V_RUN
2
1
B
Notes: Keep PVDD supply and speaker traces routed on the DGND plane. Keep away from AGND and other analog signals
2
C981 100P_0402_50V8J~D
@
1
C980 0.1U_0402_10V7K~D
R1086 20K_0402_1%~D
1 @
AUD_SENSE_A
6
place at AGND and DGND plane
R1083 2.49K_0402_1%~D 2 1
MIC_IN_R
2 2.2K_0402_5%~D
92HD90B2X5NLGXYAX8_QFN48_7X7~D
Place closely to Pin 13.
2
1
1 1
2
2
49
28 29 23
1
C966 10U_0805_10V6K~D
1 R1099
AUD_SENSE_A AUD_SENSE_B
C965 1U_0603_10V7K~D
7 @ C977 10P_0402_50V8J~D
13 14
C964 4.7U_0603_6.3V6K~D
2
No Connect
+3.3V_RUN
1 @C978 @ C978 0.1U_0402_10V7K~D
+VDDA_PVDD
C963 4.7U_0603_6.3V6K~D
1
2
45 39
No Connect CAP-
@ R1076 10_0402_1%~D
2
@ R1077 47_0402_5%~D
2
19
BCLK: Audio serial data bus bit clock input/output LRCK: Audio serial data bus word clock input/output
1
1
PCH_AZ_CODEC_SDOUT
27 38
3
Close to U72 pin5
1
U72
1
Place R1096 close to codec
PCH_AZ_CODEC_SDIN0
2
1
2
3 1
2
3 1
PCH_AZ_CODEC_BITCLK
2
C1180 1U_0603_10V7K~D
2
@ DE1 PESD5V0U2BT_SOT23-3~D
1
@ DE2 PESD5V0U2BT_SOT23-3~D
2
680P_0402_50V7K~D
680P_0402_50V7K~D
1
2
2
Place C994, C952~C957 close to Codec
9
@ C976
2
@ C975
1
680P_0402_50V7K~D
680P_0402_50V7K~D
2
@ C974
@ C973
1
B
2
1
C960 10U_0805_10V6K~D
2
MOLEX_53398-0471~D
1
C961 0.1U_0402_25V6K~D
PAD-OPEN1x1m
5 6
1
C959 0.1U_0402_25V6K~D
1 2 3 G1 4 G2
1
C958 10U_0805_10V6K~D
1 2 3 4
C956 1U_0603_10V7K~D
INT_SPKL_L+ INT_SPKR_LINT_SPKR_R+ INT_SPKR_R-
C954 10U_0805_10V6K~D
BLM18BD121SN1D_2P~D BLM18BD121SN1D_2P~D BLM18BD121SN1D_2P~D BLM18BD121SN1D_2P~D
+DVDD_CORE 1
C953 0.1U_0402_25V6K~D
2 2 2 2
C994 0.1U_0402_25V6K~D
1 1 1 1
C952 1U_0603_10V7K~D
L91 L92 L93 L94
INT_SPK_L+ INT_SPK_LINT_SPK_R+ INT_SPK_R-
JSPK1 CONN@
R1095 0_0805_5%~D
+3.3V_RUN_DVDD
@ PJP65
C955 10U_0805_10V6K~D
+3.3V_RUN_DVDD
1
DVDD_IO should match with HDA Bus level
C957 0.1U_0402_25V6K~D
+3.3V_RUN
15 mils trace
+5V_RUN
place close to pin38 L77 BLM21PG600SN1D_0805~D 1 2 +5V_RUN
1
+VDDA_AVDD
2
place close to pin27
Internal Speakers Header
5 4
2
Q106A DMN66D0LDW-7_SOT363-6~D
1
DOCK_HP_DET
DOCK_MIC_DET
Q106B DMN66D0LDW-7_SOT363-6~D
2
PORT A
External MIC
PORT B
HeadPhone Out
PORT C
Dock Audio
PORT D
Internal SPK
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn
1
Title
Azalia (HD) Codec Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet
30
of
66
5
4
3
2
1
I/O board CONN. Change to TYCO_2041300-2_60P-T and Horizonal reverse
to SSI
JIO1 SW_LAN_TX0+ SW_LAN_TX0-
D
SW_LAN_TX1 SW_LAN_TX1+ SW_LAN_TX2+ SW_LAN_TX2-
POWER_SW#_MB
POWER_SW#_MB
SW_LAN_TX3 SW_LAN_TX3+
SW1 NTC033-XJ1J-X260CM_4P 3 1 +5V_ALW
@D23 @ D23 3 2
4
2
PESD24VS2UT_SOT23-3~D
1
POWER & INSTANT ON SWITCH Media Board
Defult on, WIRELESS_ON/OFF#: LOW: ON +3.3V_ALW HIGH: OFF
USB_OC4#
USBP9+ USBP9-
USB_SIDE_EN# AUD_HP_NB_SENSE DETECT_GND
JMDIA1 1 2 3 4 5 6 7 8
VOL_MUTE VOL_DOWN VOL_UP
C
WIRELESS_ON#/OFF LID_CL# 1
1 2 3 4 5 6 7 8
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
62 64 66
GND GND GND
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
GND GND GND
61 63 65
IO_LOOP# VSYNC_BUF HSYNC_BUF
D
RED_CRT GREEN_CRT BLUE_CRT DAT_DDC2_CRT CLK_DDC2_CRT
MIC_IN_R
AUD_HP_OUT_R MIC_IN_R AUD_HP_OUT_L
+5V_ALW
1 +3.3V_ALW_PCH 2
PCH_AZ_MDC_RST1#
C1003 0.1U_0402_25V6K~D
PCH_AZ_MDC_SDIN1 PCH_AZ_MDC_SYNC PCH_AZ_MDC_SDOUT PCH_AZ_MDC_BITCLK
Analog_GND C
G1 G2
9 10
TYCO_2041300-2 CONN@
+3.3V_LAN
+3.3V_ALW_PCH 1
TYCO_2041070-8~D CONN@
C1001 0.1U_0402_25V6K~D
2
2
C50 0.1U_0402_25V6K~D
1
+5V_RUN +3.3V_LAN LED_100_ORG# LED_10_GRN# LAN_ACTLED_YEL#
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
C1000 0.1U_0402_25V6K~D
1
2
2
C997 0.1U_0402_25V6K~D
Place close to JIO1.35
Place close to JIO1.13
LED Board +5V_ALW
2
1 2 3 4 5 6
SATA_LED BATT_WHITE BATT_YELLOW WLAN_LED
1 B
JLED1
C1002 0.1U_0402_25V6K~D
1 2 3 4 5 G1 6 G2
7 8
TYCO_2041084-6~D CONN@
B
Q44 SSM3K7002FU_SC70-3~D
S
3
D
1
PCH_AZ_MDC_RST#
PCH_AZ_MDC_RST1#
A
1
2 G
+5V_ALW A
DELL CONFIDENTIAL/PROPRIETARY
2
R752 10K_0402_5%~D
2
1
R751 100K_0402_5%~D
Compal Electronics, Inc.
MDC_RST_DIS# Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
PWR SW/Sub-board Connector Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
31
of
66
5
4
3
2
1
+3.3V_LAN +3.3V_RUN 1
TP_LAN_JTAG_TMS 2 10K_0402_5%~D TP_LAN_JTAG_TCK 2 10K_0402_5%~D
R547 10K_0402_5%~D 2
1 @ R545 1 @ R546
U31
PCIE_PTX_GLANRX_P7
1 2
MDI_PLUS1 MDI_MINUS1
17 18
LAN_TX1+ LAN_TX1-
38 39
PETp PETn
MDI_PLUS2 MDI_MINUS2
20 21
LAN_TX2+ LAN_TX2-
41 42
PERp PERn
MDI_PLUS3 MDI_MINUS3
23 24
LAN_TX3+ LAN_TX3-
LAN_DISABLE#_R
3
SMB_CLK SMB_DATA
RSVD_NC
1 2 5
RSVD_VCC3P3_1 RSVD_VCC3P3_2 VDD3P3_IN
LAN_DISABLE_N
LED
LED0 LED1 LED2
1
1
XTAL_OUT XTAL_IN
LAN_TEST_EN
30
TEST_EN
RES_BIAS
12
RBIAS
JTAG
Place R548, C462, C463 and L29 close to U31
+1.0V_LAN
1 11 40 22 16 8
VDD1P0_40 VDD1P0_22 VDD1P0_16 VDD1P0_8 CTRL_1P0
7
VSS_EPAD
49
2
1
2
1
2
1
2
+3.3V_LAN
1
2
1
2
REGCTL_PNP10
Place C1178 close to pin5
82579_QFN48_6X6~D
+3.3V_M
+1.0V_LAN POWER OPTIONS Shared with PCH 1.05V SVR
@ R563 0_1206_5%~D
* Internal SRV
STUFF: R548 NO STUFF: L29
STUFF: L29 NO STUFF: R548
Q34
+3.3V_ALW
DOCK_LOM_TRD2DOCK_LOM_TRD2+
27 26
DOCK_LOM_TRD1DOCK_LOM_TRD1+
C3+ C3-
23 22
DOCK_LOM_TRD0DOCK_LOM_TRD0+
LEDC0 LEDC1 LEDC2
19 20 40
DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED_ORG# DOCK_LOM_SPD10LED_GRN#
9
LAN_TX1+R
10
LAN_TX01 2 L31 12NH_0603CS-120EJTS_5%~D LAN_TX0+ 1 2 L30 12NH_0603CS-120EJTS_5%~D
LAN_TX0-R
11
LAN_TX0+R
12
LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#
Layout Notice : Place bead as close PI3L500 as possible
15 16 42 5 43
FROM NIC
DOCKED
5
A1-
B3+ B3-
A2+ A2-
LEDB0 LEDB1 LEDB2
A3+
C0+ C0-
A3-
C1+ C1-
SEL
C2+ C2-
LEDA0 LEDA1 LEDA2 PD
LAN_ACTLED_YEL# LED_100_ORG# LED_10_GRN#
DOCK_LOM_TRD2- DOCK_LOM_TRD2+ DOCK_LOM_TRD1- DOCK_LOM_TRD1+
LOM_SPD100LED_ORG#
1
LOM_SPD10LED_GRN#
2
DOCK_LOM_TRD0- DOCK_LOM_TRD0+
O
4
D G
1
3
WLAN_LAN_DISB#
TC7SH08FU_SSOP5~D U15
Compal Electronics, Inc.
TO DOCK
www.vinafix.vn 3
A
DELL CONFIDENTIAL/PROPRIETARY
PAD_GND
4
B
A
DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED_ORG# DOCK_LOM_SPD10LED_GRN#
PI3L720ZHEX_TQFN42_9X3P5~D
B
+3.3V_LAN C478 0.1U_0402_10V7K~D 1 2
DOCK_LOM_TRD3- DOCK_LOM_TRD3+
1: TO DOCK 0: TO RJ45
3
SW_LAN_TX0- SW_LAN_TX0+
2
32 31
LAN_TX1-R
SW_LAN_TX1- SW_LAN_TX1+
4
DOCK_LOM_TRD3DOCK_LOM_TRD3+
LAN_TX11 2 L32 12NH_0603CS-120EJTS_5%~D LAN_TX1+ 1 2 L33 12NH_0603CS-120EJTS_5%~D
13
2
1 36 35
B2+ B2-
7
6
LAN_ACTLED_YEL# LED_100_ORG# LED_10_GRN#
A1+
LAN_TX2+R
1
17 18 41
6
2
2
5
SW_LAN_TX0SW_LAN_TX0+
LAN_TX2-R
2
P
SW_LAN_TX1SW_LAN_TX1+
25 24
A0-
LAN_TX21 2 L35 12NH_0603CS-120EJTS_5%~D LAN_TX2+ 1 2 L34 12NH_0603CS-120EJTS_5%~D
SIO_SLP_LAN#
SW_LAN_TX2- SW_LAN_TX2+
G
29 28
3
B1+ B1-
A0+
3
SW_LAN_TX2SW_LAN_TX2+
LAN_TX3+R
2
2
39 30 21 14 8 4 1 VDD VDD VDD VDD VDD VDD VDD
34 33
LAN_TX3-R
SW_LAN_TX3- SW_LAN_TX3+
1
1
C476 0.1U_0402_10V7K~D
SW_LAN_TX3SW_LAN_TX3+
2
C475 10U_0603_6.3V6M~D
A
DOCKED
1
C477 2200P_0402_50V7K~D
5 38 37
B0+ B0-
Q35A DMN66D0LDW-7_SOT363-6~D
4
ENAB_3VLAN R1638 1M_0402_5%~D
U32
LAN_TX31 2 L37 12NH_0603CS-120EJTS_5%~D LAN_TX3+ 1 2 L36 12NH_0603CS-120EJTS_5%~D
DOCKED
R565 100K_0402_5%~D
LAN ANALOG SWITCH
Q35B DMN66D0LDW-7_SOT363-6~D
2
6 5 2 1
R564 100K_0402_5%~D
C474 0.1U_0402_25V6K~D
2
C473 0.1U_0402_25V6K~D
C472 0.1U_0402_25V6K~D
2
B
1
+3.3V_LAN
SI3456DDV-T1-GE3_TSOP6~D
1
+3.3V_ALW2 +3.3V_LAN 1
C
Note: +1.0V_LAN will work at 0.95V to 1.15V
+PWR_SRC_S
1
2
C464 1U_0603_10V7K~D
43
VDD1P0_11
1
1
Need to verify A3 silicon drive power before removing C427 KDS crystal vender verify driving level in A3
9 10
R562 3.01K_0402_1%~D
R561 1K_0402_1%~D
1
2
2
1
4
2
GND
XTALO XTALI
2
1 +1.0V_LAN 2
VDD1P0_43
+1.05V_M @ R548 @R548 0_0805_5%~D 1 2
C1178 22U_0805_6.3V6M~D
GND
C471 33P_0402_50V8J~D
1
C470 33P_0402_50V8J~D
2
2
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK
+3.3V_LAN
47 46 37
VDD1P0_47 VDD1P0_46 VDD1P0_37
1
C1177 22U_0805_6.3V6M~D
Y3 25MHZ_18PF_X3G025000DI1H-H~D 1 IN OUT 3
32 34 33 35
1 14.7K_0402_5%~D 4.7K_0402_5%~D
C469 0.1U_0402_10V7K~D
2 0_0402_5%~D
2
C468 0.1U_0402_10V7K~D
TP_LAN_JTAG_TDI TP_LAN_JTAG_TDO TP_LAN_JTAG_TMS TP_LAN_JTAG_TCK
2 R5532 R554
C467 0.1U_0402_10V7K~D
1 R1144
1
+3.3V_LAN_OUT
15 19 29
VDD3P3_15 VDD3P3_19 VDD3P3_29
2
26 27 25
+RSVD_VCC3P3_1 +RSVD_VCC3P3_2
C466 0.1U_0402_10V7K~D
C
REGCTL_PNP10
Idc max=330mA
4
VDD3P3_OUT LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#
T142 PAD~D T143 PAD~D
+1.0V_LAN L29
6
LAN_DISABLE#_R @ R557 10K_0402_5%~D
D
4.7UH_CBC2012T4R7M_20%~D
SMBus Device Address 0xC8
2 0_0402_5%~D
MDI
PE_CLKP PE_CLKN
C463 0.1U_0402_10V7K~D
1 R555
PM_LANPHY_ENABLE
44 45
28 31
2 LAN_SMBCLK_R 0_0402_5%~D 2 LAN_SMBDATA_R 0_0402_5%~D
1 R551 1 R552
LAN_SMBCLK LAN_SMBDATA
LAN_TX0+ LAN_TX0-
C462 10U_0603_6.3V6M~D
PCIE_PTX_GLANRX_N7
R549 10K_0402_5%~D
13 14
2
+3.3V_LAN
2 C458 2 C459 1 C460 1 C461
MDI_PLUS0 MDI_MINUS0
S
PCIE_PRX_GLANTX_N7
CLK_PCIE_LAN CLK_PCIE_LAN# 1 PCIE_PRX_GLANTX_P7_C 0.1U_0402_10V7K~D 1 PCIE_PRX_GLANTX_N7_C 0.1U_0402_10V7K~D 2 PCIE_PTX_GLANRX_P7_C 0.1U_0402_10V7K~D 2 PCIE_PTX_GLANRX_N7_C 0.1U_0402_10V7K~D
CLK_REQ_N PE_RST_N
PCIE
CLK_PCIE_LAN CLK_PCIE_LAN# PCIE_PRX_GLANTX_P7
48 36
SMBUS
D
LANCLK_REQ#_R 2 0_0402_5%~D
1 R1187
LANCLK_REQ# PLTRST_LAN#
Title
Intel 82579 (Hanksville) / LAN SW Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 2
Sheet 1
32
of
66
5
+3.3V_RUN
4
3
1
+3.3V_RUN_TPM
D
D
PJP61 1
2 +3.3V_SB3V
PAD-OPEN1x1m +3.3V_SB3V
5
28
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
26 23 20 17
VCC_0 VCC_1 VCC_2
SB3V
LPCPD#
V_BAT NBO_13 NBO_14
LAD0 LAD1 LAD2 LAD3
GPIO6 CLK_PCI_TPM_TCM LPC_LFRAME# PCH_PLTRST#_EC IRQ_SERIRQ CLKRUN#
CLK_PCI_TPM_TCM LPC_LFRAME# PCH_PLTRST#_EC IRQ_SERIRQ CLKRUN#
21 22 16 27 15
LCLK LFRAME# LRESET# SERIRQ CLKRUN#
TESTBI TESTI
1
2
2
JUSH1
JETWAY_CLK14M JETWAY_CLK14M NC_P 1 2 C554 1U_0402_6.3V6K~D
1
2 TCM_BA0
ATEST_1 ATEST_2 ATEST_3
GND_4 GND_11 GND_18 GND_25
7
PP
1 @R656 @ R656
2 4.7K_0402_5%~D
1
2
2
1
2
BT_COEX_STATUS2 BT_PRI_STATUS PLTRST_USH# USH_PWR_STATE# CONTACTLESS_DET# +5V_RUN
4 11 18 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
USBP7USBP7+
USH_SMBCLK USH_SMBDAT BCM5882_ALERT#
+3.3V_RUN_TPM
AT97SC3204-X2A14-AB_TSSOP28
@
+3.3V_SUS
6 9 8
USH_SMBCLK 2 2.2K_0402_5%~D USH_SMBDAT 2 2.2K_0402_5%~D
1 R589 1 R585
1
2
CE3 27P_0402_50V8J~D
USH_DET#
21 22
C52 0.1U_0402_25V6K~D
1 2 3
2
1
C51 0.1U_0402_25V6K~D
TCM_BA1 RE5 33_0402_5%~D
12 13 14
2
1
+3.3V_RUN NC_7
CLK_PCI_TPM_TCM
10 19 24
1
C53 0.1U_0402_25V6K~D
SP_TPM_LPC_EN
1
C553 0.1U_0402_25V6K~D
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
1@ U39
C552 2200P_0402_50V7K~D
SP_TPM_LPC_EN
2
1@
C551 2200P_0402_50V7K~D
2
1@ 1
ATMEL TPM for E4 C550 2200P_0402_50V7K~D
1
C45 4700P_0402_25V7K~D
2 0_0402_5%~D
C44 0.1U_0402_25V6K~D
1 1@ R873
@
+3.3V_SUS
+3.3V_RUN_TPM
+3.3V_RUN_TPM
C
2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
C
GND1 GND2
TYCO_2-2041070-0
Co-lay U37 and U38 LPC layout: Place TCM first and then end LPC with TPM.
China TCM: NationZ & Jetway co-lay +3.3V_RUN_TPM
LOW:Power Down Mode High:Working Mode
B
B
SP_TPM_LPC_EN LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
28 26 23 20 17
CLK_PCI_TPM_TCM LPC_LFRAME# PCH_PLTRST#_EC IRQ_SERIRQ CLKRUN# PP TCM_BA1 TCM_BA0
21 22 16 27 15 7 3 9
LPCPD# LAD0 LAD1 LAD2 LAD3
VDD_0 VDD_1 VDD_2
10 19 24
GND_11 GND_18 GND_25 GND_4
11 18 25 4 +3.3V_SB3V
1
1
TCM_BA0 TCM_BA1
NC_1 NC_2 NC_6 NC_8 NC_P
1 2 6 8 14
JETWAY_CLK14M 1
NC_5 NC_12 NC_13
R660 10K_0402_5%~D
JETWAY_CLK14M
@ RE6 33_0402_5%~D NC_P
1
2
2
2
R659 10K_0402_5%~D
LCLK LFRAME# LRESET# SERIRQ CLKRUN# PP BA_1 BA_0
5 12 13
2
2
@R658 @ R658 10K_0402_5%~D 2
@ R657 10K_0402_5%~D
1
1
+3.3V_RUN_TPM
4@ U37
@ CE4 27P_0402_50V8J~D
SSX44-B-D-T1_TSSOP28~D
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
Title
USH conn/TPM Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
33
of
66
A
B
C
D
E
1
1
+3.3V_RUN
2 2 2 2
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 1 R677
PCIE_PRX_MMITX_P6_C PCIE_PRX_MMITX_N6_C PCIE_PTX_MMIRX_P6_C PCIE_PTX_MMIRX_N6_C 2 191_0402_1%~D
6 7 5 4 3 33
place close to pin U38.32
PE_TXP PE_TXM PE_RXP PE_RXM PE_REXT GPAD
13
PE_RST#
14 31
MULTI-IO1 MULTI-IO2
PLTRST_MMI#
MMICLK_REQ#
2
2
C560 4.7U_0603_6.3V6K~D
PCIE_PRX_MMITX_P6 PCIE_PRX_MMITX_N6 PCIE_PTX_MMIRX_P6 PCIE_PTX_MMIRX_N6
1 1 1 1
2
1
DVDD AVDD
10 8
+OZ_DVDD +OZ_AVDD
SKT_VCC MMI_VCC_OUT
17 15
+SKT_VCC
28 26 29 27 25 24 23 22 21 20
SD/MMCDAT1_R SD/MMCDAT2_R SD/MMCDAT0_R
R663 1 R664 1 R665 1
2 33_0402_5%~D SD/MMCDAT1 2 33_0402_5%~D SD/MMCDAT2 2 33_0402_5%~D SD/MMCDAT0
SD/MMCDAT3_R SD/MMCDAT4_R SD/MMCDAT5_R SD/MMCDAT6_R SD/MMCDAT7_R
R668 R669 R670 R672 R673
2 2 2 2 2
SD/MMCCMD_R SD/MMCCLK_R SD/MMCCD# SDWP
R674 1 1 R676
3.3VDDH VDDH PE_VDDH
2
PE_REFCLKP PE_REFCLKM
1
2
C559 0.1U_0402_25V6K~D
C569 C571 C567 C568
1
1
C564 4.7U_0603_6.3V6K~D
CLK_PCIE_MMI CLK_PCIE_MMI#
+3.3VDDH 16 +VDDH_SD 9 +PE_VDDH 2 32 BLM18BD601SN1D_0603~D 1 4.7U_0603_6.3V6K~D 2 1
C563 0.1U_0402_25V6K~D
2
C574 0.01U_0402_16V7K~D
2
C573 0.1U_0402_25V6K~D
2
1
1 U38
C566 4.7U_0603_6.3V6K~D
2 C578
2
1
C565 0.1U_0402_25V6K~D
1 L44
+PE_VDDH 1
2
1
C575 0.1U_0402_25V6K~D
2
2
1
C576 0.1U_0402_25V6K~D
2
1
C562 0.1U_0402_25V6K~D
1
C561 4.7U_0603_6.3V6K~D
L47 1 2 BLM18BD601SN1D_0603~D
C577 4.7U_0603_6.3V6K~D
L45 BLM18PG471SN1D_2P~D 1 2 1
+1.5V_RUN
SD_D1 SD_D2 MMI_D0 MS_D1 MS_D2 MMI_D3 MMI_D4 MMI_D5 MMI_D6 MMI_D7 MS_CD# SD_CMD/MS_BS MMI_CLK SD_CD# SD_WPI
11 19 18 12 30
2
1 1 1 1 1
33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D 33_0402_5%~D
+3.3V_RUN_CARD
SD/MMCDAT3 SD/MMCDAT4 SD/MMCDAT5 SD/MMCDAT6 SD/MMCDAT7
2
2 33_0402_5%~D SD/MMCCMD SD/MMCCLK 2 33_0402_5%~D
OZ600FJ0LN_QFN32_5X5~D
Note: The trace need to route as daisy-chain and the trace of SD signals need to route as short as possible
+3.3V_RUN_CARD
JSD1 CONN@
3
1
2
2
2 1
@ RE678 @RE678 33_0402_5%~D
2
R826 10K_0402_5%~D
2
1
C572 4.7U_0603_6.3V6K~D
1
SD/MMCCLK
C570 0.1U_0402_25V6K~D
EMI request
1
SD/MMCCLK SD/MMCCMD
8 9 10 12
SD/MMCDAT0 SD/MMCDAT1 SD/MMCDAT2 SD/MMCDAT3 SD/MMCDAT4 SD/MMCDAT5 SD/MMCDAT6 SD/MMCDAT7
4 3 15 14 13 11 7 5
SDWP SD/MMCCD#
1 2
SD/MMCCD#
16 17
@CE757 @ CE757 10P_0402_50V8J~D
SDWP
18 19 20 6
3
CLK/SD-5 VCC/VDD/SD-4 VSS1/SD-3 CMD/SD-2 DAT0/SD-7 DAT1/SD-8 DAT2/SD-9 DAT3/SD-1 DAT4/MMC-10 DAT5/MMC-11 DAT6/MMC-12 DAT7/MMC-13 WP SW/SD CD SW/SD GND SW CD SW WP SW CD&WP/SW/GND CD&WP/SW/GND GND/VSS2/SD6
GND1 GND2
21 22
T-SOL_156-3000000901~D
only for MMC/SD 4
4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A
B
www.vinafix.vn C
Card Reader OZ600FJ0 Size
Rev 0.1
LA-7782 Date:
D
Document Number Friday, June 10, 2011
Sheet E
34
of
66
5
4
3
2
1
+3.3V_PCIE_WWAN 1 @ R693
2
2 100K_0402_5%~D 2 R1157 2 R1158
DDR_XDP_WAN_SMBCLK DDR_XDP_WAN_SMBDAT
1 0_0402_5%~D 1 0_0402_5%~D
WLAN_RADIO_DIS#
+3.3V_ALW_PCH
2 0_0402_5%~D 1
PCIE_MCARD1_DET# 1 R692
WLAN_RADIO_DIS#_R
2
D31 RB751S40T1_SOD523-2~D
USB_MCARD1_DET# 1 @ R698
WWAN_SMBDAT
+3.3V_WLAN
HW_GPS_DISABLE2#
GND2
2 R719 1
+-9%
1000
750
+3.3Vaux
+-9%
330
250
+1.5V
+-5%
500
375
UIM_VPP UIM_DATA
WIMAX_LED#
WLAN_LED#
DMN66D0LDW-7_SOT363-6~D
4
WIRELESS_LED#
3
Q124B DMN66D0LDW-7_SOT363-6~D
1
6
+3.3V_PCIE_FLASH USB_MCARD3_DET#
2
2
1
2
1
1
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1 R710
2 PCIE_MCARD3_DET# 0_0402_5%~D
1 @R708 @ R708
B
+1.5V_RUN LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
2 PCH_PLTRST#_EC 0_0402_5%~D
USBP6USBP6+ USB_MCARD3_DET#
USBP6- USBP6+
2 @ R712
just reserve
1 100K_0402_5%~D
+3.3V_ALW_PCH
WPAN Noise USB_MCARD3_DET#
54
1
TYCO_1775861-1~D
C626 4.7U_0603_6.3V6K~D
2
1
C625 0.1U_0402_25V6K~D
2
1
C624 0.1U_0402_25V6K~D
2
2
1
C623 0.047U_0402_16V4Z~D
1
1
C622 0.047U_0402_16V4Z~D
2
5
2
UIM_DATA
1
2
C608 4.7U_0603_6.3V6K~D
Normal
@ C621 0.1U_0402_25V6K~D
SRV05-4.TCT_SOT23-6~D
1
1
+3.3V_PCIE_FLASH CONN@ JMINI3 1 1 2 3 3 Normal 4 5 5 6 7 7 8 9 9 10 CLK_PCIE_MINI3# 11 11 CLK_PCIE_MINI3# 12 CLK_PCIE_MINI3 13 13 250 (Wake enable) CLK_PCIE_MINI3 14 15 5 (Not wake enable) 15 16 PCH_PLTRST#_EC 17 17 18 PCLK_80H 19 19 PCLK_80H 20 21 NA 21 22 PCIE_PRX_WPANTX_N5 23 23 24 PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 25 25 26 PCIE_PRX_WPANTX_P5 27 27 28 C617 0.1U_0402_10V7K~D 29 29 30 PCIE_PTX_WPANRX_N5_C 1 2 31 PCIE_PTX_WPANRX_N5 31 32 PCIE_PTX_WPANRX_P5_C 1 2 33 PCIE_PTX_WPANRX_P5 33 34 C618 0.1U_0402_10V7K~D 35 35 36 PCIE_MCARD3_DET# 37 37 PCIE_MCARD3_DET# 38 39 39 40 1 2 41 41 +3.3V_RUN 42 R711 100K_0402_5%~D 43 43 44 45 45 46 47 47 48 49 49 50 51 51 52 +1.5V_RUN +3.3V_PCIE_FLASH 53 GND1 GND2
C620 0.047U_0402_16V4Z~D
4
1
2
C607 0.1U_0402_25V6K~D
+3.3V
Peak
@ C631 33P_0402_50V8J~D
2
3
2
2
PCIE_WAKE# COEX2_WLAN_ACTIVE 1 2 R709 0_0402_5%~D MINI3CLK_REQ# MINI3CLK_REQ#
+SIM_PWR
@ C630 33P_0402_50V8J~D
1
@ C629 33P_0402_50V8J~D
2
@ C628 33P_0402_50V8J~D
1
5
+3.3V_WLAN
Aux Power
C619 0.047U_0402_16V4Z~D
UIM_CLK
2
2
1
C606 0.1U_0402_25V6K~D
Voltage Tolerance
Primary Power
1
A
54
WIRELESS_LED#
UIM_VPP
6
2
1
C605 0.047U_0402_16V4Z~D
1
PWR Rail
@ U40
1
2
1
C604 0.047U_0402_16V4Z~D
C616 1U_0402_6.3V6K~D
GND VPP I/O NC GND GND MOLEX_475531001 CONN@
1
@ C603 0.1U_0402_25V6K~D
1
5 6 7 8 9 10
VCC RST CLK NC
GND2
1/2 Minicard Pink Pather/60GHz Card H=4
JSIM1 1 2 3 4
GND1
MSDATA
WIMAX_LED# STUDY FOR DEBUG
Q77 SSM3K7002FU_SC70-3~D
+SIM_PWR
UIM_RESET UIM_CLK
53
+3.3V_WLAN C602 0.047U_0402_16V4Z~D
2
3
D
+
2
MSDATA 2 0_0402_5%~D
1 @ R706
Q124A S
2
1
G
+
@ C1176 330U_D2E_6.3VM_R25~D
1
C615 330U_D2E_6.3VM_R25~D
2
C614 33P_0402_50V8J~D
2
C613 22U_0805_6.3V6M~D
2
1
LED_WWAN_OUT#
SIM Card Push-Push
UIM_RESET
+1.5V_RUN
2
B
2
2 PCIE_MCARD2_DET# 0_0402_5%~D
1
1
2 0_0402_5%~D
USBP4- USBP4+ USB_MCARD1_DET#
C
USB_MCARD2_DET# 1 @ R697 +3.3V_PCIE_WWAN
1
PCH_CL_CLK1 PCH_CL_DATA1 1 PCH_CL_RST1# R707
USBP4USBP4+ USB_MCARD1_DET# WIMAX_LED# WLAN_LED#
TYCO_1775861-1~D
TYCO_1775861-1~D
C612 33P_0402_50V8J~D
2
C611 0.047U_0402_16V4Z~D
C610 0.047U_0402_16V4Z~D
2
1
1 @ C600 33P_0402_50V8J~D
check
54
+3.3V_PCIE_WWAN
1
USBP5 USBP5+ USB_MCARD2_DET#
C601 0.047U_0402_16V4Z~D
2
GND1
COEX2_WLAN_ACTIVE
USBP5USBP5+ USB_MCARD2_DET# LED_WWAN_OUT#
2
1
C594 0.047U_0402_16V4Z~D
2
C593 33P_0402_50V8J~D
1
53
0.1U_0402_10V7K~D 2 PCIE_PTX_WLANRX_N2_C 2 PCIE_PTX_WLANRX_P2_C 0.1U_0402_10V7K~D PCIE_MCARD1_DET#
PCIE_MCARD1_DET# WWAN_SMBCLK WWAN_SMBDAT
100K_0402_5%~D
C
C596 1 1 C598
PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2
5
+1.5V_RUN
WWAN_RADIO_DIS# 2 PCH_PLTRST#_EC 0_0402_5%~D
1 R704
2
C595 4700P_0402_25V7K~D HOST_DEBUG_TX
2
0.1U_0402_10V7K~D 2 PCIE_PTX_WANRX_N1_C 2 PCIE_PTX_WANRX_P1_C 0.1U_0402_10V7K~D 2 PCIE_MCARD2_DET#_R 0_0402_5%~D
PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2
PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2
D
2 100K_0402_5%~D 2 100K_0402_5%~D
WLAN_RADIO_DIS#_R 2 1 PCH_PLTRST#_EC R703 0_0402_5%~D
2
C597 1 PCIE_PTX_WANRX_N1 1 PCIE_PTX_WANRX_P1 C599 PCIE_MCARD2_DET# R7251
HOST_DEBUG_RX MSCLK
R705
PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1
+1.5V_RUN +SIM_PWR
UIM_DATA UIM_CLK UIM_RESET UIM_VPP
1 MSDATA
1
PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1
MINI2CLK_REQ# CLK_PCIE_MINI2# CLK_PCIE_MINI2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
PCIE_MCARD1_DET# 1 @ R699 USB_MCARD1_DET# 1 R701
100K_0402_5%~D
CLK_PCIE_MINI1# CLK_PCIE_MINI1
CLK_PCIE_MINI1# CLK_PCIE_MINI1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
2
MINI1CLK_REQ#
MINI1CLK_REQ#
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
COEX2_WLAN_ACTIVE COEX1_BT_ACTIVE
+3.3V_PCIE_WWAN
+1.5V_RUN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
R718
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
CONN@ JMINI1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
1
+3.3V_PCIE_WWAN
PCIE_WAKE# 1 2 R7001 20_0402_5%~D R702 0_0402_5%~D
PCIE_WAKE# COEX2_WLAN_ACTIVE COEX1_BT_ACTIVE
+3.3V_RUN
2 PCIE_MCARD1_DET# 0_0402_5%~D
+3.3V_WLAN CONN@ JMINI2
D
Mini WWAN/GPS/LTE H=5.2
2 100K_0402_5%~D
Mini WLAN/WIMAX H=4
WWAN_SMBCLK
100K_0402_5%~D
PCIE_MCARD2_DET#_R 1 R695
2
1
+3.3V_PCIE_WWAN
@ R1160 2.2K_0402_5%~D
@ R1159 2.2K_0402_5%~D
1 100K_0402_5%~D
1
+3.3V_RUN USB_MCARD2_DET# 2 R694
2
@ C627 4700P_0402_25V7K~D A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
www.vinafix.vn 3
2
Title
Mini Card Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
35
of
66
5
4
3
2
Express Card PWR S/W
Power Control for Mini card2 +3.3V_ALW Q38 +3.3V_WLAN SI3456DDV-T1-GE3_TSOP6~D
+PWR_SRC_S
+3.3V_ALW
1
+1.5V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_CARDAUX
+1.5V_CARD
+3.3V_CARD
4
S
1
G 3
2
1 2
2 3
1 2 6 1
1
U41 17 2 12
1 R734 1 @R717 @ R717
SIO_SLP_S3# RUN_ON PCH_PLTRST#_EC
2 0_0402_5%~D 2 0_0402_5%~D
20 1 6 19
EXPRCRD_STBY_R#
4 5 13 14 16
+3.3V_RUN +3.3V_CARD +1.5V_CARD +1.5V_RUN
2
R716 100K_0402_5%~D
AUXIN 3.3VIN 1.5VIN
AUXOUT 3.3VOUT 1.5VOUT
SHDN# STBY# SYSRST# OC#
PERST# CPPE# CPUSB#
NC NC NC NC NC
RCLKEN GND PAD
1
2
1
2
1
2
1
2
1
2
C638 10U_0603_6.3V6M~D
2
C637 0.1U_0402_25V6K~D
1
C641 10U_0603_6.3V6M~D
2
C640 0.1U_0402_25V6K~D
1
C643 10U_0603_6.3V6M~D
2
C642 0.1U_0402_25V6K~D
2
1
C633 0.1U_0402_25V6K~D
1
2
C634 0.1U_0402_25V6K~D
1 R715 20K_0402_5%~D
C635 0.1U_0402_25V6K~D
AUX_EN_WOWL
4
C632 4700P_0402_25V7K~D
2
6 5 2 1
R1620 1M_0402_5%~D
Q39A DMN66D0LDW-7_SOT363-6~D
R714 DMN66D0LDW-7_SOT363-6~D 100K_0402_5%~D Q39B
R713 100K_0402_5%~D 5
D
D
1
D
15 3 11 8 10 9
CARD_RESET# EXPRCRD_CPPE# CPUSB#
18 7 21
TPS2231MRGPR-2_QFN20_4X4~D
Power Control for Mini card1 D
S
1 G
2
3
1
2 0_0402_5%~D
1 @R727 @ R727 1 1
2 0_0402_5%~D 2 2
USBP10-
4
USBP10+
4 L49
Power Control for Mini card3
3
4
D
S
1
4
G
2 R730 20K_0402_5%~D
3 1 2
1
CARD_SMBCLK CARD_SMBDAT
CARD_RESET#
2
1
2
2
1 2 3
1 2 6 1
1
C649 0.1U_0402_25V6K~D
1
3
PCIE_WAKE#
+3.3V_CARDAUX
C646 0.1U_0402_25V6K~D
MCARD_MISC_PWREN
6 5 2 1
C650 4700P_0402_25V7K~D
2
CONN@ JEXP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
+3.3V_CARD
R1628 1M_0402_5%~D
Q43A DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D R729 Q43B 100K_0402_5%~D
R728 100K_0402_5%~D 5
2
USBP10_DUSBP10_D+ CPUSB#
CARD_SMBCLK CARD_SMBDAT
Q42 +3.3V_PCIE_FLASH SI3456DDV-T1-GE3_TSOP6~D
1
DLW21SN900SQ2L_0805_4P~D
+3.3V_ALW +PWR_SRC_S
1
1 1 @R724 @ R724
2
3
4
1 2
1 2 3
1 2 6 1 2
MCARD_WWAN_PWREN#
EXPCLK_REQ#
EXPRCRD_CPPE#
CLK_PCIE_EXP# CLK_PCIE_EXP PCIE_PRX_EXPTX_N3 PCIE_PRX_EXPTX_P3 PCIE_PTX_EXPRX_N3 PCIE_PTX_EXPRX_P3
C647 1 1 C648
C645 0.1U_0402_25V6K~D
2 G S
B
+3.3V_ALW
+1.5V_CARD
R732 2.2K_0402_5%~D
2
+3.3V_SUS
D
R731 2.2K_0402_5%~D
1
1
Express Card Conn.
R723 1K_0402_1%~D
SSM3K7002FU_SC70-3~D Q73
R726 100K_0402_5%~D
4
C644 4700P_0402_25V7K~D
MCARD_WWAN_PWREN
6 5 2 1
R1625 1M_0402_5%~D
2
R722 DMN66D0LDW-7_SOT363-6~D 100K_0402_5%~D Q41B
R721 100K_0402_5%~D MCARD_WWAN_PWREN# 5
Q41A DMN66D0LDW-7_SOT363-6~D
Q40 SI3456DDV-T1-GE3_TSOP6~D
+PWR_SRC_S
+3.3V_ALW
C
Note: Add connection on pin4, pin5, pin 13 and pin14 to support GMT 2nd source part
+3.3V_PCIE_WWAN +3.3V_ALW
2
C
0.1U_0402_10V7K~D 2 PCIE_PTX_EXPRX_N3_C 2 PCIE_PTX_EXPRX_P3_C 0.1U_0402_10V7K~D
GND1 USB_DUSB_D+ CPUSB# RESERVED RESERVED SMB_CLK SMB_DAT +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PER_N0 PER_P0 GND PET_N0 PET_P0 GND
27 28 29 30
B
GND GND GND GND T-SOL_5421005002000-9_NR
R733 100K_0402_5%~D
A
2
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
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2
Title
PCIE-SATA SW / PCIE PWR Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
36
of
66
5
4
3
2
1
D
D
D79
USB3RP2
4
1
1
USB3RN2_D-
3
3
1
10
USB3RN2_D-
USB3RP2_D+
2
9
USB3RP2_D+
USB3TN2_D-
4
7
USB3TN2_D-
USB3TP2_D+
5
6
USB3TP2_D+
USB3RP2_D+
2
2
DLW21SN900HQ2L_0805_4P~D 1 2 @ R1608 0_0402_5%~D
+5V_USB_CHG_PWR
USB3RN2_D-
JUSB2 USB3TP2_D+
1
1 @ R1609
2 0_0402_5%~D
2 8
IP4292CZ10-TB_XSON10U10~D L98
USB3TN2 USB3TP2
2 C410
USB3TN2_C 1 0.01U_0402_16V7K~D
2 C411
USB3TP2_C 1 0.01U_0402_16V7K~D
4
L52
4
3
3
USB3TN2_D-
2
USB3TP2_D+
USBP1+
4
4
3
3
USBP1_D+
USBP1-
1
1
2
2
USBP1_D-
1
1
C
1
2
DLW21SN900HQ2L_0805_4P~D 1 2 @ R1612 0_0402_5%~D
DLW21SN900SQ2L_0805_4P~D 1 2 @ R737 0_0402_5%~D
1 @ R1607
1 @ R739
2 0_0402_5%~D
USBP1_D+ USB3RP2_D+ D73 PESD5V0U2BT_SOT23-3~D
3
USB3TN2_DUSBP1_D-
2
USB3RP2
4
C655 0.1U_0402_25V6K~D
USB3RN2
USB3RN2
3
L97
USB3RN2_D-
9 1 8 2 7 3 6 4 5
SSTX+ VBUS SSTXDGND D+ SSRX+ GND SSRX-
GND GND GND GND
10 11 12 13
SANTA_370300-1
C
2 0_0402_5%~D
+SATA_SIDE_PWR +5V_ALW
SLG55584AVTR_TDFN8_2X2
1
2
PWRSHARE_EN# D
S
1
2
ESATA_USB_PWR_EN# PWRSHARE_EN#
USB_OC1#
USB_OC0#
R748 24.9K_0402_1%~D
TPS2560DRCR-PG1.1_SON10_3X3~D 2
2 R816 100K_0402_5%~D
PWRSHARE_EN USBP0_DUSBP0_D+ SEL +5V_ALW
1 2 3 4 9
10 9 8 7 6 11
GND FAULT1# IN OUT1 IN OUT2 EN1# ILIM EN2# FAULT#2 T-PAD
Q48 SSM3K7002FU_SC70-3~D
2 R1614 G 10K_0402_5%~D 1
2 B
CEN DM DP SELCDP Thermal Pad
1 2 3 4 5
B
2
1
C715 0.1U_0402_25V6K~D
+5V_ALW
CB TDM TDP VDD
1
8 7 6 5
USBP0USBP0+
1
SB#
3
2 0_0402_5%~D
2
1 R1626
C675 0.1U_0402_25V6K~D
U2 USB_PWR_SHR_EN#
+5V_USB_CHG_PWR
U48 C676 10U_0805_10V6K~D
2 0_0402_5%~D
1
+5V_ALW 1 R784
USB_PWR_SHR_VBUS_EN
1
@ R1613 10K_0402_5%~D
D78
USB3RP1
1
3
1
2
USB3RN1_D-
3
1
10
USB3RN1_D-
USB3RP1_D+
2
9
USB3RP1_D+
USB3TN1_D-
4
7
USB3TN1_D-
1
USB3TP1_D+
5
6
USB3TP1_D+
+
USB3RP1_D+
2
DLW21SN900HQ2L_0805_4P~D 1 2 @ R1605 0_0402_5%~D
+5V_USB_CHG_PWR
USB3RN1_D-
JUSB1 USB3TP1_D+
1 @ R1604
2 0_0402_5%~D
2 8
1
2
USB3TN1_DUSBP0_R_D-
IP4292CZ10-TB_XSON10U10~D L96
A
USB3TN1 USB3TP1
2 C412
1 USB3TN1_C 0.01U_0402_16V7K~D
2 C413
1 USB3TP1_C 0.01U_0402_16V7K~D
4
4
L51 3
3
USB3TN1_D-
USBP0_D+
4
2
USB3TP1_D+
USBP0_D-
1
4
3
1
2
3
USBP0_R_D+
2
USBP0_R_D-
1
1
1
2
DLW21SN900HQ2L_0805_4P~D 1 2 @ R1606 0_0402_5%~D
DLW21SN900SQ2L_0805_4P~D 1 2 @ R736 0_0402_5%~D
1 @ R1603
1 @ R740
2 0_0402_5%~D
USBP0_R_D+ USB3RP1_D+ D72 PESD5V0U2BT_SOT23-3~D
3
C654 0.1U_0402_25V6K~D
USB3RP1
4
2
4
C651 150U_B2_6.3V-M~D
USB3RN1
USB3RN1
3
L95
USB3RN1_D-
9 1 8 2 7 3 6 4 5
SSTX+ VBUS SSTXDGND D+ SSRX+ GND SSRX-
GND GND GND GND
10 11 12 13
SANTA_370300-1
A
DELL CONFIDENTIAL/PROPRIETARY
2 0_0402_5%~D
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
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Title
USB x2 Size
Rev 0.1
LA-7782 Date:
2
Document Number Friday, June 10, 2011
Sheet 1
37
of
66
5
4
3
2
ESATA Repeater
+3.3V_RUN
1
+3.3V_RUN_U44
ESATA_PRX_DTX_P4_C
2 2
1 2
1 2
2
1 2
R743 0_0402_5%~D
ESATA_PRX_DTX_N4_C
1
2
@ R742 0_0402_5%~D
ESATA_PTX_DRX_N4_C
D
U44 7 17 19 18
ESATA_PTX_DRX_P4 0.01U_0402_16V7K~D 1 ESATA_PTX_DRX_N4 0.01U_0402_16V7K~D 1 ESATA_PRX_DTX_N4 0.01U_0402_16V7K~D 1 ESATA_PRX_DTX_P4 0.01U_0402_16V7K~D
2
R1594 0_0402_5%~D
ESATA_PTX_DRX_P4_C C663 ESATA_PTX_DRX_N4_C C664 ESATA_PRX_DTX_N4_C C665 ESATA_PRX_DTX_P4_C C666
ESATA_PTX_DRX_P4_C
2 0_0402_5%~D
2
R1595 0_0402_5%~D
1 R741
1
C662 0.1U_0402_25V6K~D
2 +3.3V_RUN_U44 D
C661 0.01U_0402_16V7K~D
1
1
PJP9 PAD-OPEN1x1m 1 2
1 2 4 5 3 13 21
EN VCC NC_GND_VDD VCC NC_GND_VDD PREXT/NC/VDD NC_GND_VDDNC/GND/VDD A_INp A_INn B_OUTn B_OUTp GND GND GND
A_PRE B_PRE A_OUTp A_OUTn B_INp B_INn
6 16 20 10 9 8
REXT ESATA_PE1 ESATA_PE2
15 14
ESATA_PTX_DRX_P4_RP ESATA_PTX_DRX_N4_RP
11 12
ESATA_PRX_DTX_P4_RP ESATA_PRX_DTX_N4_RP
PS8513BTQFN20GTR-A0_TQFN20_4X4
C
C
+SATA_SIDE_PWR
2
1
2
C668 0.1U_0402_25V6K~D
+
C667 150U_B2_6.3V-M~D
1
JESA1 USBP2_DUSBP2_D+
1 2 3 4
VBUS DD+ GND
USB
B
B
ESATA_PTX_DRX_P4_RP 1 C671 ESATA_PTX_DRX_N4_RP 1 C672 ESATA_PRX_DTX_N4_RP 1 C673 ESATA_PRX_DTX_P4_RP 1 C674
1
USBP2-
4
1 4
2 3
2
USBP2_D+
3
USBP2_D-
DLW21SN900SQ2L_0805_4P~D 1 2 @ R1150 0_0402_5%~D 1 @ R1151
3
USBP2+
2
L90
2 SATA_PTX_DRX_P4 0.01U_0402_16V7K~D 2 SATA_PTX_DRX_N4 0.01U_0402_16V7K~D 2 SATA_PRX_DTX_N4 0.01U_0402_16V7K~D 2 SATA_PRX_DTX_P4 0.01U_0402_16V7K~D
2 0_0402_5%~D
5 6 7 8 9 10 11
GND A+ ESATA AGND BB+ GND
12 13 14 15
GND GND GND GND
D74 TYCO_2129156-3
PESD5V0U2BT_SOT23-3~D 1
CONN@
Place D74 close to JESATA1
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
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2
Title
USB/ESATA/IO/MDC Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
38
of
66
2
1
CONN@ JDOCK1
DPD_DOCK_LANE_P1 DPD_DOCK_LANE_N1
C692 C685
2 2
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DPD_DOCK_LANE_P2 DPD_DOCK_LANE_N2
C687 C689
2 2
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DPD_DOCK_LANE_P3 DPD_DOCK_LANE_N3 DPD_DOCK_AUX DPD_DOCK_AUX#
DPD_DOCK_AUX DPD_DOCK_AUX# B
DPD_GPU_HPD
DPD_GPU_HPD
BLUE_DOCK
BLUE_DOCK
RED_DOCK
RED_DOCK
GREEN_DOCK
GREEN_DOCK HSYNC_DOCK VSYNC_DOCK
DPD_GPU_HPD
CLK_MSE DAT_MSE 1
DAI_BCLK# DAI_LRCK# R757 100K_0402_5%~D
2
DAI_DI DAI_DO# DAI_12MHZ#
D_LAD0 D_LAD1
D_LAD2 D_LAD3
D_LFRAME# D_CLKRUN# D_SERIRQ D_DLDRQ1# CLK_PCI_DOCK DOCK_SMB_CLK DOCK_SMB_DAT DOCK_SMB_ALERT# DOCK_PSID DOCK_PWR_BTN# SLICE_BAT_PRES#
SLICE_BAT_PRES#
2
2
3 1
1
@
153 154 155 156 157 158
GND1 PWR1 PWR1 PWR1 Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G
PWR2 PWR2 PWR2 GND2 Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G
DPC_DOCK_LANE_P0 DPC_DOCK_LANE_N0
C691 2 C680 2
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DPC_DOCK_LANE_P1 DPC_DOCK_LANE_N1
C682 2 C684 2
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DPC_DOCK_LANE_P2 DPC_DOCK_LANE_N2
C693 2 C686 2
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DPC_DOCK_LANE_P3 DPC_DOCK_LANE_N3
C688 2 C694 2
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DPC_DOCK_AUX DPC_DOCK_AUX#
DPC_GPU_LANE_P1 DPC_GPU_LANE_N1 DPC_GPU_LANE_P2 DPC_GPU_LANE_N2 DPC_GPU_LANE_P3 DPC_GPU_LANE_N3
DPC_DOCK_AUX DPC_DOCK_AUX#
DPC_GPU_HPD
DPC_GPU_HPD ACAV_DOCK_SRC#
1
DAT_DDC2_DOCK CLK_DDC2_DOCK 2 SATA_PRX_DKTX_P5 SATA_PRX_DKTX_N5 SATA_PTX_DKRX_P5 SATA_PTX_DKRX_N5
2 C697 2 C698 1 C699 1 C700
1 1 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 2 2 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D
SATA_PRX_DKTX_P5_C SATA_PRX_DKTX_N5_C SATA_PTX_DKRX_P5_C SATA_PTX_DKRX_N5_C
USBP8+ USBP8-
Close to DOCK Its for Enhance ESD on dock issue.
DPC_GPU_HPD
CLK_KBD DAT_KBD
R758 100K_0402_5%~D
USB3RN4 USB3RP4 USB3TN4 USB3TP4
BREATH_LED# DOCK_LOM_ACTLED_YEL# DOCK_LOM_TRD0+ DOCK_LOM_TRD0- +3.3V_ALW
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
+LOM_VCT 1
+LOM_VCT DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
2
DOCK_DET# @ C701 1U_0402_6.3V6K~D
1 R755
2 100K_0402_5%~D
DOCK_LOM_TRD3+ DOCK_LOM_TRD3- DOCK_DCIN_IS+ DOCK_DCIN_IS- D32 RB751S40T1_SOD523-2~D 1 2
DOCK_POR_RST# DOCK_DET_R#
DOCK_DET#
+DOCK_PWR_BAR
1
2
A
DAI_12MHZ# JAE_WD2F144WB1
B
USBP3+ USBP3-
149 150 151 152 159 160 161 162 163 164
DPC_GPU_LANE_P0 DPC_GPU_LANE_N0
C703 0.1U_0603_50V7K~D
@
C702 0.1U_0603_50V7K~D
2 A
CE6 4.7U_0805_25V6K~D
1
D33 PESD24VS2UT_SOT23-3~D
+DOCK_PWR_BAR
145 146 147 148
DOCK_AC_OFF DOCK_LOM_SPD100LED_ORG# DPC_CA_DET
C696 0.033U_0402_16V7K~D
2
Close to DOCK Its for Enhance ESD on dock issue.
+NBDOCK_DC_IN_SS
C695 0.033U_0402_16V7K~D
1
DPC_CA_DET
1
DPD_DOCK_LANE_P0 DPD_DOCK_LANE_N0
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
DOCK_AC_OFF
2
DPD_GPU_LANE_P3 DPD_GPU_LANE_N3
1 0.1U_0402_10V7K~D 1 0.1U_0402_10V7K~D
2 2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
DAI_BCLK#
2
@ RE11 @RE11 10_0402_1%~D
1
2
CLK_PCI_DOCK 1
DPD_GPU_LANE_P2 DPD_GPU_LANE_N2
2 2
C681 C683
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
@ RE12 10_0402_1%~D
R756 33_0402_5%~D 2
DPD_GPU_LANE_P1 DPD_GPU_LANE_N1
C690 C679
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
2
DPD_GPU_LANE_P0 DPD_GPU_LANE_N0
DPD_CA_DET
1
DOCK_LOM_SPD10LED_GRN# DPD_CA_DET
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
1
DOCK_DET_1
1 @CE8 @CE8 4.7P_0402_50V8C~D
2
1 @CE9 @CE9 4.7P_0402_50V8C~D
2
C704 12P_0402_50V8J~D
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
www.vinafix.vn
DOCKING CONN Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 1
Sheet
39
of
66
5
4
3
2
1
+3.3V_ALW
WWAN_RADIO_DIS# 2 100K_0402_5%~D
1 R776
USB_PWR_SHR_EN# 2 100K_0402_5%~D
1 R768
USB_SIDE_EN# 2 10K_0402_5%~D
C
CRT_SWITCH MDC_RST_DIS# MCARD_MISC_PWREN PROCHOT_GATE DOCK_SMB_ALERT# TOUCH_SCREEN_PD#
1 R778
USB_PWR_SHR_VBUS_EN 2 100K_0402_5%~D
1 R762
DOCK_SMB_ALERT# 2 10K_0402_5%~D
1 R775 1 R1582 1 R1583 1 R1154 1 R3
MCARD_PCIE_SATA# 2 100K_0402_5%~D WIRELESS_ON#/OFF 2 100K_0402_5%~D SP_TPM_LPC_EN 2 10K_0402_5%~D LCD_TST 2 100K_0402_5%~D SYS_LED_MASK# 2 10K_0402_5%~D DGPU_PWR_EN 2 100K_0402_5%~D GFX_MEM_VTT_ON 2 100K_0402_5%~D DP_HDMI_HPD 2 100K_0402_5%~D CHARGE_EN 2 100K_0402_5%~D
USB_SIDE_EN# EN_I2S_NB_CODEC# USH_PWR_STATE# EN_DOCK_PWR_BAR PANEL_BKEN_EC ENVDD_PCH LCD_TST PSID_DISABLE# PBAT_PRES# DOCKED DOCK_DET# AUD_NB_MUTE# MCARD_WWAN_PWREN LCD_VCC_TEST_EN CCD_OFF AUD_HP_NB_SENSE ESATA_USB_PWR_EN# MODULE_ON SLICE_BAT_ON SLICE_BAT_PRES# MODULE_BATT_PRES# CHARGE_MODULE_BATT CHARGE_PBATT DEFAULT_OVRDE
USB_PWR_SHR_EN# GFX_MEM_VTT_ON CPU_DETECT# DGPU_PWR_EN MOD_SATA_PCIE#_DET DP_HDMI_HPD ZODD_WAKE# BCM5882_ALERT# SUSACK# EDID_SELECT# DGPU_PWROK 3.3V_RUN_GFX_ON SLP_ME_CSW_DEV# LAN_DISABLE#_R
B
SYS_LED_MASK# SIO_EXT_WAKE# WIRELESS_LED# USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS#
+3.3V_ALW
VGA_ID 2 100K_0402_5%~D
1 @ R800
VGA_ID
1 R803
2 100K_0402_5%~D
WIRELESS_ON#/OFF BT_RADIO_DIS# WWAN_RADIO_DIS# SYS_PWROK DGPU_SELECT# CPU_VTT_ON PCH_DPWROK
CRT_SWITCH MDC_RST_DIS# MCARD_MISC_PWREN PROCHOT_GATE LID_CL_SIO# DOCK_SMB_ALERT#
B52 A49 B53 A50 B54 A51 B55 A52
USB_SIDE_EN# EN_I2S_NB_CODEC# USH_PWR_STATE# EN_DOCK_PWR_BAR PANEL_BKEN_EC ENVDD_PCH LCD_TST PSID_DISABLE# PBAT_PRES# DOCKED DOCK_DET# AUD_NB_MUTE# MCARD_WWAN_PWREN LCD_VCC_TEST_EN CCD_OFF AUD_HP_NB_SENSE ESATA_USB_PWR_EN#
A33 B36 A34 B37 A35 B38 A36 A37 B40 A38 B41 A39 B42 A40 B43 A41 B44
MODULE_ON SLICE_BAT_ON SLICE_BAT_PRES# MODULE_BATT_PRES# CHARGE_MODULE_BATT CHARGE_PBATT DEFAULT_OVRDE
B32 A31 B33 B15 A15 B16 A16
USB_PWR_SHR_EN# GFX_MEM_VTT_ON MCARD_PCIE_SATA# CPU_DETECT# DGPU_PWR_EN MOD_SATA_PCIE#_DET DP_HDMI_HPD ZODD_WAKE# BCM5882_ALERT# EDID_SELECT# DGPU_PWROK VGA_ID 3.3V_RUN_GFX_ON SLP_ME_CSW_DEV# LAN_DISABLE#_R CHARGE_EN SYS_LED_MASK# DYN_TURB_PWR_ALRT# R797 1 2 0_0402_5%~D WIRELESS_LED# USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# WIRELESS_ON#/OFF BT_RADIO_DIS# WWAN_RADIO_DIS# SYS_PWROK DGPU_SELECT#
GPIOB0 GPIOB1 GPOC2 GPOC3 GPOC4 GPOC5 GPOC6/TACH4 GPIOC7 GPIOD0 GPIOC1 GPIOC0 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7
A1 B2 A2 B3 A3 B45 A42 B4
GPIOE0/RXD GPIOE1/TXD GPIOE2/RTS# GPIOE3/DSR# GPIOE4/CTS# GPIOE5/DTR# GPIOE6/RI# GPIOE7/DCD#
A59 B62 A58 B61 A56 B59 A55 B58
GPIOF0 GPIOF1 GPIOF2 GPIOF3/TACH8 GPIOF4/TACH7 GPIOF5 GPIOF6 GPIOF7
B47 A45 B48 A46 B49 A47 B50 A48
B13 A13 A53 B57 B14 A14 B17 2 B18 0_0402_5%~D
CPU_VTT_ON 1 @R802 @ R802
GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7
GPIOG0/TACH5 GPIOG1 GPIOG2 GPIOG3 GPIOG4 GPIOG5 GPIOG6 GPIOG7/TACH6
GPIOI1 GPIOI2/TACH0 GPIOI3 GPIOI4 GPIOI5 GPIOI6 GPIOI7 GPIOJ0 GPIOJ1/TACH1 GPIOJ2/TACH2 GPIOJ3 GPIOJ4 GPIOJ5 GPIOJ6 GPIOJ7
UMA
1
2
2 0_0402_5%~D
SIO_SLP_LAN# SIO_SLP_SUS# MODC_EN DOCK_HP_DET DOCK_MIC_DET
GPIOL0/PWM7 GPIOL1/PWM8 GPIOL2/PWM0 GPIOL3/PWM1 GPIOL4/PWM3 GPIOL5/PWM2 GPIOL6 GPIOL7/PWM5
B60 A57 B64 B68 A9 B1 A18 A44
SUS_ON
B34 B39 B51
HW_GPS_DISABLE2# BREATH_LED#
A27 A26 B26 B25 A21 B22 A28 B20 A23 A22 B21 A32 B35
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_PLTRST#_EC CLK_PCI_5048 CLKRUN# LPC_LDRQ0# LPC_LDRQ1# IRQ_SERIRQ CLK_SIO_14M
B29 B28 A25 A24 B23 A19 B24 A20
D_LAD0 D_LAD1 D_LAD2 D_LAD3 D_LFRAME# D_CLKRUN# D_DLDRQ1# D_SERIRQ
BC_INT# BC_DAT BC_CLK
A29 B31 A30
BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048
PWRGD
A4
RUNPWROK
B56
SP_TPM_LPC_EN
B19
1 R804 +CAP_LDO
LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# PCICLK CLKRUN# LDRQ0# LDRQ1# SER_IRQ 14.318MHZ/GPIOM0 CLK32/GPIOM2 DLAD0 DLAD1 DLAD2 DLAD3 DLFRAME# DCLKRUN# DLDRQ1# DSER_IRQ
GPIOH0 GPIOH1 SYSOPT1/GPIOH2 SYSOPT0/GPIOH3 GPIOH4 GPIOH5 GPIOH6 GPIOH7
OUT65 TEST_PIN
DB Version 0.4 ECE5048-LZY_DQFN132_11X11~D
B46
1
B
2
A
DOCK_AC_OFF_EC
ME_FWP MASK_SATA_LED#
GPIOM1 GPIOM3/PWM4 GPIOM4/PWM6
+3.3V_ALW @ C711 1
SIO_SLP_A# 0.75V_DDR_VTT_ON SIO_SLP_S4# SIO_SLP_S3# IMVP_PWRGD IMVP_VR_ON
LED_SATA_DIAG_OUT# TEMP_ALERT#_R RUN_ON
AUX_EN_WOWL WLAN_LAN_DISB# SIO_SLP_LAN# SIO_SLP_SUS# GPIO_PSID_SELECT MODC_EN DOCK_HP_DET DOCK_MIC_DET ME_FWP MASK_SATA_LED# 1.8V_RUN_PWRGD LED_SATA_DIAG_OUT#
4 2 1 O D34 @ RB751S40T1_SOD523-2~D U47 @ TC7SH08FU_SSOP5~D
DOCK_AC_OFF
R770 @ 33K_0402_5%~D
TEMP_ALERT#
+3.3V_RUN D_CLKRUN#
SUS_ON
D_SERIRQ
BAT2_LED# USH_PWR_ON
BAT1_LED#
trace width 20 mils
BAT2_LED#
trace width 20 mils
2 R777 2 R780 2 R782
1 100K_0402_5%~D 1 100K_0402_5%~D 1 100K_0402_5%~D
RUN_ON
2 R786
1 100K_0402_5%~D
CPU_VTT_ON
2 R789
1 100K_0402_5%~D
0.75V_DDR_VTT_ON 2 R790 SLICE_BAT_ON 2 R791 SUS_ON 2 R878
1 100K_0402_5%~D 1 100K_0402_5%~D 1 100K_0402_5%~D
D_DLDRQ1#
HW_GPS_DISABLE2# BREATH_LED#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_PLTRST#_EC CLK_PCI_5048 CLKRUN# LPC_LDRQ0# LPC_LDRQ1# IRQ_SERIRQ CLK_SIO_14M EC_32KHZ_ECE5048
D_LAD0 D_LAD1 D_LAD2 D_LAD3 D_LFRAME# D_CLKRUN# D_DLDRQ1# D_SERIRQ
B
BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048
RUNPWROK
SP_TPM_LPC_EN
+3.3V_ALW
+CAP_LDO trace width 20 mils CLK_SIO_14M
1 C714 4.7U_0603_6.3V6K~D
CLK_PCI_5048
@R794 @ R794 10_0402_1%~D
R805 100K_0402_5%~D
@ R795 10_0402_1%~D
1
2
LID_CL_SIO#
2 R807
1 LID_CL# 10_0402_1%~D
1
1 @ C713 4.7P_0402_50V8C~D
ME_FWP PCH has internal 20K PD. (suspend power rail)
2
C716 0.047U_0402_16V4Z~D A
2
DELL CONFIDENTIAL/PROPRIETARY
1
ME_FWP
Compal Electronics, Inc.
@ R793 1K_0402_1%~D 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
www.vinafix.vn 3
C
PAD~D T117 @
2 1K_0402_1%~D
2
0.1U_0402_25V6K~D 2
SPI_WP#_SEL
BAT1_LED#
B27 C1
2TEMP_ALERT# 0_0402_5%~D
1 R738
RUN_ON
@ C712 4.7P_0402_50V8C~D
A
5
C705 10U_0603_6.3V6M~D
2
DOCK_AC_OFF_EC
2
0
B67 A64 A5 B6 A6 B7 A7 B8
1 R765
A8 B9 B10 A10 B11 A11 B12 A12
VSS EP
VGA_ID0
B63 A60 A61 B65 A62 B66 A63
ACAV_IN_NB
SIO_SLP_A# 0.75V_DDR_VTT_ON
GPIOK0 GPIOK1/TACH3 GPIOK2 GPIOK3 GPIOK4 GPIOK5 GPIOK6 GPIOK7
CAP_LDO
Discrete
2
1 C706 0.1U_0402_25V6K~D
B5 A17 B30 A43 A54
U46
ESATA_USB_PWR_EN# 2 100K_0402_5%~D
1 R457 1 R766 1 @ R772 1 R767
2
1 C707 0.1U_0402_25V6K~D
D
1 R769
+3.3V_RUN
1 C708 0.1U_0402_10V7K~D
1
1 R774
2
1 C709 0.1U_0402_25V6K~D
2
SLICE_BAT_PRES# 2 100K_0402_5%~D
2
VCC1 VCC1 VCC1 VCC1 VCC1
D
1 C710 0.1U_0402_25V6K~D
1
1 R760
1
2
CPU_DETECT# 2 100K_0402_5%~D
+3.3V_ALW PJP7 PAD-OPEN1x1m 2 1
5
1 R763
+3.3V_ALW_U46
P
PROCHOT_GATE 2 100K_0402_5%~D
G
1 R761
3
HW_GPS_DISABLE2# 2 100K_0402_5%~D
1
1 R798
2
DYN_TURB_PWR_ALRT# 2 10K_0402_5%~D
1
1 R796
2
Title
ECE5048 Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
40
of
66
5
4
3
2
1
+3.3V_ALW
+RTC_CELL
1
VCCSAPWROK
2
B A
O 3
Modify name net
@ C721 1U_0402_6.3V6K~D 1 2
R810 100K_0402_5%~D U50
2
5 1.05V_VTTPWRGD
P
VCCSAPWROK
G
1.05V_VTTPWRGD
1
C720 0.1U_0402_25V6K~D 2
1
1.05V_0.8V_PWROK
4
1.05V_0.8V_PWROK
POWER_SW_IN#
POWER_SW_IN#
1 R811
1
TC7SH08FU_SSOP5~D
2 10K_0402_5%~D
POWER_SW#_MB
C722 1U_0402_6.3V6K~D
2 +3.3V_ALW_U51
2 1
Y6 32.768KHZ_12.5PF_Q13FC1350000~D
EC_32KHZ_ECE5048
MEC_XTAL2 2 R1068 1 R867
A11 A22 B35 A41 A58 A52 B3 A26
DDR_ON HOST_DEBUG_TX HOST_DEBUG_RX RUNPWROK EN_INVPWR PCH_SATA_MOD_EN#
A61 A62 B62
BGPO0 VCI_IN2# VCI_OUT VCI_IN1# VCI_IN0# VCI_OVRD_IN VCI_IN3#
PECI DB Version 0.12
B66
15mil
VR_CAP
NC1 NC2 NC3
+VR_CAP B12
B34 A64 B68
22P_0402_50V8J~D
PECI_VREF PECI
I2S
2
1 R870 100K_0402_5%~D
DDR_HVREF_RST_GATE DYN_TUR_CURRNT_SET# CPU1.5V_S3_GATE MSDATA MSCLK SIO_A20GATE PS_ID
LAT_ON_SW#
FWP# PROCHOT#_EC
2 1K_0402_1%~D
VOL_MUTE
VOL_UP 2 1K_0402_1%~D VOL_DOWN 2 1K_0402_1%~D ME_SUS_PWR_ACK 1.5V_SUS_PWRGD PM_APWROK 1.05V_A_PWRGD ALW_PWRGD_3V_5V DEVICE_DET# RESET_OUT#
R886 1 R887 1 ME_SUS_PWR_ACK 1.5V_SUS_PWRGD PM_APWROK 1.05V_A_PWRGD ALW_PWRGD_3V_5V DEVICE_DET# RESET_OUT# PCH_RSMRST# AC_PRESENT SIO_PWRBTN#
VOL_MUTE
VOL_UP VOL_DOWN
1 @ R1179
1 @ R812
DOCK_SMB_DAT DOCK_SMB_CLK LCD_SMBDAT LCD_SMBCLK BAY_SMBDAT BAY_SMBCLK GPU_SMBDAT GPU_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK CARD_SMBDAT CARD_SMBCLK USH_SMBDAT USH_SMBCLK
20mA drive pins
I2S_DAT I2S_CLK I2S_WS
A59 B63 A60 A63 B67 B1 A1
LAT_ON_SW# ALWON VCI_IN1# POWER_SW_IN# ACAV_IN DOCK_PWR_SW#
B51 A48
+PECI_VREF PECI_EC_R
ALWON
1 RUN_ON_ENABLE#
1
PECI_EC
43_0402_5%~D
B17 B27 B28
+1.05V_RUN_VTT R863 close to U51& least 250mils 1 2 R862 0_0402_5%~D
1
2
1 2 @ C747 4.7P_0402_50V8C~D
2
2
LCD_SMBCLK
2 R418 2 R420 2 R838 2 R841
1 2.2K_0402_5%~D 1 2.2K_0402_5%~D 1 2.2K_0402_5%~D 1 2.2K_0402_5%~D
2 R854 2 R856 2 R1171 2 R1125
1 2.2K_0402_5%~D 1 2.2K_0402_5%~D 1 100K_0402_5%~D 1 100K_0402_5%~D
LCD_SMBDAT DOCK_SMB_DAT
BAY_SMBDAT BAY_SMBCLK DYN_TUR_CURRNT_SET# DEVICE_DET#
+RTC_CELL
DAT_KBD VCI_IN1#
2 R1156
1 100K_0402_5%~D
1 R869
MSDATA 2 10K_0402_5%~D
1 R876
DDR_ON 2 100K_0402_5%~D
CLK_MSE
1 R880 1 R881 1 R882 1 R883
PCH_ALW_ON 2 100K_0402_5%~D DOCK_POR_RST# 2 100K_0402_5%~D EN_INVPWR 2 100K_0402_5%~D 2 1.05V_0.8V_PWROK 10K_0402_5%~D
2 R845 2 R846 2 R851 2 R852
1 4.7K_0402_5%~D 1 4.7K_0402_5%~D 1 4.7K_0402_5%~D 1 4.7K_0402_5%~D
+3.3V_RUN
1 R872 10K_0402_5%~D
2
2
FWP#
1
2
BOARD_ID
1
2
4
Q50 SSM3K7002FU_SC70-3~D
2 G
2
RESET_OUT#
3
R871 1K_0402_1%~D
R875 240K_0402_5%~D
@ R879 10K_0402_5%~D
S
1
1
2
PCH_PWRGD# D
SYSTEM_ID
C744 4700P_0402_25V7K~D
1
2
B
+5V_RUN CLK_KBD
C740 4.7U_0603_6.3V6K~D
+3.3V_ALW
REV
BOARD_ID rise time is measured from 5%~68%. 5
1 10K_0402_5%~D
DOCK_SMB_CLK
C737 0.1U_0402_25V6K~D
GPIO024/THSEL_STRAP note i.THSEL_STRAP =1 (selects thermistor on diode channel 1) ii.THSEL_STRAP = 0 (selects remote diode on diode channel 1)
1
C744
+3.3V_ALW_PCH
2 R835
+3.3V_ALW
C742 4700P_0402_25V7K~D
1
S
AC_PRESENT
+3.3V_ALW
2
R863
D
2 G
ACAV_IN
+3.3V_M
130K 4700p X01 62K 4700p X02 33K 4700p A00 8.2K 4700p 4.3K 4700p 2K 4700p 1K 4700p
@ R885 10_0402_1%~D
2 0_0402_5%~D
RUNPWROK
MEC5055-LZY_DQFN132_11X11~D
HOST_DEBUG_TX HOST_DEBUG_RX
* 240K 4700p X00 CLK_PCI_MEC
1 R1180
R799 10K_0402_5%~D
BAY_SMBDAT BAY_SMBCLK GPU_SMBDAT GPU_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK CARD_SMBDAT CARD_SMBCLK USH_SMBDAT USH_SMBCLK
+3.3V_ALW
Place closely pin A29
S
DAT_MSE
R875
A
2 100K_0402_5%~D
DOCK_SMB_DAT DOCK_SMB_CLK
R893 100K_0402_5%~D
G1 G2 G3 G4 ACES_87153-10411
@ Q47 SSM3K7002FU_SC70-3~D
1
A3 B4 A4 B5 B7 A7 B48 B49 A47 B50 B52 A49 B53 A50
1
1
1
1 2
2
1
1
1
1
1 2
2
2
2
2
1 2
2
2 2 0_0402_5%~D 0_0402_5%~D
D
2 G
Bat2 = Amber LED Bat1 = Blue LED
PCH_RSMRST# AC_PRESENT SIO_PWRBTN#
@ R850 100K_0402_5%~D
R849 10K_0402_5%~D
1 R853 1 R855
R848 10K_0402_5%~D
JTAG_TDI JTAG_TMS JTAG_CLK JTAG_TDO MSCLK MSDATA HOST_DEB_TX HOST_DEB_RX
2
C740 close to U51.B12 R847 10K_0402_5%~D
10 11 12 13 14
R860 10K_0402_5%~D
8
R861 10K_0402_5%~D
6
1 2 3 4 5 6 7 8 9 10
R859 10K_0402_5%~D
4
1 2 3 4 5 6 7 8 9 10
R858 10K_0402_5%~D
2
R864 49.9_0402_1%~D
CONN@ JDEG2
C
PROCHOT#_EC
1 +3.3V_ALW
H_PROCHOT#
2 10K_0402_5%~D 1
R884 1
least 15mil
+3.3V_ALW
2
DDR_HVREF_RST_GATE DYN_TUR_CURRNT_SET# CPU1.5V_S3_GATE MSDATA MSCLK SIO_A20GATE PS_ID
DELL PWR SW INF
XTAL1 XTAL2 GPIO160/32KHZ_OUT
DOCK_PWR_BTN#
+RTC_CELL
3
B64
GPIO011/nSMI GPIO061/LPCPD# LDRQ# SER_IRQ LRESET# PCI_CLK LFRAME# LAD0 LAD1 LAD2 LAD3 CLKRUN# GPIO100/nEC_SCI
MASTER CLOCK
MEC_XTAL1 MEC_XTAL2_R 1 20_0402_5%~D 0_0402_5%~D
2 10K_0402_5%~D
3
A6 A27 B29 A28 B30 A29 B31 A30 B32 A31 B33 A32 A33
1 1 R825
+3.3V_RUN
GPIO003/I2C1A_DATA GPIO004/I2C1A_CLK GPIO005/I2C1B_DATA GPIO006/I2C1B_CLK GPIO012/I2C1H_DATA/I2C2D_DATA GPIO013/I2C1H_CLK/I2C2D_CLK GPIO130/I2C2A_DATA GPIO131/I2C2A_CLK GPIO132/I2C1G_DATA GPIO140/I2C1G_CLK GPIO141/I2C1F_DATA/I2C2B_DATA GPIO142/I2C1F_CLK/I2C2B_CLK GPIO143/I2C1E_DATA GPIO144/I2C1E_CLK
HOST INTERFACE
SIO_EXT_SMI# SIO_RCIN# LPC_LDRQ#_MEC IRQ_SERIRQ PCH_PLTRST#_EC CLK_PCI_MEC LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 CLKRUN# SIO_EXT_SCI#
B2 A2 B8 B18 A8 B9 A9 A14 B15 A17 B39 A44 B47 A54 B58
SMBUS INTERFACE
VSS[1] VSS[4]
C743 1
PCH_PCIE_WAKE# PCIE_WAKE# BC_CLK_ECE1117 BC_DAT_ECE1117 BC_INT#_ECE1117 BEEP SIO_SLP_S5# ACAV_IN_NB
GPIO123/BCM_A_CLK GPIO122/BCM_A_DAT GPIO121/BCM_A_INT# GPIO022/BCM_B_CLK GPIO023/BCM_B_DAT GPIO024/BCM_B_INT# GPIO044/BCM_C_CLK GPIO043/BCM_C_DAT GPIO042/BCM_C_INT# GPIO047/LSBCM_D_CLK GPIO046/LSBCM_D_DAT GPIO045/LSBCM_D_INT# GPIO032/GPTP-IN3/BCM_E_CLK GPIO31/GPTP-OUT2/BCM_E_DAT GPIO30/GPTP-IN2/BCM_E_INT#
AGND
MEC_XTAL1 B
SYSTEM_ID BOARD_ID DDR_ON HOST_DEBUG_TX HOST_DEBUG_RX RUNPWROK EN_INVPWR
EP
22P_0402_50V8J~D MEC_XTAL2
GPIO001/ECSPI_CS1 GPIO002/ECSPI_CS2 GPIO014/GPTP-IN7/HSPI_CS1 GPIO040/GPTP-OUT3/HSPI_CS2 GPIO015/GPTP-OUT7 GPIO016/GPTP-IN8 GPIO017/GPTP-OUT8 GPIO026/GPTP-IN1 GPIO027/GPTP-OUT1 GPIO041 GPIO107/nRESET_OUT GPIO125/GPTP-IN5 GPIO126 GPIO151/GPTP-IN4 GPIO152/GPTP-OUT4
BC-LINK A43 B45 A42 A12 B13 A13 B20 A18 B19 A20 B21 A19 A16 B16 A15
DOCK_PWR_SW#
+1.05V_RUN_VTT
GPIO050/FAN_TACH1 GPIO051/FAN_TACH2 GPIO052/FAN_TACH3 GPIO053/PWM0 GPIO054/PWM1 GPIO055/PWM2 GPIO056/PWM3
VSS_RO
IRQ_SERIRQ PCH_PLTRST#_EC CLK_PCI_MEC LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 CLKRUN# SIO_EXT_SCI#
2
A10 B10 B14 B44 B46 B26 A25 B36 B37 B38 A34 A35 A36 A40 B43 A45 A55 A57 B61 B65 A46
GENERAL PURPOSE I/O
C1
2
SIO_EXT_SMI# SIO_RCIN#
C741 1
GPIO145/I2C1K_DATA/JTAG_TDI GPIO146/I2C1K_CLK/JTAG_TDO GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS JTAG_RST#
@ C733 R819 1U_0402_6.3V6K~D 100K_0402_5%~D 1 2
Q45 SSM3K7002FU_SC70-3~D
PCH_PCIE_WAKE# PCIE_WAKE# BC_CLK_ECE1117 BC_DAT_ECE1117 BC_INT#_ECE1117 BEEP SIO_SLP_S5# ACAV_IN_NB
32 KHz Clock
GPIO021/RC_ID1 GPIO020/RC_ID2 GPIO025/UART_CLK GPIO120/UART_TX GPIO124/GPTP-OUT5/UART_RX VCC_PRWGD GPIO060/KBRST GPIO101/ECGP_SCLK GPIO103/ECGP_MISO GPIO105/ECGP_MOSI GPIO102/HSPI_SCLK GPIO104/HSPI_MISO GPIO106/HSPI_MOSI GPIO116/MSDATA GPIO117/MSCLK GPIO127/A20M GPIO153/LED3 GPIO156/LED1 GPIO157/LED2 nFWP PROCHOT#/PWM4
B54
1
2 1
2
2
PCH_ALW_ON BIA_PWM_EC
BC_CLK_ECE5048 BC_DAT_ECE5048 BC_INT#_ECE5048 BC_CLK_EMC4022 BC_DAT_EMC4022 BC_INT#_EMC4022
BC_CLK_ECE5048 BC_DAT_ECE5048 BC_INT#_ECE5048 BC_CLK_EMC4022 BC_DAT_EMC4022 BC_INT#_EMC4022
JTAG1 CONN@ @SHORT PADS~D
2
1
C735 0.1U_0402_25V6K~D
R836 100_0402_1%~D @
PCH_ALW_ON BIA_PWM_EC
1
1
R824 10K_0402_5%~D
JTAG_RST#
JTAG_RST# citcuit close to U51.B57
DOCK_PWR_SW#
FAN PWM & TACH B22 A21 B23 B24 A23 B25 A24
DOCK_POR_RST#
C
2
VTR[1] VTR[2] VTR[3] VTR[4] VTR[5] VTR[6] VTR[7] VTR[8]
VBAT 1 0.1U_0402_25V6K~D DOCK_POR_RST#
2
1
C730 10U_0603_6.3V6M~D
C736 2
2
1
C725 0.1U_0402_25V6K~D
+3.3V_ALW
A51 B55 B56 A53 B57
2
1
2
MISC INTERFACE
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO110/PS2_CLK2/GPTP-IN6 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO112/PS2_CLK1A GPIO113/PS2_DAT1A GPIO114/PS2_CLK0A GPIO115/PS2_DAT0A GPIO154/I2C1C_DATA/PS2_CLK1B GPIO155/I2C1C_CLK/PS2_DAT1B
JTAG INTERFACE
JTAG_TDI JTAG_TDO JTAG_CLK JTAG_TMS JTAG_RST#
2
1
C739 0.1U_0402_25V6K~D
A5 B6 A37 B40 A38 B41 A39 B42 B59 A56
2
1
C734 1U_0402_6.3V6K~D
PS/2 INTERFACE
SML1_SMBDATA SML1_SMBCLK CLK_TP_SIO DAT_TP_SIO CLK_KBD DAT_KBD CLK_MSE DAT_MSE PBAT_SMBDAT PBAT_SMBCLK
2
1
C728 0.1U_0402_25V6K~D
SML1_SMBDATA SML1_SMBCLK CLK_TP_SIO DAT_TP_SIO CLK_KBD DAT_KBD CLK_MSE DAT_MSE PBAT_SMBDAT PBAT_SMBCLK
CHARGER_SMBDAT 2 2.2K_0402_5%~D CHARGER_SMBCLK 2 2.2K_0402_5%~D
1 R827 1 R828
2
D
1
C726 0.1U_0402_25V6K~D
PBAT_SMBDAT 2 2.2K_0402_5%~D PBAT_SMBCLK 2 2.2K_0402_5%~D LPC_LDRQ#_MEC 2 100K_0402_5%~D
1 R818 1 R820 1 @ R823
2
1
C731 0.1U_0402_25V6K~D
2
U51
1
+RTC_CELL C729 0.1U_0402_25V6K~D
1
PJP8 PAD-OPEN1x1m 2 1
C727 0.1U_0402_25V6K~D
BC_DAT_EMC4022 1 100K_0402_5%~D BC_DAT_ECE5048 2 100K_0402_5%~D BC_DAT_ECE1117 2 100K_0402_5%~D
+3.3V_ALW
C732 0.1U_0402_25V6K~D
PCIE_WAKE# 2 10K_0402_5%~D
2 R821 1 R814 1 R817
C723 0.1U_0402_25V6K~D
1 R759
B11 B60
D
R815 0_0402_5%~D 1 2+RTC_CELL_VBAT
1
+RTC_CELL
2
+3.3V_ALW
1 @ R843 1 R889 1 R892
VOL_MUTE
2 R1169 VOL_DOWN 2 R1197 VOL_UP 2 R1118
1 100K_0402_5%~D 1 100K_0402_5%~D 1 100K_0402_5%~D
GPU_SMBDAT 2 R829 GPU_SMBCLK 2 R822
1 4.7K_0402_5%~D 1 4.7K_0402_5%~D
2 RESET_OUT# 8.2K_0402_5%~D 2 CPU1.5V_S3_GATE 100K_0402_5%~D 2 PCH_RSMRST# 10K_0402_5%~D
A
DELL CONFIDENTIAL/PROPRIETARY CHIPSET_ID for BID function
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn 3
2
Title
MEC5055 Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
41
of
66
5
4
3
2
+3.3V_TP
BlueTooth
2
1 2
3
2
2
1
2
TP_CLK
1 BLM18AG601SN1D_0603~D
1
2
10P_0402_50V8J~D C749
1
JTP1
1
TP_CLK TP_DATA
+3.3V_TP
PS2_DAT_TS PS2_CLK_TS
2
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
2
G1 G2
BT_DET# COEX1_BT_ACTIVE BT_COEX_STATUS2 BT_PRI_STATUS BT_ACTIVE BT_RADIO_DIS# COEX2_WLAN_ACTIVE
9 10
TYCO_2041070-8 CONN@
C748 0.1U_0402_25V6K~D
1 TP_DATA
1 BLM18AG601SN1D_0603~D
L55 2
CLK_TP_SIO
+3.3V_RUN
Touch Pad Conn. Pitch=0.5mm L54 2
10P_0402_50V8J~D C750
1
Touch Pad
C751 10P_0402_50V8J~D
Place close to JTP1
DAT_TP_SIO
C752 10P_0402_50V8J~D
D
R902 4.7K_0402_5%~D
C755 0.1U_0402_25V6K~D
D37 PESD5V0U2BT_SOT23-3~D
2
R903 4.7K_0402_5%~D
1
1
+3.3V_TP TP_CLK TP_DATA
1
Pin reverse for PT
CONN@ JBT1 D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
BT_COEX_STATUS2 BT_PRI_STATUS
USBP11USBP11+
1 2 3 4 5 6 7 8 9 10 11 12 G1 G2
E&T_3703-E12N-03R
2 0_0603_5%~D
1 @ R1162
2 0_0603_5%~D
2
1
1
2
2 BT_COEX_STATUS2 1K_0402_1%~D 2 BT_PRI_STATUS 1K_0402_1%~D
1 R1133 1 R1134
+3.3V_RUN C
2
1 1 R1161
RSMRST circuit
@ C754 100P_0402_50V8J~D
+3.3V_TP
R904 10K_0402_5%~D
+3.3V_RUN
C753 33P_0402_50V8J~D
+3.3V_ALW
C
+3.3V_ALW R1622 10K_0402_5%~D 1 2
+3.3V_ALW
2
2
VCC RESET#
3
5
EC SIDE PCH_RSMRST#
PCH_RSMRST#
1
RSMRST#
2
B A
Power Switch for debug
2 0.1U_0402_25V6K~D
U7 O
GND 3
C289 0.01U_0402_16V7K~D
1
1
1 C288 PCH_RSMRST#_Q
P
U4
@ R1623 0_0402_5%~D 1 2
G
+5V_ALW
4
PCH_RSMRST#_Q
1
POWER_SW#_MB
1
2
2
1
TC7SH08FU_SSOP5~D @ C759 100P_0402_50V8J~D
RT9818A-46GU3_SC70-3~D
@ PWRSW1 @SHORT PADS~D
2
Place on Bottom
@ LVDS cable Part Number
Change KB connector to same as JSC1 B
DC020003Y0L
KB Conn. Pitch=1.0mm +3.3V_ALW
+5V_RUN
1
2
1 C756 0.1U_0402_25V6K~D
2
C758 0.1U_0402_25V6K~D
KB_DET#
+3.3V_ALW +5V_RUN BC_INT#_ECE1117 BC_DAT_ECE1117 BC_CLK_ECE1117
KB_DET# PS2_CLK_TS PS2_DAT_TS
1 2 3 4 5 6 7 8 9 10 11 12
Place close to JKB1
@ MDC wire set cable
Part Number NBX0000RP0L
Part Number
Description FFC 6P H P1 PAD=0.7 87.4MM MB-LED/B 0FD
DC30100BL0L
@MEDIA Board FFC @ RTC BATT Part Number
JKB1
@LED Board FFC
Description H-CONN SET ZJX MB-LCD 14 WXGA+(-1ch)
Part Number
Part Number
@ FAN
GND GND
@ Speak
BATT CR2032 3V 220MAH MAXELL
Part Number DC28A000800
DC02C00180L Description
FCI_10089709-010010LF~D CONN@
PK230003Q0L
NBX0000RR0L Description
FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
Part Number
Part Number SP070007V0L
Description
Part Number
SPK PACK ZJX 2.0W 4 OHM FG
DC020014Z10
Description S SOCKET TYCO 1770551-1 10P H5.9 SMART
@BT wire cable
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
Part Number
@ Battery bridge cable Description
Description FFC 8P F P0.5 PAD=0.3 136MM MB-TP/B 0FD
@KB FFC
H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL
@ UMA DC_IN wire cable
DC30100BN0
Part Number
FFC 12P G P.5 PAD.3 75MM MB-VOLUME/B 0FD
@ LVDS cable Part Number
B
@ T/P FFC
Description
Description NBX0000RS0L
GC20323MX00
1 2 3 4 5 6 7 8 9 10
Description CONN SET 0FD MDC-RJ11
DC020014Y0L
Description H-CONN SET 0FD MB-BT
Description H-CONN SET 0FD M/B-BATTERY 9PIN
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
Title
TP/KB/BT/FAN/RESET Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
42
of
66
3
2
1
DC/DC Interface
+1.5V_RUN Source
+3.3V_ALW_PCH Source 1
1 2
G 4
1
2 1 1 1 R749
2 3 0_0402_5%~D 4
RUN_ON
1 @ R747
2 5 0_0402_5%~D 6 7
CT1
A_ON_3.3V#
D
S
2 G
PJP6 1
+5V_ALW
2
PAD-OPEN 1x3m
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
+5V_ALW_U78 C1198 1U_0603_10V7K~D
VBIAS
12 11 10 9 8
1
C1196 2
1 1
270P_0402_50V7K~D @C1197 @ C1197 1 2 270P_0402_50V7K~D
+5V_RUN Source
15 +5V_RUN
SLG59M232VTR 1 1 2 2
1
2
C770 4700P_0402_25V7K~D
1
2
SIO_SLP_S3#
R913 20K_0402_5%~D 2
ON1
2
R910 20K_0402_5%~D
B
2
1
1
3
1
VOUT1 VOUT1
C761 0.1U_0402_25V6K~D
2
@ R919 20K_0402_5%~D 2
3
2 3
2
R916 39_0603_5%~D
Q60 SSM3K7002FU_SC70-3~D
4
VIN1 VIN1
14 13
1 S
1 G
1
4
+3.3V_M_CHG
2
1 U78 1 2
+3.3V_M
C768 10U_0603_6.3V6M~D
6
2 1
1
+3.3V_ALW_U78 C1199 1U_0603_10V7K~D 2 1
+3.3V_M
D 1
6 5 2 1
R1617 1M_0402_5%~D
1
+3.3V_RUN Source
2
4
1
3
2 6 1
2
Q58 SI3456DDV-T1-GE3_TSOP6~D
A_ENABLE Q57B DMN66D0LDW-7_SOT363-6~D
Q57A DMN66D0LDW-7_SOT363-6~D SIO_SLP_A# 2
C
C764 0.1U_0402_25V6K~D
+3.3V_ALW
R917 100K_0402_5%~D
SIO_SLP_A#
2
R931 20K_0402_5%~D
+3.3V_RUN
+3.3V_ALW2
B
1
C773 2200P_0402_50V7K~D
+3.3V_ALW
1
PAD-OPEN 1x3m PJP5
+PWR_SRC_S
A_ON_3.3V# 5
S
+1.05V_RUN
2 R1611 470K_0402_5%~D
C767 4700P_0402_25V7K~D
+3.3V_M Source
R918 100K_0402_5%~D
D
2 G
1
2
1.05V_RUN_ENABLE
Q64
Q53A DMN66D0LDW-7_SOT363-6~D 2 SUS_ON
R1618 1M_0402_5%~D
5
Q53B DMN66D0LDW-7_SOT363-6~D
SUS_ON_3.3V# C
2
R914 20K_0402_5%~D 2
SUS_ENABLE
C771 4700P_0402_25V7K~D
+1.05V_M Q63 SI4164DY-T1-GE3_SO8~D 8 1 7 2 R930 6 3 100K_0402_5%~D 5
S 3
1
G
1
2
+1.05V_RUN Source
D
1 2
4
D
1
C772 10U_0603_6.3V6M~D
6 5 2 1
R921 20K_0402_5%~D
+PWR_SRC_S
2
2
Q54 SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS
C765 10U_0603_6.3V6M~D
R911 100K_0402_5%~D
R915 100K_0402_5%~D
3
2 6 2 0_0402_5%~D
1
2 0_0402_5%~D
1 @ R744
+PWR_SRC_S
+3.3V_ALW2
3
1
1
RUN_ON
1 R735
5 4
1 2
RUN_ON_ENABLE#
RUN_ON_ENABLE#
SIO_SLP_S3#
+3.3V_ALW
2
2
G 3
2 3 4
6
+3.3V_SUS Source
1
1.5V_RUN_ENABLE
C762 3300P_0402_50V7K~D
2
4
R1610 470K_0402_5%~D
1
R909 100K_0402_5%~D
Q52B DMN66D0LDW-7_SOT363-6~D
1
R908 20K_0402_5%~D
Q52A DMN66D0LDW-7_SOT363-6~D
Q51A DMN66D0LDW-7_SOT363-6~D 2 PCH_ALW_ON
2
R1619 1M_0402_5%~D
5
Q51B DMN66D0LDW-7_SOT363-6~D
ALW_ON_3.3V#
S
1 1 2
ALW_ENABLE
D
1
ALW_ENABLE
6 5 2 1
R920 100K_0402_5%~D
C769 10U_0603_6.3V6M~D
R905 100K_0402_5%~D
4
1
+3.3V_ALW2
6 5 2 1
C760 10U_0603_6.3V6M~D
R907 100K_0402_5%~D
Q59 NTGS4141NT1G_TSOP6~D +1.5V_RUN D
+PWR_SRC_S
D
+3.3V_ALW2
+1.5V_MEM
2
Q49 +3.3V_ALW_PCH SI3456DDV-T1-GE3_TSOP6~D
3
+3.3V_ALW
SSM3K7002FU_SC70-3~D
+PWR_SRC_S
2
4
S
5
Discharg Circuit 1 2 1
S
2 G
D
3
1
S
D
3
1 3
1 3
2
2
2
2 1
1
1
1
1
1 2
3
1
1 3
2 G
RUN_ON_CPU1.5VS3#
S
2 G
Q72 SSM3K7002FU_SC70-3~D
3
R927 22_0603_5%~D
+DDR_CHG
D
Q71 SSM3K7002FU_SC70-3~D
1
+0.75V_DDR_VTT
R926 220_0402_5%~D +1.5V_CPU_VDDQ_CHG
S
@
@ Q70 SSM3K7002FU_SC70-3~D
S
2 G
+1.05V_RUN_CHG
2 G
D
Q69 SSM3K7002FU_SC70-3~D
S
D
+1.5V_CPU_VDDQ
@ R925 39_0402_5%~D
+3.3V_RUN_CHG
2 G
+1.05V_RUN
@ R929 39_0603_5%~D
@ R924 1K_0402_1%~D
@ Q68 SSM3K7002FU_SC70-3~D
3
+3.3V_RUN
+1.5V_RUN_CHG
RUN_ON_ENABLE#
D
@ Q67 SSM3K7002FU_SC70-3~D
S
+5V_RUN_CHG
D
ALW_ON_3.3V# 2 G
@ Q66 SSM3K7002FU_SC70-3~D
S
@ Q65 SSM3K7002FU_SC70-3~D
D
2 G
+1.5V_RUN
@ R923 1K_0402_1%~D
+3.3V_ALWPCH_CHG
+3.3V_SUS_CHG
A
@ R928 @R928 1K_0402_1%~D 2
2
@ R922 1K_0402_1%~D
SUS_ON_3.3V#
+5V_RUN
1
+3.3V_ALW_PCH
1
+3.3V_SUS
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
Title
POWER CONTROL Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
43
of
66
5
4
3
2
1
HDD LED solution for White LED
Battery LED
+3.3V_ALW
Q83B
1
+5V_ALW BAT2_LED#
3 2
Q74B DMN66D0LDW-7_SOT363-6~D 4
3
1
R949 4.7K_0402_5%~D 1 2
BAT2_LED#_Q
BATT_WHITE
BATT_YELLOW
MASK_BASE_LEDS#
D
Q74A DMN66D0LDW-7_SOT363-6~D 1 6 2
D59 SATA_ACT#
5
R932 10K_0402_5%~D D
DMN66D0LDW-7_SOT363-6~D 4 3
2
Q75 PDTA114EU_SC70-3~D
1
R958 4.7K_0402_5%~D 2
BATT_WHITE_LED
1
2
5
RB751S40T1_SOD523-2~D
MASK_SATA_LED#
BATT_YELLOW_LED
D62 1
LED_SATA_DIAG_OUT#
1 R934
MASK_BASE_LEDS#
2
2 4.7K_0402_5%~D
SATA_LED
PANEL_HDD_LED
RB751S40T1_SOD523-2~D
Q83A DMN66D0LDW-7_SOT363-6~D 1 6
BAT1_LED#
3
2
PANEL_HDD_LED
R953 475_0402_1%~D 1 2
Q81 PDTA114EU_SC70-3~D 1
2
R951 475_0402_1%~D 1 2
MASK_BASE_LEDS#
Q80A DMN66D0LDW-7_SOT363-6~D 1 6 2
5
Q80B DMN66D0LDW-7_SOT363-6~D 4 3
BAT1_LED#_Q
1 R938
SYS_LED_MASK#
1 2
Breath LED
5
+5V_ALW
Q84A DMN66D0LDW-7_SOT363-6~D 1 6
BREATH_LED#
+5V_ALW
LED1 LTW-193ZDS5_WHITE~D BREATH_WHITE_LED_SNIFF 1 2
BREATH_LED#_Q
C
1 R957
2 1K_0402_1%~D
3
2
R937 100K_0402_5%~D
Place LED1 close to SW1
MASK_BASE_LEDS#
Q78A DMN66D0LDW-7_SOT363-6~D 1 6 2 Q79 PDTA114EU_SC70-3~D
2
WIRELESS_LED#
Q84B DMN66D0LDW-7_SOT363-6~D 4 3
WLAN LED solution for White LED
+3.3V_ALW
C
2 4.7K_0402_5%~D
R955 4.7K_0402_5%~D 2
BREATH_WHITE_LED
3
1
MASK_BASE_LEDS#
1
Q78B DMN66D0LDW-7_SOT363-6~D 5 4
BT_ACTIVE
1
1 R939
2 4.7K_0402_5%~D
WLAN_LED
2
R950 100K_0402_5%~D
B
B
+3.3V_ALW
@ FD1 1
SYS_LED_MASK#
LID_CL#
LID_CL#
SYS_LED_MASK#
1
LID_CL#
2
B
O A
3
SYS_LED_MASK#
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function) Mask Base MB LEDs (Lid Closed) Do not Mask LEDs (Lid Opened)
A
@ FD2 1 FIDUCIAL MARK~D
0 1 1
CLIP1 EMI_CLIP
U58
GND 4
CLIP2 EMI_CLIP
TC7SH08FU_SSOP5~D GND
X 0 1
@ FD3 1
5
4
@ H16 H_3P0
@ H17 H_2P3
@ H19 H_3P0x2P0
@ H20 H_2P0N
@ H22 H_3P0
A
Compal Electronics, Inc.
@ H23 H_2P3 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
1
1
1
1
1
www.vinafix.vn 1
@ H15 H_3P0
1
@ H14 H_3P0
1
@ H13 H_3P0
1
@ H12 H_3P0
1
@ H10 H_3P3
1
@ H9 H_3P0
1
@ H8 H_3P2
1
@ H7 H_3P0
1
@ H6 H_3P0
1
@ H5 H_3P0
1
@ H4 H_3P3
1
@ H3 H_3P0
1
@ H2 H_3P3
1
@ H1 H_3P3
1
FIDUCIAL MARK~D
1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D @ FD4 1
1
MASK_BASE_LEDS#
G
LED Circuit Control Table
Fiducial Mark
EMI CLIP
0.1U_0402_25V6K~D 2
P
5
C778 1
2
Title
PAD and Standoff Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
44
of
66
5
4
3
2
1
UV1A
DV2 DPC_GPU_HPD
D
PEG_CRX_GTX_C_P0 PEG_CRX_GTX_C_N0
PEG_CRX_GTX_P1 PEG_CRX_GTX_N1
CV4 CV3
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P1 PEG_CRX_GTX_C_N1
PEG_CRX_GTX_P2 PEG_CRX_GTX_N2
CV5 CV6
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P2 PEG_CRX_GTX_C_N2
PEG_CRX_GTX_P3 PEG_CRX_GTX_N3
CV7 CV8
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P3 PEG_CRX_GTX_C_N3
PEG_CRX_GTX_P4 PEG_CRX_GTX_N4
CV9 CV10
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P4 PEG_CRX_GTX_C_N4
PEG_CRX_GTX_P5 PEG_CRX_GTX_N5
CV11 CV12
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P5 PEG_CRX_GTX_C_N5
PEG_CRX_GTX_P6 PEG_CRX_GTX_N6
CV14 CV15
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P6 PEG_CRX_GTX_C_N6
PEG_CRX_GTX_P7 PEG_CRX_GTX_N7
CV16 CV17
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P7 PEG_CRX_GTX_C_N7
PEG_CRX_GTX_P8 PEG_CRX_GTX_N8
CV18 CV19
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P8 PEG_CRX_GTX_C_N8
PEG_CRX_GTX_P9 PEG_CRX_GTX_N9
CV20 CV21
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P9 PEG_CRX_GTX_C_N9
PEG_CRX_GTX_P10 PEG_CRX_GTX_N10
CV22 CV23
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P10 PEG_CRX_GTX_C_N10
PEG_CRX_GTX_P11 PEG_CRX_GTX_N11
CV24 CV25
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P11 PEG_CRX_GTX_C_N11
PEG_CRX_GTX_P12 PEG_CRX_GTX_N12
CV26 CV27
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P12 PEG_CRX_GTX_C_N12
PEG_CRX_GTX_P13 PEG_CRX_GTX_N13
CV28 CV29
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P13 PEG_CRX_GTX_C_N13
PEG_CRX_GTX_P14 PEG_CRX_GTX_N14
CV30 CV31
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P14 PEG_CRX_GTX_C_N14
PEG_CRX_GTX_P15 PEG_CRX_GTX_N15
CV32 CV33
2 2
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
PEG_CRX_GTX_C_P15 PEG_CRX_GTX_C_N15
PEG_CRX_GTX_C_P0 PEG_CRX_GTX_C_N0 PEG_CRX_GTX_C_P1 PEG_CRX_GTX_C_N1 PEG_CRX_GTX_C_P2 PEG_CRX_GTX_C_N2 PEG_CRX_GTX_C_P3 PEG_CRX_GTX_C_N3 PEG_CRX_GTX_C_P4 PEG_CRX_GTX_C_N4 PEG_CRX_GTX_C_P5 PEG_CRX_GTX_C_N5 PEG_CRX_GTX_C_P6 PEG_CRX_GTX_C_N6 PEG_CRX_GTX_C_P7 PEG_CRX_GTX_C_N7 PEG_CRX_GTX_C_P8 PEG_CRX_GTX_C_N8 PEG_CRX_GTX_C_P9 PEG_CRX_GTX_C_N9 PEG_CRX_GTX_C_P10 PEG_CRX_GTX_C_N10 PEG_CRX_GTX_C_P11 PEG_CRX_GTX_C_N11 PEG_CRX_GTX_C_P12 PEG_CRX_GTX_C_N12 PEG_CRX_GTX_C_P13 PEG_CRX_GTX_C_N13 PEG_CRX_GTX_C_P14 PEG_CRX_GTX_C_N14 PEG_CRX_GTX_C_P15 PEG_CRX_GTX_C_N15
AK14 AJ14 AH14 AG14 AK15 AJ15 AL16 AK16 AK17 AJ17 AH17 AG17 AK18 AJ18 AL19 AK19 AK20 AJ20 AH20 AG20 AK21 AJ21 AL22 AK22 AK23 AJ23 AH23 AG23 AK24 AJ24 AL25 AK25
PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N
PEX_WAKE_N
GPU_CRT_RED GPU_CRT_GRN GPU_CRT_BLU
DACA_HSYNC DACA_VSYNC
AM9 AN9
GPU_CRT_HSYNC GPU_CRT_VSYNC
GPU_CRT_CLK_DDC_R GPU_CRT_DAT_DDC_R
I2CB_SCL I2CB_SDA
R7 R6
I2CB_SCL I2CB_SDA
I2CC_SCL I2CC_SDA
R2 R3
I2CS_SCL I2CS_SDA
T4 T3
A
O
4
CLK
1
2
C
LDDC_CLK_GPU LDDC_DATA_GPU
GPU_SMBCLK_R GPU_SMBDAT_R
+CLK_PLLVDD 1
2
CLK_27M_IN CLK_27M_OUT XTALSSIN 1 XTALOUTBUFF RV12 1 RV16
RV29 2.2K_0402_5%~D
YV1 27MHZ_12PF_X1E000021042600~D 1 IN OUT 3 2
GND
1
4
GND
2 10K_0402_5%~D 2 10K_0402_5%~D
1
2
1
2
1
2
1
2
1
2
LV8 2 1 +1.05V_PEX_VDD BLM18PG181SN1D_2P
B
2
CLK_27M_OUT CV35 20P_0402_50V8J~D
CV34 20P_0402_50V8J~D
1
+3.3V_RUN_GFX
2
P
5 B
G
2
3
1
PLTRST_GPU#
0.1U_0402_10V7K~D CV87
1 2 DGPU_HOLD_RST#
2
GPU_CRT_CLK_DDC GPU_CRT_DAT_DDC
AD7
H1 J4
1
LV13 2 1 +3.3V_RUN_GFX BLM18PG300SN1D_2P~D
CV73 22U_0805_6.3V6M~D
CLK_27M_IN
2
2
AE8
H3 H2
1
CV112 4.7U_0603_6.3V6K~D
RV33 100K_0402_5%~D
XTAL_SSIN XTAL_OUTBUFF
RV10 33_0402_5%~D 2 1 RV14 1 2 33_0402_5%~D
LDDC_CLK_GPU LDDC_DATA_GPU
AD8
PEX_RST_N PEX_TERMP
+3.3V_RUN
1
AG10 +DACA_VDD AP9 DACA_VREF CV13 1 2 0.01U_0402_16V7K~D DACA_RSET AP8 1 2 RV6 124_0402_1%~D
N13M_FCBGA908~D
don't connect to PCH +3.3V_RUN
AJ12 AP29
GPU_CRT_HSYNC GPU_CRT_VSYNC
R4 R5
XTAL_IN XTAL_OUT
2 150_0402_1%~D 2 150_0402_1%~D 2 150_0402_1%~D
CV89 0.1U_0402_10V7K~D
RV18 DGPU_PEX_RST_R 1 0_0402_5%~D 2 2 1 RV15 2.49K_0402_1%~D
PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N
1 RV3 GPU_CRT_GRN 1 RV4 GPU_CRT_BLU 1 RV5
GPU_CRT_RED GPU_CRT_GRN GPU_CRT_BLU
I2CA_SCL I2CA_SDA
VID_PLLVDD
2 100K_0402_5%~D
Close to GPU
CV88 0.1U_0402_10V7K~D
DGPU_PEX_RST
AJ26 AK26
AJ11
AK9 AL10 AL9
SP_PLLVDD PEX_REFCLK PEX_REFCLK_N PEX_CLKREQ_N
1 RV1
CV86 0.1U_0402_10V7K~D
B
AL13 AK13 AK12
ENVDD_GPU
DPD_GPU_HPD DPE_GPU_HPD
CV85 0.1U_0402_10V7K~D
CLK_PCIE_VGA CLK_PCIE_VGA# CLK_REQ# 1 2 +3.3V_RUN_GFX RV21 10K_0402_5%~D PEX_TSTCLK_OUT 1 2 @ RV13 200_0402_1%~D PEX_TSTCLK_OUT#
1
D
DPC_GPU_HPD
DPD_GPU_HPD DPE_GPU_HPD
DACA_RED DACA_GREEN DACA_BLUE
PLLVDD
2
RB751V-40GTE-17_SOD323-2~D
FBVREF_ALTV GPU_VID_1 GPU_HOT# GPU_VID_6
DPC_GPU_HPD
1
DV4 DPE_GPU_HPD
THERMTRIP_VGA#
GPU_CRT_RED
DACA_VDD DACA_VREF DACA_RSET
2
CV111 4.7U_0603_6.3V6K~D
1 0.22U_0402_16V7K~D 1 0.22U_0402_16V7K~D
DP_HDMI_HPD
RB751V-40GTE-17_SOD323-2~D
CV107 1U_0603_10V7K~D
2 2
DPD_GPU_HPD
CV200 0.1U_0402_10V7K~D
CV1 CV2
1
DV3
CV202 0.1U_0402_10V7K~D
C
PEG_CRX_GTX_P0 PEG_CRX_GTX_N0
THERMTRIP_VGA# GPU_GPIO9 FBVREF_ALTV GPU_VID_1 GPU_HOT# GPU_VID_6
2
RB751V-40GTE-17_SOD323-2~D
GPU_VID_5 GPU_VID_4 BIA_PWM_GPU ENVDD_GPU PANEL_BKEN_DGPU GPU_VID_2 GPU_VID_3
1
PEG_CRX_GTX_N[0..15]
PEG_CRX_GTX_N[0..15]
GPU_VID_5 GPU_VID_4 BIA_PWM_GPU ENVDD_GPU PANEL_BKEN_DGPU GPU_VID_2 GPU_VID_3
P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 N4 P2 R8 M6 R1 P3 P4 P1
2
PEG_CRX_GTX_P[0..15]
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21
GPIO
PEG_CRX_GTX_P[0..15]
Part 1 of 7
DACs
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_N[0..15]
PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N
I2C
PEG_CTX_GRX_P[0..15]
AN12 AM12 AN14 AM14 AP14 AP15 AN15 AM15 AN17 AM17 AP17 AP18 AN18 AM18 AN20 AM20 AP20 AP21 AN21 AM21 AN23 AM23 AP23 AP24 AN24 AM24 AN26 AM26 AP26 AP27 AN27 AM27
PCI EXPRESS
PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 PEG_CTX_GRX_P10 PEG_CTX_GRX_N10 PEG_CTX_GRX_P11 PEG_CTX_GRX_N11 PEG_CTX_GRX_P12 PEG_CTX_GRX_N12 PEG_CTX_GRX_P13 PEG_CTX_GRX_N13 PEG_CTX_GRX_P14 PEG_CTX_GRX_N14 PEG_CTX_GRX_P15 PEG_CTX_GRX_N15
MAX14885EETL has internal 3K pu for GPU_CRT_CLK_DDC and GPU_CRT_DAT_DDC
+3.3V_RUN_GFX 1 1 @ RV23 1 @ RV24
2
GPU_CRT_CLK_DDC 2 4.7K_0402_5%~D GPU_CRT_DAT_DDC 2 4.7K_0402_5%~D
DGPU_PEX_RST
74AHC1G09GW_TSSOP5~D UV14
1 2 RV30 0_0402_5%~D @ QV14B GPU_SMBCLK 4 3
2
5
GPU_SMBCLK_R
A
GPU_SMBDAT_R
1
DMN66D0LDW-7_SOT363-6~D DGPU_PWR_EN
GPU_SMBCLK
DGPU_PWR_EN
DMN66D0LDW-7_SOT363-6~D 6
GPU_SMBDAT
1 RV104 2 RV27 2 RV28 1 RV102 1 RV103
GPU_HOT# 2 10K_0402_5%~D I2CB_SCL 1 2.2K_0402_5%~D I2CB_SDA 1 2.2K_0402_5%~D GPU_GPIO9 2 10K_0402_5%~D THERMTRIP_VGA# 2 10K_0402_5%~D A
GPU_SMBDAT
@ QV14A 1 2 RV26 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
Title
N12P PCIE,I2C,DAC,GPIO Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
45
of
66
5
4
3
2
1
UV1F UV1D
D
AK1 AJ1 AJ3 AJ2 AH3 AH4 AG5 AG4
IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N
DPD_GPU_LANE_P0 DPD_GPU_LANE_N0 DPD_GPU_LANE_P1 DPD_GPU_LANE_N1 DPD_GPU_LANE_P2 DPD_GPU_LANE_N2 DPD_GPU_LANE_P3 DPD_GPU_LANE_N3
AM1 AM2 AM3 AM4 AL3 AL4 AK4 AK5
IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N
TMDSE_GPU_P2 TMDSE_GPU_N2 TMDSE_GPU_P1 TMDSE_GPU_N1 TMDSE_GPU_P0 TMDSE_GPU_N0 TMDSE_GPU_CLK TMDSE_GPU_CLK#
AD2 AD3 AD1 AC1 AC2 AC3 AC4 AC5
IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N
DPC_GPU_LANE_P0 DPC_GPU_LANE_N0 DPC_GPU_LANE_P1 DPC_GPU_LANE_N1 DPC_GPU_LANE_P2 DPC_GPU_LANE_N2 DPC_GPU_LANE_P3 DPC_GPU_LANE_N3
1 RV35 1 RV36
DPD_GPU_AUX/DDC 2 100K_0402_5%~D DPD_GPU_AUX#/DDC 2 100K_0402_5%~D
AE3 AE4 AF4 AF5 AD4 AD5 AG1 AF1
DPC_GPU_AUX/DDC DPC_GPU_AUX#/DDC
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
NC
MULTI_STRAP_REF0_GND
IFPF_L0 IFPF_L0_N IFPF_L1 IFPF_L1_N IFPF_L2 IFPF_L2_N IFPF_L3 IFPF_L3_N
THERMDP THERMDN
L3 J2 J7 J6 J5 J3
J1
1
+3.3V_RUN_GFX
MULTI_STRAP_REF0_GND 1 RV93
K3
2 40.2K_0402_1%~D
VGA_THERMDP 1
K4 2
VDD_SENSE
2
10K_0402_5%~D STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
L4
@ CV37 @CV37 100P_0402_50V8J~D VGA_THERMDN
GPU_VDD_SENSE
Use 16mils trace for sense pin GND_SENSE
L5
+3.3V_RUN_GFX
GPU_VSS_SENSE
TMDS_E_GPU_DDC TMDS_E_GPU_DDC#
AK3 AK2 AB3 AB4
IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N
TEST
IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N
TESTMODE JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
IFPF_AUX_I2CZ_SCL IFPF_AUX_I2CZ_SDA_N
SERIAL
AK11 GPU_TESTMODE AM10 GPU_JTAG_TCK AM11 GPU_JTAG_TDI AP12 GPU_JTAG_TDO AP11 GPU_JTAG_TMS AN11 GPU_JTAG_TRST#
@ TV2 @ TV3 @ TV4 2
1 RV9
2
TMDS_E_GPU_DDC TMDS_E_GPU_DDC#
DPD_GPU_AUX/DDC DPD_GPU_AUX#/DDC
IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N
1
2
1
2
RV39 +3.3V_RUN_GFX
RV40
???
TMDS_E_GPU_DDC 1.5K_0402_5%~D TMDS_E_GPU_DDC# 1.5K_0402_5%~D
ROM_SI_GPU ROM_SO_GPU ROM_SCLK_GPU
@ RV98 10K_0402_1%~D 1 2
RV54 10K_0402_1%~D 1 2
RV53 34.8K_0402_1%~D 1 2
RV52 4.99K_0402_1%~D 1 2
RV97 34.8K_0402_1%~D 1 2
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 ROM_SCLK_GPU ROM_SI_GPU ROM_SO_GPU
5
RV99 20K_0402_1%~D 1 2
@ RV41 4.99K_0402_1%~D 1 2
@ RV60 10K_0402_1%~D 1 2
@ RV59 15K_0402_1%~D 1 2
@ RV58 15K_0402_1%~D 1 2
RV57 34.8K_0402_1%~D 1 2
A
RV56 34.8K_0402_1%~D 1 2
H6 H5 H7 H4
N13M_FCBGA908~D
@ RV51 45.3K_0402_1%~D 1 2
@ RV50 34.8K_0402_1%~D 1 2
RV49 45.3K_0402_1%~D 1 2
1K_0402_1%~D
ROM_CS_N ROM_SI ROM_SO ROM_SCLK
+3.3V_RUN_GFX
@ RV55 4.99K_0402_1%~D 1 2
AF3 AF2
@
RV8 10K_0402_5%~D
Decive ID change to 0x1056
DPC_GPU_AUX/DDC AG3 DPC_GPU_AUX#/DDC AG2
RV25 10K_0402_5%~D
DPD_GPU_AUX/DDC DPD_GPU_AUX#/DDC B
RV11 CEC
1
DPC_GPU_AUX/DDC 2 100K_0402_5%~D DPC_GPU_AUX#/DDC 2 100K_0402_5%~D
L2
RV20 10K_0402_5%~D
1 RV38 1 RV37
BUFRST_N
2
TO MB HDMI
IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N
P8 AC6 AJ28 AJ4 AJ5 AL11 C15 D19 D20 D23 D26 H31 T8 V32
1
TO DOCKING C
AJ9 AH9 AP6 AP5 AM7 AL7 AN8 AM8 AK8 AL8
NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13
2
TO DOCKING
LCD_BCLK+_GPU LCD_BCLK-_GPU LCD_B0+_GPU LCD_B0-_GPU LCD_B1+_GPU LCD_B1-_GPU LCD_B2+_GPU LCD_B2-_GPU
IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N
1
AM6 AN6 AP3 AN3 AN5 AM5 AL6 AK6 AJ6 AH6
GENERAL
LCD_ACLK+_GPU LCD_ACLK-_GPU LCD_A0+_GPU LCD_A0-_GPU LCD_A1+_GPU LCD_A1-_GPU LCD_A2+_GPU LCD_A2-_GPU
LVDS/TMDS
**
GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100
Part 6 of 7
GND
AG11 A2 A33 AA13 AA15 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22 AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7
Part 4 of 7
GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199
D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11
GND_OPT GND_OPT
C16 W32
D
C
B
N13M_FCBGA908~D A
DELL CONFIDENTIAL/PROPRIETARY Hynix 128Mx16 GDDR5 part stuff RV53=35K Samsung 128Mx16 GDDR5 part stuff RV53=45K
4
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn 3
2
Title
N12P DP, STRAP, GND Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
46
of
66
5
4
3
2
1
UV1E
+1.05V_PEX_VDD Part 5 of 7
1 2
POWER
H27
1 RV44
2 40.2_0402_1%~D
FB_GND_SENSE FB_VDDQ_SENSE
IFPC_PLLVDD IFPC_RSET IFPC_IOVDD
H25
1 RV43 1 RV126
2 100_0402_1%~D
F1
1 RV125
2 100_0402_1%~D
PEX_PLL_HVDD
AH12
PEX_SVDD_3V3
AG12
AB8 AD6 AC7 AC8
IFPEF_PLLVDD IFPEF_RSET IFPE_IOVDD IFPF_IOVDD
1
2
+1.05V_PEX_VDD
+1.5V_MEM_GFX
C
+1.5V_MEM_GFX
+3.3V_RUN_GFX 1
2 +IFPEF_PLLVDD IFPEF_RSET +IFPEF_IOVDD
2
2
2 60.4_0402_1%~D
F2
IFPD_PLLVDD IFPD_RSET IFPD_IOVDD
1
1
D
CV77 22U_0805_6.3V6M~D
FB_CAL_PU_GND
1
2
CV74 22U_0805_6.3V6M~D
2 40.2_0402_1%~D
2
LV14 BLM18AG121SN1D_0603~D
1
2
CV71 22U_0805_6.3V6M~D
1 RV42
2
2
1
+1.05V_PEX_VDD
PLACE NEAR GPU 1
CV67 22U_0805_6.3V6M~D
IFPD_RSET
AG7 AN2 AG6
J27
2
2
2
CV53 10U_0603_6.3V6M~D
AF7 AF8 AF6
FB_CAL_PD_VDDQ
2 +3.3V_RUN_VDD33
1
1
1
2
1
2
CV106 4.7U_0603_6.3V6K~D
+IFPCD_PLLVDD IFPC_RSET +IFPCD_IOVDD
1
J8 K8 L8 M8
CV108 4.7U_0603_6.3V6K~D
2
+IFPAB_IOVDD
1
VDD33_0 VDD33_1 VDD33_2 VDD33_3
CV64 0.1U_0402_10V7K~D
2
1
CV174 0.1U_0402_10V7K~D
2
1
CV166 0.1U_0402_10V7K~D
2
1
CV172 1U_0402_6.3V6K~D
1
CV175 4.7U_0603_6.3V6K~D
2
CV173 1U_0402_6.3V6K~D
1
+IFPAB_IOVDD
2
2
CV51 10U_0603_6.3V6M~D
LV11 BLM18PG181SN1D_2P 1 2
1
FB_CAL_TERM_GND
IFPAB_PLLVDD IFPAB_RSET IFPA_IOVDD IFPB_IOVDD
AG26
1
1
CV54 10U_0603_6.3V6M~D
+1.8V_RUN_GFX
AH8 AJ8 AG8 AG9
2
CV204 1U_0402_6.3V6K~D
+IFPAB_PLLVDD IFPAB_RSET
2
1
CV52 10U_0603_6.3V6M~D
2
2
CV99 4.7U_0603_6.3V6K~D
1
CV167 0.1U_0402_10V7K~D
2
CV168 1U_0603_10V7K~D
1
CV109 4.7U_0603_6.3V6K~D
2 C
CV169 1U_0402_6.3V6K~D
1
+IFPAB_PLLVDD
PEX_PLLVDD
AG19 AG21 AG22 AG24 AH21 AH25
CV205 1U_0402_6.3V6K~D
LV10 BLM18AG121SN1D_0603~D 1 2
1 PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5
2
1
PLACE UNDER BGA
CV63 0.1U_0402_10V7K~D
+1.05V_PEX_VDD
2
1
CV70 4.7U_0603_6.3V6K~D
2
1
CV213 1U_0402_6.3V6K~D
1
AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28
CV214 1U_0402_6.3V6K~D
2
@
CV161 0.1U_0402_10V7K~D
1
2
CV116 0.1U_0402_10V7K~D
2
2
1
CV160 0.1U_0402_10V7K~D
1
1
CV115 0.1U_0402_10V7K~D
@
CV127 1U_0402_6.3V6K~D
2
2
CV125 1U_0402_6.3V6K~D
2
1
1
CV126 1U_0402_6.3V6K~D
1
2
CV124 1U_0402_6.3V6K~D
@
1
CV56 4.7U_0603_6.3V6K~D
2
2
CV48 4.7U_0603_6.3V6K~D
2
1
1
CV55 4.7U_0603_6.3V6K~D
A/B
1
2
CV40 10U_0603_6.3V6M~D
2
CV79 22U_0805_6.3V6M~D
1
2
1
CV47 4.7U_0603_6.3V6K~D
2
1
CV39 10U_0603_6.3V6M~D
D
CV78 22U_0805_6.3V6M~D
1
Close to Pin
PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13
CV65 4.7U_0603_6.3V6K~D
close to the GPU
FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43
CV211 1U_0402_6.3V6K~D
+1.5V_MEM_GFX
CV212 1U_0402_6.3V6K~D
AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27
C/D N13M_FCBGA908~D +3.3V_RUN_GFX
+3.3V_RUN_GFX
LV15 MMZ1608R301AT_2P~D 1 2
1 2
2
1
2
CV215 0.1U_0402_10V7K~D
2
1
CV197 0.1U_0402_10V7K~D
2
1
CV69 0.1U_0402_10V7K~D
2
1
CV76 0.1U_0402_10V7K~D
2
1
CV68 0.1U_0402_10V7K~D
2
1
CV75 1U_0402_6.3V6K~D
2
1
CV198 1U_0402_6.3V6K~D
2
1
CV170 4.7U_0603_6.3V6K~D
1
B
Near Ball
+3.3V_RUN_VDD33 2 0_0603_5%~D CV123 4.7U_0603_6.3V6K~D
2
1 RV7
Near GPU
+1.05V_PEX_VDD LV12 BLM18PG221SN1D_2P~D 1 2
2
1
2
CV193 0.1U_0402_10V7K~D
1
CV184 0.1U_0402_10V7K~D
2
+IFPEF_IOVDD CV183 1U_0603_10V7K~D
1
CV110 4.7U_0603_6.3V6K~D
CV195 1U_0402_6.3V6K~D
1
2
IFPAB_RSET
2
1
CV101 0.1U_0402_10V7K~D
2
2
1
CV105 0.1U_0402_10V7K~D
2
1
1
CV104 0.1U_0402_10V7K~D
2
1
CV206 0.1U_0402_10V7K~D
2
1
CV194 0.1U_0402_10V7K~D
2
1
CV122 0.1U_0402_10V7K~D
2
1
CV121 0.1U_0402_10V7K~D
1
CV120 1U_0402_6.3V6K~D
CV119 4.7U_0603_6.3V6K~D
2
CV118 1U_0402_6.3V6K~D
1
+IFPCD_IOVDD
CV103 1U_0603_10V7K~D
2 +1.05V_PEX_VDD LV9 BLM18PG221SN1D_2P~D 1 2
+IFPEF_PLLVDD
CV102 4.7U_0603_6.3V6K~D
1
1
2
+3.3V_RUN_GFX
2
1 2
2
1
E/F
CV100 0.1U_0402_10V7K~D
2
1
CV98 0.1U_0402_10V7K~D
2
1
CV97 0.1U_0402_10V7K~D
2
1
CV96 1U_0603_10V7K~D
1
+IFPCD_PLLVDD
CV95 4.7U_0603_6.3V6K~D
B
CV94 4.7U_0603_6.3V6K~D
LV6 MMZ1608R301AT_2P~D 1 2
1 @ RV32 2 1K_0402_1%~D
A
IFPC_RSET
A
1 RV45 2 1K_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
IFPD_RSET 1 RV47 2 1K_0402_1%~D IFPEF_RSET
5
Compal Electronics, Inc.
1 RV48 2 1K_0402_1%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
www.vinafix.vn 3
2
Title
N12P Power Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
47
of
66
5
4
3
2
1
D
D
+GPU_CORE UV1G
Caps on Power Side
C
B
VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55
+GPU_CORE Part 7 of 7
POWER
AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15
VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71
V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22
XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16 XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22 XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30 XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38
U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8 W2 W3 W4 W5 W7 W8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8
C
B
N13M_FCBGA908~D
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
Title
N12P Power GFX Core Size
Document Number
Date:
Friday, May 20, 2011
Rev 0.1
LA-7782 Sheet 1
48
of
66
5
FBA_D[0..63]
4
3
2
1
FBA_D[0..63] FBA_CMD[0..31]
+1.8V_RUN_GFX Source +1.8V_RUN_GFX QV7 PMV45EN_SOT23-3~D
D
D
1
2
2 G
D 1 2
1 2
G 3
2 3 4
S
1 1 2 6 1
C
S
S
4
3.3V_RUN_GFX_ON#
2
4 1
2
1
1
B
+1.05V_M
8 7 6 5
D
S
2 G
1 2
1
S
2
QV3 +1.05V_PEX_VDD SI4164DY-T1-GE3_SO8~D 1 2 3 1
2
1.05V_RUN_VTT_GFX#_EN
3
D
2 G
1
4
1
1
D
+1.5V_MEM_GFX
+1.05V_RUN_VTT_GFX Source +PWR_SRC_S
2
2 2 G
2
1 2 3
1 2 6 1 S
D
1
2 G
1
2
D
QV1 SI4164DY-T1-GE3_SO8~D 1 2 3
GFX_MEM_VTT_EN
+3.3V_RUN_GFX
3
3
2 G
1
J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33
+1.05V_PEX_VDD 1
+1.5V_MEM_GFX
3
+1.8V_RUN_GFX
FBA_WCK01 FBA_WCK01# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67#
1
CLKA1 CLKA1#
8 7 6 5
1
2
CV132 2200P_0402_50V7K~D
2 1 RV46 60.4_0402_1%~D 2 1 RV61 60.4_0402_1%~D
CLKA0 CLKA0#
AB31 AC31
3
1 2 1 2 1
R30 R31
+1.5V_MEM
RV81 470K_0402_5%~D
5
2
1
CV81 0.1U_0402_10V7K~D
2
1
CV135 1U_0402_6.3V6K~D
CV199 1U_0402_6.3V6K~D
2
1
CV72 22U_0805_6.3V6M~D
+FBA_PLL_AVDD LV7 BLM18PG300SN1D_2P~D +FBA_PLL_AVDD 1 2
1
2
GFX_MEM_VTT_ON
GFX_MEM_VTT_ON# +1.05V_PEX_VDD
2
RV74 20K_0402_5%~D
2
GFX_MEM_VTT_ON# 5
N13M_FCBGA908~D A
+PWR_SRC_S
QV4 SSM3K7002FU_SC70-3~D
FBA_DEBUG0 FBA_DEBUG1 THE FBA_ECKBxx ARE USED ON GK107. NC FBA_WCKB01 ON GF108 AND GF117 FBA_WCKB01_N FBA_WCKB23 FBA_WCKB23_N FBA_WCKB45 FBA_WCKB45_N FBA_WCKB67 FBA_WCKB67_N
1
RV70 20K_0402_5%~D
FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7
K31 FBA_WCK01 L30 FBA_WCK01# H34 FBA_WCK23 J34 FBA_WCK23# AG30 FBA_WCK45 AG31 FBA_WCK45# AJ34 FBA_WCK67 AK34 FBA_WCK67#
2
CV46 10U_0603_6.3V6M~D
FBA_WCK01 FBA_WCK01_N FBA_WCK23 FBA_WCK23_N FBA_WCK45 FBA_WCK45_N FBA_WCK67 FBA_WCK67_N
1
3.3V_RUN_GFX_EN
RV73 100K_0402_5%~D
+1.5V_MEM_GFX
FBA_CLK1 FBA_CLK1_N
4
+1.5V_MEM_GFX Source +3.3V_ALW2
QV13 SSM3K7002FU_SC70-3~D RV130 39_0402_5%~D +3.3V_RUN_GFX_CHG
@ CV128 0.01U_0402_16V7K~D
@ RV78
2
R28 AC28
FB_CLAMP
FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7
QV12 RV129 SSM3K7002FU_SC70-3~D 39_0402_5%~D +1.05V_PEX_VDD_CHG
+FB_VREF
E1
FBA_CLK0 FBA_CLK0_N
FB_DLL_AVDD
QV6A DMN66D0LDW-7_SOT363-6~D 2 3.3V_RUN_GFX_ON
QV11 RV128 SSM3K7002FU_SC70-3~D 39_0402_5%~D +1.5V_MEM_GFX_CHG
2
CV82 0.1U_0402_10V7K~D
16mil
K27
R32 AC32
FBA_PLL_AVDD FB_VREF
3.3V_RUN_GFX_ON# 5
QV10 RV127 SSM3K7002FU_SC70-3~D 39_0402_5%~D +1.8V_RUN_GFX_CHG
@RV77 @ RV77
1.1K_0402_1%~D 1.1K_0402_1%~D
1+FBA_PLL_AVDD
FBA_CMD_RFU0 FBA_CMD_RFU1
6 5 2 1
RV91 100K_0402_5%~D
CV45 10U_0603_6.3V6M~D
H26
M31 G31 E33 M33 AE31 AK30 AN33 AF33
QV5 +3.3V_RUN_GFX SI3456DDV-T1-GE3_TSOP6~D
CV129 2200P_0402_50V7K~D
+FB_VREF
RV92 100K_0402_5%~D
M30 H30 E34 M34 AF30 AK31 AM34 AF32
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
+3.3V_ALW
RV80 470K_0402_5%~D
+1.5V_MEM_GFX
U27
+PWR_SRC_S +3.3V_ALW2
QV2B DMN66D0LDW-7_SOT363-6~D
+FBA_PLL_AVDD
for Test/Debug
+3.3V_RUN_GFX Source
QV2A DMN66D0LDW-7_SOT363-6~D
B
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
RAS# CAS# WE# CS# ABI# A0_A10 A1_A9 A2_BA0 A3_BA3 A4_BA2 A5_BA1 A6_A11 A7_A8 A12_FRU CKE# RESET#
RV69 100K_0402_5%~D
RV72 10K_0402_5%~D
RST_L*
P30 F31 F34 M32 AD31 AL29 AM32 AF34
CMD28 CMD31 CMD21 CMD16 CMD24 CMD26 CMD27 CMD18 CMD17 CMD19 CMD20 CMD23 CMD22 CMD25 CMD30 CMD29
2
Memory
RV67 100K_0402_5%~D
FBA_CMD13
FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7
CMD12 CMD15 CMD5 CMD0 CMD8 CMD10 CMD11 CMD2 CMD1 CMD3 CMD4 CMD7 CMD6 CMD9 CMD14 CMD13
1
2 1 2
RV71 10K_0402_5%~D
RST_H*
2 1.05V_RUN_VTT_GFX#_EN_R 0_0402_5%~D
RV90 20K_0402_5%~D
FBA_CMD29
1.05V_RUN_VTT_GFX#_EN 1 RV95
CV186 3300P_0402_50V7K~D
C
FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31
RV94 1M_0402_5%~D
FBA_CMD14
U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31
CV49 10U_0603_6.3V6M~D
CKE_L
FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31
QV6B DMN66D0LDW-7_SOT363-6~D
RV68 10K_0402_5%~D
1
+1.5V_MEM_GFX
Part 2 of 7
2
FBA_CMD30
FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
1
CKE_H
L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33
MEMORY INTERFACE A
1 2
RV66 10K_0402_5%~D
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
RV96 20K_0402_5%~D
1
GDDR5 CMD Mapping Table
1
D
3
UV1B
CV50 10U_0603_6.3V6M~D
+1.5V_MEM_GFX
2
FBA_EDC[0..7]
1
+1.8V_RUN FBA_EDC[0..7]
2
1
FBA_DBI[0..7]
2
FBA_DBI[0..7]
S
FBA_CMD[0..31]
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
www.vinafix.vn 3
2
Title
N12P Memory Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
49
of
66
5
4
3
2
1
CHANNEL-B NOT TO USE, NEED TO BE DISABLED UV1C D
D
Part 3 of 7
C
B
+FBA_PLL_AVDD +FBA_PLL_AVDD
+1.5V_MEM_GFX
G14 G20
2 1 RV63 60.4_0402_1%~D 2 1 RV62 60.4_0402_1%~D
2
H17
FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31 FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7 FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7 FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7 FBB_CMD_RFU0 FBB_CMD_RFU1
D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17
C
E11 E3 A3 C9 F23 F27 C30 A24 D9 E4 B2 A9 D22 D28 A30 B23 D10 D5 C3 B9 E23 E28 B30 A23 C12 C20 B
FBB_CLK0 FBB_CLK0_N FBB_PLL_AVDD FBB_CLK1 FBB_CLK1_N
CV83 0.1U_0402_10V7K~D
1
FBB_D00 FBB_D01 FBB_D02 FBB_D03 FBB_D04 FBB_D05 FBB_D06 FBB_D07 FBB_D08 FBB_D09 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63
MEMORY INTERFACE B
G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26
FBB_WCK01 FBB_WCK01_N FBB_WCK23 FBB_WCK23_N FBB_WCK45 FBB_WCK45_N FBB_WCK67 FBB_WCK67_N
FBB_DEBUG0 FBB_DEBUG1 THE FBA_ECKBxx ARE FBB_WCKB01 USED ON GK107. FBB_WCKB01_N NC ON GF108 AND FBB_WCKB23 GF117 FBB_WCKB23_N FBB_WCKB45 FBB_WCKB45_N FBB_WCKB67 FBB_WCKB67_N
D12 E12 E20 F20 F8 E8 A5 A6 D24 D25 B27 C27 D6 D7 C6 B6 F26 E26 A26 A27
N13M_FCBGA908~D
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
www.vinafix.vn 3
2
Title
N12P Memory (2) Size
Document Number
Date:
Friday, May 20, 2011
Rev 0.1
LA-7782 Sheet 1
50
of
66
5
4
3
2
64X32 GDDR5
Memory Partition A - Lower 32 NORMAL bits
1
MIRROR
UV5 MF=0
MF=1
MF=1
MF=0
UV4
MF=0
FBA_EDC0
???
FBA_EDC2
MF=1
C2 C13 R13 R2
EDC0 EDC1 EDC2 EDC3
EDC3 EDC2 EDC1 EDC0
D2 D13 P13 P2
DBI0# DBI1# DBI2# DBI3#
DBI3# DBI2# DBI1# DBI0#
FBA_DBI2
CLKA0 CLKA0#
RV105 40.2_0402_1%~D 1 2 1 2 RV106 40.2_0402_1%~D
2
C
FBA_CMD9
J5
FBA_CMD6 FBA_CMD7 FBA_CMD4 FBA_CMD3
K4 K5 K10 K11
FBA_CMD1 FBA_CMD2 FBA_CMD11 FBA_CMD10
H10 H11 H5 H4
CLKA0#
A5 U5
CV165 0.01U_0402_16V7K~D
1
CLKA0
FBA_CMD14
J12 J11 J3
RV17 RV22 RV108
2 1K_0402_1%~D 2 1K_0402_1%~D 2 121_0402_1%~D
1 1 1
J1 FBA_SEN0J10 J13
FBA_CMD8 FBA_CMD12 FBA_CMD0 FBA_CMD15 FBA_CMD5
FBA_WCK01# FBA_WCK01
549_0402_1%~D +FBA_VREFC_L
1 FBVREF_ALTV
D
3
SGRAM GDDR5
S
QV8 SSM3K7002FU_SC70-3~D
2 G
H5GQ2H24MFR-T2C
5
4
A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14
+FBA_VREFC_L
A10 U10 J14
FBA_CMD13
1
2
1
2
1
2
1
2
1
2
1
2
+1.5V_MEM_GFX
1
2
1
2
1
2
1
2
J2
1
2
CV151 0.1U_0402_10V7K~D
931_0402_1% A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS170-BALL
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
P5 P4
CV155 0.1U_0402_10V7K~D
549_0402_1%~D RV114 2 1
H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
D5 D4
FBA_WCK01# FBA_WCK01 +FBA_VREFD_L
CV154 0.1U_0402_10V7K~D
1
931_0402_1% RV113 2 1
G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14
FBA_WCK01# FBA_WCK01
J4 G3 G12 L3 L12
FBA_WCK23# FBA_WCK23
CV143 0.1U_0402_10V7K~D
CV208 CV207 820P_0402_50V7K~D 820P_0402_50V7K~D 2 1 2 1 RV110 RV109 1.33K_0402_1%~D 1.33K_0402_1%~D
RESET#
J1 J10 J13
G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14
H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14
A8/A7 A11/A6 BA1/A5 BA2/A4
A10/A0 A9/A1 BA3/A3 BA0/A2
BA3/A3 BA0/A2 A9/A1 A10/A0
BA1/A5 BA2/A4 A11/A6 A8/A7
VPP/NC VPP/NC
FBA_CMD[0..31]
FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31
FBA_D[0..31]
FBA_DBI[0..3]
FBA_DBI[0..3]
FBA_EDC[0..3]
FBA_EDC[0..3]
D
FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15
+1.5V_MEM_GFX
MF SEN ZQ ABI# RAS# CS# CAS# WE#
CAS# WE# RAS# CS#
WCK01# WCK01
WCK23# WCK23
WCK23# WCK23
WCK01# WCK01
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFD VREFD VREFC
RESET#
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS170-BALL SGRAM GDDR5
B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14
C
1
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn
2
1
2
1
2
1
2
1
2
1
2
B
A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
H5GQ2H24MFR-T2C
3
FBA_CMD[0..31]
FBA_D[0..31]
CV182 0.1U_0402_10V7K~D
VREFD VREFD VREFC
A5 U5
A12/RFU/NC
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
CV179 0.1U_0402_10V7K~D
WCK01# WCK01
J5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CV140 0.1U_0402_10V7K~D
WCK23# WCK23
WCK23# WCK23
CK CK# CKE#
H10 H11 H5 H4
FBA_WCK23# FBA_WCK23
CV131 1U_0402_6.3V6K~D
2
WCK01# WCK01
J12 J11 J3
FBA_CMD4 FBA_CMD3 FBA_CMD7 FBA_CMD6
CV142 0.1U_0402_10V7K~D
2
RV112 1
CAS# WE# RAS# CS#
DBI3# DBI2# DBI1# DBI0#
K4 K5 K10 K11
FBA_SEN0 2 RV107 121_0402_1%~D FBA_CMD8 FBA_CMD15 FBA_CMD5 FBA_CMD12 FBA_CMD0
CV141 0.1U_0402_10V7K~D
2
2
1
+1.5V_MEM_GFX
RV111
ABI# RAS# CS# CAS# WE#
B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14
DBI0# DBI1# DBI2# DBI3#
FBA_CMD10 FBA_CMD11 FBA_CMD1 FBA_CMD2
1
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
D2 D13 P13 P2
RV19 1K_0402_1%~D 1 2
+1.5V_MEM_GFX
CV130 1U_0402_6.3V6K~D
+FBA_VREFD_L
1
CV153 0.1U_0402_10V7K~D
2
J2
MF SEN ZQ
EDC3 EDC2 EDC1 EDC0
FBA_CMD9 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23
+1.5V_MEM_GFX
+1.5V_MEM_GFX
CV152 0.1U_0402_10V7K~D
2
1
CV177 1U_0402_6.3V6K~D
1
CV176 1U_0402_6.3V6K~D
2
CV41 10U_0603_6.3V6M~D
1
FBA_CMD13
VPP/NC VPP/NC
CLKA0 CLKA0# FBA_CMD14
CV188 1U_0402_6.3V6K~D
B
A10 U10 J14
BA1/A5 BA2/A4 A11/A6 A8/A7
FBA_DBI1
CV178 1U_0402_6.3V6K~D
2
P5 P4
BA3/A3 BA0/A2 A9/A1 A10/A0
FBA_DBI3
CV42 10U_0603_6.3V6M~D
+FBA_VREFC_L 1
FBA_WCK23# FBA_WCK23
A10/A0 A9/A1 BA3/A3 BA0/A2
FBA_EDC1
EDC0 EDC1 EDC2 EDC3
CV139 0.1U_0402_10V7K~D
2
D5 D4
A8/A7 A11/A6 BA1/A5 BA2/A4
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7
C2 C13 R13 R2
CV138 1U_0402_6.3V6K~D
+FBA_VREFD_L 1
FBA_WCK01# FBA_WCK01
A12/RFU/NC
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
???
CV137 1U_0402_6.3V6K~D
FBA_WCK23# FBA_WCK23
J4 G3 G12 L3 L12
CK CK# CKE#
FBA_EDC3
MF=0
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
D
FBA_DBI0
MF=1
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
Title
VRAM A Lower Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
51
of
66
5
4
3
2
Memory Partition A - Upper MIRROR 32 bits
1
NORMAL
UV6 MF=0
MF=1
MF=1
MF=0 FBA_CMD[0..31]
UV3
MF=0
FBA_EDC7
???
FBA_EDC5
D
FBA_DBI7 FBA_DBI5
CLKA1 CLKA1#
RV115 40.2_0402_1%~D 1 2 1
1
2
C
CLKA1
+1.5V_MEM_GFX RV34 RV118
FBA_CMD20 FBA_CMD19 FBA_CMD23 FBA_CMD22
H10 H11 H5 H4 A5 U5
FBA_WCK67# FBA_WCK67
J1 FBA_SEN2J10 J13 J4 G3 G12 L3 L12
DBI3# DBI2# DBI1# DBI0#
A12/RFU/NC A8/A7 A11/A6 BA1/A5 BA2/A4
A10/A0 A9/A1 BA3/A3 BA0/A2
BA3/A3 BA0/A2 A9/A1 A10/A0
BA1/A5 BA2/A4 A11/A6 A8/A7
VPP/NC VPP/NC
RESET#
1
D
3
FBVREF_ALTV
S
QV9 SSM3K7002FU_SC70-3~D
2 G
2
1
2
1
2
1
2
2
1
2
1
2
BA1/A5 BA2/A4 A11/A6 A8/A7
VPP/NC VPP/NC
J4 G3 G12 L3 L12
ABI# RAS# CS# CAS# WE#
CAS# WE# RAS# CS#
WCK01# WCK01
WCK23# WCK23
P5 P4
WCK23# WCK23
WCK01# WCK01
A10 U10 J14
1
2
1
2
J2
1
2
G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14
H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14
FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39
FBA_CMD[0..31]
FBA_D[32..63]
FBA_D[32..63]
FBA_DBI[4..7]
FBA_DBI[4..7]
FBA_EDC[4..7]
FBA_EDC[4..7]
FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFD VREFD VREFC
RESET#
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS170-BALL SGRAM GDDR5
H5GQ2H24MFR-T2C
B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14
C
1
2
1
2
1
2
1
2
1
2
1
2
A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14
B
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
H5GQ2H24MFR-T2C
5
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn 3
D
+1.5V_MEM_GFX
D5 D4
+1.5V_MEM_GFX
1
BA3/A3 BA0/A2 A9/A1 A10/A0
MF SEN ZQ
CV156 0.1U_0402_10V7K~D
A
1
A10/A0 A9/A1 BA3/A3 BA0/A2
FBA_WCK67# FBA_WCK67
CV162 0.1U_0402_10V7K~D
SGRAM GDDR5
2
A8/A7 A11/A6 BA1/A5 BA2/A4
J1 J10 J13
FBA_CMD29
1
A12/RFU/NC
FBA_WCK45# FBA_WCK45
CV144 0.1U_0402_10V7K~D
549_0402_1%~D +FBA_VREFC_H
A5 U5
+FBA_VREFC_H
CV159 0.1U_0402_10V7K~D
931_0402_1%
H10 H11 H5 H4
CV146 0.1U_0402_10V7K~D
549_0402_1%~D RV124 2 1
FBA_CMD17 FBA_CMD18 FBA_CMD27 FBA_CMD26
+FBA_VREFD_H
CV133 1U_0402_6.3V6K~D
1
931_0402_1% RV123 2 1
J5
FBA_WCK67# FBA_WCK67
CV145 0.1U_0402_10V7K~D
2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS170-BALL
A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14
CK CK# CKE#
K4 K5 K10 K11
FBA_WCK45# FBA_WCK45
CV134 1U_0402_6.3V6K~D
RV122 1
H1 K1 B5 G5 L5 T5 B10 D10 G10 L10 P10 T10 H14 K14
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
J12 J11 J3
FBA_CMD22 FBA_CMD23 FBA_CMD20 FBA_CMD19
FBA_SEN2 2 RV117 121_0402_1%~D FBA_CMD24 FBA_CMD28 FBA_CMD16 FBA_CMD31 FBA_CMD21
CV189 1U_0402_6.3V6K~D
+1.5V_MEM_GFX
RV121 2
2
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
DBI3# DBI2# DBI1# DBI0#
FBA_CMD25
1
B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14
DBI0# DBI1# DBI2# DBI3#
RV65 1K_0402_1%~D 1 2
CV180 1U_0402_6.3V6K~D
+FBA_VREFD_H
2
1
CV158 0.1U_0402_10V7K~D
2
1
CV157 0.1U_0402_10V7K~D
2
1
CV192 1U_0402_6.3V6K~D
2
1
CV191 1U_0402_6.3V6K~D
CV43 10U_0603_6.3V6M~D
1
FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47
CV44 10U_0603_6.3V6M~D
B
FBA_DBI6 CLKA1 CLKA1# FBA_CMD30
D2 D13 P13 P2
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
CV185 0.1U_0402_10V7K~D
VREFD VREFD VREFC
+1.5V_MEM_GFX
G1 L1 G4 L4 C5 R5 C10 R10 D11 G11 L11 P11 G14 L14
FBA_DBI4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CV181 0.1U_0402_10V7K~D
WCK01# WCK01
FBA_EDC6
EDC3 EDC2 EDC1 EDC0
CV150 0.1U_0402_10V7K~D
WCK23# WCK23
+FBA_VREFC_H 1
2
FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
EDC0 EDC1 EDC2 EDC3
CV147 0.1U_0402_10V7K~D
WCK23# WCK23
P5 P4
J2
A4 A2 B4 B2 E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2
C2 C13 R13 R2
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CV148 1U_0402_6.3V6K~D
WCK01# WCK01
FBA_WCK45# FBA_WCK45
FBA_CMD29
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
CAS# WE# RAS# CS#
D5 D4
A10 U10 J14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
???
+1.5V_MEM_GFX
MF SEN ZQ ABI# RAS# CS# CAS# WE#
FBA_EDC4
MF=0
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
EDC3 EDC2 EDC1 EDC0
FBA_WCK67# FBA_WCK67
+FBA_VREFD_H
CV210 CV209 820P_0402_50V7K~D 820P_0402_50V7K~D 2 1 2 1 RV120 RV119 1.33K_0402_1%~D 1.33K_0402_1%~D
MF=1
CV149 1U_0402_6.3V6K~D
FBA_WCK45# FBA_WCK45
2
CK CK# CKE#
J5
FBA_CMD24 FBA_CMD31 FBA_CMD21 FBA_CMD28 FBA_CMD16
1
J12 J11 J3
K4 K5 K10 K11
2 1K_0402_1%~D 2 121_0402_1%~D
1 1
DBI0# DBI1# DBI2# DBI3#
FBA_CMD26 FBA_CMD27 FBA_CMD17 FBA_CMD18
RV64 1K_0402_1%~D 1 2
EDC0 EDC1 EDC2 EDC3
D2 D13 P13 P2
FBA_CMD25
CLKA1#
CV190 0.01U_0402_16V7K~D
2 RV116 40.2_0402_1%~D
FBA_CMD30
C2 C13 R13 R2
MF=1
2
Title
VRAM A Upper Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
52
of
66
5
4
3
2
1
+COINCELL
ESD Diodes
1 PL1 FBMJ4516HS720NT_2P~D 1 2
GND GND
BAY_SMBCLK BAY_SMBDAT
7 8
PAD-OPEN 1x2m~D
JRTC1
Z4012
MPBATT+
1 2
+COINCELL
1 G 2 G
3 4 D
TYCO_2-1775293-2~D
2
PR5 100_0402_5%~D 1 2
1
3
Z5304 Z5305 Z5306
PR4 100_0402_5%~D 1 2
PJP1
+RTC_CELL MODULE_BATT_PRES#
PD4
1
1 2 3 4 5 6
PC1 0.1U_0603_25V7K~D 2 1
PC2 2200P_0402_50V7K~D 2 1
1 2 3 4 5 6
PR3 100_0402_5%~D 1 2
PR1 1K_0402_5%~D
+3.3V_RTC_LDO
PR2 100K_0402_5%~D 2 1
@ 2
MBATT+_C MBATT1
D
+3.3V_ALW
2
1 2
3
2
Media Bay Battery Connector
@ PD2 PESD24VS2UT_SOT23-3~D
3
1
COIN RTC Battery @ PD1 PESD24VS2UT_SOT23-3~D
RB715FGT106_UMD3
1
SUYIN_150010GR006M500ZR
PC3 1U_0603_10V4Z~D
2
ESD Diodes PL2 FBMJ4516HS720NT_2P~D 1 2
@ PD6 PESD24VS2UT_SOT23-3~D
PL3 FBMJ4516HS720NT_2P~D 1 2
PR7 100_0402_5%~D 1 2
Z4304 Z4305 Z4306
PR9 100_0402_5%~D 1 2
PR8 100_0402_5%~D 1 2
PBAT_SMBCLK PBAT_SMBDAT
PC4 0.1U_0603_25V7K~D 2 1
PC5 2200P_0402_50V7K~D 2 1
C
11 10 9 8 7 6 5 4 3 2 1
PJP2 2
PBATT+
PAD-OPEN 1x3m
PR6 100K_0402_5%~D 2 1
@ 1
PBATT+_C GND GND 9 8 7 6 5 4 3 2 1
+3.3V_ALW
3
2
@ PD5 PESD24VS2UT_SOT23-3~D
3
2
Primary Battery Connector
1
1
GND
PBAT_PRES#
C
PBATT1 SUYIN_200275MR009G50PZR
GND
+3.3V_ALW
PR13 33_0402_5%~D 1 2
NO
2 NB_PSID_TS5A63157
IN
GND
3
PQ2 FDV301N_G_NL_SOT23-3~D
V+
NC
COM
6
GPIO_PSID_SELECT
5
+5V_ALW
4
PS_ID
1
1
PQ3 MMST3904-7-F_SOT323~D E
2
3
B
PR17 1
2
PSID_DISABLE#
10K_0402_5%~D
+PWR_SRC_S
+PWR_SRC
2
1VSB_N_003
PR25 0_0402_5% 2VSB_N_002 1
1
PC17 .1U_0402_16V7K
+3.3V_ALW
D
3
1 2
PC15 10U_1206_25V6M~D
PR22 100K_0402_5%~D 2 1
PC14 0.1U_0603_25V7K~D 2 1
SOFT_START_GC
PC12 0.1U_0603_25V7K~D 2 1
1M_0402_5%~D
PL6 FBMA-L18-453215-900LMA90T_1812~D 1 2
2
10K_0402_5%~D
PC11 0.1U_0603_25V7K~D 2 1
1M_0402_5%~D
PR20 2
PC10 0.022U_0805_50V7K~D 1 2
1 PR26
@
PR24 1
2
+DCIN_JACK
@ 2
@ PR23 4.7K_0805_5%~D 2 1
-DCIN_JACK
S
1 2 2
PC8 0.22U_0603_25V7K
1
PQ4 TP0610K-T1-E3_SOT23-3
VSB_N_001
PQ6 SSM3K7002FU_SC70-3
2 G
A
DELL CONFIDENTIAL/PROPRIETARY PC18 0.1U_0603_25V7K~D 2 1
A
PC13 0.1U_0603_25V7K~D 2 1
1 MOLEX_87438-0743 7 7 6 6 5 5 4 4 3 3 2 2 1 1 PJPDC1
PD13 VZ0603M260APT_0603 PC16 0.1U_0603_25V7K~D 2 1
1
PR21 22K_0402_1% 1 2
2
2 1 PR19 100K_0402_1%
PQ5 FDS6679AZ_G_SO8~D 1 8 S D 2 7 S D 3 6 S D 4 5 G D
1
3 +DC_IN_SS
PC9 0.1U_0603_25V7K
@
+DC_IN
+DC_IN
TS5A63157DCKR_SC70-6~D
DC_IN+ Source
PL5 FBMA-L18-453215-900LMA90T_1812~D 1 2
+5V_ALW
C
2 B
PR16 15K_0402_1%~D 1 2
B
3
2 G
PR14 100K_0402_1%~D 1 2
1
PU1 1
DOCK_PSID
PR15 10K_0402_1%~D
D
PL4 BLM18BD102SN1D_0603~D 2 1
NB_PSID
PR12 2.2K_0402_5%~D 1 2
PR11 1 2 0_0402_5%~D
S
@
5
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
www.vinafix.vn 3
2
+DCIN Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
53
of
66
A
B
C
D
E
1
2VREF_6182
1
PJP100 1
PR101 13K_0402_1% 1
2
1
2
PC101 1U_0603_16V6K
2
1
PR102 30.9K_0402_1% 2
PAD-OPEN 1x3m
+DC1_PWR_SRC
+PWR_SRC @ PL100 1UH_PCMB053T-1R0MS_7A_20% 2 1
FB_3V
FB_5V 1
PR104 20K_0402_1% 2
+DC1_PWR_SRC
7
VO1
5
PC118 10U_0805_25V6K 2 1
PC106 10U_0805_25V6K 2 1
PC105 2200P_0402_50V7K 2 1
PC104 0.1U_0402_25V6 2 1
1
3
2 FB1
REF
4
5
VO2
@
24
PQ101 FDMC8884_POWER33-8-5
4
2
1 2 3
2
ENTRIP1
P PAD
PR106 86.6K_0402_1% ENTRIP1 1 2
TONSEL
25 2
4
PC107 10U_0805_6.3V6M
1
PU100
@
FB2
PQ100 FDMC8884_POWER33-8-5
6
PR105 143K_0402_1%~D 1 2 ENTRIP2
ENTRIP2
PR100 0_0402_5% 1 2
5
PC119 10U_0805_25V6K 2 1
PC103 10U_0805_25V6K 2 1
+3.3V_ALW2 PC102 2200P_0402_50V7K 2 1
PC100 0.1U_0402_25V6 2 1
PR103 20K_0402_1% 1 2
+3.3V_RTC_LDO
3 2 1
1 2 1 2
ENTRIP1
ALW_PWRGD_3V_5V
5VALWP TDC 9.044A Peak Current 12.874A OCP current 15.5A
DMN66D0LDW-7 2N_SOT363-6~D 1
4
2
PJP101 1 PR114
1
100K_0402_1% 1 2
4
THERM_STP#
PR115 2K_0402_1%~D 1 2
2 PAD-OPEN 1x3m PJP102
+5V_ALW2
+5V_ALWP
1
2
+5V_ALW
PAD-OPEN 1x3m PJP103
PQ105 PDTC115EU_SOT323-3
+3.3V_ALWP
2
1
2
+3.3V_ALW
PAD-OPEN 1x3m PJP104
PR116 0_0402_5% 1 2
1
3
ALWON
@
3
PC116 0.1U_0603_25V7K
PQ104A 5
+ 2
PR112 100K_0402_1%
6
3 PQ104B DMN66D0LDW-7 2N_SOT363-6~D
1
2
1
1 2
+DC1_PWR_SRC
@
+3.3V_ALW
PC114 4.7U_0805_10V6K
PC113 680P_0603_50V7K
PQ103 FDMC7692S_POWER33-8-5
SNUB_5V
@ 4
1
PD100 PR113 MMSZ5229BS_SOD323~D 499K_0402_1%~D 1 2 2 1
2VREF_6182
3 2 1
+5V_ALWP
PC111 220U_D_6.3VM_R25M
LG_5V
18
17
16
EN
14
13
19
PL102 3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D 1 2
@
+PWR_SRC ENTRIP2
LX_5V
+5V_ALW2
2
2
3.3VALWP TDC 4.729A Peak Current 6.756A OCP current 8.107A
20
RT8205LZQW(2) WQFN 24P PWM
PC115 1U_0603_10V6K 2 1
1
2
PR111 300K_0402_1%
SNUB_3V
4
21
PR110 4.7_1206_5% 2 1
LGATE1
22
BST_5V 1 PR108 2 2.2_0603_5% UG_5V
PC109 0.22U_0603_16V7K BST1_5V 1 2
5
LGATE2
23
NC
PHASE1
VREG5
PHASE2
VIN
UGATE1
GND
12
BOOT1
UGATE2
15
LG_3V
PGOOD
BOOT2
2
@
3
11
VREG3
1 2 3
+
9
UG_3V 10
PQ102 FDMC8878_POWER33-8-5
PC112 680P_0603_50V7K
1
BST_3V
LX_3V 5
PR109 4.7_1206_5%
PC110 220U_D_6.3VM_R25M
+3.3V_ALWP
1
PL101 3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D 1 2
8
SKIPSEL
PC108 0.22U_0603_16V7K BST1_3V 1 PR107 2 1 2 2.2_0603_5%
4
2
PC117 1U_0603_10V6K 2 1
PAD-OPEN 1x3m
Compal Electronics, Inc.
@
A
Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
www.vinafix.vn C
+5V_ALW/+3.3V_ALW Size
Rev 0.1
LA-7782 Date:
D
Document Number Friday, June 10, 2011
Sheet E
54
of
66
5
4
3
2
1
0.75Volt +/- 5% TDC 0.525A Peak Current 0.75A OCP Current 0.9A
1.5Volt +/- 5% TDC 9.74A Peak Current 13.915A OCP current 16.698A +PWR_SRC
PJP200
2
D
1.5V_B+
1
PJP204 PR200 1 2 2.2_0603_5%~D
PAD-OPEN 1x2m~D
BOOT_1.5V
VLDOIN_1.5V
1
D
+1.5V_MEN_P
2
CS
2
GND
3
VTTREF
4
VDDQ
5
Level L L H
+0.75V_P off off on
+V_DDR_REF off on on
C
6
7
S3
FB
PC211 0.033U_0402_16V7~D
@ PR207 0_0402_5%~D 2 1
1.5V_SUS_PW RGD
2
PR205 1M_0402_1%~D 1 2
PR209 0_0402_5%~D
2
S5_1.5V
2
Mode S5 S3 S0
1
+1.5V_MEN_P
PR204 100K_0402_1%~D
1.5V_B+
+V_DDR_REF
+V_DDR_REF
1
+5V_ALW
S5
+3.3V_ALW 1U_0603_10V6K~D
8
VDD
TON
11
9
VDDP
PC210
1.5V_SUS_PW RGD PR206 0_0402_5%~D 1 2
PC206 10U_0805_6.3V6M~D
1
VTTSNS
2
VTT
2
20
19
18 BOOT
21 1
RT8207MZQW _W QFN20_3X3
PGOOD
VDD_1.5V
2
12
10
1
VLDOIN
13
UGATE
PGND
PC207 1U_0603_10V6K~D
+5V_ALW
17
16 14
PAD
VTTGND
CS_1.5V
PR202 5.1_0603_5%~D
4
PHASE LGATE
PC213 @ 0.1U_0402_16V7K~D
1
1
DDR_ON
15
PU200
PC205 10U_0805_6.3V6M~D
0.22U_0603_16V7K~D
2 1
PR201 5.1K_0402_1%~D 1 2
2
@
PQ201 SIR818DP-T1-GE3_POWERPAK8-5 1 2 3 5
PR203 4.7_1206_5%
2
0.1U_0603_25V7K~D
@ PC209 1
+
2
2
+
C
1
1SNUB_1.5V
1
DL_1.5V
4
2
PC208 330U_SX_2VY~D
@ PC214 330U_SX_2VY~D
PL200 1UH 20% FDUE1040D-H-1R0M=P3_21.3A_20%~D 1 2
+0.75V_P
SW _1.5V
1
+1.5V_MEN_P
PC204
PQ200 SIR472DP-T1-GE3_POWERPAK8-5~D 1 2 3 5
1 2
PC203 2200P_0402_50V7K~D
1 2
PC202 0.1U_0402_25V6K~D
2
1
PC201 4.7U_0805_25V6K~D
2
1
PC200 4.7U_0805_25V6K~D
PAD-OPEN1x1m DH_1.5V
PC212 @ 0.1U_0402_16V7K~D
S3_1.5V
PR208 0_0402_5%~D 1 2
0.75V_DDR_VTT_ON
B
B
Note: S3 - sleep ; S5 - power off
+1.5V_MEN_P PJP201
2
2
1
1
JUMP_1x3m PJP203
+1.5V_MEN_P
PJP202
2
2
1
1
+1.5V_MEM
+0.75V_P
1
2
+0.75V_DDR_VTT
JUMP_1x3m PAD-OPEN1x1m
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
www.vinafix.vn 3
2
+1.5V_MEN/+0.75V_DDR_VTT Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
55
of
66
A
B
C
D
PR300
1
2
1
10K_0402_5%~D 1.8V_RUN_PWRGD
2
1
PC306 47P_0402_50V8J~D
2
1 2
PC303 22U_0805_6.3VAM
1 2
SNUB_1.8VSP
1
PC302 22U_0805_6.3VAM
NC 7
11 1
PR305 10K_0402_1%
@
1
2
PR306 0_0402_5%
SYN470DBC_DFN10_3X3
PC305 680P_0603_50V7K
1
SIO_SLP_S3#
2
@PR304 @ PR304 47K_0402_5%
2
@PR303 @ PR303 0_0402_5%
PC304 0.1U_0402_10V7K
EN_1.8VSP 1
RUN_ON
2
PR302 20K_0402_1%
@
2
1
PC301 22P_0402_50V8J 2 1
1.8VSP_FB
1
6
2
FB
2
EN
+1.8V_RUNP
1
5
3
2
2
SVIN
LX
1
8
LX
1.8VSP_LX
PR301 4.7_0805_5%~D
PVIN
2
NC
1
PC307 0.1U_0603_25V7K~D
PVIN
9
2
PC300 22U_0805_6.3VAM
2
1
PAD-OPEN 1x2m~D
10
PG
1.8VSP_VIN
1
TP
2
PL301 1UH_PH041H-1R0MS_3.8A_20% 1 2
4
PU300 PJP301
+3.3V_ALW
1
1.8Volt +/-5% TDC 0.85A Peak Current 1.215A OCP current 1.458A
+3.3V_RUN
@
VFB=0.6V Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V
3
3
PJP300
+1.8V_RUNP
2
1
+1.8V_RUN
PAD-OPEN 1x2m~D
DELL CONFIDENTIAL/PROPRIETARY
4
4
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.8V_RUN Size
B
C
www.vinafix.vn
Rev 0.1
LA-7782 Date:
A
Document Number Friday, June 10, 2011
Sheet D
56
of
66
5
4
3
2
1
PJP400 +V1.05SP_B+
2
1
+PWR_SRC
PC400 4.7U_0805_25V6K
1 2
PR400 100K_0402_1%~D 2 1
3 2 1 DRVH
9
UG_+V1.05SP
SW
8
SW_+V1.05SP
VFB
V5IN
7
RF
DRVL
6
3
EN
FB_+V1.05SP
4
RF_+V1.05SP
5
PL400 1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D 1 2
+1.05V_MP
5
TRIP
EN_+V1.05SP
1
1
PC406 220U_D2_4VM
+5V_ALW
LG_+V1.05SP
PC405 1U_0603_6.3V6M
@PR404 @ PR404 4.7_1206_5%
4 PQ401 FDMC7692S_POWER33-8-5
1
3 2 1
1
2
TPS51212DSCR_SON10_3X3
2
1
TP
11
2
C
10
2
PQ400 FDMC8884_POWER33-8-5
BST_+V1.05SP
VBST
PGOOD
TRIP_+V1.05SP
S0 mode be high level @ PC407 0.1U_0402_16V7K
PC404 0.1U_0603_25V7K 1 2
PU400 1
PR403 0_0402_5% 1 2
SIO_SLP_A#
D
4 PR401 2.2_0603_5% 1 2
1.05V_A_PWRGD PR402 60.4K_0402_1% 1 2
PC403 4.7U_0805_25V6K 2 1
+3.3V_ALW D
PC402 2200P_0402_50V7K 2 1
5
PC401 0.1U_0402_25V6 2 1
PAD-OPEN 1x2m~D
PR405 470K_0402_1%
1 + 2 C
@PC408 @ PC408
2
2
1000P_0603_50V7K
PR406
2
4.99K_0402_1% 2 1
+1.05Volt +/- 5% TDC 4.7A Peak Current 6.5A OCP current 7.8A
PJP401 PR407 10K_0402_1%
2
1
PAD-OPEN 1x2m~D
1
B
+1.05V_MP
PJP402 2
1
B
+1.05V_M
PAD-OPEN 1x2m~D
DELL CONFIDENTIAL/PROPRIETARY
A
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05V_M Size
4
3
www.vinafix.vn
2
Rev 0.1
LA-7782 Date:
5
Document Number Friday, June 10, 2011
Sheet 1
57
of
66
A
5
4
3
2
1
PJP500 +V1.05S_VCCPP_B+
2
1
+PWR_SRC
1
PR502 2.2_0603_5% 1 2
1.05V_VTTPWRGD
PC504 0.1U_0603_25V7K 1 2
1 2
PC500 4.7U_0805_25V6K
PQ500 FDMC8884_POWER33-8-5
PC503 4.7U_0805_25V6K 2 1
PR500 100K_0402_5%
PC501 0.1U_0402_25V6 2 1
D
5
2
+3.3V_RUN
PC502 2200P_0402_50V7K 2 1
PAD-OPEN 1x2m~D
D
4
PU500
SW_+V1.05S_VCCPP
VFB
V5IN
7
RF
DRVL
6
FB_+V1.05S_VCCPP
4
RF_+V1.05S_VCCPP
5
PL500 1UH_FDVE0630-H-1R0M-P3_11.9A_20%~D 1 2
+1.05VTTP
+5V_ALW
LG_+V1.05S_VCCPP
PC505 1U_0603_6.3V6M
@ PR504 4.7_1206_5% 2
2
TPS51212DSCR_SON10_3X3
1
1 PR505 470K_0402_1%
1
2
4
+ 2 C
@ PC508 1000P_0603_50V7K
3 2 1
2
PQ501 FDMC7692S_POWER33-8-5
@ PC510 .1U_0402_16V7K
1
2
C
11
PC507 220U_D2_4VM
8
EN
1
UG_+V1.05S_VCCPP
SW
TRIP
3
3 2 1
DRVH
9
TP 2
@ PC506 0.1U_0402_16V7K
10
1
1
CPU_VTT_ON
BST_+V1.05S_VCCPP
VBST
PGOOD
2
EN_+V1.05S_VCCPP
PR503 0_0402_5% 1 2
1
5
PR501 84.5K_0402_1%~D 1 2 TRIP_+V1.05S_VCCPP
Local sense put on HW site PR507 4.32K_0402_1% 2 1
PR508 0_0402_5% 2 1
VTT_SENSE_FB
VTT_SENSE
PR513 0_0402_5% 2 1
VSSIO_SENSE_R
1
VSSIO_SENSE_R_FB
+3.3V_RUN
PR509 71.5K_0402_1% B
B
2
2
2
VCCP_PWRCTRL = "High" , VCCP_PWRCTRL = "Low" ,
PR510 10K_0402_1%
Vo = 1.05V (SNB) Vo = 1V (IVB)
PR511 10K_0402_5% 1 1
D
2 G
VCCP_PWRCTRL
PC509 .01U_0402_16V7K~D 2 1
S
3
PQ502 1 2
@PR514 @ PR514 10_0402_1%~D
SSM3K7002FU_SC70-3
1
+1.05Volt +/- 2% TDC 6A Peak Current 8.5A OCP current 10.2A
From GPIO
@
PJP501 2
1
PAD-OPEN 1x2m~D A
PJP502
+1.05VTTP
2
1
DELL CONFIDENTIAL/PROPRIETARY
+1.05V_RUN_VTT
Compal Electronics, Inc.
PAD-OPEN 1x2m~D Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
www.vinafix.vn
2
+1.05V_RUN_VTT Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
58
of
66
A
4
3
2
1
VID [0] 0 0 1 1
The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.
D
PR603 100K_0402_5% 1
+3.3V_RUN
PR604 0_0402_5% 1 2
VCCSA_VID_0
SW
23
SW
24
7
VIN
@
@
MODE
TP
25
6
SLEW
VOUT 5
4
GND 1
COMP
@ VREF
+VCCSA_PWR_SRC
PAD-OPEN 1x2m
3
+VCCSA_PWR_SRC
@ PC604 1000P_0603_50V7K
8
VIN
2
2
9
C
PC612 22U_0805_6.3V6M 1 2
SW
1 2
TPS51461RGER_QFN24_4X4~D VIN
+VCCSA_P PC611 22U_0805_6.3V6M 1 2
PGND
PJP600 1
10
1
SW
22
1
PL600 0.47UH_FDVE0630-H-R47M=P3_17.7A_20% 1 2
2
1
+VCCSA_PHASE
PGND
21
2
11
PR608 PC603 2.2_0603_1% 0.1U_0603_25V7K 2+VCCSA_BT_1 1 2
PR609 4.7_0805_5%~D
2
10U_0805_25V6M PC615
10U_0805_25V6M PC614
2
0.1U_0603_25V7K PC613 1 2
2200P_0402_50V7K PC600
+3.3V_ALW
1
+VCCSA_BT 1
PC610 2200P_0402_50V7K 2 1
SW
12
PC609 22U_0805_6.3V6M 1 2
14
15
13 EN
VID0
BST
C
20
D
PC607 0.1U_0402_25V6K~D 2 1
PGND
VID1
16
V5FILT
19
PGOOD
V5DRV
PU600
1.05V_VTTPWRGD
PC606 22U_0805_6.3V6M 1 2
17
PR607 0_0402_5% 1 2
+VCCSA_EN
PC602 2.2U_0603_10V7K 1 2
PC605 22U_0805_6.3V6M 1 2
1
18
2 PR606 10_0402_1% 2 1
PC601 1U_0603_10V6K
+5V_ALW
VCCSA Vout 0.9V 0.8V 0.725V 0.675V
VCCSA TDC 4.2A Peak Current 6A OCP current 7.2A
PR605 1K_0402_5% 2 1
+VCCSA_PWRGD
VCCSAPWROK
VCCSA_VID_1
VID[1] 0 1 0 1
output voltage adjustable network
2
PR600 0_0402_5% 2 1
PR601 1K_0402_5% 2 1 PR602 0_0402_5% 1 2
PC608 22U_0805_6.3V6M 1 2
5
@ PR610 2
1
33K_0402_5%
2
GNDA_VCCSA
PR611 100_0402_5% 2 1
PC616 1
0.22U_0402_10V6K
PC617 3300P_0402_50V7K
B
1
2
PR612 0_0402_5% 2 1
1
PR613 5.1K_0402_1%~D
PC618 0.01U_0402_25V7K 1 2
2
VCCSA_SENSE
B
PJP601
+VCCSA_P
1
2
PAD-OPEN 1x3m
+VCC_SA
PJP602 2
1 PAD-OPEN1x1m
GNDA_VCCSA
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+VCC_SA Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
59
of
66
4
3
2
2
3.57K_0402_1%
PC703 1
PR703 267K_0402_1%
PR704 330P_0402_50V7K~D
2
499_0402_1%~D
PC706 1 2
VSS_AXG_SENSE
PC704 2 1
1
1
390P_0402_50V7K
VCC_core TDC 52A Peak Current 94A OCP current 116A Load line -1.9mV/A FSW=400kHz
PC702 2 1
1
150P_0402_50V8F~D
1
@
2
1
PC705 2
47P_0402_50V8J~D
42.2K_0402_1%~D
PR702
2
PR705
Local sense put on HW site
VCC_AXG_SENSE
1
PR701 PC701 2K_0402_1% 330P_0402_50V7K~D 2 1 2 1
2
5
0.01U_0402_50V7K D
D
+5V_RUN
PR736 27.4K_0402_1% 2 1
PR737 2
UGATE2
75_0402_5% 1 ALERT#
PR746 2
130_0402_1% SDA 1
2
PC733 2 1
VSUM-
2
PC766 1
PC736 2 PC738 2
0.1U_0402_25V6K~D
499_0402_1%~D
47P_0402_50V8J~D
1 0.22U_0402_6.3V6K PR749
1 0.22U_0402_6.3V6K
2
PR750
1
1
LGATE2
B
PC734 2
2
1
2
PR751 5.76K_0402_1% 1 2
PC737 1
267K_0402_1% 150P_0402_50V8F~D PR753 PC739 2K_0402_1% 680P_0402_50V7K~D 1 2 1 2
UGATE1
330P_0402_50V7K PC748 1 2
VCCSENSE
VSSSENSE
PHASE1
2
1
Local sense put on HW site PC751
2
649_0402_1%~D 2200P_0402_25V7K~D
1
1 2
2
PC749 0.22U_0603_16V7K LGATE1
@
PC767 2200P_0402_50V7K~D 1 2
PC724
100U_25V_M
PC723
100U_25V_M
PC722
100U_25V_M
PC768 2200P_0402_50V7K~D 1 2
PL701 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
+VCC_CORE
PR761 ISEN1 1 10K_0603_1%
2
@PR762 @ PR762 2 1 10K_0402_1%
ISEN2
@PR765 @ PR765 2 1 10K_0402_1%
ISEN3
PR766 VSUM-
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
PR752 1 1_0402_5%
PR764 VSUM+ 1 2 3.65K_0603_1%
@
DELL CONFIDENTIAL/PROPRIETARY
4
ISEN3
@
@
5
@ PR748 2 1 10K_0402_1%
2
P1_SW
PR760 4.7_1206_5% 2 1
2 1 523_0402_1%
@PR763 @ PR763
7 6 5
3 4
PR758 BOOT1 2 1 1 4.7_0603_5%~D
+
2
2
0.01U_0402_50V7K PR759
@
1
PQ701 CSD87351Q5D_SON8~D
PC744
2
2
1
B
PR747 VSUM+ 1 2 3.65K_0603_1%
+VCC_PWR_SRC
8
1 2
0.068U_0402_16V7K
1
0.22U_0603_10V7K
PC746 2
@ PC747
1
0.01UF_0402_25V7K
PC745 2
1 11K_0402_1% 2 PR756
1
+
@ PR743 2 1ISEN1 10K_0402_1%
2
VSUM-
PC774 2200P_0402_50V7K~D 1 2
A
10KB_0402_5%_ERTJ0ER103J
PR755 2.61K_0402_1% 12 1 PH703
2
PC750 .1U_0402_16V7K 2 1
VSUM-
PR742 ISEN2 1 10K_0603_1%
@
VSUM+ @
2
1
@
@ 3.57K_0402_1%
1 0.22U_0402_6.3V6K
+
+VCC_CORE
PC743 0.1U_0402_25V6K~D 2 1
PR744 2
2
PC731 0.22U_0603_16V7K
PC732 PR745 390P_0402_50V7K 1 2 1
PC742 10U_0805_25V6K 2 1
@
0_0402_5% 2
1
PL702 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
P2_SW
PC752 680P_0603_50V7K
+5V_RUN
4 PR738 BOOT2 2 1 1 4.7_0603_5%~D
2
@ PR741 1
SCLK
7 6 5
3
PC741 10U_0805_25V6K 2 1
1
@
PR729 1 1_0402_5%
2
PC773 2200P_0402_50V7K~D 1 2
2
VSUM2
C
@ PR724 2 1ISEN2 10K_0402_1%
PR725 1 2 3.65K_0603_1%
+3.3V_RUN
@ PC730 10P_0402_25V8J COMP 2 1
54.9_0402_1%
1
PQ702 CSD87351Q5D_SON8~D
PHASE2 PR739
2 +VCC_PWR_SRC
IMVP_PWRGD 1.91K_0402_1% 1
VSUM+
PC769 2200P_0402_50V7K~D 1 2
0_0402_5% 2
@ PR717 2 1ISEN1 10K_0402_1%
2
@
PC728 0.1U_0402_25V6K~D 2 1
PR735 1
+VCC_CORE
@
BOOT1
+PWR_SRC
2 PAD-OPEN 1x3m
PR720 ISEN3 1 10K_0603_1%
PC727 10U_0805_25V6K 2 1
ISL95836HRTZ-T_TQFN40_5X5~D
@
1_0402_1%~D
PC719 680P_0603_50V7K
2
PR719 4.7_1206_5% 2 1
PR723
0_0402_5%~D PR728 2 1
PJP700
1
PL703 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
P3_SW
PC726 10U_0805_25V6K 2 1
+5V_RUN
1
UGATE1
7 6 5
3 4
LGATE1
@
9
@PR718 @ PR718 0_0402_5%~D 1 2
PWM3
PC700 0.1U_0402_25V6K~D 2 1
2
PC715 10U_0805_25V6K 2 1
PQ703 CSD87351Q5D_SON8~D
LGATE3
PC714 10U_0805_25V6K 2 1
PHASE3
4
ISL6208CRZ-T_QFN8_3X3
VCCP
PHASE1
PC713 10U_0805_25V6K 2 1
UGATE3
7
1
1
8
PC735 680P_0603_50V7K
1 PH702 470K_0402_5%_ TSM0B474J4702RE
2
PC707 2 1
LGATE2
LGATE PGND
1 2
30 29 28 27 26 25 24 23 22 21
PHASE
PC725 10U_0805_25V6K 2 1
11 12 13 14 15 16 17 18 19 20
2
3.83K_0402_1%
PHASE2
BOOT2 UGATE2 PHASE2 LGATE2 VCCP VDD PWM3 LGATE1 PHASE1 UGATE1
PWM
PC740 10U_0805_25V6K 2 1
2
ISEN3 ISEN2 ISEN1
1 2
PR734
1
PR716
2
TP
2 0_0402_5%
2
0_0402_5%
PC729 43P_0402_50V8J
+1.05V_RUN_VTT
1 PR732
1.05V_0.8V_PWROK
41
UGATE2
0_0402_5%~D
ISUMPG ISEN1G ISEN2G NTCG SCLK ALERT# SDA VR_HOT# VR_ON NTC
BOOT2
UGATE
GND
1
BOOT
FCCM
PR740 4.7_1206_5% 2 1
VR_EN NTC
SDA
VR_HOT# 2 0_0402_5% @PR731 @ PR731 0_0402_5% IMVP_VR_ON 1 2 @ PR733 1
PWM3_12
VCC
8
0_0402_5% 2 0_0402_5% 2 0_0402_5% 2
1 2 3 4 5 6 7 8 9 10
ISEN1G ISEN2G NTCG SCLK ALERT#
1 PR730
H_PROCHOT#
6
1
VIDSOUT
5
8
VIDALERT_N
PC772 2200P_0402_50V7K~D 1 2
PR722 1 PR726 1 PR727 1
VIDSCLK
BOOT1G
PC712 0.22U_0603_16V7K
1U_0603_10V6K
PR721 1 27.4K_0402_1%
UGATE1G
PU701
PC721 1
2
PC720 1
@ PR715 1 2 0_0402_5%
+5V_RUN
C
PHASE1G
2 1 4.7_0603_5%~D BOOT3
40 39 38 37 36 35 34 33 32 31
PU700
ISEN2G
COMP PGOOD
0.22U_0402_16V7K~D 2 1 PH701 470K_0402_5%_ TSM0B474J4702RE
2
3
ISUMNG RTNG FBG COMPG PGOODG PWM2G LGATE1G PHASE1G UGATE1G BOOT1G
1
LGATE1G
@ PL706 HCB4532KF-800T90_1812 1 2 PR711
2
PGOODG
2
ISEN1G
PWMG2
+VCC_PWR_SRC
1U_0603_10V6K
1
@ PC711 @PC711 3300P_0402_50V7K~D
PR714
3.83K_0402_1%
2 1 0_0603_5%
PR710 @ PR712 @PR712 649_0402_1%~D 1 2
0.22U_0402_16V7K~D PC718 2 1
VSUMG-
IMVP_PWRGD
0_0402_5%
PR713 348_0402_1%~D 1 2
PC717 2 1
2
1U_0603_10V6K
PC710 0.1U_0402_10V7K~D
PC709 0.068U_0603_50V7K~D 2 1
1 2
@ PC708 0.022U_0402_25V7K 2 1
@ PR708 1
ISEN3/FB2 ISEN2 ISEN1 ISUMP ISUMN RTN FB COMP PGOOD BOOT1
2
10KB_0402_5%_ERTJ0ER103J
PH700
2
VSUMGPC716 .1U_0402_16V7K 2 1
1 PR709 11K_0402_1%
VSUMG+ PR707 2.61K_0402_1% 1 2 1
2
2
1 1_0402_5%
Compal Electronics, Inc. Title
+VCC_CORE Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
60
of
66
A
5
4
3
2
PJP702 +GFX_PWR_SRC
UGATE2G
PC770 2200P_0402_50V7K~D 1 2
PC756 0.1U_0402_25V6K~D 2 1
PC755 10U_0805_25V6K 2 1
PAD-OPEN 1x3m @ PL707 HCB4532KF-800T90_1812 1 2
D
7 6 5
UGATE
2
PWM
PHASE
7
3
GND
LGATE
4
PGND
9
PC758 0.22U_0603_16V7K PHASE2G LGATE2G
@
ISL6208CRZ-T_QFN8_3X3
C
PR769 4.7_1206_5% 2 1
FCCM
8
+VCC_GFXCORE
1 PR770 10K_0603_1% 2 1 PR771 3.65K_0603_1%
2 4
6
PL705 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
GP2_SW
PR772 2
1_0402_5% 1
VSUMG-
ISEN1G
2
3
PC759 680P_0603_50V7K 2 1
PR768 4.7_0603_5%~D 1 2BOOT2G 1 1
8
BOOT
2
PC775 2200P_0402_50V7K~D 1 2
VCC
+VCC_PWR_SRC
2
1
PC757 2 1
PR767 2 1 0_0603_5% 5 PWMG2
@
PQ705 CSD87351Q5D_SON8~D
PU702
PC754 10U_0805_25V6K 2 1
PC753 10U_0805_25V6K 2 1
1U_0603_10V6K
+5V_RUN D
1
1
VCC_GFXCORE TDC 38A Peak Current 46A OCP current 57.18A Load line -3.9mV/A FSW=400kHz
VSUMG+ ISEN2G
PR773 1
10K_0402_1% 2
C
@
@
7 6 5
3
PHASE1G
@
LGATE1G
@
PR775 1_0402_5% 1 2 PR778 10K_0402_1%
2
1
2 PR777 10K_0603_1% 1 2 PR774 3.65K_0603_1%
1 2
8
PR776 4.7_1206_5% 1
BOOT1G
ISEN2G VSUMG+
VSUMG-
2
2
PR779 4.7_0603_5%~D
+VCC_GFXCORE
@ PC776 2200P_0402_50V7K~D 1 2
1 1
PC764 0.22U_0603_16V7K
PL704 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
GP1_SW
4
PC771 2200P_0402_50V7K~D 1 2
B
2
2
UGATE1G
1
PC765 680P_0603_50V7K
B
PC763 0.1U_0402_25V6K~D 2 1
PC762 10U_0805_25V6K 2 1
@
1
PQ704 CSD87351Q5D_SON8~D
PC761 10U_0805_25V6K 2 1
PC760 10U_0805_25V6K 2 1
+GFX_PWR_SRC
ISEN1G
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+VCC_GFXCORE Size
4
3
www.vinafix.vn
2
Rev 0.1
LA-7782 Date:
5
Document Number Friday, June 10, 2011
Sheet 1
61
of
66
A
A
B
C
@ PD1300 2 1 ES2AA-13-F PQ1300 SI4835DDY-T1-GE3_SO8~D 8 1 7 2 6 3 5
PR1301 0.01_1206_1%~D
+SDC_IN
1
PR1306 100K_0402_1%~D 1
5
3
PC1309 1U_0603_10V6K~D 2 1
PR1307 100K_0402_1%~D 2 1
2
2
27 PGND CSOP
CE
CSON
@ PC1317 220P_0402_50V7K~D CHG_LGATE
@ PR1327 1 2 10K_0402_5%~D
7 12 29
@
@
PQ1305
17 15 VFB
VFB GND
1 PR1328 2 100_0402_5%~D
16
NC
+VCHGR
TP
4
ISL88731C_QFN28_5X5~D PJP1301 1
2
PAD-OPEN1x1m GNDA_CHG GNDA_CHG
Maximum charging current is 7.2A
PC1315 10U_1206_25V6M~D 2 1 +VCHGR
PR1326 PL1301 0.01_1206_1%~D 5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D 2 1+VCHGR_L 4 1
@
19 18
3 PC1322 1000P_0603_50V7K~D
2
PR1332 4.7_1206_5%~D
@ PC1333 0.1U_0603_25V7K~D 1 2
PC1334 1 2
PC1332 10U_1206_25V6M~D 2 1
VREF
20
1
LGATE
PC1331 10U_1206_25V6M~D 2 1
2 EAO
3 2 1
@
EAI
2
PC1320 56P_0402_50V8~D 1 2
@ @ PC1321 120P_0402_50VNPO~D 1 2
3
PC1328 0.1U_0402_10V7K~D 2 1
@
4
MAX8731_REF
PC1327 1U_0603_10V6K~D 2 1
@
@ PR1324 1 2 7.5K_0402_5%~D
2
+VCHGR_B
1 0_0603_5%~D
2
PHASE FBO
2
PR1330 10_0402_5%~D 2 1
23
PC1314 10U_1206_25V6M~D 2 1
2
PR1322
VICM
2200P_0402_50V7K~D
PC1326 0.01U_0402_25V7K~D 2 1
Vref TI bq24747 = 3.3V Intersil ISL88731C = 3.2V VDDP TI bq24747 = 6V Intersil ISL88731C = 5.1V
PC1323 220P_0402_50V8J~D 2 1
PR1329 8.45K_0402_1%~D 2 1
MAX8731_IINP
PC1325 0.01U_0402_25V7K~D 2 1
CHARGER_SMBDAT
5 @ PC1318 2 1
@ PR1323 200K_0402_5%~D
PC1324 0.01U_0402_25V7K~D 2 1
PR1325 4.7K_0402_5%~D 2 1
GNDA_CHG CHARGER_SMBCLK
2
4
PC1330 10U_1206_25V6M~D 2 1
UGATE
SIR472DP-T1-GE3_POWERPAK8-5
1U_0603_10V6K~D
CHG_UGATE
PC1329 0.1U_0603_25V7K~D 2 1
24
PQ1304
PC1311 1 2
PR1331 0_0402_5%~D 2 1
NC
GNDA_CHG
@
PC1313 0.1U_0603_25V7K~D 2 1
21 MAX8731A_LDO
VDDP
PC1312 2200P_0402_50V7K~D 2 1
SCL
1
28 CSSP
CSSN
ICREF
1
BOOT VDDSMB
2
6 1
1
8
DK_CSS_GC
SI7716ADN-T1-GE3_POWERPAK8-5
1
MAX8731_IINP
PR1312 0_0402_5%~D 1 2
3 2 1
14
GNDA_CHG
PR1319 4.7_0603_5%~D PR1318 2.2_0603_1%~D BOOT_D 2
BOOT 25 1
ACOK
SDA
5
9
DOCK_DCIN_IS-
PC1319 3300P_0402_50V7K~D 2 1
10
ACIN
PD1301 BAT54HT1G_SOD323-2~D 2 1
11
4
ICOUT 26
ICOUT
PC1310 0.1U_0603_25V7K~D 2 1
13
2
PC1316 0.1U_0402_10V7K~D
PR1305 CSSN_1 1 10_0402_5%~D
PR1304 10_0402_5%~D CSSP_1 1
PR1320 1 2 0_0402_5%~D
GNDA_CHG
1
+5V_ALW
2
0.1U_0603_25V7K~D PC1306 GNDA_CHG PU1300 0.1U_0805_50V7M~D +DCIN 22 2 1 DCIN
PR1316 15.8K_0402_1%~D 2 1
0.01U_0402_25V7K~D GNDA_CHG
2
PR1311 10K_0402_5%~D 2 1
PR1310 10K_0402_1%~D 2 1
PR1313 226K_0402_1%~D 1 2
@
PC1305 1 2
D
ACAV_IN
PC1304 0.047U_0603_25V7M~D 1 2
DOCK_DCIN_IS+
G
6
PQ1303B NTGD4161PT1G_TSOP6~D
PR1303 10K_0402_5%~D 2 1
1_0805_5%~D
2
1
5
S
PC1303 0.1U_0603_25V7K~D 1 2
@ PR1309 1 2
1
G
MAX8731_REF
PR1317 49.9K_0402_1%~D 2 1 PC1307
PQ1303A NTGD4161PT1G_TSOP6~D
@
S
2
+SDC_IN
2
S
D
2 G PQ1302 NTR4502PT1G_SOT23-3~D
BAT54CW_SOT323~D
+CHGR_DC_IN
PQ1301 NTR4502PT1G_SOT23-3~D
2 G
PC1302 0.1U_0603_25V7K~D 2 1
D
3
+DC_IN_SS
PAD-OPEN 4x4m
D
1
PR1313 TI bq24745 = 316K Intersil ISL88731 = 226K Maxim = 383K
2
S
+DOCK_PWR_BAR
2
PC1301 47P_0402_50V8J~D 2 1
2
PD1302
E2 AC_OK=17.7 Volt
3
3
1
CSS_GC
1
1
2
PR1302
3
DC_BLOCK_GC
1
1
1 2
0_0402_5%~D
MAX8731A_LDO
CHAGER_SRC
4 @
4
PR1300 1 0_0402_5%~D
1
+PWR_SRC PJP1300
PC1300 0.1U_0603_25V7K~D
+DC_IN_SS
D
@ PL1300 1UH_PCMB053T-1R0MS_7A_20% 2 1
@ PC1335 1 2
0.22U_0603_25V7K~D
0.1U_0603_25V7K~D
GNDA_CHG GNDA_CHG MAX8731_REF
1
2
ACAV_IN_NB
PR1348 41.2K_0402_1%~D 2 1
8 P 4
7
LM393DR_SO8~D
@ +3.3V_ALW
PR1351 100K_0402_5%~D
2
2
PC1342 0.1U_0402_25V4Z~D 1
5
Adapter Protection Circuit for Turbo Mode
P
B
G
A
O 3
4
1
PU1302
D
1 2
TC7SH08FU_SSOP5~D
PROCHOT_GATE
To preset system to throtlle switching from AC to DC
2 G
ACAV_IN
S
3
PQ1309 RHU002N06_SOT323-3~D
PR1342 0_0402_5%~D
PU1303B O
+3.3V_ALW
2 G
DYN_TUR_CURRNT_SET#
-
G
6
+
3
1
5
PR1338 10K_0402_1%~D 2 1
PR1336 47K_0402_1%~D 2 1
PR1335 232K_0402_1%~D 2 1
+5V_ALW
PC1339 100P_0402_50V8J~D 2 1
2 LM393DR_SO8~D
PR1333 1M_0402_1%~D 1 2
PR1347 42.2K_0402_1%~D 2 1
-
1
PR1346 22.6K_0402_1%~D 2 1
O
PC1338 100P_0402_50V8J~D 2 1
2 PR1339
PU1303A
MAX8731_REF
5 PQ1307B DMN66D0LDW-7 2N_SOT363-6~D 4 3
2
1 S
PC1341 100P_0402_50V8J~D 2 1
PR1350 113K_0402_1%~D 2 1
3
PR1349 162K_0402_1%~D 2 1 1
D
PC1340 220P_0402_50V8J~D
2
+
0_0402_5%~D
1 3
6
PR1343 20K_0402_1%~D 1 2
1
2
MAX8731_IINP
8
PR1341 150K_0402_1%~D
DMN66D0LDW-7 2N_SOT363-6~D PQ1307A
1
221K_0402_1%~D
PR1340 1.8M_0402_1% 1 2
PR1334 2
+5V_ALW
H_PROCHOT#
P
Low
@
G
130W
@
+3.3V_ALW2
4
High 1
90W
+DC_IN
PC1337 0.01U_0402_25V7K~D 2 1
DYN_TUR_CURRENT_SET# 3
PC1336 100P_0402_50V8J~D 2 1
+5V_ALW
PQ1306 RHU002N06_SOT323-3~D
4
4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Charger Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 D
Sheet
62
of
66
5
4
PR901 330K_0402_5%~D
2
1
@ PR934 1
1
PD908 RB751V-40GTE-17_SOD323~D 2 1
DEFAULT_OVRDE PR923 10K_0402_5%~D 2 1
C
2
PQ911 2N7002W-7-F_SOT323-3~D
D
@
2 G
ACAV_IN
S
100K_0402_5%~D 2
PR937 0_0402_5%~D 2 MODULE_BATT_PRES#
2 +DOCK_PWR_BAR
1 PR939 1 PR940
2 0_0402_5%~D 2 0_0402_5%~D
PR941 0_0402_5%~D
1 PR948
+SDC_IN
1 PR951
2ACAVDK_SRC 0_0402_5%~D
2 0_0402_5%~D CD3301_SDC_IN
DC_BLOCK_GC ACAV_IN
1 PR955
+3.3V_ALW2
1 PR957
1 2 ERC1 3 4 5 6 7 ACAVIN 8 P33ALW2 9
2 0_0402_5%~D
37
TP
2 5
PC914 1500P_0402_7K~D
4
1 ERC2
PC913 0.1U_0402_25V4Z~D 2 1
ERC3
1
1 2 0_0402_5%~D
CSS_GC DK_CSS_GC
PC912 0.047U_0603_25V7K~D 2 1
DOCK_SMB_ALERT#
PR961
PC911 0.1U_0603_25V7K~D 2 1
3
3
2 2
1
P50ALW PBATT_OFF DK_AC_OFF_EN ACAV_IN_NB GND DK_AC_OFF_EN SL_BAT_PRES# BLKNG_MOSFET_GC NBDK_DCINSS
@
27 26 25 24 23 22 21 20 19
1 PR945
+5V_ALW 2 0_0402_5%~D
CD_PBATT_OFF 1 PR947
2 0_0402_5%~D
SLICE_BAT_ON
1 PR949
2 0_0402_5%~D
DOCK_AC_OFF
DK_AC_OFF
1 3301_ACAV_IN_NB
DK_AC_OFF_EN SL_BAT_PRES#
1 PR953
2 0_0402_5%~D 1 PR954 BLKNG_MOSFET_GC
1 PR956 1 PR958
2 0_0402_5%~D 2 0_0402_5%~D
ACAV_IN_NB 2 0_0402_5%~D
SLICE_BAT_PRES#
DOCK_AC_OFF_EC
2
1M_0402_5%~D PR952
+NBDOCK_DC_IN_SS
CD3301RHHR_QFN36_6X6~D
10 11 12 13 14 15 16 17 18
2 0_0402_5%~D
DC_IN SS_GC ERC1 ACAVDK_SRC GND SDC_IN DC_BLK_GC ACAV_IN P33ALW2
PQ915 FDN338P_G_NL_SOT23-3~D 1
1 PD917 2
RB751V-40GTE-17_SOD323~D
1 PD916 2
RB751V-40GTE-17_SOD323~D
36 35 34 33 32 31 30 29 28
100K_0402_5%~D
NC CHARGERVR_DCIN DC_IN_SS DK_PWRBAR GND NC BLK_MOSFET_GC DSCHRG_MOSFET_GC PBatt+
PR946
P50ALW
CSS_GC DK_CSS_GC ERC3 ERC2 GND PWR_SRC SS_DCBLK_GC EN_DK_PWRBAR P33ALW
PU900
SOFT_START_GC 1 2
ACAV_DOCK_SRC#
SLICE_BAT_PRES#
CHGVR_DCIN DC_IN_SS DK_PWRBAR
1
0.1U_0603_50V4Z~D
+3.3V_ALW2
2 0_0402_5%~D
CD3301_DCIN
2 47_0805_5%~D PC910
A
1 PR943
B
@ PR942 0_0402_5%~D
1
+DC_IN_SS
2
PBAT_PRES#
2
1 PR944
PC905 2200P_0402_50V7K~D 2 1
PD907 RB751V-40GTE-17_SOD323~D 2 1
PBATT+
+CHGR_DC_IN +DC_IN
+PWR_SRC
PR924 499K_0402_1%~D 2 1
1
PDS5100H-13_POWERDI5-3~D PQ914 1 D S 2 D S 3 D S 4 D G
FDS6679AZ_G_SO8~D
PC907 0.01U_0603_25V7K~D
2
2
PBATT_IN_SS
1
MPBATT+
PR933 510K_0402_5%~D 2 1
PD915 RB751V-40GTE-17_SOD323~D
2
5
1 3
PR911 0_0402_5%~D
3
MODULE_ON
D
PR907 330K_0402_5%~D
2
1 PR928 499K_0402_1%~D
2 0_0402_5%~D
FDS6679AZ_G_SO8~D
2
4
390K_0402_5%~D
1 PQ906B DMN66D0LDW-7 2N_SOT363-6~D 4 3
2 SLICE_BAT_PRES#
PR925 51
PQ905B DMN66D0LDW-7 2N_SOT363-6~D 4 3 1
PD913 RB751V-40GTE-17_SOD323~D 1 2
6 PR932 PD912 0_0402_5%~D RB751V-40GTE-17_SOD323~D 2 1 1 2 1
2
PD911 RB751V-40GTE-17_SOD323~D
2
DMN66D0LDW-7 2N_SOT363-6~D PQ906A
1
2
1 3 PR936 0_0402_5%~D 1 2 4
PR922
2 PR921 20K_0402_1%~D
DMN66D0LDW-7 2N_SOT363-6~D PQ907B
5
@ B
PQ908A DMN66D0LDW-7 2N_SOT363-6~D 1 6
3 4 2
PR938 499K_0402_1%~D 2 1
2 0_0402_5%~D
1
1 PR935
PD910 RB751V-40GTE-17_SOD323~D 1 2
PR931 200K_0402_1%~D 6 2 1
SLICE_BAT_ON
DMN66D0LDW-7 2N_SOT363-6~D PQ907A
1
PBATT+
DEFAULT_OVRDE
DMN66D0LDW-7 2N_SOT363-6~D PQ908B
5
PR926 0_0402_5%~D
1
2
2
S
2 G
DMN66D0LDW-7 2N_SOT363-6~D PQ910A
PR919 10K_0402_5%~D 6 2 1
PR920 10K_0402_5%~D 2 1 1 3
PBAT_PRES#
D
2N7002W-7-F_SOT323-3~D
C
PQ916
5
1 2 3 4
S S S G
PD905
2
PR917 820_0603_1%~D 1 2
PQ905A DMN66D0LDW-7 2N_SOT363-6~D 1 6
3
PR916 20K_0402_1%~D
1
8 7 6 5
DMN66D0LDW-7 2N_SOT363-6~D PQ910B
PR914 620K_0402_5%~D 2 1
4
@
1
TC7SH08FU_SSOP5~D
PR913 390K_0402_5%~D 2 1
4
O A
2
B
PC904 0.1U_0603_25V7K~D 2 1
5 2
P
CHARGE_PBATT
G
1
3
ACAV_IN
PR915 100K_0402_5%~D 1 2
+VCHGR
PU901
PQ912 FDS6679AZ_G_SO8~D 1 8 S D 2 7 S D 3 6 S D 4 5 G D
D D D D
1
1
PD904 RB751V-40GTE-17_SOD323~D 2 1
PC903 0.01U_0603_25V7K~D
PQ904B DMN66D0LDW-7 2N_SOT363-6~D
PBATT+
+DOCK_PWR_BAR
PD903 RB751V-40GTE-17_SOD323~D 2 1
PR912 330K_0402_5%~D
PQ913 SI4835DDY-T1-GE3_SO8~D 1 8 2 7 3 6 5
PQ903 8 7 6 5
FDS6679AZ_G_SO8~D
1 +3.3V_ALW2
ES2AA-13-F SMA PD902 2 1
1
MPBATT_IN_SS
3 DMN66D0LDW-7 2N_SOT363-6~D
2
PC916 0.1U_0402_10V7K~D 1 2
8 7 6 5
PR905 820_0603_1%~D 1 2
5
PDS5100H-13_POWERDI5-3~D PQ902 1 D S 2 D S 3 D S 4 D G
2
FDS6679AZ_G_SO8~D PQ901
1 3
2
PC902 0.47U_0805_25V7K~D
1
2
8 7 6 5
D D D D
PC906 0.1U_0603_25V7K~D 2 1
S S S G
STSTART_DCBLOCK_GC
3
PR904 620K_0402_5%~D 2 1
4
PQ904A S
1 2 3 4
PR910 499K_0402_1%~D 2 1
D
2 G
MODULE_BATT_PRES#
PR909 390K_0402_5%~D 2 1
1
PQ909 2N7002W-7-F_SOT323-3~D
@
6
D
MPBATT+
PR906 10K_0402_5%~D 2 1
PR908 10K_0402_5%~D 2 1
3 TC7SH08FU_SSOP5~D
1
2
4
4
O A
PC900 0.1U_0603_25V7K~D 2 1
B
2
CHARGE_MODULE_BATT
PU902
P
1
ACAV_IN
G
PR900 100K_0402_5%~D 1 2
5
+VCHGR
2
PD901
PR903 390K_0402_5%~D 2 1
+3.3V_ALW2 PC915 0.1U_0402_10V7K~D 1 2
3
PQ900 SI4835DDY-T1-GE3_SO8~D 1 8 2 7 3 6 5
A
P33ALW
1 PR959
2 +3.3V_ALW 0_0402_5%~D
EN_DK_PWRBAR 1 PR960
2 0_0402_5%~D
EN_DOCK_PWR_BAR 1
STSTART_DCBLOCK_GC
DELL CONFIDENTIAL/PROPRIETARY
2
1M_0402_5%~D @ PR962
Compal Electronics, Inc. Title
3301_PWRSRC
1 PR963
2 0_0402_5%~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
www.vinafix.vn +PWR_SRC
3
2
Selector Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 Sheet 1
63
of
66
8
7
6
5
Initial voltage is 0.975V
4
3
2
1
+VGA_B+
+3.3V_RUN_GFX
PJP1000
PR1020 47K_0402_1%~D 2 1
GNDA_GPU_CORE @ PR1050 0_0402_5% 1
GPU_HOT#
PR1019 100K_0402_5% 2
GPU_VID6 GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0
1
+3.3V_RUN
PU1000 2
GNDA_GPU_CORE PR1046 1.4K_0402_1% 2 1
E
PH1001 470K_0402_5%_TSM0B474J4702RE 1 2
AGND
GPU_VID_5
GPU_VID_4
GPU_VID_3
7 6 5
3
GPU_VID_2
GPU_VID_1
1
PL1000 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
P2_VGA_SW
4
@
LGATE2_VGA
PR1009 1_0402_5%
1 +
PR1015 10K_0402_1%~D 1 2+GPU_CORE
VSUM+_VGA
@ PR1007 2.2_1206_5%
G
+GPU_CORE
2 VSUM-_VGA
ISEN2_VGA F
30 29 28 27 26 25 24 23 22 21
PR1022 1
0_0402_5% 2
1
2
+GPU_CORE TDC 35A Peak Current 42A OCP current 51A No Load line FSW=400kHz
+5V_RUN
PR1021 0_0402_5%
E
PC1010 1U_0603_10V6K
2
41
BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1
PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2
1
PR1025 499_0402_1%~D 2 1
11 12 13 14 15 16 17 18 19 20
1 2
2
@ PC1009 22P_0402_50V8J
PC1011 1000P_0402_50V7K
PR1024 6.81K_0402_1%~D 2 1
1
@ PR1023 249K_0402_1% 1 2
1 2 3 4 5 6 7 8 9 10
PHASE2_VGA
40 39 38 37 36 35 34 33 32 31
F
CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0
,40> DGPU_PWROK
2
ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1
PR1017 0_0402_5% 1
2
PR1013 1.91K_0402_1%
2
UGATE2_VGA
PC1006 470U_D2_2VM_R4.5M
CLK_ENABLE#_VGA
GPU_VID_6
8
PR1010 1.91K_0402_1% 1 2 1
+3.3V_RUN
1 PR1002 0_0402_5% 2 1 PR1005 0_0402_5% 2 1 PR1006 0_0402_5% 2 1 PR1011 0_0402_5% 2 1 PR1014 0_0402_5% 2 1 PR1016 0_0402_5% 2 1 PR1018 1K_0402_1%~D
1
GNDA_GPU_CORE
2
PQ1001 CSD87351Q5D_SON8~D
PC1005 0.22U_0603_10V7K BOOT2_2_VGA 1 2
H
1
PR1003 4.7_0603_5%~D 2 1
@ PC1008 2200P_0402_50V7K 2 1
PR1004 10K_0402_1% 1 2
+PWR_SRC
2
10K_0402_1% 2
2
PR1047 1
BOOT2_VGA G
1
1
PC1000 10U_1206_25V6M 2 1
10K_0402_1% 2
PR1012 10K_0402_1%~D
@ PR1059 1
10K_0402_1% 2
PC1003 10U_0805_25V6K
10K_0402_1% 2
10K_0402_1% 2
PC1002 2200P_0402_50V7K 2 1
PR1052 1
PR1049 1 @ PR1062 1
PC1001 0.1U_0402_25V6K~D 2 1
10K_0402_1% 2
1
PC1004 22P_0402_50V8J 1 2
@ PR1058 1
2
JUMP_1X3m
2
GNDA_GPU_CORE
10K_0402_1% 2
10K_0402_1% 2 10K_0402_1% 2
PR1008 3.65K_0402_1% 2 1
@ PR1001 10K_0402_1% 1 2
PR1054 1
PR1051 1 @ PR1061 1
2
PC1007 1000P_0603_50V7K 2 1
RUN_ON
10K_0402_1% 2
10K_0402_1% 2
1
PR1000 10K_0402_1% 1 2
DGPU_PWR_EN
@ PR1057 1
@ PR1060 1
2
H
10K_0402_1% 2
1
PR1056 1
PC1012 2
ISL62883CHRTZ-T_TQFN40_5X5
GNDA_GPU_CORE
470P_0402_50V8J~D
PC1013 47P_0402_50V8J~D 1 2
PR1027 3.57K_0402_1% 1 2
1
2
+5V_RUN
PR1026 0_0402_5%
D
D
1
+VGA_B+
1 2
PC1022 10U_0805_25V6K
PC1021 2200P_0402_50V7K 2 1
PC1023 10U_1206_25V6M 2 1 PL1001 0.22UH_FDUE0640-H-R22M=P3_25A_20%~D 2 1
Layout Note: Place near Phase1 Choke
VSUM+_VGA
1 2
1 1 PR1040 1_0402_5% + 2
@
PR1039 10K_0402_1%~D
PH1000 10K_0402_1%_TSM0A103F34D1RZ
PR1038 3.65K_0402_1% 2 1
PC1032 1000P_0603_50V7K 1 2 1
1
LGATE1_VGA
PR1042 10K_0402_1%~D 1 2+GPU_CORE
2
1 + 2
VSUM-_VGA
B
@ PR1037 2.2_1206_5% ISEN1_VGA
2
PC1033 0.1U_0402_16V7K
2
PAD-OPEN1x1m
DELL CONFIDENTIAL/PROPRIETARY
GNDA_GPU_CORE
A
+GPU_CORE PC1030 470U_D2_2VM_R4.5M
P1_VGA_SW
4
VSUM-_VGA
PJP1004 1
7 6 5
3
8
PR1045 953_0402_1% 1 2
1
PR1044 10_0402_5% 1 2
PHASE1_VGA
2
2
PR1043 0_0402_5% 1 2
GPU_VSS_SENSE
PR1041 11K_0402_1% 2 1
B
1
PC1031 1000P_0402_50V7K
PC1028 0.1U_0402_16V7K 2 1
2
@ GNDA_GPU_CORE
PC1027 0.068U_0603_50V7K~D 2 1
1
1 PC1025 330P_0402_50V7K
PC1026 0.01U_0402_25V7K
2
2 PR1036 0_0402_5%
2
1
GPU_VDD_SENSE
C
2
PC1029 470U_D2_2VM_R4.5M
PR1035 2.61K_0402_1% 2 1
@
PQ1000 CSD87351Q5D_SON8~D
PR1034 PC1024 4.7_0603_5%~D 0.22U_0603_10V7K 2 1 BOOT1_1_VGA 1 2
2
1
PR1033 82.5_0402_5%
2
PR1032 10_0402_5%
C
UGATE1_VGA
VSUM+_VGA
VSUM-_VGA 1
+GPU_CORE
PC1020 0.1U_0402_25V6K~D 2 1
+5V_RUN
1
1
GNDA_GPU_CORE
+VGA_B+
PC1019 0.22U_0603_25V7K
PC1018 1U_0603_10V6K 2 1
1 2
2 GNDA_GPU_CORE
2 PR1029 0_0402_5% 1 2 PR1031 1_0402_5%
BOOT1_VGA
2
PR1030 249K_0402_1%
2
PR1028 324K_0402_1%~D
PC1017 0.22U_0402_10V4Z
ISEN1_VGA
@ PC1014 2200P_0402_50V7K 2 1
ISEN2_VGA
2
1
PC1015 150P_0402_50V8J
1
PC1016 0.22U_0402_10V4Z
2
1
1
GNDA_GPU_CORE
A
Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
8
7
6
www.vinafix.vn 5
4
3
+GPU_CORE Size
Document Number
Date:
Friday, June 10, 2011
Rev 0.1
LA-7782 2
64
Sheet 1
of
66
5
4
3
+VCC_CORE
+VCC_CORE
1
2
1 PC1100 10U_0805_4VAM
2
1 PC1101 10U_0805_4VAM
2
1 PC1102 10U_0805_4VAM
2
2
1
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+VCC_GFXCORE
Socket Bottom
5 x 22 µF (0805) 5 x (0805) no-stuff sites
Socket Top
7 x 22 µF (0805) 2 x (0805) no-stuff sites
1 PC1103 10U_0805_4VAM
2
PC1104 10U_0805_4VAM
+VCC_GFXCORE
D
2
1
2
1
2
1
2
1
2
1
2
PC1118 22U_0805_6.3V6M
2
1
PC1117 22U_0805_6.3V6M
2
+VCC_CORE
1
PC1116 22U_0805_6.3V6M
2
1 PC1109 10U_0805_4VAM
PC1115 22U_0805_6.3V6M
2
1 PC1108 10U_0805_4VAM
PC1114 22U_0805_6.3V6M
2
1 PC1107 10U_0805_4VAM
PC1113 22U_0805_6.3V6M
2
1 PC1106 10U_0805_4VAM
PC1112 22U_0805_6.3V6M
2
1 PC1105 10U_0805_4VAM
PC1111 22U_0805_6.3V6M
1
+1.05V_RUN_VTT
+
2
1 +
2
1 +
2
1 +
PC1164 22U_0805_6.3VAM
2
2
2
C
1 +
2
1 +
2
PC1187 470U_D2_2VM_R4.5M
2
1
2
PC1175 470U_D2_2VM_R4.5M
+
1 PC1163 22U_0805_6.3VAM
PC1174 470U_D2_2VM_R4.5M
1
PC1168 22U_0805_6.3VAM
2
PC1173 470U_D2_2VM_R4.5M
2
PC1172 470U_D2_2VM_R4.5M
1
2
1 PC1162 22U_0805_6.3VAM
2
1
PC1155 22U_0805_6.3VAM
2
1 PC1161 22U_0805_6.3VAM
2
2
PC1134 22U_0805_6.3VAM
2
1 PC1160 22U_0805_6.3VAM
2
1
1
PC1166 330U_X_2VM_R6M
1
2
2
PC1165 330U_X_2VM_R6M
2
+
1
2
@
PC1154 22U_0805_6.3VAM
C
1
@
1
PC1133 22U_0805_6.3VAM
+
1
2
@
PC1152 22U_0805_6.3VAM
2 1
1
1
PC1132 22U_0805_6.3VAM
PC1153 22U_0805_6.3VAM
1
2
PC1151 22U_0805_6.3VAM
2
@
2
1
PC1131 22U_0805_6.3VAM
PC1146 22U_0805_6.3VAM
1
2
@
PC1150 22U_0805_6.3VAM
2
1
2
PC1130 22U_0805_6.3VAM
PC1145 22U_0805_6.3VAM
2
PC1149 22U_0805_6.3VAM
2
2
PC1129 22U_0805_6.3VAM
PC1144 22U_0805_6.3VAM
2
1
PC1157 470U_D2_2VM_R4.5M
2
1
2
2
PC1148 22U_0805_6.3VAM
PC1143 22U_0805_6.3VAM
1
PC1156 470U_D2_2VM_R4.5M
2
1
2
1
PC1147 22U_0805_6.3VAM
1
2
1
1
+1.05V_RUN_VTT 1 1 1 @ PC1128 22U_0805_6.3VAM
2
1
1
PC1127 22U_0805_6.3VAM
1
@
PC1126 22U_0805_6.3VAM
2
PC1123 22U_0805_6.3VAM
1
PC1125 22U_0805_6.3VAM
2
PC1122 22U_0805_6.3VAM
PC1138 22U_0805_6.3V6M
2
PC1121 22U_0805_6.3VAM
1 PC1137 22U_0805_6.3V6M
2
PC1120 22U_0805_6.3VAM
1
PC1136 22U_0805_6.3V6M
PC1119 22U_0805_6.3VAM
1
PC1135 22U_0805_6.3V6M
2
1
PC1124 22U_0805_6.3VAM
1 1
D
2 @
B
B
(place under GPU)
+GPU_CORE
+GPU_CORE
(place near GPU)
1 2
1 2
1
1 2
1 2
1 2
1 2
1 2
A
1
@
2
1
1 2
2
1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
1 2 1 2
2 1 2
PC1218 4.7U_0603_6.3V6K~D
PC1217 4.7U_0603_6.3V6K~D
PC1216 4.7U_0603_6.3V6K~D
PC1215 4.7U_0603_6.3V6K~D
PC1214 4.7U_0603_6.3V6K~D
PC1213 22U_0805_6.3V6M
@
PC1197 4.7U_0603_6.3V6K~D
PC1196 4.7U_0603_6.3V6K~D
PC1195 4.7U_0603_6.3V6K~D
@
PC1212 47U_0805_6.3V6M~D
@
PC1186 4.7U_0603_6.3V6K~D
PC1185 4.7U_0603_6.3V6K~D
PC1194 4.7U_0603_6.3V6K~D
@
PC1184 4.7U_0603_6.3V6K~D
@
PC1211 .1U_0402_16V7K
@
PC1183 4.7U_0603_6.3V6K~D
PC1210 .1U_0402_16V7K
@
PC1182 4.7U_0603_6.3V6K~D
PC1209 .1U_0402_16V7K
PC1193 .1U_0402_16V7K
PC1192 .1U_0402_16V7K
PC1191 .1U_0402_16V7K
PC1190 .1U_0402_16V7K
@
+GPU_CORE
+GPU_CORE
PC1181 4.7U_0603_6.3V6K~D
PC1180 4.7U_0603_6.3V6K~D
PC1179 4.7U_0603_6.3V6K~D
PC1178 4.7U_0603_6.3V6K~D
PC1177 4.7U_0603_6.3V6K~D
PC1189 .1U_0402_16V7K
A
PC1176 4.7U_0603_6.3V6K~D
1
+GPU_CORE
2
+GPU_CORE
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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PROCESSOR DECOUPLING Size
Document Number
Date:
Friday, June 10, 2011
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V ersion Change L ist ( P. I. R . L ist ) Item Page#
Title
D ate
R equest O w ner
2
1
Page 1
Issue D escription
Solution D escription
R ev.
D
D
C
C
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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PWR_PIR 1 Size
Rev 0.1
LA-7782 Date:
2
Document Number Friday, June 10, 2011
Sheet 1
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