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Digital Circuit Testing and Testability Parag K. Lala Ekctncal Enginecnng IVpartmcrt Nonh Caiottna Agncultural ind Tecimical Stale Univrixity Greensboro. Nocih Carolina

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Contents

Chapter 3 3.1 3.2 3.3 3.4

3.5 3.6 3.7

Testable Combinational Logic Circuit Design

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The Reed-Muller Expansion Technique Three-Level OR-AND-OR Design Automatic Synthesis of Testable Loeic Testable Design of Multilevel Combinational Circuits 3.4.1 Single Cube Extraction 3.4.2 Double Cube Divisor 3.4.3 Extraction of a Double Cube Divisor and Its Complement Synthesis of Random Panem Testable Combmational Circuits Path Delav Fault Testable Combinational Logic Design Testable PLA Design References

53 '** ^ ^ ^ « Z. ! '^ 77

Chapter 4 4.1 4.2 4.3 4.4 4.5

Testing of Sequential Circuits as Iterative Combinational Circuits State Table Verification Test Generation Based on Circuit Structure Functional Fault Models Test Generation Based on Functional Fault Models References

Chapter 5 5.1 5.2 5.3 5.4 5.5

Test Generation for Sequential Circuits

Design of Testable Sequential Circuits

Controllability and Obser\ability Ad Hoc Design Rules for Improving Testability Design of Diagnosable Sequential Circuits The Scan-Path Technique for Testable Sequential Circuit Design Level-Sensitive Scan Design (LSSD) 5.5.1 Clocked Hazard-Free Latches 5.5.2 LSSD Design Rules 5.5.3 Advantages of the LSSD Technique

5.6 Random Access Scan Technique 5.7 Partial Scan 5.8 Testable Sequential Circuit Design Using Nonscan Techniques 5.9 Crosscheck 5.10 Boundary- Scan References

Chapter 6

Built-in Self Test

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6.1

Test Panem Generation for BiST 6.1.1 Exhaustive Testing 6.1.2 Pseudo-Exhaustive Pattem Generation

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Contents

6.3

6.L3 ^^udo-Random Pattem Generator G.I.4 Deterministic Testing Output Response Analysis 6.2.1 Transition Count 6.2.2 Syndrome Checking 6.2.3 Signature Analvsis Circular BIST

6.4

BIST Architectures

6.2

6.4.1 6.4.2

B I L B O (Built-In Logic Block Observer*

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6.4.3 LOCST (LSSD On-Chip Self-Test) References

Chapter 7 7.1 7.2

7.3 7.4 7.5

Testable Memory Design

RAM Fault Models Test Algorithms for RAMs 7.2.1 GALPAT (Galloping Os and Is) 7.2.2 Walking Os and Is 7.2.3 March Test 7.2.4 Checkerboard Test Detection of Pattern-Sensitive Faults BIST Techniques for RAM Chips Test Generation and BIST for Embedded RAMs References

Appendix

Index

Markov Models

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