Digital Principles and System Design

Digital Logic Design Principles

Norman Balabanian University of Florida

Bradley Carlson Symbol ymb ol Tech chn nolog olo gies, ies, Inc. Inc.

John Wiley iley & Sons, Sons, Inc. Inc. New York • Chic Chichester hester • Weinhei einheim m • Bris Brisbane • Toronto • Singapore ngapore

AQU ISITIONS E D ITO R MA R KE TING MANAG E R PRO DUCTIO N SE RVICE S MA NAG ER COVE R DE SIGNE R ILLUSTR ATION E D ITOR P R O D UC TI O N MA NA G E ME N T SE R VI CE S

Bill Z obrist Katherine Hepburn Jeanine M. Furino (pending) G ene A iello P ub lica tio n Se rvice s

This book was set in Times R oman b y Publication Services and pr inted and bound b y Courier Com panies. The cover was printed by Phoen ix Color Corp oration. This book is printed on acid-free paper. ᭺ ∞

Copyright 2001 © John Wiley & Sons, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retr ieval system or tra nsmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as per mitted unde r Section 107 or 108 of the 1976 United State s Copyright Act, without either the p rior written permission of the Publisher, or author ization through payment of the ap propriate per-copy fee to the Copyright Clearance Center, 222 Rosewood D rive, Danvers, MA 01923, (978) 750-8400, fax (978) 7504470. Requests to t he Publisher for permission should be addressed to the Permissions Department, John Wiley & Son s, Inc., 605 Third Avenue, New York, NY 10158-0012, (212) 850-6011, fax (212) 850-6008, EMail: PE RM RE Q@WILE Y.COM. To orde r books please call 1(800)-225-5945. ISBN 0–471–29351-2 Printed in the U nited States of Amer ica 10 9 8 7 6 5 4 3 2 1

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Preface THE BOOK This in an intr oductory-level book on the  principles of digital logic design. It is intende d for u se by firstor second-year students of electrical engineering, computer engineering, or computer science. No pr evious knowledge of electrical circuits or of electronics is assumed. Ot hers who need a first exposure to, or a refre sher on, digital design principles may also find it useful.

Pedagogical Issues The deductive process—applying general principles to specific cases—is usually well illustrated in textbooks. Often, on the authority of the author, a general concept or an approach to a topic, or some result, is stated, followed by examples of how to apply the concept. As students begin a topic, it is unclear to them what the mot ivation is for introducing a particular definition or general procedure. Students don ’t have a clear idea why this particular topic may be useful or intere sting, or why and how anybody tho ught it up in th e first place. In this book, we include an inductive approach in the development of subject matter. This appro ach involves the de velopment of a gene rally valid result from an e xamination of specific cases, the way a research investigation pro ceeds.A n investigator r eaches a genera lly valid result by carrying out a numbe r of specific experiments or calculations. Sometimes th e study of one o r mor e specific cases leads to a con ject ur e abou t som et hing ge ne ra lly va lid. The conjectur e is t he n explor ed and justified using p re viously established r esults. In a similar vein, we introdu ce most topics in an exploratory spirit, rather than drop ping them on the reade r without any pr eceding justification.The tenor of the t ext is that we are conducting an investigative exploration, almost like a research pro ject, for the purpo se of discovering and assimilating knowledge about the subject under study.When a t opic is introdu ced, a considerab le effort is made to help students understan d why we ought to devote time to it. After a particular topic has been exhausted (t hat is, when we are faced with the need for taking a further step) alternatives are explored. “We could do this or we could do that,” the commentary might go; “let’s first try this, for th e following reasons.” W hy to pursue a particular thread and how a part icular procedur e might come about are just as important to clarify for the learner as the d etails of following that specific procedure or o f applying some par ticular algorithm. When a subject such as digital circuits reaches a de gree of mat urity, there is a tendency for a textbook to accquire some of the characteristics of an encyclopedia: every conceivable topic is “covered.” This approa ch robs the learn er of all the joys of discovery. The learner is given the complete story and told to learn it, mainly by practicing on exercises and problems like those that the book h as just worked out. In this book, we try to avoid the pitfall of cataloguing for students all that we know on a subject. In the form of problems, we leave for students the pleasure of developing (with guidance) some results that are no t essential for going on with the subject matte r being developed, and so need n ot be pa rt of the e xposition. Student s learn be st if they are engaged. There isn ’t much that authors can do to keep them engaged, but we do remind them to participate in the derivation of an equation by carrying out the missing steps, to observe the r elevant feature s of a diagram or tab le by describing it carefully to themselves, or to think  thro ugh a proposed plan befor e carrying it out in detail. We do this often.

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The present ation of mater ial in this book is at the intro ductory level, first or second year of college. However, the level of a book should not dictate the degree of rigor in the presentation. Everything treated in this book is treated with rigor.

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Preface

Topic Selection There is nothing unusual in the selection of subject matt er. The selection and orde ring of topics has been carried out to facilitate u se of the boo k at institutions with different calend ars and a variety of emphases. The book can be used in courses spanning an academic year, either two semesters or three quarter s, especially if attention is given to the labora tory componen t. (See the description of the laborator y manual in what follows.) By proper selection of chapters and to pics within chapte rs, a one-semeste r course can also be accommodated. Several “enrichment” topics are introduced in sections that instructors can omit without incurr ing a subsequent pe nalty. Later sections or prob lems based on this mate rial can be similarly omitted . The inclusion of such material permits students having more time or inte rest to benefit without penalizing others. The choice of ABEL to introduce hardware description language (HDL) as a tool for design minimizes the effort of students to learn the language, thus enabling them to concentrate on th e concepts behind designing with an HDL . All concepts of HD L specification, simulation, and synthesis can be taught using AB EL , and the stud ent is not burdene d with the ta sk of learn ing the syntax and semant ics of a complex language such as VHDL or Verilog.

Numbering Scheme for Equations and Figures Some schemes for numbering sections, equations, and figures, and the manner of referring to them, can cause students to be distracted as they engage unproductively in reading the numbers and searching for them. In this book a sequential numbering system, starting fresh in each chapter, is used for both equations and figures. (O n the few occasions when refer ence might be made to an equ ation in an earlier chapter, the chapter number is also given.) Similarly, major sections within a chapter are numbered consecutively, without a chapter identifier, but subsections and sub-subsections are not numbered, thus obviating the unp roductive rea ding of such section nu mber s as 4.3-5 that might ident ify subsection 5 of  section 3 in Chapter 4. Subsequent r eferen ce to such a particular subsection is rar ely, if ever mad e in any book; hence, there is no r eference value to such a numbering scheme. Not all equations, only significant ones or those to which reference might be made later, are numbered. When referring to an equation or figure, we spell out the name: "E quation ” or “Figure.”

Illustrations, Examples, Exercises, and Problems When a particular topic is being developed, illustrations are used to illuminate it. Indeed, an illustration might precede the development of the topic as part of the process of induction. Illustrations are thus incorporated into the development of the material.There are also numbered examples, separated from the text and easily distinguished, which are worked out using the concepts just developed, together with other recently assimilated ideas. Scattered throughout the development, but in a format that distinguishes them from the text, are numbered exercises for students to work out at the time they are studying the relevant sections.The purpose of these exercises is to pro vide reinforcement for the concept s under study by having students carry out some simple calculations and apply results then unde r discussion. They form part of the “research project” idea. The excitation req uiremen ts for one type of flip-flop might be developed within the text, for example; the excitation requirem ents for other t ypes of flip-flops are th en left as an exercise for the students to work out. Where useful,answers are pr ovided so that students can confirm the results of their efforts. (Most of the time, especially if answers are br ief and thus easy for studen ts to glance at within the text, they are p rovided as footnote s.) The exercises do not simply call for rep eating the steps of a justworked-out examp le using changed values or circuit configurations. He nce, ther e is no need to pro vide worked-out examples before asking students to perform an exercise. At t he end of each chapter is a set of  pro blem s . The problems in each set range from a simple application of procedures developed in the book to a challenging solution of a more complex problem. Sometimes a problem requires students to apply a specified technique. At ot her times they are asked to solve a prob lem using two or more specified approaches and to compa re the e ase or difficulty. In both cases, they are pr acticing specific techniques and re inforcing their understand ing of them. Sometimes the problem is open-ended so that students have to make decisions about the methods to use, and then apply them.

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Text Supplements There are two packages of supplements. One is provided to instructors who adopt the book for use in their courses and is not available to student s. It includes a solutions manual that conta ins full solutions of all the pro blems in the book . It also includes a set of transpar encies of appr opriate figures from the book. The figures are enlarged so that instructors can use the m in the classroom. The other p ackage consists of a laborat ory manual. In the bo ok itself, although specific families of  digital circuits are refer red to fro m time to time ( e.g., 74LS02), major stress is on design  principles .The laboratory manual is intended to engage students in the  practice of digital design, using the latest in current ly available tehnology. We show how specific design projects from the m anual can be incorpo rate d at specific points in the book . Even th ough some students may be learning about digital design from other texts, they too can use this labor ator y manual to gain experience with digital design practice. For additional information concerning the labora tory manu al, please review the text web site (http://www. wiley.com/college/elec/balabanian293512).

SOFTWARE We recommend the use of schematic entry and timing and functional simulation in the laboratory from the beginning (even with simple experiments or labs). The Xilinx WebPack software can be used, and is available for free from t he X ilinx web site (ht tp://www.xilinx.com). This software support s the m ost re cent version of ABE L, so students will be familiar with the user interface by the time Ch apter 8 is reached.

ACKNOWLEDGMENTS We would like to acknowledge our indebtedness to several people who have contributed to the developmen t of this book in man y ways. The first author wants to than k specifically Dr. Vijay Pitchumani (no w with Intel) and Dr. Dikran Meliksetian (now with IBM), both formerly at Syracuse University. At different times they were to be coauthors of this book, and they made important contributions to the development of the text. Individuals who made invaluable comments and observations when evaluating the manuscript at different stages in its development include: Yu Hen H u, Un iversity of Wisconsin –Madison David R. Kaeli, Northeastern University Juanita De Loach, Un iversity of Wisconsin –Milwaukee Mehmet Celenk, Ohio University James G. Ha rris, California Polytechnic State University, San Luis Ob ispo Sotirios G. Ziavras, New Jersey Institute of Technology James H. Aylor, Un iversity of Virginia Ward D. Getty, University of Michigan,A nn Arbor Alexandr os Elefther iadis, Columbia Un iversity in the City of New York  Ike E vans, The University of Iowa and Evolutionary Heu ristics Shahram La tifi, University of Nevada, Las Vegas Gregory B. Lush, University of Texas at El P aso Finally, we want to thank Ko-Chi Kuo, who produced the solutions for the chapter-end problems and created the solutions manual.

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Contents Chapter 1. CO D E CON VE RSIO N

NUMBER REPRESENTATION, CODES, AND 00

1. 2. 3.

Syst em s: D igit al A nd A na lo g 00 H a rd wa re, So ft wa re, A n d Fir mwa re 00 Number Systems 00 Binary And Other Number Systems 00 B ase C on ve rsio ns 00 Converting To The Decimal System 00 Converting From The Decimal System 00 From Octal Or Hexadecimal To Binary 00 B in ar y A r it hm et ic 00 A ddition 00 Subtraction 00 M ult ip lica tio n 00 D ivision 00 Complements: Two’s And One ’s 00 Addition Of Binary Numbers 00 4. Co de s a nd Co de Con ve rsion 00 Binary-Coded Decimals 00 We igh te d C od es 00 G ray Code 00 Se ve n-Se gm en t C od e 00 A lp ha nu me ric C od es 00 5. E r ro r D e te ct io n A n d C or re ct io n 00 E r r or-D e t ect in g C od es 00 E r r or-C or re ct in g C od es 00 H am min g C od es 00 C h ap t er Su m ma r y a n d R e vie w 00 Problems 00

Chapter 2. A N D LO GIC G ATES 1. Short Even

Boolean A lgebra D u a lit y P rin cip le

SWITCHING A LGEBRA 00 00 00 vii

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F un da me nt al Th eo ru ms 00 Swit ch in g A lge br a 00 2. Swit chin g O pe ra tio ns 00 Th e A nd O pe ra tion 00 A n d Tr ut h Ta ble 00 Th e O r O pe ra tio n 00 Th e No t O pe ra tion 00 Commentary 00 3. Swit ch in g E xp re ssio ns 00 Minterms, Maxterms, And Canonic Forms 00 Ge neralization of De Morgan’s Laws 00 4. Swit chin g F un ct io ns 00 Switching Operations On Switching Functions 00 Number Of Terms In Canonic Forms 00 Shannon’s E xp an sio n Th eo ru m 00 Sum-Of-Products Form 00 Product-Of-Sums Form 00 5. O t he r Swit ch in g O p er at io ns 00 E xclu sive -O r 00 N an d, N or , A n d Xn or O p er at io ns 00 6. U niversal operat ions 00 7. Logic G ates 00 Alternative Forms Of Nand And Nor Gates 00 E xclu sive -O r G a te s 00 Commentary 00 8. So me Pr act ica l M at te rs R e ga rd in g G a t es 00 Positive, Negative, And Mixed Logic 00 L ogic fa m ilie s 00 Ttl, C mos 00 Input/Output Characteristics Of Logic Gates 00 Fa n-O u t A n d Fa n-I n 00 Buffers 00 Po we r C on su mp tio n 00 9. Int egrated Circuits 00 Some Characteristics Of Ics 00 D esign E co nom y 00 Application-Specific Noise Margin 00 Speed And Propagation Delay Ics 00 10. Wired Logic 00 Tri-State (High-Impedance) Logic Gates 00 Open-Controller And Open-Drain Logic Gates 00 C ha pt e r Su mm ar y a nd R e vie w 00 Problems 00

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Chapter 3. LO GIC FU N CTIO NS

REPRESENTATION OF 00

1.

Min te rm A nd Ma xt er m L ist s 00 Minterm Lists And Sum-Of-Products Form 00 Maxterm Lists And Sum-Of-Products Form 00 2. Logic Maps 00 Logical Adjacency And Geometrical Adjacency 00 C ube s O f O rd er K 00 3. Minimal Realizations Of Switching Functions 00 Irreducible And Minimal Expressions 00 P rim e I mp lica nt s 00 Minimal Sum-Of-Products Expressions 00 Minimal Product-Of-Sums Expressions 00 Two-Level Implementations 00 A n d-O r I m ple me nt at io n 00 N an d Im ple me nt at io n 00 O r-A n d I mp le me nt at io n 00 4. I mp le m en ta tio n O f L ogic E xp re ssio ns 00 A nalysis 00 Features Of Gate Circuits 00 5. Timing D iagrams 00 6. I nco mp le te ly Sp ecifie d Fu nct io ns 00 D on ’t Cares 00 7. Comparators 00 2-B it C o mp ar at or s 00 G e ne ra liza tio n 00 4-B it C o mp ar at or s 00 Comparators Of Even Number Of Bits 00 Comparators Of Odd Number Of Bits 00 8. P rim e-I mp lica nt D e t er min at io n: Ta bu la r M e t ho d 00 Representations Of Adjacent K-Cubes 00 R a nk in g B y I nd ex 00 Incompletely Specified Functions 00 Selection Of A Minimal Expression 00 Completely Specified Functions 00 Handling Don’t Cares 00 9. M ult ip le -O u tp ut C ir cu it s 00 Chapter Summary and Review 00 Problems 00

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Binary A dder 00 Full A dder 00

COMBINATIONAL LOGIC DESIGN

00

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R ip ple -C ar ry A d de r 00 C ar ry-L oo ka he ad A d de r 00 B in ar y Su bt ra ct or 00 Two’s Complement Adder And Subtractor 00 O ne ’s Complement Adder And Subtractor 00 2. Multiplexers 00 Multiplexers As General-Purpose Logic Circuits 00 3. D ecoders A nd E ncoders 00 D e mu lt ip le xe rs 00 n -t o2n -L in e D e co de r 00 Tre e D ecode r 00 Decoders As G eneral-Purpose Logic Circuits: Code Conversion 4. R ead-O nly Memory - R O M 00 5. O t h er L SI P ro gr am me d L ogic D e vice s 00 Programmed Logic Arrarys (PLA) 00 Programmed Array Logic (PAL) 00 C ha pt e r Su mm ar y a nd R e vie w 00 Problems 00

Chapter 5.

00

SEQUENTIAL CIRCUIT COMPONENTS

D e fin it io ns A n d Ba sic Co nce pt s 00 Flip-Flops 00 SR Latch 00 Timing Problems And Clocked SR Latches J K La tch a nd F lip -F lo p 00 M ast er-Sla ve L a t ch 00 A Po ssib le D e sign 00 An Alternative Master-Slave Design 00 Edge-Triggering Parameters 00 D e la y ( D ) Flip -F lo ps 00 Edge-Triggered D Flip-Flop 00 T F lip -Flo p 00 Flip-Flop Excitation Requirements 00 2. R egisters 00 Serial-Load Shift Registers 00 Parallel-Load Register 00 Parallel-To-Serial Conversion 00 U n ive rsa l R e gist er s 00 C ha pt e r Su mm ar y a nd R e vie w 00 Problems 00

00

1. 2.

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Chapter 6. MACHINES 1.

SYNCHRONOUS SEQUENTIAL

00

Basic Concepts 00 St at e D ia gr am 00 Stat e Table 00 Constructing a State Table from a State Diagram 00 2. State A ssignments 00 A nalysis 00 Rules of Thumb for Assigning States 00 3. G en er al D esign P ro ce du re 00 Me aly Ma ch in e 00 Mo or e M ach in e 00 4. State Equivalence And Machine Minimization 00 Distinguishability And Equivalence 00 Machine Minimization 00 5. M ach in e Wit h Fin it e-M em or y Sp an s 00 Machines With Finite Input Memory 00 Machines With Finite Output Memory 00 Finite-Memory Machines 00 6. Synchronous Counters 00 Sin gle -M od e C o un t er s 00 U n it -D ist an ce C o un te rs 00 R in g Co un te rs 00 H an g-U p St at es 00 M ult i-M od e C ou nt er s 00 M od ulo -6 U p-D o wn C o un t er 00 O ther Counters 00 7. A lgo rit hm ic St at e M ach in es 00 B asic P rin cip le s 00 St at es A n d Clo ck s 00 A sm Sym bo ls A n d N ot at io n 00 Timing Considerations 00 R e a liza tio ns O f A sm s 00 Traditional Synthesis 00 Multiplexer-Controlled Approach 00 O ne-H ot Met hod 00 R om -Ba se d Me th od 00 8. A synchronous Inputs 00 Asynchronous Communication (Hand-shaking) 00 Chapter Summary and Review 00 Problems 00

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Chapter 7. MACHINES

ASYNCHRONOUS SEQUENTIAL

00

1. 2.

Th e Fu nd am en ta l-Mo de Mo de l 00 The Flow Table 00 Primitive Flow Tables 00 Assigning Outputs to Unstable States 00 3. Reduction of Incompletely Specified Machines 00 Th e Me rge r Ta ble 00 C om pa tib ilit y 00 Construction Of Merger Table 00 Determination Of Minimal, Closed Covers 00 Transition Tables 00 4. R aces A nd Cycles 00 Critical And Noncritical Races 00 Cycles And O scillations 00 10. Hazards In Fundamental-Mode Circuits 00 St at ic H a za rd s 00 D yn am ic H a za rd s 00 E sse nt ia l H aza rd s 00 C ha pt e r Su mm ar y a nd R e vie w 00 Problems 00

Chapter 8.

DESIGN USING HARDWARE

DESCRIPTION LANGUAGES

00

1.

Th e H a r dwa re D escr ip tio n L an gu age A B E L 00 Adder Specification In ABEL 00 Behavioral vs Operational Description 00 Sequential-Circuit Specification in ABEL 00 D on ’t -C ar e C on dit io n I n A B E L 00 Hierarchical Specifications In ABEL 00 2. P ro gr am ma ble L ogic D evice s ( PL D ) 00 Complex Programmable Logic Devices (CPLD) 00 Field-Programmable Gate Arrays (FPGA) 00 3. Th e D e sign F lo w Fo r H D L Sp ecifica tio ns 00 Synthesis and Technology-Mapping of ABE L Specifications Simulation Of ABEL Specifications 00 C ha pt e r Su mm ar y a nd R e vie w 00 Problems 00

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Chapter 9.

COMPUTER ORGANIZATION

1.

C on tr ol a nd D a ta pa th U n it s o f a Pr oce sso r 00 D ata pa th U nit 00 Cont rol U nit 00 Serial Multiplier Example 00 2. B asic St or ed -P ro gr am Co mp ut er 00 Central Processing Unit (CPU) 00 Sim ple D at ap at h 00 Controlling the Simple Datapath 00 3. C on tr ol U n it I mp le me nt at io ns 00 H a r d-Wir ed Co nt ro l U n it 00 M em or y a nd I/O I n te rfa ce 00 Microprogrammed Control Unit 00 4. Contemporary Microprocessor Architectures 00 Instruction Pipelining 00 P ar alle l H a r dwa re U n it s 00 M em or y H ie ra rch y 00 Complex Instruction-Set Computer (CISC) 00 Reduced Instruction-Set Computer (RISC) 00 5. M icr oco nt ro lle r A r ch it ect ur es 00 Chapter Summary and Review 00 Problems 00

A PPEND IX

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MOSFETS and Bipolar Junction Transistors

IND EX

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00

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