Digital Lab Manual

Digital Simulation Labs Revision 2.0

Developed by,

University Support Team Cadence, Bangalore

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Table of Contents General Notes Lab1: An Inverter.

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Lab 2: A Buffer

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Lab 3: ALU

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Lab 4: Flip Flop

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Lab 5: Clock gating enabled RTL Synthesis of the circuit studied in lab4

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Lab 6: Synthesis and Automatic layout generation followed simulation of the ALU circuit studied in Lab 26

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General Notes There are a number of things to consider before beginning these lab exercises. Please read through this section completely, and perform any needed steps in order to ensure a successful workshop. These labs were designed for use with Incisive Unified Simulator. Before running any of these labs, ensure that you‘ve set up IUS correctly: %> setenv IUSHOME

To setup the lab environment, please perform the following steps: 1. Ensure the software mentioned above is correctly setup. 2. Source the C-Shell related commands file i.e (csh). These labs were designed to be run using Root Simulator and the synthesis engine.

LINUX BASICS Determining your working directory To find out what directory you are currently working in, use the pwd (Print Working Directory) command. root@cadence:~$ pwd

The pwd command displays the full name of the directory in which you are working. The name of a user's home directory is his or her username, so yours will be different from the example (root is the person's username and the path to her home directory is /home/root.)

What is in a directory? To find out what's in a directory, you can use the ls command to list its contents. Typing the command by itself lists the contents of your current working directory, but you also can use the command to list the contents of any directory. For now, just type ls and press Enter. root@cadence:~$ ls Desktop

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Single dot - Current Directory A single dot is an "object" that represents the current directory, your "working directory". If you are working in /usr/lib/ then the single dot represents /usr/lib ; if you are working in your home directory, the dot represents your home directory. Compare the output from entering the following variations of the ls command while working in the user's home directory: root@cadence:~$ ls

Double dot - Parent Directory the double dot (two dots) is an object that represents the relative parent directory. This represents the directory immediately "above" (or which contains) the current directory. In the example, "home" is the parent of "root" in /home/root/. Type the ls command, a space, and the two dots, as shown, then press Enter. This will list the contents of the parent directory for your current working directory. root@cadence:~$ ls ..

Making a new directory Use the mkdir command to make a new directory using an unique name and then use ls to verify that your new directory was created. Before: root@cadence:~$ ls

Make your new directory: root@cadence:~$ mkdir file1

After: root@cadence:~$ ls file1

Change your working directory In Linux, you use the cd command to change your working directory. You can specify a directory change in several ways.

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Typing the cd command and pressing Enter will take you to your home directory from anywhere on the system. For example: root@cadence:cd file1 root@cadence:~$ pwd

Typing cd and the full name of a directory will take you to that directory from anywhere on the system. Full directory names begin with a leading forward slash. For example: root@cadence:~$ cd /home root@cadence:/home$ pwd /home

Return back to previous directory : root@cadence : cd -

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Lab1: An Inverter In this lab we will simulate the inverter code modeled using switch level by the help of Incisive unified simulator.In this lab we will see how to perform simulation in command mode using testbench without using GUI window. 1. Change directory to digitallabs/lab1/Inverter 2. You will need to copy each file present in solutions folder to Workarea/Inverter location by using the below mentioned command : 3. View the Code of Inverter and also the testbench for the same. 4. Compile the source Descriptions : (i) Compile the Inverter description with the -messages option:

ncvlog inverter.v –messages

The compiler places the inverter description in the INCA_libs library. (ii) Compile the testbench description with the -MESS option:

ncvlog inverter_test.v –MESS

The compiler places the inverter_test description in the INCA_libs library. Note: You can abbreviate options down to their shortest unique string and use upper or Lower case.

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List all “inverter” library objects (ncls inverter).

What library objects does the compiler create? Answer: The compiler creates Verilog VST objects. 5. Elaborate the top level Design (i) Elaborate the testbench

ncelab inv_test -messages The elaborator places the inv_test code and snapshot in the INCA_libs library.

List all ―inv_test" library objects (ncls inv_test). What library objects does the elaborator create? Answer: The elaborator creates SIG (signature), HDLCODE (code), and SSS (snapshot) objects.

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6. Simulate the Top-Level Design (i) Simulate the testbench:

ncsim inv_test The simulator displays results similar to the following:

Lab Summary: In this lab we saw how to compile, elaborate and simulate the tesbench for Inverter module.

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Lab 2: A Buffer In this lab, you will simulate a design using the Incisive simulator. You will: Perform this lab in the Buffer directory. This directory contains the following files (which you should briefly examine) describing a simple Buffer and its testbench: File(s) Description Buffer.v Buffer_test.v

Buffer code Testbench

1. Change directory to digitallabs/lab2/Buffer. 2. View the Code of Inverter and also the testbench for the same.

3 . Compile the Source Descriptions (i). Compile the buffer description with the -messages option:

ncvlog buffer.v –messages

The compiler places the Buffer description in the Buffer_lib library.

(ii). Compile the testbench description with the -MESS option:

ncvlog buffer_test.v –MESS

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The compiler places the buffer_test description in the Buffer_lib library. Note: You can abbreviate options down to their shortest unique string and use upper or lower case. List all “mux” library objects (ncls buffer).

What library objects does the compiler create? Answer: The compiler creates Verilog VST objects.

6. Elaborate the Top-Level Design

1. Elaborate the testbench:

ncelab buf_test The elaborator places the buffer_test code and snapshot in the Buffer_lib library.

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7. Simulate the Top-Level Design (i) Simulate the testbench:

ncsim buf_test The simulator displays results similar to the following:

Lab Summary In this lab, you simulated a design using the Incisive simulator. You: * Compiled, elaborated, and simulated the design and testbench

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Lab 3: ALU In this lab, you will simulate a design using the Incisive simulator. You will: * Create the cds.lib and hdl.var files * Compile, elaborate, and simulate the design and testbench Perform this lab in the TG directory. This directory contains the following files (which you should briefly examine) describing a simple Transmission gate and its testbench: File(s) Description alu.v -- Transmission Gate code test_alu.v -- Testbench 1. Change directory to lab3. 2. View the Code of alu and also the testbench for the same.:

Compile the Source Descriptions (i). Compile the alu design description with the -messages option:

ncvlog alu.v –messages

The compiler places the Transmission Gate description in the tg_lib library.

(ii). Compile the testbench description with the -MESS option:

ncvlog test_alu.v –mess

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3. Elaborate the design:

ncelab TESTGEN_ALU -access +rwc -mess .

4. Simulate the top level design: (i)

Simulate the testbench: with –gui option:

ncsim TESTGEN_ALU –gui The -gui option opens the Console and Design Browser windows. Tour the Graphical Interface 1. Examine the Console window.

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a. You can use the Menu Bar to run or step the simulation, set scopes and stops, show the value of objects, and start other graphical tools. b. You can use the Tool Bar to run, interrupt, reset, step, or next the simulation, and shut down the interface or the simulation, or disconnect the simulation. c. You can use the command line interface to the simulation in the I/O Region.

2. Examine the Design Browser window. Open an existing Design Browser window or select the Windows— new — Design Browser menu item or the Design Browser button. a. Display the objects of a scope and their value in the Objects List pane (Select any displayed scope in the Scope Tree pane). b. Display the component instances of the scope (double-click the scope in the Scope Tree pane).

Examine the Design and Testbench Hierarchy In this section of the lab you visit the Source Browser, Schematic Tracer and Waveform window.

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1. In the Design Browser window select the top-level (TESTGEN_ALU) scope and select the Source Browser button to send it to the target Source Browser window. As no such window yet exists, this opens a Source Browser window displaying the source of the Top-level unit, and makes it the default Source Browser target window. 2. In the Source Browser window ensure that just the top-level scope is selected (navigate up as needed and Select—This Scope) and send it to the target Schematic Tracer window. As no such window yet exists, this opens a Schematic Tracer window displaying the top-level unit, and makes it the default Schematic Tracer target. 3. In the Source Browser window ensure that just the top-level scope is selected and send it tothe target Waveform window. As no such window yet exists, this opens a Waveform window displaying the signals of the top-level unit, and makes it the default Waveform target window. a. In the left sidebar, select the Design Browser tab toexpand the sidebar area and display the embedded Design Browser. --- Run the simulation

--- Move primary cursor to previous edge of select signal.

Once the simulation is done you can see the following waveform window and console window with the outputs.

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Lab 4: Flip-Flop In this lab, you will simulate a design using the Incisive simulator. You will: * Compile, elaborate, and simulate the design and testbench using nclaunch command in single step mode. Perform this lab in the lab4 directory. This directory contains the following files (which you should briefly examine) describing a Flipflops and its testbenches: File(s) Description: ff.v

ff_t.v

1. Change directory to Root_Digital_labs/Workarea/lab4.View the Code of Flipflop and also the testbench for the same. Use the following command to invoke user friendly GUI: irun ff.v ff_t.v –access +rwc –gui

Now the Console & Design Browser window opens Before proceeding to the next step analyze the messages in the terminal window a. You can use the Menu Bar to run or step the simulation, set scopes and stops, show the value of objects, and start other graphical tools. b. You can use the Tool Bar to run, interrupt, reset, step, or next the simulation, and

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shut down the interface or the simulation, or disconnect the simulation. 2. Examine the Design Browser window. Open an existing Design Browser window or select the Windows— new — Design Browser menu item or the Design Browser button. a. Display the objects of a scope and their value in the Objects List pane (Select any displayed scope in the Scope Tree pane). b. Display the component instances of the scope (double-click the scope in the Scope Tree pane).

3. Tour the Waveform window. Open an existing Waveform window or select the Windows - New - Waveform menu item or the Waveform button.The simulator creates a default SHM database and sets a probe on any selected signals and opens a Waveform window displaying the selected signals. a. In the Design Browser window select all signals at the testbench scope. b. Add the selected signal(s) to the Waveform window (select the Waveform button or the Add Selected button or drag and drop the signals into the Waveform window).Note: To add additional signals simply select them in any window and click the Waveform button again. Waveform window appears as shown below

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Select ff_t and click on the wave form window button

Waveform window appears as shown below:

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Run the testbech simulation by clicking the following icon

We will obtain the required output of Flip flop in the waveform window as shown below:

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Lab 5: Clock gating enabled RTL Synthesis of the circuit studied in lab4

There are a number of things to consider before beginning the lab exercises. Please read through this section completely, and perform any needed steps in order to ensure a successful workshop. Go to directory lab4.

Lab directory details: lib

Contains the lib files for mapping the code to specified rtl.

work

It‘s a place to run Synthesis .

rtl

Flip flop rtl code ff.v

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Lets do the Synthesis first. 1. Invoke RTL Compiler by typing ―rc -gui‖ on your terminal window. The below picture can be seen after typing the above command.

The tool window look like the below image:

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The terminal will look like the below image after the tool is invoked.

2. Give the path of the library w.r.t to the directory you are in using the command: ―set_attribute lib_search_path ../lib‖

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3 Give the path of the RTL files with respect to the directory you are in using the below command: ―set_attribute hdl_search_path ../rtl‖ 4 Read the library from the directory specified in giving the path for the library files in step 2 using the command: ―set_attribute library slow.lib‖ ―slow_normal.lib‖ is the name of the library file in the directory ―library‖. There is another library there in that directory with name ―slow_highvt.lib‖. Any one of these two libraries could be used at a time. 5 Read the RTL files from the directory specified in the path in step 3. The RTL files are in the directory name ―rtl‖: ―read_hdl {ff.v }. 6 Now Elaborate the design using ―elaborate‖command. 7 .Give the command ―gui_show‖ to see the circuit in Tool window: The terminal window after the step 7 will look like

The Tool window looks like image on next page 8. Give the standard delay constraints using: ―read_sdc ./constraints_top.g‖. The terminal window looks like the image on next page.

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9. Synthesize the circuit using the command: ―synthesize -to_mapped -effort medium‖. The terminal window and the synthesized circuit in tool window will appear to be as on next page:

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Now report power of design using ―report power‖ in terminal Note down from the report: Leakage :

Dynamic :

Total:

Report timing to determine the critical path using ―report timing‖ command : How much slack do you observe ? ……………………ps If the slack is negative how would you optimize the design .? 10. Write the hdl code in terms of library components for the synthesized circuit using the command: ―write_hdl >> ff_synth.v‖ ―nco.hdl‖ is the name of file in which the code gets write. 11. Similarly write the constraint file using ―write_sdc >> ff_synth.sdc‖. 12. Similarly for Gates ―report gates‖. 13. Check area using ―report area‖. How much area do you observe ? ……………………………

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Enabling Clock Gating Now resynthesize design with clock gating . Circuit with Flip-Flops

Circuit with Flip-Flops clock gated

To ensure that clock-gating logic is inserted during synthesis, set the following attribute: set_attr lp_insert_clock_gating true / Open setup.g

file and see the added attribute.

Synthesize the design script by below command rc –f setup.g

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After the Synthesis do ―report power‖.

Note down the values below. Leakage : Dynamic:

Total:

How much percentage of improvent in dynamic power ?...................%

What is the impact on timing? Slack difference...................................

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Lab6: Synthesis and Automatic layout generation followed by simulation of the ALU circuit studied in Lab3 In this lab we will do the Synthsesis and Physical Design of NCO Design for which simulation is done in Lab6. Synthesis will be done using RTL Compiler and Physical Design will be done using Encounter Digital Implementation System. Go to directory /NCO/rclabs/work. Lets do the Synthesis first. Move to lab6 . Do listing to see the directories ‗ls‘. Go inside ALU .Then move to the work directory. cd work. Here you will find setup.g file. Open setup.g by typing below command nedit setup.g You will find the below code set_attr lib_search_path ../lib set_attr hdl_search_path ../rtl set_attr library {slow.lib} set_attr library slow.lib read_hdl alu.v elaborate read_sdc ./constraints.g synthesize -to_mapped report timing Let us understand the script.

1. Set the library directory path where library files are stored. set_attr lib_search_path ../lib 2. Give the path of the RTL files with respect to the local directory ―set_attr hdl_search_path ../rtl‖ 3. Read the library from the directory specified in giving the path for the library files in step 2 using the command: ―set_attr library slow.lib‖

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―slow.lib‖ is the name of the library file in the directory ―library‖. There is another library there in that directory with name ―fast.lib‖. Any one of these two libraries could be used at a time. 4 Read the RTL files from the directory specified in the path in step 3. The RTL files are in the directory name ―rtl‖: ―read_hdl alu.v 5 Elaborate the design using ―elaborate‖ command. 6 Give the command to see the circuit in Tool window: The terminal window after the step 7 will look like The Tool window looks like image on next page 7. Give the standard delay constraints using: ―read_sdc ./constraints.g‖.

8. Synthesize the circuit using the command: ―synthesize -to_mapped‖. 9. Report the critical path of the design. ―report timing‖ 10. Now synthesize the design by executing below command in the terminal/ Execute the script by typing ―rc –f setup.g‖ on your terminal window as given below

Type ― gui_show‖ in the terminal to see graphic window .

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Report power by using below command in terminal ―report power‖ What do find for the below column 11. Write the hdl code in terms of library components for the synthesized circuit using the command: ―write_hdl >> alu.v‖ ―nco.hdl‖ is the name of file in which the code gets write. 12. Similarly write the constraint file using ―write_sdc > > alu.sdc‖. 14. Timing could be check using ―report timing‖. 15. Similarly for Gates ―report gates‖. 16. Check area using ―report area‖. 17. Check Power dissipation using ―report power‖. After the Synthesis Physical Design can be done by invoking the tool ―Encounter Digital implementation‖. 18. Invoke the tool using ―encounter‖ or ―velocity‖. The tool starts as below image:

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The terminal window and tool window can be seens as similar to images on next page

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Go the Tool window and click on the File and select Import Design. A new window will open.

19. Select the verilog files using browse button. A new window ―Netlist files‖ will open.

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20. Click on the arrow button >> and select the verilog File ―alu_netlist.v‖ and click the Add button and then click the close button.

21. Click on Auto assign after top cell. 22. Similarly select the lef file by clicking the browse button and then add the lef file with name ―all.lef‖ in the lef directory. 23. Select the timing libraries. For maximum timing libraries select all libraries with ―slow‖ in their name and for minimum timing libraries select all libraries with fast in their names. Alternatively, instead of selecting all the libraries for Maximum timing libraries, type ―../lib/*slow*.lib‖ in space in front of Maximum Timing Libraries. This will select all the slow libraries. Similarly in front of Minimum Timing Libraries write ―../lib/*fast*.lib‖. 24. Similarly select ―alu.sdc‖ for timing constraint file. The Design Import window will look like the image on next page

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25. In the Design Import window click on Advanced Tab. Select Power out of the list on the left side of window. Enter the power nets as VDD and Ground nets as VSS. The screen shot is shown in the next page.

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26. Select OK. The tool window will look like image on next page.

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This is floorplan view of the design.

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27. Click on Floorplan and select ―Specify Floorplan‖.

Select the Aspect Ratio as per the requirement. Set aspect ratio to 1. Give some dimension in ―Core to left‖, ―Core to right‖, ―Core to top‖,―Core to bottom‖. e.g. give 20 to each. This is to create the space for Power rings which will be created in power planning. Click OK and the Tool window will be look like as below.

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28. Next step is to do global net connect .Click on Power - Connect Global Nets A browser opens as shown in the next page

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In the ―To Global Net‖ Column type VDD Select ―Pin‖ button from Connect and in Pin Names(s) type VDD , then click on ―Add to in list‖ ,so that it is added in Connection List column as shown next page . Similarly global net connect has to created to VSS as described above .After crating global net connect for VSS , click Apply button close the Global Net Connection window.

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29. Equivalent tcl command : globalNetConnect VDD -type pgpin -pin VDD -inst * -module {} globalNetConnect VSS -type pgpin -pin VSS -inst * -module {} Next step is power planning. Click on Power, select power planning and click on Add Rings.

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30. Select the top and bottom layer as Metal5, Left and Right as Metal6. Set the width as per the requirement ex 5 and taking the space between core boundary and I/O pad considerations. Select the option for offset as ―center in channel‖ and click OK. The power ring will get created in between the channel. The image on the next page is showing the power ring created.

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31 After the power planning, go to ―Place‖ and click Place Standard Cells. A new Window Place will appear. 32 Click OK on Place window and in physical view the blue coloured standard cells can be seen as a result of placement of standard cells.

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33 Click OK with all default settings. This is done to provide power to standard cells. The horizontal blue coloured metal1 stripes created as a result of Special Route.

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34 Now we power routing has to be done for the placed standard cells.For power routing , click on Route and select Special Route .When the window opens unckeck the Block Pins Pad Pins and Pad Rings ,because we are doing Sroute for standard cells as shown in the next page.

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Click on OK to power route for the standard cells.

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35 efore CTS, timing analysis has to be done for any setup violations. Click on Timing, and select Report Timing. A Timing analysis window will get open. In the window select the ―Pre-CTS‖ as Design Stage and select the ―Setup‖ as Analysis Type.

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36 Click OK to complet the Timing analysis. The timing information will get display on terminal in tabular form. In the table displayed on the terminal under ―timeDesign Summary‖, check for any negative value under WNS(Worst Negative Slack) and TNS(Total Negative Slack). The terminal will look as the image below and Tool window as on next page.

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The multi-coloured lines visible in the tool window are the connections between standard cells using metal layers. If any part of this design is Zoom-in, metal layers can be viewed easily.

Different colours show different metal 37 If there is any of the negative slack value under WNS or TNS, click Optimize in Tool window and Select Optimize Design. A new window ―Optimization‖ will get open. Select ―Pre-CTS‖ as Design Stage and ―Setup‖ as optimization type and click OK. The tool will optimize the design and the optimized timing results will be displayed over terminal again.

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In this case we did not get any negative slack, so this step is skipped here. 38 Go to Clock, click ―Synthesize Clock Tree‖, a new window ―Synthesize Clock Tree‖ will get open.

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39 Click on Gen Spec and a new window ―Generate Clock Spec‖ will open.

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40 From Cells List, Select all clocks starting with ―CLK‖ and click on Add button to add them to the Selected Cells. Select a name for Output specification.

41 Click OK. Then specify a name for Results Directory. and click OK. The tool window looks like the image below.

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42 Again Perform the Timing by clicking on Timing and selecting Report Timing. Select ―Post-CTS‖ under Design Stage and do the select ―Set-up‖ as Analysis Type.

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43 Click Ok to perform the timing. The timing information will be displayed over the terminal window. Again check for any negative slacks under WNS or TNS.

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44 If there is any negative value found for either of WNS or TNS then perform the Optimization Technique to reduce the negative slack. No negative slack is found in the terminal image on previous page so this step is skipped here. 45 Timing Analysis for ―Setup‖ as Analysis Type is done. Repeat Step 27 for performing timing for ―Post CTS‖ as Design Stage and ―Hold‖ as Analysis Type. The tool will show the timing results in the terminal window.

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46 After Timing Analysis is performed, the timeDesign Summary is showing the negative slack values for both TNS and WNS. Perform the Optimization. Go to Optimize and click on Optimize Design. Select ―Post-CTS‖ as and ―HOLD‖ as the Optimization Type

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47 Click OK to perform the Optimization and Tool will perform the optimization and displays the optimized results in the terminal window under timeDesign Summary. The results of Optimization can be seen on the next page in tabular form for both Setup and Hold mode. As compare to the Timng Results performed for Hold mode in Step 30, the design has been optimized and tabular results shows that all slack values are now positive values and no more negative values for slack.

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Now we have to connect all new cells to VDD/GND Type below commands in the terminal globalNetConnect VDD -type tiehi globalNetConnect VDD -type pgpin -pin VDD -override globalNetConnect VSS -type tielo globalNetConnect VSS -type pgpin -pin VSS -override 48 Perform Routing by clicking Route, and select NanoRoute and then click Route. A window NanoRoute will open.

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Equivalent tcl command # Run global Routing # utilizes the nano router globalDetailRoute

49 Click Ok to Perform Routing. The tool will Perform the Routing and the Routing statistics can be seen on terminal window including DRC violations.

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After routing tool window looks like the below image.

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50 Perform the timing again. Go to Timing, seelct Report Timing and a Timing Analysis window will get open. Select ―Post-Route‖ as the Design Stage and ―Setup‖ as Analysis Type. Click Ok. The timing results will be displayed in terminal window for Set up mode.

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Since there is no negative value of slack so design does not require optimization for Setup mode in Post-Route stage. 51 Repeat Step 36 for ―Post-Route‖ as Design Stage and ―Hold‖ as the Analysis Type. Click OK. The timing results can be seen in the terminal window for hold mode.

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As there is no negative value of slack, the optimization is not require to perform. The final view of the circuit is as below: Write the final gds file Go to File – Save – GDS/OASIS

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Equivalent tcl command: streamOut final.gds -mapFile streamOut.map -libName DesignLib -units 2000 -mode ALL

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