Difference Between Harvard and Princeton or Von Neumann Architecture

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Difference between Harvard and Princeton or Von Neumann Architecture mbedlabsAdmin

February 17, 2015

There are two basic Computer architectures: -Harvard Architecture -Princeton Architecture(Von Neumann Architecture) In Harvard Architecture, the CPU can have separate data and instruction memory and busses, allowing transfers to be performed simultaneously on both busses. In Von Neumann architecture, the CPU can be either reading an instruction or reading/writing data from/to the memory. Both cannot occur at the same time since the instructions and data use the same bus system. Harvard architecture machine have distinct code and data address spaces: instruction address zero is not the same as data address zero. Instruction address zero might identify a twenty-four bit value, while data address zero might indicate an eight bit byte that isn’t part of that twenty-four bit value. While in Von Neumann architecture, Instruction and Data addresses are same. In Harvard architecture, Processor can execute an instruction in one clock cycle, if appropriate pipelining strategies are implemented. In the first stage of pipeline, the instruction to be executed is fetched from program memory and decoded. In the second stage, data is taken from the data memory using the decoded instruction or address.While in von Neumann architecture, Processor needs two clock cycles to complete an instruction. Pipelining the instructions is not possible. The Von Neumann architecture’s largest advantage is that it simplifies the microcontroller chip design because only one memory is accessed. For microcontrollers, its biggest asset is that the contents of RAM (random-access memory) can be used for both variable (data) storage as well as program instruction storage. An advantage for some applications is the program counter stack contents that are available for access by the program. This allows greater flexibility in developing software, primarily in the areas of real-time operating systems.

The Harvard architecture executes instructions in fewer instruction cycles that the Von Neumann architecture. This is because a much greater amount of instruction parallelism is possible in the Harvard architecture. Parallelism means that fetches for the next instruction can take place during the execution of the current instruction, without having to either wait for a “dead” cycle of the instruction’s execution or stop the processor’s operation while the next instruction is being fetched.

Princeton (Von Neumann) Instruction: Read a data byte from memory and store in the accumulator. 1. If this instruction is executed in Princeton architecture then it is executed as follows.

The following cycles are required to execute the above instruction Cycle 1: read instruction(Instruction Fetch cycle) Cycle 2: Read Data out from memory and store in accumulator Using Harvard Architecture

The execution above instruction will be done in the following cycles Cycle 1: Complete the previous instructions and Read the present instruction. (Note: this will not be done only for jump instruction as previous instruction.Because if jump is there, it flushes off the instructions int the stack). Cycle 2 : Execute , Read Data memory and store in Accumulator. Read next instruction.

Advantage of this architecture is that each instruction takes one instruction cycle. Example: in PIC Microcontroller, of 4 MHz , it requires 4 clock cycles to execute one instruction cycle. Hence, 1 million instructions could be executed in one second. Summary: Princeton Architecture

Harvard Architecture

Only one Memory interface is there.

Two memory banks Prg store and data store

Avg computation speed is low(no parallelism)

Avg computation speed is high

Less no of control signals

More no of control signal