Dft Basics

Vishwani D. Agrawal  Rutgers University, Dept. of ECE  New Jersey 

http://cm.bell-labs.com/cm/cs/who/va 

January 2003 

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Basic concepts and definitions Fault modeling Fault simulation ATPG DFT and scan design BIST Boundary scan IDDQ test

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Basic concepts and definitions Fault modeling Fault simulation ATPG DFT and scan design BIST Boundary scan IDDQ test

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Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

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Based on analyzable fault models, which may not map onto real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.  Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. 

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Design for testability (DFT) 

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Chip area overhead and yield reduction  Performance overhead Software processes of test  Test generation and fault simulation  Test programming and debugging Manufacturing test  Automatic test equipment  (ATE) capital cost  Test center operational cost

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0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price  = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation)  = Depreciation + Maintenance + Operation  = $0.854M + $0.085M + $0.5M  = $1.439M/year  Test cost (24 hour ATE operation)  = $1.439M/(365 x 24 x 3,600)  = 4.5 cents/second Agrawal: Digital

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1997--2001 2003--2006 Feature size (micron) 0.25 - 0.15 Transistors/sq. cm

0.13 - 0.10

4 - 10M

18 - 39M

Pin count

100 - 900

160 - 1475

Clock rate (MHz)

200 - 730

530 - 1100

Power (Watts)

1.2 - 61

2 - 96

* SIA Roadmap, IEEE Spectrum , July 1999 2003

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A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y . Cost of a chip:

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Defect level  (DL) is the ratio of faulty chips among the chips that pass tests.

DL is measured as parts per million (ppm). DL is a measure of the effectiveness of  tests. DL is a quantitative measure of the manufactured product quality. For  commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

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Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.45 CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM) Agrawal: Digital

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VLSI Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of  chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99%

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Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -  Semiconductor Devices and Circuits,  Wiley, 1981. 2003

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Occurrence frequency (%)

Defect classes

51 1 6 13 6 8 5 5 5

Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing)

Ref.: J. Bateson, In-Circuit Testing , Van Nostrand Reinhold, 1985. 2003

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Three properties define a single stuck-at fault   

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Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value  j 

c  1 0

a  b 

d  e 

0(1)

s-a-0

g  1

1(0)

h  i 

z  1

k 

f 

Test vector for h  s-a-0 fault 2003

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Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

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sa0 sa1

Faults in red removed by equivalence collapsing

sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 2003

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Fault models are analyzable approximations of  defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technologydependent faults require special tests. Memory and analog circuits need other  specialized fault models and tests. Agrawal: Digital

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Fault simulation Problem: Given   

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Determine 

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Fault coverage - fraction (or percentage) of  modeled faults detected by test vectors Set of undetected faults

Motivation  

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A circuit A sequence of test vectors A fault model

Determine test quality and in turn product quality Find undetected fault targets to improve tests

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Verified design netlist

Verification input stimuli

Fault simulator

Test vectors

Modeled Remove  fault list tested faults  Fault Low  coverage ? Adequate 

Test Delete  compactor  vectors 

Test generator 

Add vectors 

Stop  2003

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Circuit model: mixed-level 

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Signal states: logic 

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Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits

Timing: 

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Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback

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Faults:  

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Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large

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Test vectors

Fault-free circuit

Comparator 

f1 detected?

Comparator 

f2 detected?

Comparator 

fn detected?

Circuit with fault f1

Circuit with fault f2

Circuit with fault fn

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Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together 

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A randomly selected subset (sample) of  faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults.

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Detected fault All faults with a fixed but unknown coverage

Undetected fault

Random picking N s = sample size

N   p = total number of faults

N s