Design Example

Introduction to Gm/ID-based sizing

B. Murmann

1

Motivation: Basic Design Example • CL

RL

CL

+ vod +vid/2

Rs -vid/2 VIC

B. Murmann

ITAIL

Given specifications and objectives – 0.18mm technology – Low frequency gain = -4 – RL=1k, CL=50fF, Rs=10kΩ – Maximize bandwidth while keeping ITAIL  600mA – Determine W/L – Estimate dominant and non-dominant pole

2

To Be Avoided: Spice Monkeying •

One way to solve this problem is to “poke around” in Spice and play this out like a video game…

•

Issues – Learn nothing about fundamental tradeoffs and optimality – Will not detect simulation or modeling errors

B. Murmann

3

Better: Systematic Design •

Start with a circuit model

•

Establish links between design specs and model parameters

•

Establish links between model parameters and transistor parameters – This is where things get problematic… Cgd Rs vi

B. Murmann

+ vgs -

Cgs+Cgb

gmvgs

ro

RL

CL+Cdb

+ vo -

4

Textbook Transistor Model

ID 

1 W mCox (VGS  Vt )2 (1  VDS ) 2 L

gm 

dID 2I W  mCox VOV 1  VDS   D dVGS L VOV

go 

dID ID 1 W  mCox VOV 2     ID dVDS 2 L 1  VDS

Cgs 

B. Murmann

2 WLCox 3

VOV  VGS  Vt

etc.

5

What are mCox (KP) and  (LAMBDA)? .MODEL nmos214 nmos +acm +VERSION +XJ +K1 +K3B +DVT0W +DVT0 +U0 +UC +AGS +KETA +RDSW +WR +XL +DWB +CIT +CDSCB +DSUB +PDIBLC2 +PSCBE1 +DELTA +PRT +KT1L +UB1 +WL +WWN +LLN +LWL +CGDO +CJ +CJSW +CJSWG +CF +PK2 +PU0 +PVSAT +nlev

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

3 3.1 1E-7 0.5916053 2.3938862 0 1.3127368 256.74093 5.182125E-11 0.4347252 -9.888408E-3 128.705483 1 0 9.111767E-9 0 0 0.0159753 2.543351E-3 8E10 0.01 0 0 -7.61E-18 0 1 1 0 4.91E-10 9.652028E-4 2.326465E-10 3.3E-10 0 9.619963E-4 4.5760891 1.19774E3 3

B. Murmann

hdif TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA PUA PETA0 kf

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

0.32e-6 27 2.3549E17 3.225139E-3 1E-7 0 0.3876801 -1.585658E-9 1.003268E5 4.989266E-7 6.164533E-4 0.5 0 -1E-8 -0.0854824 2.4E-4 2.981159E-3 0.7245546 -0.1 1.876443E-9 6.6 -1.5 0.022 -5.6E-11 1 0 0 2 4.91E-10 0.8 0.8 0.8 -7.714081E-4 -1.060423E-4 1.469028E-14 9.968409E-5 0.5e-25

LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG NFACTOR CDSCD ETAB PDIBLC1 DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA PUB PKETA

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

49 4.1E-9 0.3618397 1E-3 1.776268E-7 0 0.0238708 2.528203E-18 1.981392 5E-6 0.9388917 -0.2 1.617316E-8 -5.383413E-9 2.2420572 0 9.289544E-6 0.1568183 0.7445011 7.200284E-3 1 -0.11 4.31E-9 3.3E4 0 0 1 1 1E-12 0.3836899 0.1253131 0.1253131 -2.5827257 -5.373522E-3 1.783193E-23 -2.51194E-3

 Even for a relatively old 0.18mm process, the models used in simulation are quite complex  The model card shown on the left is a 110-parameter BSIM3v3 model – More recent models require even more parameters (e.g. PSP, BSIM6) – KP and LAMBDA are nowhere to be found  It turns out that the I-V characteristics of a modern MOSFET cannot be accurately described by the square law

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Simulation (NMOS, 5/0.18mm, VDS=1.8V) 3.5

2 Square Law

3

SQRT(I D [mA])

ID [mA]

2.5 2 1.5 1

1.5

1

0.5

0.5 0 0

•

0.5

1 VGS [V]

1.5

0 0

0.5

1 VGS [V]

1.5

Two observations – The transistor does not abruptly turn off at some Vt – The current is not perfectly quadratic in (VGS–Vt)

B. Murmann

7

Current on a Log Scale

0

10

NMOS214 Square Law NPN214

ID, IC [mA]

-2

10

~90mV/decade -4

60mV/decade

10

-6

10

0

B. Murmann

0.2

0.4

0.6

0.8 1 VGS, VBE [V]

1.2

1.4

1.6

8

gm/ID 40 NMOS214 Square Law (2ID/VOV)

30

gm/ID [S/A]

BJT (q/kT) 20

10

0

•

0.2

0.4

0.6

0.8

1 VGS [V]

1.2

1.4

1.6

1.8

The square law fails miserably at predicting gm/ID for low VGS

B. Murmann

9

0.2

0.48

0.19

0.46

0.18

0.44

Vt [V]

IDL [mAmm]

Length Scaling and Vt

0.17 0.16 0.15

0.42 0.4

0.2

0.4

0.6 L [mm]

0.8

1

0.38

0.2

0.4

0.6 L [mm]

0.8

1

•

The current does not scale perfectly with 1/L (IDL ≠ const.)

•

The threshold voltage of the device depends on the channel length B. Murmann

10

Cause of these Complications •

Weak inversion – For VGS below of near Vt, the current is caused by diffusion instead of drift; MOSFET behaves similar to BJT

•

Moderate inversion – A wild mix of drift and diffusion currents

•

Strong inversion – Mostly drift current, but short channel effects complicate the transistor behavior • Velocity saturation due to high lateral field • Mobility degradation due to high vertical field

•

In addition, there are several effects related to small geometries – Strong VDS dependence of ID, ro and Vt (DIBL) – Vt depends on channel length (SCE and RSCE)

B. Murmann

11

The Problem Specifications Square Law

Hand Calculations Circuit

BSIM or PSP

Spice Results

•

Since there is a disconnect between actual transistor behavior and the simple square law model, any square-law driven design optimization will be far off from Spice results

B. Murmann

12

The Solution Specifications BSIM

Spice

Design Tables

Hand Calculations Circuit

BSIM

Spice Results

 Use pre-computed spice data in hand calculations

B. Murmann

13

Starting Point: Technology Characterization via DC Sweep * /usr/class/ee214b/hspice/techchar.sp .inc '/usr/class/ee214b/hspice/ee214_hspice.sp' .inc 'techchar_params.sp' .param ds = 0.9 .param gs = 0.9 vdsn vgsn vbsn mn

vdn vgn vbn vdn

0 0 0 vgn 0 vbn

.options dccap post brief accurate nomod .dc gs 0 'gsmax' 'gsstep' ds 0 'dsmax' 'dsstep' .probe .probe .probe .probe .probe .probe .probe .probe .probe .probe .probe

n_id n_vt n_gm n_gmb n_gds n_cgg n_cgs n_cgd n_cgb n_cdd n_css

B. Murmann

= = = = = = = = = = =

W/L

dc 'ds' dc 'gs' dc '-subvol' nmos214 L='length' W='width'

par('i(mn)') par('vth(mn)') par('gmo(mn)') par('gmbso(mn)') par('gdso(mn)') par('cggbo(mn)') par('-cgsbo(mn)') par('-cgdbo(mn)') par('cbgbo(mn)') par('cddbo(mn)') par('-cbsbo(mn)-cgsbo(mn)')

VGS -VSB VDS

14

Store Data in a Matlab Structure >> load 180n.mat; >> nch nch = ID: VT: GM: GMB: GDS: CGG: CGS: CGD: CGB: CDD: CSS: VGS: VDS: VSB: L: W:

[4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [4-D double] [73x1 double] [73x1 double] [11x1 double] [22x1 double] 5

Four-dimensional arrays

𝐼𝐷 (𝐿, 𝑉𝐺𝑆 , 𝑉𝐷𝑆 , 𝑉𝑆𝐵 ) 𝑉𝑡 (𝐿, 𝑉𝐺𝑆 , 𝑉𝐷𝑆 , 𝑉𝑆𝐵 )

𝑔𝑚 (𝐿, 𝑉𝐺𝑆 , 𝑉𝐷𝑆 , 𝑉𝑆𝐵 ) …

>> size(nch.ID) ans = 22

B. Murmann

73

73

11

15

Lookup Function (For Convenience) >> lookup(nch, 'ID', 'VGS', 0.5, 'VDS', 0.5) ans = 8.4181e-006 >> help lookup The function "lookup" extracts a desired subset from the 4-dimensional simulation data. The function interpolates when the requested points lie off the simulation grid. There are three basic usage modes: (1) Simple lookup of parameters at given (L, VGS, VDS, VSB) (2) Lookup of arbitrary ratios of parameters, e.g. GM_ID, GM_CGG at given (L, VGS, VDS, VSB) (3) Cross-lookup of one ratio against another, e.g. GM_CGG for some GM_ID

In usage scenarios (1) and (2) the input parameters (L, VGS, VDS, VSB) can be listed in any order and default to the following values when not specified: L = VGS VDS VSB

B. Murmann

min(data.L); (minimum length used in simulation) = data.VGS; (VGS vector used during simulation) = max(data.VDS)/2; (VDD/2) = 0;

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Key Question •

How can we use all this data for systematic design?

•

Many options exist – And you can invent your own, if you like

•

Method that I promote – Look at the transistor in terms of width-independent figures of merit that are intimately linked to design specification • Rather than some physical modeling parameters that do not directly relate to circuit specs)

– Think about the design tradeoffs in terms of the MOSFET’s inversion level, using gm/ID as a proxy

B. Murmann

17

Figures of Merit for Design Square Law

•

Transconductance efficiency – Want large gm, for as little current as possible

•

Transit frequency – Want large gm, without large Cgg

•

Intrinsic gain – Want large gm, but no go

B. Murmann

gm ID



gm Cgg

3 mVOV  2 L2

gm go

2  VOV

2 VOV

18

Design Tradeoff: gm/ID and fT

gm/ID [S/A], f T [GHz]

40

fT

Moderate Inversion

30

gm/ID 20

Weak Inversion

Strong Inversion

10

0 -0.4

-0.3

-0.2

-0.1

0

0.1 VOV [V]

0.2

0.3

•

Weak inversion: Large gm/ID (>20 S/A), but small fT

•

Strong inversion: Small gm/ID (20S/A …

15 S/A

…