Design Compiler J-2014.09 TrainingUpdate

Design Compiler J-2014.09 Update Training RTL Synthesis

CONFIDENTIAL INFORMATION The following material is confidential information of Synopsys and is being disclosed to you pursuant to a non-disclosure agreement between you or your employer and Synopsys. The material being disclosed may only be used as permitted under such non-disclosure agreement. IMPORTANT NOTICE In the event information in this presentation reflects Synopsys’ future plans, such plans are as of the date of this presentation and are subject to change. Synopsys is not obligated to develop the software with the features and functionality discussed in these materials. In any event, Synopsys’ products products may be offered and purchased only pursuant to an authorized quote and purchase order or a mutually agreed upon written contract.

Design Compiler J-2014.09 QoR Highlights • 15% smaller area compared to H-2013.03 • 20% reduction in leakage power compared to H-2013.03 • 25% runtime improvement compared to I-2013.12 on designs with long runtime (20+ hours)

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

Optimization One-Pass Retiming Improvement Checkpoint Guidance for Formality Verification Improved Area Optimization of Gate-Level Netlist Multibit Mapping Improvements Changes to Shift Register Identification Register Replication Enhancements Manual Control of MUX Mapping

One-Pass Retiming Improvement •  Automatically detects the number of pipeline stages and adjusts the timing constraints before retiming • Produces better QoR • Beneficial for designs with a large number of pipeline stages create_clock  period 1.0 clk set_optimize_registers true compile_ultra scan –

–

Before Retiming

After Retiming

Delay goal 4.0

clk 1.0

I-2013.12-SP4

Checkpoint Guidance For Formality Verification • Enables higher completion rate in one-pass retiming • Eliminates the manual two-pass verification process with placement-aware multibit mapping • Creates an intermediate netlist and writes the guide_checkpoint guidance command to the .svf file when  – Retiming a design using the set_optimize_registers command before running the compile_ultra command  – Performing placement-aware multibit mapping of replicated registers, using the create_register_bank command

• Works with Formality I-2013.12-SP4 and later

I-2013.12-SP2

Improved Area Optimization Of Gate-Level Netlist • The optimize_netlist -area  command was added in Design Compiler in I-2013.12 to improve the area of new and legacy netlists • This flow enhancement improves area by 10% compared to the H-2013.03 release • Run this command after compile_ultra : compile_ultra optimize_netlist -area

• The optimize_netlist  command is included in the I-2013.12-SP2 Design Compiler Reference Methodology

I-2013.12-SP2

Improved Area Optimization Of Gate-Level Netlist: Reference Methodology Flow Library setup Read RTL Apply constraints Apply power settings Tcl or DEF

Optional Floorplan

compile_ultra

scan

–

gate_clock

–

insert_dft compile_ultra

incremental -scan

–

optimize_netlist -area Write design and reports (.ddc, Milkyway, Verilog) To next reference methodology

I-2013.12-SP2

Multibit Mapping Improvements set_multibit_options -mode timing_only • Multibit register inference in compile_ultra  now supports a new timing_only  mode set_multibit_options [-mode non_timing_driven ;# default ;# maps to multibit register whenever possible

| timing_driven ;# maps to multibit register only when it does not ;# hurt timing or area QoR

| timing_only ] ;# maps to multibit register only when it does not ;# hurt timing QoR even if area QoR is adversely ;# affected

I-2013.12-SP1

Multibit Mapping Improvements  Additional Scan Scan Register Support Support • Multibit register inference in compile_ultra  now supports multibit scan registers with internal scan chains and a and a dedicated or gated scan output 1-bit register

New

(SDFF_SO)

2-bit register

2-bit register

(SDFF2_SO)

Multibit Mapping Improvements Scan Cell Library Modeling Requirements • Both single bit and multibit versions of scan registers must be present in the same .lib file • This type of multibit register is marked as “blackbox “blackbox””  – Recommended: Specify the user_function_class attribute for sizing optimization optimization • Compile the .lib using Library Compiler I-2013.12 I- 2013.12 or later versions • See Library Compiler I-2013.12 update training for more information

I-2013.12-SP2

Shift Register Identification Synchronous Shift Registers Not Identified by Default • Synchronous shift register identification is disabled by default to achieve higher multibit cell usage  – Preserves multibit mapping throughout the flow

• Enable only under both conditions:  – When multibit cells are not used

 – When it helps to improve area for your design set_app_var compile_seqmap_identify_shift_registers_with_synchronous_logic true (default is now false)

I-2013.12-SP2

Shift Register Identification Short Shift Registers Not Identified Across Hierarchy • Shift registers are only identified across hierarchical boundaries if they have a length of 3 or more  – Reduces excessive scan chain criss-crossing with registered interfaces  – Helps improve congestion and scan chain wire lengths  – Reduces port punching during scan insertion Shift register identified Shift register not identified (all registers scan-replaced)

I-2013.12-SP1

Manual Register Replication  Across Hierarchy • Design Compiler version I-2013.12 can replicate registers and combinational logic on a timing path from or to that register  – Limited to logic in the same hierarchy or across one level of hierarchy

• Starting in I-2013.12-SP1, Design Compiler can now replicate registers and combinational logic that are beyond a single level of hierarchy

I-2013.12-SP1

Manual Register Replication  Across Hierarchy m1 m1/m2/m3

m1/m2 U2

Original logic U3

 A_reg

U1 U4

m1/m2/m3

m1

m1/m2 U1_rep1

 A_reg_rep1

 A_reg

U1

U2

New logic after using the following command

U3

U4

set_register_replication

num_copies 2 m1/m2/m3/A_reg -include_fanout_logic U1

–

I-2013.12-SP2

map_to_mux Attribute Manual Control for MUX Mapping

Design Compiler Graphical

• New map_to_mux attribute to specify MUX mapping  – Set on specific MUX_OP or SELECT_OP instances in GTECH  – Does not restrict optimization (no size_only or dont_touch)

 – Replaces hdlin_infer_mux with size_only or the //synopsys infer_mux_override  directive  – In some situations, MUX mapping can help improve congestion

• Use with compile_ultra spg to ensure mapping to library MUX cells –

 – Use cross-probing data from the congestion map to help identify the target instances

 – Set the map_to_mux attribute on these specific instances before running

compile_ultra -spg  – Verify with get_attribute or report_attribute -cell

I-2013.12-SP2

map_to_mux Attribute Example

Design Compiler Graphical

read_verilog test.v link ... report_cell [get_cells block1_0/C572] ;# identify targeted SELECT_OP ... #Cell Reference Library Area Attributes #----------------------------------------------------------------------------#block1_0/C572 *SELECT_OP_32.16_32.1_16 0.000000 s, u #----------------------------------------------------------------------------#Total 1 cells 0.000000 set_attribute [get_cells block1_0/C572] "map_to_mux" true compile_ultra -spg report_reference ;# muxes now present ... #Reference Library Unit Area Count Total Area Attributes #----------------------------------------------------------------------------... #mylib_mux2_b1 mylib 1.001000 16 16.016001 #mylib_mux4_a1 mylib 2.717000 160 434.720001 ...

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

Improved Usability (1 of 2) Enhanced report_resources Multiple-Port Net Fixing Options ILM Obsolescence Multicore Enhancements Infeasible Paths Support New -physical option with report_timing Support for Flat Query Commands

Improved Usability (2 of 2) Cross-Probing from RTL to Gates RTL Browser Enhancements RTL Cross-Probing for Datapath

Enhanced report_resources • Reports datapath leakage that blocks datapath extraction after synthesis • Generates the following HDL messages from analyze_datapath_extraction in report_resources  – HDL-120: Datapath leakage blocks extraction  – HDL-125: Instantiated DesignWare component cannot be extracted  – HDL-132: Mixed sign data types blocks extraction

•  Available in text report, HTML report, and RTL crossprobing Datapath Extraction Report Information: The output of subtractor associated with resources 'sub_388 (test.v:388)' is treated as signed signal. (HDL-132)

Multiple-Port Net Fixing Options User Interface • The set_fix_multiple_port_nets  command has two new options:  – Use the new -exclude_clock_network  option to exclude nets belonging to the clock network from multiple-port net fixing  – Use the new no_rewire  option to disable rewiring attempts before buffering multiple-port and constant-port nets –

 – Effective when advanced multiple-port net fixing is enabled

• The compile_advanced_fix_multiple_port_nets variable still controls advanced multiple-port net fixing  – Enabled by default in DC Explorer (default: true)

 – Disabled by default in Design Compiler topographical and wire load modes (default: false)

H-2013.03

ILM Obsolescence In Design Compiler • Beginning in H-2013.03, log messages warned you that ILMs are in the flow • Block-level message with create_ilm  : Information: Use of command 'create_ilm' is not recommended. This command will be obsolete in a future release. (INFO-103)

• Top-level message when using ILM blocks: Information: Use of ILM blocks is not recommended. The use of ILM blocks will be obsolete in a future release. (ABS-259)

ILM Obsolescence No Support for ILMs in J-2014.09 • Design Compiler no longer supports the creation or use of ILMs • IC Compiler no longer supports ILM usage • Ensure that you have successfully migrated to the use of block abstractions in your flow • Work with your AC or Synopsys support center if you face issues when trying block abstractions

J-2014.09

ILM Obsolescence In Design Compiler • Beginning in J-2014.09, error messages are issued when ILMs are used in the flow • Block-level message with create_ilm  : Error: Starting with version 2014.09, the create_ilm command is no longer supported. Use the 'create_block_abstraction' command instead. (OBS-012)

• Top-level message when trying to read ILM designs: Error: Reading of ILM designs is no longer supported. Cannot read ILM.ddc. (DDC-35)

I-2013.12-SP2

Multicore Enhancements Overview

• set_host_options  max_cores invokes multicore capability in Design Compiler –

 – Helps improve the tool runtime

• The license requirement in Design Compiler has changed to one set of licenses for every four cores  – In previous releases, one set of licenses were needed for every two cores

• If the number of available cores on the machine is less than the number of cores requested, performance can be impacted

Multicore Enhancements Enhanced set_host_options -max_cores Command • Case 1: Machine with fewer cores

I-2013.12-SP1

 – Number of cores on the machine < number of user-specified cores  – set_host_options  resets the max cores to the maximum number of cores on the machine  Warning: You requested 4 cores. However, the host hostname1 only has 2 available cores. The tool will ignore the request and use -max_cores 2. (UIO-230)

• Case 2: Machine with high load

I-2013.12-SP2

 – Most of the cores on the machine are already overloaded  – set_host_options  limits the number of cores based on the machine load  Warning: You requested 14 cores. However, load on host hostname2 is 10.150000. Tool will ignore the request and use 6 cores. (UIO-231)

I-2013.12-SP3

Multicore Enhancements Enhanced set_host_options -max_cores Command • Both checks are on by default • To disable the checks: set_app_var disable_multicore_resource_checks true  – Setting to true can impact multicore performance

I-2013.12-SP2

Infeasible Paths Support  Automatic Detection During Compile • Paths are infeasible when timing cannot be met due to:  – Unreasonable input or output delays  – Missing timing exceptions (false path and multicycle path)

• Starting in I-2013.12-SP2, Design Compiler  – Detects and treats infeasible paths as false paths during synthesis  – Optimizes other critical paths in presence of infeasible paths

 – Removes tool-derived timing exceptions at the end of compile  – The write_sdc command writes out only user-specified timing exceptions

 – Supports consistent capability with DC Explorer

• Supporting infeasible paths helps improve synthesis runtime and timing QoR of feasible paths

I-2013.12-SP2

Infeasible Paths Support Impact on Design Timing Constraints and Reports • There maybe differences between the timing numbers reported in the compile log and the post-compile timing, QoR, and constraint reports  – Timing numbers reported in the log take the tool-derived infeasible path exceptions into account  – Post-compile reports do not account for infeasible path exceptions  – Use the new ignore_infeasible_paths  option with report_timing , report_qor , and report_constraints  to exclude infeasible paths from the reports –

I-2013.12-SP2

Infeasible Paths Support Timing Reports • The report_timing attributes command adds a new “inf ” attribute to the startpoint and endpoint of tool-detected infeasible paths –

 Attributes: d - dont_touch u - dont_use  mo - map_only so - size_only i - ideal_net or ideal_network inf - infeasible path

New attribute

Point Fanout Cap Trans Incr Path Attributes ------------------------------------------------------------------------------------clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 6.00 6.00 f in1 (in) 0.00 0.00 6.00 f inf in1 (net) 2 4.75 0.00 6.00 f u_in1/A_in (unit_0) 0.00 6.00 f startpoint & u_in1/A_in (net) 4.75 0.00 6.00 f endpoints u_in1/U7/INP (INVX0_LVT) 0.00 0.00 6.00 f marked as u_in1/U7/ZN (INVX0_LVT) 0.06 0.03 6.03 r infeasible u_in1/N0 (net) 1 2.12 0.00 6.03 r u_in1/A_out_reg/D (DFFX1_LVT) 0.06 0.00 6.03 r inf data arrival time 6.03

I-2013.12-SP2

Infeasible Paths Support Categorized Timing Reports • Use the new infeasible_paths option of create_qor_snapshot and query_qor_snapshot  to capture the paths and add an infeasible path column in the HTML-based report: –

create_qor_snapshot -name snap1 -max_paths 30 -infeasible_paths query_qor_snapshot -name snap1 -infeasible_paths -columns \ {path_group infeasible_paths startpoint endpoint wns zero_path}

I-2013.12-SP1

Support for report_timing -physical Reports Pin Locations and Capacitive Loads • The new  physical option of report_timing  reports pin locations and capacitive loads for pins and nets –

 – Consistent with IC Compiler  – Works in Design Compiler topographical and DC Explorer physical flows

I-2013.12-SP1

Support for Flat Query Commands get_flat_cell, get_flat_net, get_flat_pin • Design Compiler supports new flat versions of query commands, similar to IC Compiler:  – get_flat_cells  – get_flat_nets  – get_flat_pins

• The arguments for these commands are:  – [-quiet]  – [-regexp |-exact]  – [-nocase]  – [-filter expression]  – [patterns | -of_objects objects]  – [-all] The of_objects  option is supported in Design Compiler only –

Cross-Probing from RTL to Gates Overview • Works with Verilog, VHDL, and SystemVerilog RTL • Helps you analyze inferred cells from RTL source files  – Use to find and analyze the implementation and placement of timing-critical or congestion-critical portions of RTL source files

• Helps you find and analyze the placement of instantiated cells (clock gates for example) • Cross-probing from RTL to datapath resource reports can help you to better understand datapath extraction  – This analysis can help you to improve the datapath coding style for better extraction

Cross-Probing from RTL to Gates User Interface 1. Choose Open RTL Files on the AnalyzeRTL menu

2. The Open RTL Files dialog box appears

The current directory

The design RTL files mentioned in the run script

Cross-Probing from RTL to Gates User Interface 3. Open the RTL file to be cross-probed

The RTL file appears in the RTL browser

The lines that can be cross-probed are highlighted in green

Cross-Probing from RTL to Gates User Interface 4. Follow these steps to cross-probe from RTL to gates: Step 1: Select a line in the RTL file, and then right-click to open the pop-up menu

Step 2: Choose Select Objects of Selected Line(s)

Step 3: The Selection List dialog box appears showing the cells inferred from the selected line Note: Multiple line cross-probing is not supported

Cross-Probing from RTL to Gates Inferred Cells Selected in Schematic and Layout Views Step 1: Select a line in the RTL file, and then right-click to open the pop-up menu

Step 2: Choose Select Objects of Selected Line(s)

Step 3: The Inferred cells are selected and colored white in any schematic and layout views in which they appear

Cross-probing from RTL to gates opens only the Selection List dialog box

Cross-Probing from RTL to Gates RTL That Can Be Cross-Probed • Only RTL lines that have netlist correspondence can be cross-probed

Select Objects of Selected Line(s) is dimmed for lines that cannot be cross-probed

RTL Browser Enhancements First Column Grouping The first column shows the file names, line numbers, and cell names

The default view has the first RTL file name in expanded format

The second column shows the number of cells inferred by the line

RTL Browser Enhancements Multi-Source Cell Support •  A cell might be associated with two RTL files • The RTL browser displays the other RTL files associated with that cell A “ +” symbol in the cell name list indicates multiple sources for the corresponding cell

RTL Browser Enhancements Multi-Source Cell Support Click the “+” symbol to view the other source file names

This line shows the second RTL file associated with cell m2/O_reg

I-2013.12-SP1

RTL Cross-Probing for Datapath Generating a Datapath Extraction Report • Run analyze_datapath_extraction  from GUI menu  – Use either AnalyzeRTL > Analyze Datapath Extraction  – or Design > Analyze Datapath Extraction

• Cross-probe from datapath extraction report to RTL  – Clicking a file name in datapath extraction report opens a new RTL browser and highlights the corresponding line number

Click the RTL file Cross-probed line

I-2013.12-SP3

RTL Cross-Probing for Datapath Generating a Datapath Resource Report • To generate a design resources report from the RTL browser:  – Select a cell, right-click and choose Report Resources of Selected  – report_resources  runs for the design that contains this cell

I-2013.12-SP2

RTL Cross-Probing for Datapath Cross-Probing from RTL to Datapath Resources Report • Find the datapath report for the operators in the selected line in the RTL browser 3

2

The line number is displayed, click the Find button

Choose Search in Resource Report

4 1

Select a line and right-click

Observe cross-probed report

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

Correlation to Layout Zroute-Based Global Buffering Zroute-Based Congestion-Driven Placement Milkyway Schema V8.1 Update  Analyzing RTL Congestion Congestion Report Enhancements Faster Execution of start_icc_dp Command

Zroute-Based Global Buffering Improves Congestion in Narrow Channels

Design Compiler Graphical

• Congestion-aware global buffering reduces congestion along narrow channels across macros  – Based on Zroute estimation

• Use the new -global_route true  option of the set_ahfs_options  command to enable  – The default is false in Design Compiler

 – report_ahfs_options  will show status “Global Route: ON”

• Enable for macro-intensive designs with narrow channels  – Enable in both Design Compiler and IC Compiler for best results

• Might impact QoR and runtime  – Use only when needed to improve congestion in narrow channels

Congestion-Driven Placement Zroute-Based for Improved Correlation

Design Compiler Graphical

• Improves congestion estimation and correlation with IC Compiler on highly congested designs  – Zroute-based, consistent with IC Compiler  – Uses the same congestion thresholds as IC Compiler

• Set the new placer_enable_enhanced_router variable to true to enable  – The default is false in Design Compiler  – The default is true in IC Compiler

• Might impact QoR and runtime  – Use only when needed for highly congested designs

Milkyway Schema V8.1 Update Two Release Interoperability Model • Schema version has changed to v8.1 in J-2014.09 • Two release schema interoperability model:  – No schema change in I-2013.12 (default schema is v7)  – Schema change in J-2014.09 (default schema is v8.1)

• Full backward compatibility across previous releases  – Older schema versions can always be read by a newer release

 – Implicit conversion supported, explicit conversion recommended

• Forward compatibility for one release, then on by default:  – Design Compiler I-2013.12-SP4, SP5 supports Schema v8.1  – Design Compiler J-2014.09 generated Milkyway can be read by Design Compiler I-2013.12-SP4 and later, but not I-2013.12-SP3

 – Design Compiler J-2014.09 has schema v8.1 on by default

Milkyway Schema V8.1 Update Details • Why the change?  – Emerging node designs need more data types per layer and a routing layer index above 187

 –  All routes at 10nm and below need native coloring support

• Milkyway v8.1 Schema supports 2 layer modes  – Default mode: Milkyway database and technology file support up to 255 layers and 4096 data types per layer  – Extended mode: Milkyway database and technology file support up to 4095 layers and 4096 data types per layer  – Use the extend_mw_layers command to enable

• The change is transparent in default layer mode • See IC Compiler J-2014.09 update training for further details on Schema v8.1

I-2013.12-SP2

Analyzing RTL Congestion Pre-Synthesis Congestion Analysis

Design Compiler Graphical

• Predicts RTL congestion before synthesis  – Provides early feedback to influence RTL decisions for congestion  –  Allows you to try alternatives in RTL to alleviate congestion

• Provides a report to identify potential congestion sources in the RTL such as:  – Large MUX (MUX_OP)

 – Large selector (SELECT_OP)  – Large data switch network  – Large ROM  – Parallel high-fanout nets

• Identifies RTL source files and includes line numbers

I-2013.12-SP2

Analyzing RTL Congestion User Interface

Design Compiler Graphical

• New analyze_rtl_congestion  command does not require physical data • Required input  – Link libraries  – Target libraries (for any instantiated gates)  – RTL

•  Available in Design Compiler and DC Explorer • Still need post-synthesis report_congestion  to identify floorplan congestion

I-2013.12-SP2

Analyzing RTL Congestion Example

Design Compiler Graphical

dc_shell> analyze_rtl_congestion **************************************** Report : RTL congestion Design : my_design  Version: I-2013.12-SP2 Date : Thu Feb 27 03:54:00 2014 **************************************** ######################################## Large MUX details ######################################## -----------------------------------------------------------------------Structure Cell name Size (width) Line No RTL File ----------------------------------------------------------------------- MUX_OP C10567 16 x 1 (163) 83 /u/9000560869.v  MUX_OP C10566 16 x 1 (163) 82 /u/9000560869.v ...

I-2013.12-SP1

report_congestion Now Reports Cells in Congested Regions

Design Compiler Graphical

• New option for report_congestion  provides a text-based report of cells in congested regions:

-list_cells_over_grc_violation grc_violation_threshold  – The grc_violation_threshold   is an integer value  – Cells are listed if they have a Max number at or above the threshold

• Cells are presorted to list designs with the most congested cells first • Does not require interactive GUI session •  Also works in DC Explorer • Cross-probing to RTL source not supported

I-2013.12-SP1

report_congestion Report Example

Design Compiler Graphical

dc_shell-topo> report_congestion -list_cells_over_grc_violation 30 **************************************** Report : congestion Design : my_design  Version: I-2013.12-SP1 Date : Wed Apr 23 15:37:28 2014 **************************************** Both Dirs: Overflow = 590305 Max = 33 (1 GRCs) GRCs = 85938 (67.13%) H routing: Overflow = 275009 Max = 29 (1 GRCs) GRCs = 43141 (33.70%)  V routing: Overflow = 315296 Max = 33 (1 GRCs) GRCs = 42797 (33.43%) Cells in Congested Regions: Design Cell Reference Congestion -------------------------------------------------------------------------- my_subdesign U2359 MYLIB_AO22X1 33  my_subdesign U7117 MYLIB_AOI22X1 31  my_subdesign U12115 MYLIB_INVX4 32  my_subdesign U12002 MYLIB_BUFFX8 30

I-2013.12-SP2

Floorplan Exploration Faster Execution of start_icc_dp command

Design Compiler Graphical

• The start_icc_dp  command now executes faster with a new default location for storing temporary files  – Previous releases stored in current working directory  – New default stores at $TMPDIR/ dcg_unique_string  – The $TMPDIR   is the TMPDIR UNIX environment variable  – If TMPDIR UNIX environment variable is not defined, Design Compiler Graphical stores the files in the /tmp directory

• You can override the default behavior by using the -work_dir  option with the set_icc_dp_options command

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

Improved Test Support Physical Scan Cell Repartitioning During Incremental Compile New SCANDEF Flow

Physical Scan Cell Repartitioning During Incremental Compile

Design Compiler Graphical

• Starting with J-2014.09:  – Design Compiler now also supports physical scan cell repartitioning in the binary flow for both DFTMAX compressed and standard scan designs

• Provides improved results and QoR after incremental compile in terms of cell count, congestion, and timing • Requires:  – DFT Compiler license for standard scan designs  – DFTMAX license for compressed scan designs  – Design Compiler Graphical license

Physical Scan Cell Repartitioning During Incremental Compile: User Interface

Design Compiler Graphical

• Starting with J-2014.09, you must specify the -scan and -spg options in the incremental compile command to perform reordering: compile_ultra

incremental

–

scan -spg

–

• Physical scan cell repartitioning is disabled by default • Use the set_optimize_dft_options  command to enable and configure repartitioning set_optimize_dft_options [-repartitioning_method none | single_directional | multi_directional | adaptive ] ;# default is none [-single_dir_option vertical | horizontal ] ;# default is horizontal

Physical Scan Cell Repartitioning During Incremental Compile: Behavior

Design Compiler Graphical

• Behavior of physical optimization features under different conditions Reordering

Repartitioning

ON

OFF

set_optimize_dft_options repartitioning_method single_directional | multi_directional | adaptive

ON

ON

set test_enable_scan_reordering_in_compile_ incremental false (default: true)

OFF

OFF

Conditions

Default

–

Physical Scan Cell Repartitioning During Incremental Compile: Example 1

Design Compiler Graphical

• Running in a single session: # Perform initial compile with compile_ultra scan -spg

spg option

–

–

# Insert DFT insert_dft # Perform incremental compile with re-ordering and multi-directional # re-partitioning set_optimize_dft_options repartitioning_method multi_directional compile_ultra incremental scan -spg –

–

–

Physical Scan Cell Repartitioning During Incremental Compile: Example 2

Design Compiler Graphical

• Running in multiple sessions: ### Session 1 ### # Perform initial compile with compile_ultra scan -spg

spg option

–

–

# Insert DFT insert_dft # Write the design  write_file format ddc –

hierarchy

–

output ./design.ddc

–

### Session 2 ### # Read the design read_ddc ./design.ddc …

# Perform incremental compile with re-ordering and multi-directional # re-partitioning set_optimize_dft_options repartitioning_method multi_directional compile_ultra incremental scan -spg –

–

–

New SCANDEF Flow Overview • Starting in J-2014.09:  – Design Compiler uses a new SCANDEF writer  – New SCANDEF writer is enabled by default in J-2014.09

• Benefits:  – Solution is more solid and robust

• Requires:  – DFT Compiler license (no change from previous release)

• Limitations:  – Hierarchical SCANDEF still uses the old SCANDEF writer

New SCANDEF Flow Supported Features • The following DFT features are supported:  – Standard scan and compressed scan  – Multiple test-mode scan  – Internal pins flow  – Memories with test models  – Multivoltage

 – PLL flows  – Core wrapping  – Shift registers  – Multibit registers

New SCANDEF Flow Single Session Example # Perform initial compile compile_ultra scan –

# Perform Insert DFT insert_dft # Write SCANDEF before writing .ddc file  write_scan_def output before_inc.def # Always check the SCANDEF file check_scan_def # Write the design  write_file format ddc hierarchy output ./before_inc.ddc –

–

–

–

# Perform incremental compile compile_ultra incremental scan –

–

# Write SCANDEF before writing .ddc file  write_scan_def output after_inc.def # Always check the SCANDEF file check_scan_def # Write the design  write_file format ddc hierarchy output ./after_inc.ddc –

–

–

–

New SCANDEF Flow Multiple Session Example ### Session 1 ### # Perform initial compile compile_ultra scan # Perform Insert DFT insert_dft # Write SCANDEF before writing .ddc file  write_scan_def output before_inc.def # Always check the SCANDEF file check_scan_def # Write the design  write_file format ddc hierarchy output ./before_inc.ddc –

–

–

–

–

### Session 2 ### # Read the design read_ddc ./before_inc.ddc # Perform incremental compile compile_ultra incremental scan # Write SCANDEF before writing .ddc file  write_scan_def output after_inc.def # Always check the SCANDEF file check_scan_def # Write the design  write_file format ddc hierarchy output ./after_inc.ddc –

–

–

–

–

–

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

Improved Timing Support Launch Clock Behavior of Transparent Latches Support for –rise_exclude and –fall_exclude options

I-2013.12-SP4

Launch Clock Behavior Of Transparent Latches • The behavior of the variable

timing_early_launch_at_borrowing_latches has been changed for consistency with PrimeTime • This variable became public in the Design Compiler I-2013.12-SP4 release • This variable is true by default and removes clock latency pessimism for paths that begin at the data pin of a transparent latch

I-2013.12-SP4

Launch Clock Behavior Of Transparent Latches: Time Borrowing Example F1 D

L1 Q

CP

Big delay

D

Q GN

CLK

F1-L1 path borrowed timing from L1-F2 Borrowing path launched from L1/D : Blue Arrow

F2 D

Q

CP

I-2013.12-SP4

Launch Clock Behavior Of Transparent Latches: Solution • The F1-L1 path needs to time borrow

F1

Big D Q delay

• The setup time for L1/GN uses the early launch clock edge

CP CLK

• The L1-F2 path needs to use the early launch clock edge to calculate timing correctly if time borrowing has occurred

CLK

*Green edge : early launch

F1-L1

*Red edge : late launch *TB : amount of time borrow

L1-F2

TB

L1

F2

D Q

D Q

GN

CP

I-2013.12-SP4

Launch Clock Behavior Of Transparent Latches: Usage Recommendation timing_early_launch_ at_borrowing_latches

CRPR

Behavior

Note

True

False

Use early skew launch

False

False

Use late skew launch (pessimistic pessimistic))

NOT recommended

True

True

Use early skew launch CRPR applied (can be optimistic optimistic))

Check for nonzero CRPR value

False

True

Use late skew launch CRPR applied

Note: CRPR = Clock Reconvergence Pessimism Removal

I-2013.12-SP4

 –rise_exclude  –rise_exclude and – and –fall_exclude fall_exclude New Options for report_timing and get_timing_paths • The new exclude option for the report_timing  and get_timing_paths  commands was added in Design Compiler I-2013.12 –

 – Prevents reporting of all data paths from, through, or to the named pins, ports, nets, and cell instances

• The new rise_exclude  and fall_exclude  options are added in Design Compiler I-2013.12-SP4 –

–

 – These options behave the same as -exclude, but only apply to rising or falling paths at the named pins, ports, nets, and cell instances

• These options do not apply to clock pins, clock paths, or time borrowing latch paths

I-2013.12-SP4

 –rise_exclude  –rise_exclude and – and –fall_exclude fall_exclude Usage Example report_timing -from ff3/CK -to latch3/D -rise_exclude inv6/Z

report_timing -from ff3/CK -to latch3/D -fall_exclude inv6/Z

J-2014.09 RTL Synthesis Optimization Improved Usability Correlation to Layout Improved Test Support Improved Timing Support DC Explorer

DC Explorer  AnalyzeRTL Multicycle Path Histogram Support for UPF Flow in DC Explorer

I-2013.12-SP3

AnalyzeRTL Multicycle Path Histogram In DC Explorer

Multicycle Paths

• Starting in I-2013.12-SP3, you can create separate path slack and logic-level histograms for multicycle paths •  A new Clock Cycles column in the data table shows the number of clock cycles for a timing path

I-2013.12-SP2

UPF Flow in DC Explorer Create Design Data and Explore Results • UPF in DC Explorer is different than UPF in Design Compiler

UPF Support UPF (incomplete)

RTL (incomplete)

• DC Explorer:  – Works with minimal UPF  –  Automates insertion of power management cells  –  Allows exploration of power plan

DC Explorer High quality design data, including UPF

 – Outputs a complete RTL UPF for Design Compiler

Explore the impact of low power intent

I-2013.12-SP2

UPF Flow in DC Explorer  Automated Approach to Handle UPF • Inputs  – Minimal UPF input needed to start the exploration  – Power domain definitions  – Power state table (PSTs)

 – RTL: Pre-instantiated power management cells will be treated as standard cells

• Outputs  – Gate-level netlist with power management cells  – Full UPF with power management cell strategies

 – Early floorplanning for Design Compiler topographical and IC Compiler implementation

I-2013.12-SP2

UPF Flow in DC Explorer  Automated Approach to Handle UPF • Isolation insertion: on all outputs of shutdown domains  – Example: Output ports of PD1 and PD2

• Level-shifter insertion: on power domain boundaries with a voltage difference in any state  – Example: Between PD1 and PD2 (voltage difference in S1, S3)  – Example: Between PD1 and PD3 (voltage difference in S1)

•  Always-on buffers: on all feedthrough paths that cross domain boundaries  – Example: on a net from PD1 to PD3 that goes through PD2

• No support for retention registers yet

Power State Table (PST) PD1

PD2

PD3

S1

1.2V

0.8V

0.8V

S2

off

off

0.8V

S3

1.2V

0.8V

1.2V

I-2013.12-SP2

UPF Flow in DC Explorer Power Exploration Summary Report Power domain

# Instances

Area

Leakage

PD1

32465

942.3

1100

PD2

5678

59.5

370

…… * Generated by report_mv_qor

• Top-level table with basic information • HTML links to get detailed information on a specific power domain • Overhead from power management cells – level shifters and isolation cells

Power-domain centric view of area and leakage

I-2013.12-SP2

UPF Flow in DC Explorer Power Exploration Detailed Report Domain: PD2

# Instances

Area

Leakage

Level shifters

70

4.5

45

Isolation cells

60

7.0

25

Always-on cells

50

3.5

20

PM cells total

180

15.0

90

Macros

0

0

0

I/O Pads

0

0

0

Standard cells

5488

15.0

280

Total

5678

59.5

370

* Generated by report_mv_qor

Power domain details provide area and leakage requirements to meet multivoltage design goals

Thank You

APPENDIX Command and Variable Changes

New, Changed, and Removed Commands and Variables in J-2014.09 Compared to I-2013.12

LEGEND Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

New Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

analyze_library analyze_rtl_congestion check_upf get_defined_commands get_shift_register_chains gui_create_task_item gui_create_tk_palette_type gui_report_task remove_scan_skew_group report_ieee_1500_configuration report_scaling_lib_group report_scan_skew_group reset_ieee_1500_configuration set_ieee_1500_configuration set_scan_skew_group set_upf_query_options

Removed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

change_macro_view change_selection_no_core change_selection_too_many_objects compare_interface_timing create_ilm get_ilm_objects get_ilms  print_proc_new_vars report_ilm set_clock_skew set_delay_calculation  write_interface_timing

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

all_registers: Removed -inverted_output option analyze_dw_power:  Added -sort_ascending option Removed -sort_asending option change_names:  Added -skip_inactive_constraints option create_command_group:  Added -info option create_net_shape: Removed -quiet option create_qor_snapshot:  Added -nosplit option create_qtm_delay_arc:  Added -max_insertion_delay option  Added -min_insertion_delay option create_qtm_drive_type: Removed -lib_cell_input_transition option create_route_guide: Removed -switch_preferred_direction option create_user_shape: Removed -quiet option

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

create_via: Removed -no_snap option define_dft_partition:  Added -extest_cells option define_name_maps:  Added -design_name option Removed -design option define_test_mode:  Added -target option  Added -transparent_mode_of option Removed -inherit option find_objects:  Added -exact option  Added model argument to object_type option get_cells:  Added -at option  Added -intersect option  Added -touching option  Added -within option get_timing_paths:  Added -fall_exclude option  Added -rise_exclude option –

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

get_tracks: Removed -nocase option Removed -regexp option gui_set_current_task:  Added -task option Removed -name option read_file: Removed -ilm option read_lib:  Added -imported_jcr option remove_core_area: Removed -verbose option remove_die_area:  Added -verbose option remove_placement_blockage:  Added -verbose option remove_route_guide:  Added -verbose option remove_target_library_subset: Removed -clock_path option remove_terminal:  Added -verbose option

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

report_annotated_delay:  Added -min option report_clock_gating:  Added -enable_conditions option report_congestion:  Added -list_cells_over_grc_violation option report_constraint:  Added -ignore_infeasible_paths option  Added -min_period option report_datapath_gating:  Added -gated option report_lib:  Added -jcr option report_power_domain:  Added -hierarchy option  Added object_list2 argument report_qor:  Added -ignore_infeasible_paths option report_resources:  Added design_list argument

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

report_timing:  Added -fall_exclude option  Added -ignore_infeasible_paths option  Added -rise_exclude option save_qtm_model:  Added -format option set_ahfs_options:  Added -global_route option set_always_on_strategy: Removed -bias_type option set_annotated_delay:  Added -dont_touch option set_check_library_options:  Added -char_integrity option  Added -significant_digits option set_dft_configuration:  Added -ieee_1500 option Removed -lbist option Removed -logicbist option set_fix_multiple_port_nets:  Added -exclude_clock_network option  Added -no_rewire option

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

set_route_zrt_common_options:  Added -extra_via_off_grid_cost_multiplier_by_layer_ name option  Added -ignore_var_spacing_to_blockage option  Added -ignore_var_spacing_to_pg option  Added -ignore_var_spacing_to_shield option  Added -min_edge_offset_for_macro_pin_connection_by_ layer_name option  Added -separate_tie_off_from_secondary_pg option  Added -via_on_grid_by_layer_name option  Added -wire_on_grid_by_layer_name option set_scan_compression_configuration:  Added -shared_codec_controls option set_scan_path:  Added -init_data option  Added -opcode option set_scan_replacement: Removed -aux_clock_lssd option set_streaming_compression_configuration:  Added -exclude_clocks option set_target_library_subset: Removed -clock_path option

Changed Commands in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

set_test_point_configuration: Removed -exclude_elements option  write_test_protocol:  Added -disable_codecs option

New Variables in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler

compile_seqmap_honor_sync_set_reset (Default is false) disable_multicore_resource_checks (Default is false) dont_bind_unused_pins_to_logic_constant (Default is false) hdlin_report_sequential_pruning (Default is false) link_portname_allow_period_to_match_underscore (Default is false)  mv_make_primary_supply_available_for_always_on (Default is true)

DesignWare minPower  placer_channel_detect_mode (Default is false) Tcl built-in

 placer_enable_enhanced_router (Default is false) route_guide_naming_style (Default is %s_%d  ) sh_help_shows_group_overview (Default is true) test_dedicated_clock_chain_clock (Default is false) test_fast_feedthrough_analysis (Default is false) test_sync_occ_1x_period (Default is 20)

New Variables in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

timing_consider_internal_startpoints (Default is true) timing_dont_traverse_pg_net (Default is true) timing_early_launch_at_borrowing_latches (Default is true) timing_enable_slack_distribution (Default is false) timing_use_ceff_for_drc (Default is false) upf_allow_refer_before_define (Default is false) upf_block_partition (Default is "") upf_iso_filter_elements_with_applies_to (Default is ENABLE) upf_isols_allow_instances_in_elements (Default is true) upf_suppress_etm_model_checking (Default is false)

Changed Variables in J-2014.09 Compared to I-2013.12 Design Compiler Power Compiler Timing related DFT Compiler DesignWare minPower Tcl built-in

compile_seqmap_identify_shift_registers_with_synchronous_  logic: Default changed to false from true hdlin_preserve_sequential: Default changed to none from false hdlin_while_loop_iterations: Default changed to 4096 from 1024