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REFERENCES [1] A. Chowdhary, Chowdhary, K. Rajagopal, Rajagopal, S. Venkatesan, enkatesan, T. Cao, V. Tiourin, Tiourin, Y. Parasuram, and B. Halpin, “How accurately can we model timing in a placement engine?,” in Proc. IEEE Des. Autom. Conf., 2005, pp. 801–806. [2] C. Schmidt and I. E. Grossmanm, Grossmanm, “The exact overall overall time distribution distribution of uncertain task durations,” Eur. J. Oper. Res. , vol. 126, no. 3, pp. 614–636, 614–636, 2000. [3] >D. Patil, Patil, S. Yun, S. Kim, A. Cheung, M. Horowitz, Horowitz, and S. Boyd, “A new method for robust digital circuits,” in Proc. Int. Symp. Quality  Electron. Des., 2005, pp. 676–681. [4] G. N. Rafail and K. Yenilmez, Yenilmez, “Fuzzy “Fuzzy linear programming programming problems with fuzzy membership functions,” Math. Subject Classification, pp. 375–396, 375–396, 2000. [5] J. J. Buckley, Buckley, “Stochastic “Stochastic versus versus possibilis possibilistic tic programming, programming,”” Fuzzy Sets Syst., vol. 34, no. 2, pp. 173–177, 1990. [6] J. Singh, V. Nookala, Z. Luo, and S. Sapatnekar, Sapatnekar, “Robust gate sizing sizing by geometric programming,” in Proc. IEEE Des. Autom. Conf. , 2005, pp. 315–320. [7] K. Agarwal, Agarwal, D. Sylvester Sylvester,, F. Liu, S. Nassif, and S. Vrudhula, Vrudhula, “Delay metrics for interconnect timing analysis,” in Proc. IEEE Des. Autom. Conf., 2004, pp. 381–384. [8] M. Hrkic, J. Lillis, Lillis, and G. Beraudo, Beraudo, “An approach to placement coupled logic replication,” in Proc. IEEE Des. Autom. Conf. , 2004, pp. 711–716. [9] M. Mani and M. Orshansky, “A new statistical optimization optimization algorithm for gate sizing,” in Proc. Int. Conf. Comput. Des., 2004, pp. 272–277. [10] >R. E. Bellman and L. A. Zadeh, “Decision “Decision making making in fuzzy environment,” Manag. Sci., vol. 17, no. 4, pp. 141–164, 1970. [11] R. H. Byrd, J. Nocedal, Nocedal, and R. A. Waltz, “KNITRO “KNITRO:: An integrated integrated package for nonlinear optimization,” Large-Scale Nonlinear Opt., pp. 35–59, 2006 [Online]. Available: http://www-neos.mcs.anl.gov/neos/  solvers/nco:KNITRO/AMPL.html [12] S. Devadas, Devadas, H. F. Jyu, K. Keutzer, Keutzer, and S. Malik, “Statisti “Statistical cal timing Proc. Int. Conf. Comput. Des., analysis of combinational circuits,” in Proc. 1992, pp. 38–43. [13] S. Srinivasa Srinivasan n and V. Narayanan, Narayanan, “Variation “Variation aware placement for FPGAs,” FPGAs,” in Proc. ISVLSI , 2006, pp. 1–2. [14] T. Luo, D. Newmark, and D. Z. Pan, “A new LP based incremental incremental timing driven placement for high performance designs,” in Proc. IEEE   Des. Autom. Conf., 2006, pp. 1115–1120. [15] V. Mahalingam and N. Ranganathan, Ranganathan, “Variati “Variation on aware timing based Proc.Int. Symp. Symp. Qualit Qualityy ElecElecplacement placement using fuzzy programming, programming,”” in Proc.Int. tron. Des., 2007, pp. 327–332. [16] V. Mahalingam, Mahalingam, N. Ranganathan, Ranganathan, and J. E. Harlow, Harlow, “Fuzzy optimizaoptimization approach for gate sizing in the presence of process variations,”  IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 8, pp. 975–984, 975–984, Aug. 2008.

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Identification of Delay Measurable PDFs Using Linear Dependency Relationships Edward Flanigan and Spyros Tragoudas

 Abstract—Recently several methods have been presented to measure the dela delay y ofa smal smalll set set ofpathdelayfau ofpathdelayfault ltss (PDF (PDFs) s),, know known n asa basi basiss set set whic which h is used to compute the delays of PDFs. All methods assume that the basis consists of strong robustly tested PDFs because their delays can be measured. This paper presents procedures to identify measurable PDFs whose delays otherwise could not be measured by traditional strong robust sensitization. Path measurem measurement ent techniques techniques that conditer conditer the bounded bounded delaymodel allow allow us to compute the delays of almost all PDFs in existing benchmarks.  Index Terms—Bounded delay, path delay faults (PDF), strong robust.

I. INTRODUCTION Modern day IC design has drawn a lot of attention towards the path delay fault (PDF) model [15], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [12]. The work presented in [3] and [13] show how to determine an upper bound on circuit delay using a small set of basis paths, however the approach is limited by the number of paths that can be measured. The basis path set is the smallest set such that every PDF can be represented as a linear combination of that set and has been shown to be linear with respect to the size of the circuit [13]. The testable basis set consists only of the testable PDFs within a basis set whose delays are measurable. The work in [13] insists on using strong robustly testable PDFs to create the basis set. The circuit timing characteristics are determined by using a basis set of strong robustly testable PDFs to calculate the delay of all PDFs which are linearly dependent on that strong robustly testable basis set. It is desirable to find the largest possible testable basis set to maximize the number of PDFs whose delays can be calculated thus eliminating the need to test those PDFs on the automatic test equipment (ATE). Strong robustly testable PDFs [2], [4] guarantee that the delay measurement for the path taken on the ATE is the delay of the on input transition of the path for which test generation was performed. Unlike strong robustly testable PDFs, delays measured for robust and non-robustly testable PDFs [11], [16] could unintentionally be the delay of an off input transition because of masking. A precise delay measurement is obtained by using a binary search with the clock frequency [13]. The number of strong robustly testable PDFs is usually limited in size due to the stringent path sensitization criteria. Hence there still remains a significant percentage of PDFs whose timing characteristics cannot be determined because they are not linearly dependent on the small strong robustly testable basis set.

Manusc Manuscrip riptt receiv received ed June June 25, 2008; 2008; revis revised ed Octobe Octoberr 24, 2008and Januar January y 27, 2009. First published July 21, 2009; current version published May 26, 2010. This work has been supported by a grant from Intel Corp. Portions of this paper appear in “Enhanced Identification of Strong Robustly Testable Paths,” ISQED ’07: Proceedings of the 8th International Symposium on Quality Electronic Design, pp. 729-736, 2007. The authors authors are with the Departmen Departmentt of Electr Electrica icall and Compute Computerr EngiEngineering, neering, Southern Southern Illinois Illinois Universit University, y, Carbondale, IL 62901 USA (e-mail: (e-mail: fl[email protected]; [email protected]). Digital Object Identifier 10.1109/TVLSI.2009.2017541 U.S. Government Government work not protected by U.S. copyright.

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This work identifies additional PDFs whose delays can be measured. Such PDFs are referred to as delay measurable PDFs (DM-PDFs) [4]. Unlike strong robustly testable paths, the sensitization criteria for a DM-PDF allows transitions along the off inputs of the path. However, the off input transitions are restricted to transitions that guarantee the on-input transition delay propagates to the output of a gate. It is shown that the measurable delay of off input transitions as well as the bounded delay model allow for the delay measurement of the path under test (on input transition). In this work the bounded delay model is used to overcome deficiencies of the path delay fault model. Bounded gate delays [5], [10] are used to address process variation by specifying minimum and maximum delay values for gates, wires, and interconnects. All combinations of delay and process variation are modeled within the minimum and maximum range of the bounded delay model. Under this model it is assumed that any delay which appears outside of the bounded delay range are considered gross delay defects and will be identified by transition delay fault testing. It is shown that the proposed work allows basis sets to extend beyond the limitations of the traditional strong robustly testable basis set while maintaining the same level of accuracy when determining circuit timing characteristics. Results show that the presented work produces a significant increase in the number of identifiable DM-PDFs. Improvements such as maximizing the size of the testable basis set allows one hundred percent coverage of all circuit paths. Techniques presented in this paper often produce 100% coverage of all paths and always result in high coverage of critical paths which was not obtainable using previous techniques [13]. This paper is organized as follows. Sections II and III present a pathbased procedure that identifies DM-PDFs by considering the bounded delay model. Experimental results in Section IV demonstrate that the useof DM-PDFs increasesthe numberof critical paths forwhich circuit timing characterization can be determined. Section V concludes this paper.

II. MEASURABLE PATH IDENTIFICATION All transitions at a gate must be of the same type either rising or falling, and the transition that appears at the output of a gate must be the on-input transition for DM-PDF. Under the bounded delay model there are two conditions which allow for off-input sensitization of a DM-PDFs at a gate. Condition 1 (Robust DM-PDF Sensitization) : All transitions at a gate are to non-controlling value (NCV). The maximum delay of each off-input is less than the on input transitioning to noncontrolling value. Condition 2 (Functional DM-PDF Sensitization): All transitions at a gate are to controlling value (CV). The minimum delay of each off-input is less that the on input transitioning to controlling value. Fig. 1 shows the s27 circuit from the ISCAS’89 benchmark collection. Assume the bounded delay of each gate in the circuit is in the range of 1 and 2 units. This bounded delay value is denoted as (1, 2). Consider path {1, 8, 17}, which can be tested strong robustly. Its measured delay should be within the range (2, 4). The latter is calculated by adding the bounded delays on its gates. If the measured delay is greater than 4 or less than 2, a delay defect exists along path {1, 8, 17}. Fig. 1 shows a PDF {1, 8, 10, 13, 15, 16, 17} that cannot be tested strong robustly but is a DM-PDF. Applying the test pattern as shown in Fig. 1, a delay measurement at primary output 17 could reflect the delay of the falling off-input transition occurring on node 8 or the falling on-input transition occurring on node 16. This is explained in the following.

Fig. 1. Delay measurable PDF.

Fig. 1 shows the sensitization and bounded delay values for paths {1, 8, 17} and {1, 8, 10, 13, 15, 16, 17}. The inputs of the NOR gate driving output 17 has bounded delay values of (1, 2) (line 8), and (5, 10) (line 16). Transitions on nodes 8 and 16 are from controlling value to non-controlling value, therefore the later of the two transitions will be measured at output 17. The delay of path {1, 8, 17} has already been verified by applying a strong robust test for that path. Therefore the latest transition is (6, 12) because of path {1, 8, 10, 13, 15, 16, 17} has a bounded delay of (6, 12). Thus the measured delay reflects the delay along path {1, 8, 10, 13, 15, 16, 17}.

 A. Off Input Path Selection

Before generating tests for DM-PDFs, the existing set of DM-PDFs is considered because they can potentially sensitize a sub path leading into an off input of a target DM-PDF. The set of known delay measurable PDFs is denoted as . The set initially is the set of strong robustly testable PDFs. A DM-PDF restricts all off inputs to either a stable non-controlling value or a transition that is sensitized using one of the PDFs from the pre-existing measurable set . Target paths are a set of user defined paths that are candidates to be identified as DM-PDFs. The target paths selected for test generation will be determined by what the DM-PDFs will be used for. In the case of forming a testable basis [3], linearly independent paths should be selected. The test generation procedure begins by assuming all off inputs of  the target DM-PDF take stable non-controlling values. To guarantee the delay of the on input transition is measured at the primary output, the delay of the target PDF is calculated using the bounded delay model. Any measurable PDF within the set that violates Condition 1 or Condition 2 is removed from consideration for sensitizing an off input transition. What remains is the set of PDFs which can be sensitized with delay measurable criteria up to an off input of the target path without affecting the delay measurement of the target path. From the remaining set of PDFs in we determine the appropriate set of PDFs which will be taken into consideration for validating eachindividual off-input along the target path. Eachindividual off input will have a set of paths that can sensitize the DM-PDF; those paths are stored in an off input set . The set of delay measurable PDFs from that meet the timing constraints mentioned in Condition 1 or Condition 2 are added to the off-input measurable transition set only if the path has the same identical sub-path as the target path. The sub-path starts from the output of the off-input gate and ends at the primary output. The identification of the paths which coincide with the on-input sub-path can be done efficiently using zero suppressed binary decision diagrams (ZBDDs) [7], [8].

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Any off input transition occurring along an off input of a DM-PDF must obey the conditions stated in Definition 1. is  Definition 1: For a single off input of the target path, the set of all paths which are contained in and obey the following selection criteria. 1) The measured delay of the candidate path taken from must obey either Condition 1 or Condition 2. 2) The delay measurable sensitization of the off input path must be maintained up to the point where the off input and the target path converge. 3) The sub-path must follow the same identical sub-path as the target path beginning with the output of the gate for which the off-input and on-input converge. Theorem 1: Any DM-PDF has a measurable delay if all off-inputs along that DM-PDF are sensitized by any path in the respective set as defined in Definition 1, or a stable non-controlling value. The proof of Theorem 1 is presented below with an induction argument on the number of gates along the DM-PDF. The base case for induction shows the PDF delay is measurable through the first gate of  the DM-PDF. Proof: Any off-input which has a stable non-controlling value does not affect the propagating on-input transition. Considering a single two-input gate along a DM-PDF, the delay measured at the primary output is determined by either the transition occurring on the on-input or the transition occurring on the off-input. Therefore under robust (functional) sensitization the measured output response is the one which has the latest (fastest) transition among all transitioning inputs of the gate along the DM-PDF. The delay of all paths are measurable because they are also elements of  and have known delay values that obey the bounded delay model; if they do not obey the bounded delay model a defect is present in the circuit. To be elements of  the paths must obey Condition 1 or Condition 2. The on-input transition is always measurable at the output of a gate because bounded delay values are satisfied for all off-input transitions, and all off-input transitions occur before (after) the on-input transition under robust (functional) sensitization. If a delay is measured and is not within the bounded delay of the on-input path a defect exists. The argument above holds for any number of off-inputs because all paths transitioning through those off inputs must be elements of  , and have measurable delays that obey the bounded delay values. The same argument applies for any number of gates because at each gate, all off-inputs are restricted in a way such that the on-input transition propagates as the measurable delay value. To illustrate the procedure in Theorem 1, consider the previous example described by Fig. 1. Definition 1 states that {1, 8, 17} can be used to generate an off-input transition for PDF {1, 8, 10, 13, 15, 16, 17}. Theorem 1 classifies {1, 8, 10,13, 15, 16, 17} as a DM-PDF under the sensitization conditions described for Fig. 1. The falling off-input transition on node 8 has a maximum delay of 2 which is less than the minimum on-input transition delay of line 16, which has a minimum delay of 5. The delay measured at the primary output is the delay of  path {1, 8, 10, 13, 15, 16, 17} which is (6, 12).   B. Test Generation

Once the off-input sensitization path sets are determined, function-based automatic test pattern generation [1], [2], [9], [14] is used to determine a delay measurable test for the target PDF. During the test generation phase all off inputs along the target path are restricted to either a stable non-controlling value [1], [2] or an off input transition which is sensitized using one of the paths from the existing measurable path set contained in . A delay measurabletest for a PDF isthe con junction of the set of off-input functions that either hold the off-input at

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a stable non-controlling value or produce a transition that obeys Definition 1. Procedures to derive off-input stability functions have been presented in [2], [13]. When forming a test function for a delay measurable off-input transition, it is important that the off-input sub-path taken from (starting at a primary input and ending at the off input of the target path) is sensitized using the same measurable sensitization criteria for which the delay measurement for that paths was taken. Any path within can be sensitized in this manner because all of the paths in obey the selection criteria as stated in Definition 1. Enforcing the off input sensitization criteria, the test function for a particular off input is the disjunction of all delay measurable tests sensitizing the sub-paths of  along with the stable non-controlling value for that respective off input. The measurable sensitization of the off input must be maintained only up to the point where the off input and the targeted path converge. III. ADVANCED MEASUREMENT PROCEDURES This section presents an extension for identifying DM-PDFs that were not identified in Section II. In Section II the sub paths within were sensitized with stable non-controlling values up to the off-input of the target path. The validation sensitization conditions will now be extended to allow delay measurable PDF sensitization of the sub-paths within by applying the arguments in Section II to the off-input sub-paths. In other words, the technique will sensitize the off-input sub-paths using other DM-PDFs as long as the propagating transition reaching the off-input obeys the off-input sensitization requirements described in Theorem 1. Also the number of DM-PDFs can be increased by using newly identified DM-PDFs to sensitize off-input transition for other target paths. These techniques effectively increase the size of set , which in turn improves the chances for DM-PDF sensitization of the on-input transition. Any off-input sub-path which leads into an off-input of a target path can also be delay measured sensitized based on Theorem 1. Assume PDF is an element of  and has the longest (shortest) delay of all paths in . The sub-path of  is treated as an artificial on-input path starting the sub-path at a primary input and ending at the off-input of the target path. A test function must sensitizes the sub-path as a DM-PDF to ensure the off-inputof the target path hasa measurable (known) delay that sensitizes the target path as stated in Theorem 1. Based on Definition 1 all paths within can be used to sensitize the off-input transitions along the artificial on-input sub-path . Subpath starts at a primary input and ends at the off-input of the target path. Performing this type of sub-path sensitization increases the possibilities for generating a DM-PDF because for a given off input, any combination of one or more PDFs from (DM-PDFs through that off input path set ) can be used to produce a measurable off-input transition for the target path. Off-input sub-path sensitization gives the test pattern generator greater flexibility for findinga test for a DM-PDF. A second extension to the method allows for an increase in the size of the set by reusing DM-PDFs. This is accomplished by adding any DM-PDF to the set and then placing those paths into any eligible off input set. Adding DM-PDFs to allows us to use the newly added paths to help sensitize other paths. Test generation can be performed again on any PDF which has a new DM-PDF added to any of its off-input sets . The major limitation ingenerating a testfor a DM-PDF isthe number of off-inputs that require a stable non-controlling value and the cardinality of  at eachoff-input. The cardinality of  can be drastically increased by adding any PDF that is linearly dependent on . These linearly dependent paths can be safely added because the delay value can be calculated using linear dependency relationships [3], [13]. The impressive results shown in Section IV are a result of increasing the

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TABLE I BASIS SIZES BY DIFFERENT METHODS

TABLE II TESTABLE BASIS COVERAGE OF CRITICAL PATHS

cardinality of  by adding the paths which are linearly dependent on . The advanced DM-PDF identification procedures increase in the number of DM-PDFs significantly. The large number of DM-PDFs allows very large testable basis sets, which results in a large percentage of critical paths whose circuit timing characteristics can be determined by using linear dependency relationships. IV. EXPERIMENTAL RESULTS Experimental results were performed on the ISCAS’85 and ISCAS’89 benchmarks, and are summarized in Tables I–III. The first column in each of these tables indicates the name of each benchmark. A function-based test pattern generator [9] is used to determine testable paths and the techniques from [3] are used to identify linear dependency relationships for critical paths. Critical paths are identified by using the techniques in [9] and considering all paths within ten percent of the longest path as critical. Bounded delay values are determined by applying the TSMC 0.18- m technology with 1.8 Volt Stage-XTM Standard Cell Library Data Book [6].

TABLE III NUMBER OF IDENTIFIED DM-PDFS

An auxiliary basis set [3]1 is a basis set that has reached the maximum possible cardinality and this size will be used as a reference for comparing cardinality of testable basis sets. The maximum possible size of the basis set is the size of the auxiliary set [3] which is listed in column 2 of Table I. Column 3 of Table I shows the size of the testable basis considering only strong robustly testable PDFs. The size of  consisting of both strongrobust PDFs and DM-PDFs is listed in column 4 of Table I. Column 5 of Table I represents the size of  consisting of strong robust, DM-PDFs, and advanced DM-PDFs, where denotes the cardinality of the testable basis. The DM-PDFs are identified using the techniques described in Section II, and the advanced DM-PDFs use the techniques described in Section III. Table I demonstrates the increase in the size of the testable basis set when DM-PDFs, and advanced DM-PDFs are considered. The size of the basis set increases for every circuit when DM-PDF techniques are utilized, and comes very close to the size of the auxiliary set for almost all benchmarks, which is not the case for the basis set consisting only of strong robustly tested PDFs. Bold entries in Table I indicate testable basis sets which have cardinality equal to the circuit auxiliary set size. Bold entries indicate circuits for which linear dependencies can be used to determine the circuit timing characteristics of every PDF in the circuit because every PDF in the circuit is linearly dependent on the testable basis set. Over 50% of the circuits listed in Table I reach a maximum testable basis set by using the advanced DM-PDF techniques whereas only one circuit (C880) reaches a maximum basis set size when strong robustly testable PDFs are considered. Once the basis sets are found, the circuit timing characteristics of  critical paths are determined by using the testable basis sets listed in Table I. The critical path coverage of the testable basis sets shown in Table I are listed in Table II. The number of critical paths is listed in column 2 of Table II. The total number of critical paths which are linearly dependent on the strong robust testable basis sets is listed in column 3 and the percent of critical paths linearly dependent on that basis set is listed in column 4. The total number of critical paths which are linearly dependent on the DM-PDF and advanced DM-PDF basis sets are listed in columns 5 and 7, respectively. The corresponding percentages of linearly dependent critical paths are listed in columns 6 and 8. 1An auxiliary basis set [3] is a basis set with maximum cardinality, and every single PDF in the circuit is linearly dependent on this set.

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The results in Table II show a large percentage of critical paths whose circuit timing characteristics can be determined by utilizing the procedures presented in this paper. Table II shows that the number of critical paths which are linearly dependent on the enhanced testable basis set can be over two times the number of critical paths linearly dependent on the strong robustly testable basis set [13]. For some benchmarks, the proposed work explicitly identified that zero critical paths are covered using the strong robust basis set. However the percent of critical paths covered increases to over 64% for all benchmarks, and in most cases covers one hundred percent of critical paths when the techniques from this paper are applied. Table III shows the total number of identified DM-PDFs alongside the percent increase when compared to traditional strong robustly testable PDFs. Column 2 of Table III shows the number of strong robustly testable paths and column 3 shows the number of DM-PDFs obtained using the test generation based on the algorithms presented in Section II. Column 5 represents the number of DM-PDFs identified using the advanced techniques described in Section III. Columns 4 and 6 represent the respective percentage increases in the number of strong robustly testable paths when comparing columns 3 and 5 with column 2. The percent increase from DM-PDFs (column 4) to the advanced DM-PDFs (column 6) is tremendous and shows the techniques presented in this paper drastically increase the number of  identifiable delay measurable PDFs when compared to previous work  [4]. Test generation and ATE test application is only performed on the linearly independent strong robustly testable paths. The cardinality of  those basis set sizes (shown in column 4 of Table I) is significantly smaller than the number of DM-PDFs (column 5 of Table III). The results in Tables I–III show that the presented methods increase the number of DM-PDFs significantly. The listed benchmarks display a good representation of the overall collection and similar results have been observed for the remaining circuits in the collection. An impressive percentage of critical paths are covered by the advanced basis set and in most cases a maximum basis set is found, producing 100% coverage of every path in the circuit. The increased size of the testable basis set is shown to produce improvements when determining circuit timing characteristics as demonstrated in Table II. An advantage of determining circuit timing characteristics using linear dependency relationships is that only the testable basis path set is tested.

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[2] R. Drechsler, “Bites: A bdd based test pattern generator for strong robust path delay faults,” in Proc. Conf. Eur. Des. Autom. (EURO-DAC) , Los Alamitos, CA, 1994, pp. 322–327. [3] E. Flanigan, T. Haniotakis, and S. Tragoudas, “An improved method for identifying linear dependencies in path delay faults,” in Proc. 7th  Int. Symp. Quality Electron. Des. (ISQED), Washington, DC, 2006, pp. 457–462. [4] E. Flanigan and S. Tragoudas, “Enhanced identification of strong robustly testable paths,” in Proc. 8th Int. Symp. Quality Electron. Des. (ISQED), Washington, DC, 2007, pp. 729–736. [5] S. Hassoun, “Critical path analysis using a dynamically bounded delay model,” in Proc. 37th Conf. Des. Autom. (DAC) , New York, 2000, pp. 260–265, ACM. [6] Artisan Components Inc., Sunnyvale, CA, “TSMC 0.18 m Process 1.8-Volt Sage x(tm) Standard Cell Library Databook, Release 3.1”Oct. 2001. [7] S. Minato, “Zero-suppressed bdds for set manipulation in combinatorial problems,” in Proc. 30th Conf. Des. Autom., Jun. 1993, pp. 272–277. [8] S. Padmanaban and S. Tragoudas, “Exact grading of multiple path delay faults,” in Proc. Des. Autom. Test Eur. Conf. , 2002, p. 84. [9] S. Padmanaban and S. Tragoudas, “Efficient identification of (critical) testable path delay faults using decision diagrams,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 1, pp. 77–87, Jan. 2005. [10] E. S. Park, M. R. Mercer, and T. W. Williams, “A statistical model for delay-fault testing,” IEEE Des. Test , vol. 6, no. 1, pp. 45–55, Jan. 1989. [11] A. K. Pramanick and S. M. Reddy, “On the detection of delay faults,” in Proc. Int. Test Conf. New Frontiers Test. , Sep. 1988, pp. 845–856. [12] R. Adapa, E. Flanigan, S. Tragoudas, M. Laisne, H. Cui, and T. Petrov, “Function-based test generation for (non-robust) path delay faults using the launch-off-capture scan architecture,” 2007. [13] M. Sharma and J. H. Patel, “Bounding circuit delay by testing a very small subset of paths,” in Proc. 18th IEEE VLSI Test Symp. (VTS) , Washington, DC, 2000, p. 333. [14] S. M. Reddy, C. Lin, and S. Patil, “An automatic test pattern generator for the detection of path delay faults,” in Proc. Int. Conf. Comput. Aided Des., 1987, pp. 284–287. [15] G. L. Smith, “Model for delay faults based upon paths,” in Proc. Int. Test Conf., 1985, pp. 342–349. [16] R. C. Tekumalla and P. R. Menon, “Test generation for primitive path delay faults in combinational circuits,” in Proc. IEEE/ACM    Int. Conf. Comput.-Aided Des. (ICCAD), Washington, DC, 1997, pp. 636–641.

V. CONCLUSION This work presents an improved approach for determining delay values of critical paths by using linear dependency relationships. Theoretical aspects of delay measurable PDF sensitization are extended and results show an increase in the number of DM-PDFs. The improved measuring techniques and other practical aspects of delay fault testing are effectively utilized to improve coverage for determining timing characteristics of critical paths. Experimental results show a significant increase in coverage of critical paths for most circuits.

REFERENCES [1] P. Agrawal, D. Bhattacharya, and V. D. Agrawal, “Test generation for path delay faults using binary decision diagrams,” IEEE Trans. Comput., vol. 44, no. 3, pp. 434–447, Mar. 1995.

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