_Delay - Timing Path Delay_ _ Static Timing Analysis (STA) Basic (Part 4a) _VLSI Concepts

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"Delay - Timing path Delay" : Static Timing Analysis (STA) basic (Part 4a) Part1

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Static Timing analysis is divided into several parts: Part1 -> Timing Paths Part2 -> Time Borrowing Part3a -> Basic Concept Of Setup and Hold Part3b -> Basic Concept of Setup and Hold Violation Part3c -> Practical Examples for Setup and Hold Time / Violation Part4a -> Delay - Timing Path Delay

"Timing Paths" : Static Timing Analysis (STA) basic (Part 1) "Examples Of Setup and Hold time" : Static Timing Analysis (STA) basic (Part 3c)

Note: Part 4, 5 and 6 are still under development.

"Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b)

This particular post is inspired by a question asked by Lalit. And Frankly speaking I am not able to resist myself to write a blog on this. I was thinking to capture all this since long but every time because of work I have to drop my thoughts.. But today after reading his question.. I am not able to control myself. :)

"Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a)

Part4b -> Delay - Interconnect Delay Models

So the Question is: (original question) I have a doubt regarding how delay is calculated along a path.i think there are two ways 1) to calculate max delay and min delay, we k eep adding max delays and min delays of all cells(buffer/inverter/mux) from start point to end point respectively. 2)in other way, we calculate path delay for rising edge and falling edge separately. we apply a rise edge at start point and k eep adding cell delay. cell delay depends upon input transition and output fanout. so now we have two path delay values for rise edge and falling edge. greater one is considered as Max delay and smaller one is min delay. which one is correct ?

"Time Borrowing" : Static Timing Analysis (STA) basic (Part 2) Antenna Effects Basic of Timing Analysis in Physical Design

"Delay - Timing path Delay" : Static Timing Analysis (STA) basic (Part 4a)

As I have mention that for Setup and Hold calculation , you have to calculate the Delay of the Timing path (capture path or launch path). Now in a circuit there are 2 major type of Delay.

Delay - "Interconnect Delay Models" : Static Timing Analysis (STA) basic (Part 4b)

Timing Delay between an input pin and an output pin of a cell. Cell delay information is contained in the library of the cell. e.g- .lef file 2. NET DELAY. Interconnect delay between a driver pin and a load pin. To calculate the NET delay generally you require 3 most important information. Characteristics of the Driver cell (which is driving the particular net) Load characteristic of the receiver cell. (which is driven by the net)

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Short Ans is .. both are correct and you have to use both. May be you all become confuse, so let me give you few details.

1. CELL DELAY

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RC (resistance capacitance) value of the net. (It depends on several factor- which we will discuss later) Both the delay can be calculated by multiple ways. It depends at what stage you require this information with in the design. e.g During pre layout or Post layout or during Signoff timing. As per the stage you are using this, you can use different ways to calculate these Delay. Sometime you require accurate numbers and sometime approximate numbers are also sufficient.

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Now lets discuss this with previous background and then we will discuss few new concepts.

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Now in the above fig- If I will ask you to calculate the delay of the circuit, then the delay will be Delay=0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns (if all the delay in ns) Now lets add few more value in this. As we know that every gate and net has max and min value, so in that case we can find out the max delay and min delay. (on what basis these max delay and min delay we are calculating .. we will discuss after that)

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So in the above example, first value is max value and 2nd value is min value. So

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Delay(max)= 0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns Delay(min)= 0.4+0.03+0.6+0.18+0.8+0.1+0.8+0.1+0.5=3.51ns

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Till now every one know the concept. Now lets see what's the meaning of min and max delay.

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The delay of a cell or net depends on various parameters. Few of them are listed below. Library setup time Library delay model External delay

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Back annotated Delay If any of these parameter vary , the delay vary accordingly. Few of them are mutually exclusive. and In that case we have to consider the effect of only one parameter at a time. If that's the case , then for STA, we calculated the delay in both the condition and then categorize them in worst (max delay) condition or the best condition (min delay). E.g- if a cell has different delay for rise edge and fall edge. Then we are sure that in delay calculation we have to use only one value. So as per their value , we can categorize fall and rise delay of all the cell in the max and min bucket. And finally we come up with max Delay and min delay.

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Information used in Cell and net delay calculation (Picture Source - Synopsys)

The way delay is calculated also depends which tool are you using for STA or delay calculation. Cadence may have different algorithm from Synopsys and same is the case of other vendor tools like mentor,magma and all. But in general the basic or say concepts always remain same. I will explain about all these parameter in detail in next of few blogs, but right now just one example which can help you to understand the situation when you have a lot of information about the circuit and you want to calculate the delay.

In the above diagram, you have 2 paths between UFF1 and UFF3. So when ever you are doing setup and hold analysis, these path will be the part of launch path (arrival time). So lets assume you want to calculate the max and min value of delay between UFF1 and UFF2. Information1: DELAY(ns)

UOR4

UNAND6

UNAND0

UBUF2

UOR2

5

6

6

2

5

Calculation: Delay in Path1 : 5+6=11ns, Delay in Path2: 6+2+5+6=19ns, So Max Delay = 19ns - Path2 - Longest Path - Worst Path Min Delay = 11ns - Path1 - Smallest Path - Best Path Information2: UOR4

UNAND6

UNAND0

UBUF2

UOR2

Rise Delay (ns)

5

6

4

1

1

Fall Delay (ns)

6

7

3

1

1

Calculation: Delay in Path1 : Rise Delay : 5+6=11ns, Delay in Path2: Rise Delay : 4+1+1+6=12ns, So Max Delay = 13ns -Path1 (Fall Delay) Min Delay = 11ns - Path1 (Rise Delay)

Fall Delay: 6+7=13ns Fall Delay: 3+1+1+7=12ns

Note: here there are lot of more concepts which can impact the delay calculation sequence, like unate. We are not considering all those right now. I will explain later. Information3: Library Delay

Min

Max

UOR4

UNAND6

UNAND0

UBUF2

UOR2

Rise (ns)

Delay

5

6

4

1

1

Fall (ns)

Delay

6

7

3

1

1

Rise (ns)

Delay

5.5

6.5

4.5

1.5

1.5

Fall (ns)

Delay

5.5

6.5

2.5

0.5

0.5

Calculation: For Min Library: Delay in Path1 : Delay in Path2: For Max Library: Delay in Path1 : Delay in Path2:

Rise Delay : 5+6=11ns, Rise Delay : 4+1+1+6=12ns,

Fall Delay: 6+7=13ns Fall Delay: 3+1+1+7=12ns

Rise Delay : 5.5+6.5=12ns, Fall Delay: 5.5+6.5=14ns Rise Delay : 4.5+1.5+1.5+6.5=14ns, Fall Delay:

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2.5+0.5+0.5+6.5=10ns So Max Delay = 14ns- Path1(Fall Delay)/Path2(Rise Delay) Min Delay = 10ns - Path2(Fall Delay) As we have calculated above, STA tool also uses similar approach for finding the Max delay and Min Delay. Once Max and Min delay is calculated then during setup and hold calculation, we use corresponding value. Once again I am mentioning that all these values are picked randomly. So it may be possible that practically the type/amount of variation in value is not possible. In next part we will discuss these parameter in detail one by one.

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14 comments: Anonymous August 21, 2011 2:22 AM Nice article. Many thanks to the author Reply

Karadi October 5, 2011 7:36 AM Isn't propagating rise and fall delays without considering the transitions an over or under estimate as some transitions may not even be possible. Is there some way to workaround this without having to use the input vectors. Reply

Your VLSI October 7, 2011 9:15 AM Hi Karadi, You are right but usually we do the worst case analysis. Or you can sat most of the STA tool do the calculation based like this. But if you need to check the actual calculation, then there is a methodology - know as PATH BASED ANALYSIS. In that we do delay calcualtion with respect to a particular path (timing path- please cehck the detials of timing path in my previous blogs.) And in that you can avoide all those transitions which is not possible. Reply

Anonymous December 8, 2011 6:03 PM one correction pls....When you explained Cell Delay you said it is mentioned in .lef file but it is in .lib file right? Reply

Maninder January 31, 2012 6:35 AM Hi Your VLSI..... This is the best explanation ever for Setup and hold timing and its violations.....I am waiting for your next blog.... Reply Replies your VLSI

February 7, 2012 9:56 AM

thanks Maninder. I was busy in last few months.. but soon you will see few more updates from my side. Reply

Anonymous February 3, 2012 11:33 AM Hi, I have just started to understand about the STA concepts. I got great idea about the setup and hold time from your blogs. Thank you for sharing this knowledge.

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I want to know how can I apply these concepts in the real design. i.e If I want to add some constraints in the design then how can I add ? Reply Replies your VLSI

February 7, 2012 10:01 AM

In the real design - these concept help you to debug a lot of things and in understanding the reports and all .. for applying the constraint - there is a file - SDC ( if you are using this ), in the SDC, you can define the constraint as per your requirement. I have written very introductory blog regarding the SDC file. please have a look in that. http://vlsi-expert.blogspot.in/2011/02/synopsys-design-constraintssdc-basics.html I hope that will help you. In case you have any specific question , please let me know.

Anonymous February 16, 2012 3:21 PM Thank you so much. If I will face any difficulty then surely I will ask you. Thanks again.

Anonymous February 22, 2012 1:02 PM Respected Sir, I am facing one error in SDC constraint. Actually I have made one virtual clock for constrained Input and Output port. As this clock is virtual, timing analyzer would not find any relationship between this clock and system clock. But In my design It will give negative slack and defines relationship between system clock and virtual clock. What would be the possible solution for this?

your VLSI

February 27, 2012 9:27 AM

Hi, Can you please let me know the commands and values /steps- you are using for constraining your input and output port? Just one request (please dnt mind) - constraint related questionplease ask in respective blog.It will help other people also.

Anonymous February 29, 2012 4:16 PM It is ok. Next time I will ask questions related to the constraints in related blogs only. Reply

Animesh Sharma April 5, 2012 2:54 PM This comment has b een removed b y the author. Reply

Sharan Correa June 11, 2012 11:21 PM Dear Sir, Really appreciate your handwork and sharing your knowledge to millions of ppl out there. I just need to clear one doubt on calculating the longest path combinational delay: If a path consist of two gates U1 a nand and U2 a not with (rise, fall) timings as U1:(5,6), U2(8,4).Now(rise, fall) delays for the path are (5+8,6+4).As per your description above Max delay=13, min delay=10. My doubt is, what if a 1->0 pulse is applied to inpiut of nand gate, whose other input is tied to 1? what should be the max dealy it encounters in reaching the output? it will be 6+8=14, and min dealy when a 0->1 transition at the i/p 5+4=9. Which is correct? Please clarify Reply

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