DCT700 ph0
August 24, 2017 | Author: waltech2005 | Category: N/A
Short Description
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Description
5
4
3
2
3
2
1
DCT700 Phase 0
4
Main Board Schematic
Revision History D
Schematic
Table of Contents D
MODIFICATION RECORDS
Sheet
A Rev. .00
DMR SD_299, DMR SD_301, DMR SD_303, DMR SD_304
REV.2
DMR SD_307-1, DMR SD_311-1, DMR SD_309, DMR SD_312, DMR BCST_3, DMR BCST_4
REV.3
DMR SD_317,DS_321,BCST_021,SD_326,SD_330,SD_332,SD_335,SD_341,SD_342,BCST_022
REV.4
REV.A
C
Initial Proto Rev. DMR SD_284 , DMR SD_286 , DMR SD_287, DMR SD_288, DMR SD_289, DMR SD_290, DMR SD_291, DMR SD_292, DMR SD_293, DMR SD_294, DMR BCST_1, DMR BCST_2, DMR SD_295, DMR SD_297
REV.1
1
Rev.
Ref
Description
1
.00
2
.00
DCT700 Phase 0 Title Sheet DCT.SCH. Top level connections
1
DIGITAL.SCH
Hierarchical Grouping
1
Hierarchical Analog Grouping
1
3
.00
4
.00
ANALOG.SCH
5
.00
PWR.SCH
6
.00
POR.SCH
7
.00
QUAKE_RP_DIGITAL.SCH
8
.00
PLATFORM_FLASH & SRAM.SCH
300
9
.00
DDR_SDRAM.SCH
400
10
.00
SECURITY.SCH
11
.00
QUAKE_RP_ANALOG.SCH
12
.00
VIDEO_AUDIO.SCH
13
.00
AFE.SCH.
14
.00
TUNER_UPSTREAM.SCH
Power Distribution 100
Power On Reset
200
QUAKE_RP Digital I/O
Release for mass production(REV.A=REV.4)
B
A
1
900
MC1.7, Battery, and TVPC
200/400
7114 Analog I/O
B
700/800
Baseband / Remod Output
C
1100
Analog front end.
500/600
Tuner, Upstream Amp & Diplexer
Acceptable Dielectric Material for 10 uF Multilayer Chip Capacitors. For power supply bypass applications (not AC signals). Applied Voltage
PCB Requirements
5V
Place all terminating resistors as close to source as possible. The series terminating resistors will have a value of 0, 33, or 51 Ohms.
3.3V
C B
2.5V
1.2V
Notes : 1.
These schematics are grouped heirachically by function
2.
Each page in the schematics is assigned a set of reference designators (Ref)
Dielectric Material & Size
Voltage Rating
Cap change at applied voltage.
Acceptable for use?
Y5V X7R X5R X6S Y5V X7R X5R X6S Y5V X7R X5R X6S Y5V X7R X5R X6S
10V 6.3V 10V 10V 10V 6.3V 10V 10V 10V 6.3V 10V 6.3V 10V 6.3V 10V 6.3V
-85% -10% -10% -28% -75% -3% -2% -15% -65% -2% -2% -15% -20% EBI_DATA_[6..4] = 010
DNI 10K_s EBI_DATA_7
C301 0.1U_s
R300 10K_s
DDR SDRAM SPEED SETTING
2
10K_s DNI
1
1
DNI
2
B
SRAM_VBATT
10K_s
10K_s 10K_s
The placement of C303 should be near the D6 and E1 of U301.
RP300 EBI_DATA_9 EBI_DATA_10 EBI_DATA_11 EBI_DATA_12
1 2 3 4
8 7 6 5 10000_4
EBI_RDB
A2 B5 A6
/OE /CS1 ncCS2
G5 H1 H6 G2
/WE nc1 nc2 nc3
EBI_R/WB 8 7 6 5
EBI_DATA_[15..13] to be used by F/W to detect HW configurations. EBI_DATA_[15..13] EBI_DATA_[15..13]
10000_4
111 = 000 =
3
1 2 3 4
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 nc17
R301 POR_RAM_ENB
Quake Installed Quake RP Installed
POR_RAM_ENB
Q300 2sc2712
1 1K_s
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
G1 F1 F2 E2 D2 C2 C1 B1 G6 F6 F5 E5 D5 C6 C5 B6
/UB /LB
B2 A1
GND1 GND2
D1 E6
nc4
E3
EBI_DATA_15 EBI_DATA_14 EBI_DATA_13 EBI_DATA_12 EBI_DATA_11 EBI_DATA_10 EBI_DATA_9 EBI_DATA_8 EBI_DATA_7 EBI_DATA_6 EBI_DATA_5 EBI_DATA_4 EBI_DATA_3 EBI_DATA_2 EBI_DATA_1 EBI_DATA_0 SRAMUB_CSB SRAMLB_CSB
CY62137VLL 481396-001-69
2
EBI_DATA_13 EBI_DATA_14 EBI_DATA_15
A3 A4 A5 B3 B4 C3 C4 D4 H2 H3 H4 H5 G3 G4 F3 F4 E4 D3
SRAM_CSB
RP301
B
EBI_ADDR_1 EBI_ADDR_2 EBI_ADDR_3 EBI_ADDR_4 EBI_ADDR_5 EBI_ADDR_6 EBI_ADDR_7 EBI_ADDR_8 EBI_ADDR_9 EBI_ADDR_10 EBI_ADDR_11 EBI_ADDR_12 EBI_ADDR_13 EBI_ADDR_14 EBI_ADDR_15 EBI_ADDR_16 EBI_ADDR_17
VCC1 VCC2
10K_s EBI_DATA_0
R312
E1 D6
R311
SRAMUB_CSB SRAMLB_CSB
D
D
A
RESET CONFIGURATION: cp_data00 RC: ebi_config Bit cp_data01 RC: boot_config Bit cp_data02 RC: Memory Clock Speed Select Bus Bit 0 cp_data03 RC: Memory Clock Speed Select Bus Bit 1 cp_data04 RC: MIPS Clock Speed Select Bus Bit 0 cp_data05 RC: MIPS Clock Speed Select Bus Bit 1 cp_data06 RC: MIPS Clock Speed Select Bus Bit 2 cp_data07 RC: USB Normal Clock Source Select cp_data08 RC: Internal clk27 Alternate Source Select cp_data09 RC: MIPS After Reset Delay Enable cp_data10 RC: Staggered Reset Off Select cp_data11 RC: Slip ckt control cp_data12 RC: PLL By-Pass Select 5
D
A
San Diego, California, USA.
Taipei, Taiwan, R.O.C.
Title
PLATFORM_FLASH & SRAM.SCH Size C
File Name
Document Number
Date: Friday, September 26, 2003 4
3
2
Rev A
864684-049 Sheet 1
8
of
14
5
4
3
1
RP400 DDR_ADDR_10 DDR_ADDR_0 DDR_ADDR_1 DDR_ADDR_2 DDR_ADDR_3 DDR_ADDR_4 DDR_ADDR_6 DDR_ADDR_5
16 MBYTES UNIFIED DDR_SDRAM
DDR_LDQS_0 DDR_LDM DDR_WEB DDR_CASB DDR_RASB DDR_CSB_0 DDR_BA_0 DDR_BA_1
C403 1000P_s
SD_ADDR_7 SD_ADDR_8 SD_ADDR_9 SD_ADDR_11 SD_ADDR_12
SD_ADDR_7 SD_ADDR_8 SD_ADDR_9 SD_ADDR_11 SD_ADDR_12
1 2 3 4 5 6 7 8 R408 R409 R410 R411 R412
33_8
33_s 33_s 33_s 33_s 33_s
DDR_ADDR_7 DDR_ADDR_8 DDR_ADDR_9 DDR_ADDR_11 DDR_ADDR_12
2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
1 3 15 18 33 55 61 9
U400 DDR_DATA_0 DDR_DATA_1 DDR_DATA_2 DDR_DATA_3 DDR_DATA_4 DDR_DATA_5 DDR_DATA_6 DDR_DATA_7 DDR_DATA_8 DDR_DATA_9 DDR_DATA_10 DDR_DATA_11 DDR_DATA_12 DDR_DATA_13 DDR_DATA_14 DDR_DATA_15
DDR_DATA_0 DDR_DATA_1 DDR_DATA_2 DDR_DATA_3 DDR_DATA_4 DDR_DATA_5 DDR_DATA_6 DDR_DATA_7
16 15 14 13 12 11 10 9
467639-001 C401 6.3V X5R 10U_c 1206 See table page 1 D
RP402 SD_DATA_0 SD_DATA_1 SD_DATA_2 SD_DATA_3 SD_DATA_4 SD_DATA_5 SD_DATA_6 SD_DATA_7
C405 0.1U_s
D
33_8 SD_DATA_[7..0]
1
1 C404 0.01U_s
VDD VDDQ VDDQ VDD VDD VDDQ VDDQ VDDQ
16 15 14 13 12 11 10 9
C411 1U_s
2
1 2 3 4 5 6 7 8
2
SD_LDQS_0 SD_LDM SD_WEB SD_CASB SD_RASB SD_CSB_0 SD_BA_0 SD_BA_1
SD_LDQS_0 SD_LDM SD_WEB SD_CASB SD_RASB SD_CSB_0 SD_BA_0 SD_BA_1
C410 1000P_s
2
C409 0.01U_s
2
1
33_8 RP401
1
+2.5V
1
16 15 14 13 12 11 10 9
2
1 2 3 4 5 6 7 8
1
SD_ADDR_10 SD_ADDR_0 SD_ADDR_1 SD_ADDR_2 SD_ADDR_3 SD_ADDR_4 SD_ADDR_6 SD_ADDR_5
SD_ADDR_10
2
SD_ADDR_[6..0]
D
2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 NC (A13)
29 30 31 32 35 36 37 38 39 40 28 41 42 17
DDR_ADDR_0 DDR_ADDR_1 DDR_ADDR_2 DDR_ADDR_3 DDR_ADDR_4 DDR_ADDR_5 DDR_ADDR_6 DDR_ADDR_7 DDR_ADDR_8 DDR_ADDR_9 DDR_ADDR_10 DDR_ADDR_11 DDR_ADDR_12
+2.5V
8M x16
+2.5V
R401 1K_s
SD_DATA_[15..8]
R402 10K_s R407 121_s
R403 10K_s
R405 121_s
D
DDR_CK DDR_CKB
C
SD_CLK SD_CLKB
SD_CLK
R414
20_s
DDR_CK
SD_CLKB
R428
20_s
DDR_CKB
DDR_UDM DDR_LDM R404 121_s
R406 121_s
C407 10P_s
Place this cap close to the U200 D (QUAKE) SD_CLKE SD_UDQS_1 SD_UDM
SD_CLKE SD_UDQS_1 SD_UDM
R422 R423 R424
33_s 33_s 33_s
C408 10P_s
51 16 21 22 23 24 26 27 44 45 46 47 20 19 50
UDQS LDQS WE CAS RAS CS BA0 BA1 CKE CK CK UDM LDM DNU DNU
VREF
49
SD_VREF
Place caps near U202 (DDR_SDRAM)
1
DDR_DATA_8 DDR_DATA_9 DDR_DATA_10 DDR_DATA_11 DDR_DATA_12 DDR_DATA_13 DDR_DATA_14 DDR_DATA_15
2
33_s 33_s 33_s 33_s 33_s 33_s 33_s 33_s
NC NC NC NC
VSSQ VSS VSS VSSQ VSSQ VSSQ VSS VSSQ
R413 R415 R416 R417 R418 R419 R420 R421
C400 0.01U_s 10% 50V X7R
D
53 43 25 14
C406 0.01U_s 10% 50V X7R
1%
R400 1K_s 1% C
D
D
D
Place this cap close to the U202
6 34 48 52 58 64 66 12
SD_DATA_8 SD_DATA_9 SD_DATA_10 SD_DATA_11 SD_DATA_12 SD_DATA_13 SD_DATA_14 SD_DATA_15
DDR_UDQS_1 DDR_LDQS_0 DDR_WEB DDR_CASB DDR_RASB DDR_CSB_0 DDR_BA_0 DDR_BA_1 DDR_CLKE
MICRON - MT46V8M16TG-6T D
DDR_CLKE DDR_UDQS_1 DDR_UDM
LAYOUT NOTES:
B
1. DDR_DATA[15:0] lines and strobes should be the shortest (and most direct) trace lengths as possible. 2. CK & CKB traces again should be the shortest possible lengths, with CK & CKB being adjacent to each other on ALL layers. 3. DDR_ADDR[15:0], & control signals are not as critical as layout items 1 and 2. 4. NO data or data strobe traces should exceed 2 inches in length. (The 2 inches includes traces to and from series termination resistors) Less critical signals should be less than 3 inches. Clock traces can be up to 3 inches, but should be as short as possible. Route DQS and clock pair signal traces FIRST when laying out the board. 5. Trace length variations are as follows: Data, DQS signal traces have no more than 0.5 inch variation Address, DQM, control signal traces have no more than 1.0 inch variation Clock traces should be as closely matched as possible. 6. Clock traces should be on same layer(s) and should be spaced 5 mils from each other, with other signal traces spaced 10 mils away. 7. Number of vias for data and DQS lines should be restricted to maximum of 2 per signal trace. Other signals should be restricted to no more than 3 vias per signal trace. Micro-vias (14 mil through hole) can be used for signals, with larger (20 mil minimum through hole) used for power and grounds. 8. Trace widths for signals should be 5-6 mils. Power and ground signals should have minimum 10 mil traces from pins to vias (that drop down to power/ground planes) 8a. DDR_VREF signal should be 20mil trace. 9. DDR section of board should keep all signals that are NOT part of the DDR interface outside of defined area on ALL layers. 10. Decoupling capacitors should be used in accordance with the DDR manufacturer's recommendations. Bulk bypass capacitors should be located nearby DDR memory. 11. Power and ground pins should have dedicated traces to VIA, with adjacent power and ground pins using common trace only when distance to via is less than .2 inch from any one pin/ball. In this case a more robust trace should be used to connect more than one pin to the via. (15 mil trace minimum)
B
A
A
San Diego, California, USA.
Taipei, Taiwan, R.O.C.
Title
DDR_SDRAM.SCH Size C
File Name
Document Number
Date: Friday, September 26, 2003 5
4
3
2
Rev A
864684-049 Sheet 1
9
of
14
5
4
3
2
1
+3.3V
C915 47P_s 2
C909 0.1U_s
2
2
C908 4700P_s
1
1
1
1 C907 47P_s 2
C906 0.1U_s
2
2
C905 4700P_s
2
C904 0.1U_s
1
1
1
1
C903 4700P_s 2
C902 0.1U_s 2
C901 0.1U_s
2
2
C900 4700P_s
1
1
1
Bypass
D
+3.3V D
D
MC_RESETB
3
97
RESETB
1 2 3
SCLK SPL_CSB MOSI
22 23 24 25
TMROEB TMS TCK TDI
49 51
FUSE1 FUSE0
76 77 78
MIERROR MCLKI MIVAL
INFO_DATA
81 82 83 84 85 86 87 88
MDI7 MDI6 MDI5 MDI4 MDI3 MDI2 MDI1 PKTDATAIN/MDI0
INFO_SYNC
89
PKTSTARTIN/MISTAT
INFO_CLK MC_CLK40 MC_CLK27
92 94 100
SPI_CLK MC_SPI_CSB SPI_MOSI RP901 5 6 7 8
4 3 2 1
D
+3.3V
+3.3V
1
CLK27M TEST_PAD
D901 1n5711 3
VB901 TESTPIN
PKTCLKIN/BITCLK SYNC_CLK CLK_27
99
CTRL_CLK_27
61 62 63 64 65 66 67 68
TAD7 TAD6 TAD5 TAD4 TAD3 TAD2 TAD1 TAD0
73 74 75
TESTCLK TESTWRB TESTSEL
16 17
VBATT GNDBATT
1
1
VBATT
C911 0.1U_s
SPI_MISO
UP_INTB
5
MC_IRQB
SPI_MISO MC_IRQB TD900 TDO
TDO
26
FUSE1RTN FUSE0RTN
50 52
MOERROR MCLKO MOVAL
45 44 43
MDO7 MDO6 MDO5 MDO4 MDO3 MDO2 MDO1 PKTDATAOUT/MDO0
40 39 38 37 36 35 34 33
MC_PKTDATA
PKTSTARTOUT/MOSTRT
32
MC_PKTSTART
PKTCLKOUT
28
MC_PKTCLK
TESTOUT3 TESTOUT2 TESTOUT1 TESTOUT0
55 56 57 58
PDUNDERB VSUPPLY
18 19
VBATT_EN
98
MC1_7C
D
C
RP900 1 2 3 4
R926
51_s R914 4.7K_s
D
C913 0.1U_s
B
D
D
2
2
+ C914 10u_50v
Low Leakage Cap
D VB900 TESTPIN
SRAM_VBATT
D
B
D
D
SRAM_VBATT
2
D911 1n4148w
PKT_DATA PKT_SYNC PKT_CLK
POR_RAM_ENB
2
1
1
2
D902 1n4148w
PKT_DATA PKT_SYNC PKT_CLK
8 7 6 5 33_4_s
2
+ C910 100uf_07
4
1
C
INFO_CLK MC_CLK40 MC_CLK27
MISO
1
R904 470K_s
D
INFO_SYNC
10 8 11 13 12
470_4
D WRPROT_1 WRPROT_3
R903 470K_s
MC1.7
GND GND GND GND GND GND GND GND GND
+3.3V
TVPC_SIO TVPC_CLOCK TVPC_RESETB TVPC_5V_SENSE TVPC_3V_SENSE
48 53 59 70 72 80 91 93 95
SPI_CLK MC_SPI_CSB SPI_MOSI
INFO_DATA
TVPC_DETECTB
GND GND GND GND GND GND
POR_RESETB
POR_RESETB
2 D912 bat54alt1 1
7 15 20 27 29 42
SYS_RESETB
SYS_RESETB
9
VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3
U900 R922 10K_s
6 14 21 30 46 47 54 71 79 90 96 31 41 60 69
+3.3V
1
3
BTV
2
BT905 3_0V_BR2032T3L_B
VB902
JET
TESTPIN R906 620_s
VB903 TESTPIN D
DNI BTV
1
1
3
BTV
1
3
BTV
1
3
BTV
BT907 106007-002
A
JET
BT904 3_0V_BR2450A_GB 414816-003-99 JET
A
2
BT906 3_0V_BR2330A_GA 2
2
2
BT903 3_0V_BR2335T3L_B 123002-020-99
JET
JET
San Diego, California, USA.
Taipei, Taiwan, R.O.C.
Title
SECURITY.SCH Size C
Document Number
Date: Friday, September 26, 2003 5
4
3
2
Rev A
File Name
864684-049 Sheet 1
10
of
14
A
B
C
D
E
+2.5V
AB5 AB6
AB12 AB13
Place bypass capacitors of +3.3v, +2.5v, and +1.2V near IC's pin on bottom side. QUAKE pin numbers for each cap are indicated.
+3.3V C427 0.1U_s
+3.3V
D L415 ferrite_0603 1 L425 ferrite_0603 1
C432 0.1U_s D
C440 0.1U_s
+3.3V
AA5 AB16 AB19 AB20 E6 E7 E11 E21 E22 M5 N5 U22 V22
C443 0.1U_s
C444 0.01U_s
C445 0.1U_s
C446 0.01U_s
C447 0.1U_s
C448 0.01U_s 4
D
AB16
AB19 AB20
AA5
C419 0.1U_s
C420 0.01U_s
E6 E7
C421 0.1U_s
E21 E22
E11
C422 0.1U_s
C423 0.01U_s
M5 N5
C424 0.01U_s
+3.3V
U22 V22 C425 0.01U_s
C426 0.1U_s
D
E19
+3.3VA1 +3.3VA2
M26 N24
BTSC_ADC2_PSUPA BTSC_ADC2_NSUPA_SHA BTSC_ADC2_PSUPA_SHA BTSC_ADC2_NSUPA
M22 L23
K24 H26
1
2 C455 0.1U_s
L421 ferrite_0603 1
C484 0.1U_s
2
1
R24 P26
DO_ADC3_NSUPA DO_ADC3_PSUPA_SHA DO_ADC3_NSUPA_SHA DO_ADC3_PSUPA
N23 P22
+3.3VA7
K23
QFE_XTAL_PSUPA
QFE_XTAL_NSUPA QFE_ADC_ASUB
L25 L24
UO_DAC_ASUB UO_DAC_BG_NSUPA UO_DAC_NSUPA
E25 E26 E24
1
C486 0.1U_s
2 C487 0.1U_s
UO_DAC_PSUPA
C472 1U_s
UO_VBIAS
F25
+3.3VA9
T26
DO_LO_VBB
DO_LO_BGND
R23
+1.2VA1
T22
DO_LO_VDDB
DO_LO_VSSB
T23
+1.2VA2
D22
QFE_VPP
QFE_PGND
C22
VDD_PLL
VSS_PLL
G25
UO_DAC_NSUPD
G26
UO_QUIET_NSUPD
D24
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
T16 T15 T14 T13 T12 T11 R16 R15 R14 R13 R12
G24
+1.2VA4
D25
+1.2VA5
F22
UO_QUIET_PSUPD
L11 L12 L13 L14 L15 L16 M11 M12 M13 M14
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
8 7 6 5
OOB_IF_POS OOB_IF_NEG QAM_AGCI
OOB_VCO_POS OOB_VCO_NEG
UO_DAC_PSUPD
C475 0.1U_s
A
R472 8.06K_s 1%
C473 0.1U_s
R473 30.1K_s 1% R474 562_s 1%
1
DO_ADC3_VIP DO_ADC3_VIN DO_AAGC_SD DO_LO_BP DO_LO_BN
U24 U25 U26
UO_IOUTP UO_IOUTN
F26 E23
TUNER_SDA TUNER_SCLK
TX_DAC+ TX_DAC-
3
AUD_I2SI_CLK AUD_I2SI_LRCLK AUD_I2SI_DATA
N25 N26
BTSC_ADC2_VIP BTSC_ADC2_VIN
J24 J23
AVD_ADC1_VIP AVD_ADC1_VIN
D18
AUD_DIGAUD
F23
(UO_IREFD) UO_DAC_BG_PSUPA
H24
QFE_ADC_VBGOUT
H25
QFE_EXT_IREF
C18
QVD_RBIAS
A18
QVD_VREF
C17
QVD_AVSS_BIAS
C16
QVD_AVSS_BIAS2
AUD_LEFT_POS AUD_LEFT_NEG AUD_RIGHT_POS AUD_RIGHT_NEG
C14 D14 A14 B14
QVD_DV_A_P QVD_DV_B_P QVD_DV_C_P QVD_DV_D_P
E17 B17 E16 B16
UO_PWR0_GATEB UO_PWR1_CLK UO_PWR2_DATA UO_PWR3
D26 C24 A24 B26
US_CTL_CSB US_CTL_CLK US_CTL_DATA
UO_RF_SD_OUT
B23
TX_OEN
DI_ADC1_VREFN DI_ADC1_VREFP DI_ADC1_VCM
J26 H22 H23
BTSC_ADC2_VREFN BTSC_ADC2_VREFP BTSC_ADC2_VCM
M24 M23 M25
DO_ADC3_VREFN DO_ADC3_VREFP DO_ADC3_VCM
P24 P23 P25
AUDIO_LEFT_POS AUDIO_LEFT_NEG AUDIO_RIGHT_POS AUDIO_RIGHT_NEG
DIG_COMPOSITE
DAC A, C & D not used.
Place no traces or parts between AUDIO_LEFT_POS/AUDIO_LEFT_NEG and AUDIO_RIGHT_POS/AUDIO_RIGHT_NEG. Keep traces close in length and route traces next to one another. Surround each pair with DGND. Surround video trace DIG_COMPOSITE with DGND.
C474 0.1U_s
2
C492 C481 C493 C463 C464 C465 C466 C467 C471 1U_s 1U_s 1U_s 1U_s 1U_s
A D
2 C438 0.1U_s
L414 ferrite_0603
R25 R26 C23 T25 T24
TNR_RFTE0 TNR_RFTD TNR_RFTCK
D
C437 0.1U_s
A
DI_RFAGC_SDV DI_AGC_SDV
470_s
2
1
A23 A25
QAM_AGCT
C436 0.1U_s
L413 ferrite_0603
DI_ADC1_VIP DI_ADC1_VIN
AF22 AE22 AD22 R475
D
L412 ferrite_0603
K26 K25
C457 0.1U_s
D
2
1
IB_IF_POS IB_IF_NEG
C435 0.1U_s
L411 ferrite_0603 1
RP411 1000_4
RP412 470_4 1 2 3 4
RP410 1000_4
QUAKE Analog
M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R11
L410 ferrite_0603 1
+3.3VA8 F24
+1.2VA3
2
L424 ferrite_0603
G23 J25
+3.3VA5 +3.3VA6
C485 0.1U_s
L423 ferrite_0603
Place these parts near QUAKE.
Quake
+3.3V
1
1
Signal Opitimize
C456 0.1U_s
2
L422 ferrite_0603
DI_ADC1_NSUPA DI_ADC1_NSUPA_SHA
U200A
D
OOB_AGC
2 C454 0.1U_s
DI_ADC1_PSUPA_SHA DI_ADC1_PSUPA
+3.3V
8 7 6 5
E14
XTAL_CLK27_NSUPA
1 2 3 4
SDC_AGND
XTAL_CLK27_PSUPA
8 7 6 5
SDC_AVDD
C20
1 2 3 4
E13
+3.3VA0
C453 0.1U_s
L420 ferrite_0603
ANA_1.2V
QVD_AVDD_A QVD_AVDD_B QVD_AVDD_BIAS QVD_AVDD_C QVD_AVDD_D
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
C442 0.1U_s
1
1
C450 467639-001 10U_c 6.3V X5R 1206 See table page 1
QUAKE Power
VDD25 VDD25 VDD25 VDD25
VDD12 VDD12 VDD12
V5 W22 Y5
SDC_AVDD
+3.3VA3 +3.3VA4
2
L419 ferrite_0603
2
+1.2V
2
1
L401 10uH_c_1008
V5 Y5
D
L418 ferrite_0603
+1.2V
D17 A17 B18 D16 A16
DAC A, C & D not used.
A
3
AB5 AB6 AB12 AB13
2
C434 467639-001 6.3V X5R 10U_c 1206 See table page 1
K5 L5
2
ANA_3.3V
2
E15 E18
1
10uH_c_1008
E8 E9 E10
2
L402
A17 (DAC B)
C441 0.01U_s
Quake
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
+3.3V
U200C AB21 VDD12 AB18 VDD12 AB17 VDD12 AB15 VDD12 AB14 VDD12
AB22 E8 E9 E10 E15 E18 G22 J22 K5 L5 L22 N22 R22
0.1U_s
4
AB21 AB22 W22
G22 J22 L22 N22 R22
D
VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12
C482
C428 0.1U_s
AB14 AB15 AB17 AB18
2 C439 0.1U_s
VIDEO DAC CALCULATIONS Ioutfs = 17.4 mA with Rbias = 628 ohms Choose Rbias = 562 ohms Rload = 75 ohms (see video page) Dwhite = 364 (9 bit value) NTSC Dsync = 14 (9 bit value) NTSC Vout p-p = Ioutfs * (628 ohms / Rbias) * Rload * ((Dwhite - Dsync)/511) = 1 Vp-p
1U_s 1U_s 1U_s 1U_s
A
A
1
1
San Diego, California, USA.
Taipei, Taiwan, R.O.C.
Title
QUAKE_ANALOG.SCH Size Custom
Document Number 864684-049
Date: Friday, September 26, 2003 A
B
C
D
E
File Name Sheet
Rev A 11
of
14
5
4
3
2
1
Audio DAC Filter and Output Amp +5V 1%
Video DAC Filter and Output Amp 1
C721 22P_s 1 2
C719 0.1U_s
D
+5V
2
D
2
-
DAC_AUD_LEFT
R713 3.3K_s
2 Vrms at 0 dBFS.
LINE_OUT_LEFT
-5V
REMOD_VIDEO
C702 0.1U_s
R703 1.2K_s
C739 100P_s
3
R730 47.5K_s 1%
4
AUDIO_LEFT_NEG
C720 270P_s 2
R728 8.25K_s 1%
D 1
+
U700A NJM4580 128006-129-26 1
2
3
1
AUDIO_LEFT_POS
8
D R729 47.5K_s 1%
R727 8.25K_s 1%
Q701 2sc2712
2
C701 150P_s
R701 280_s 1%
Q700 2sc2712
D
5
+
6
R737 47.5K_s 1%
U700B NJM4580 128006-129-26 7
R714 3.3K_s
2 Vrms at 0 dBFS.
-
-5V
D DAC_AUD_RIGHT
LINE_OUT_RIGHT
D
C703 0.1U_s
C745 100P_s
-5V
R707 1K_s
1
R736 47.5K_s 1%
C707 100P_s
R706 887_s 1%
R705 510_s
4
C725 270P_s
C700 270P_s
COMP_OUT
2
D
R700 102_s 1%
+5V
R708 75_s 1%
C704 10P_s 1 2
1
1
2
1 2
1
DIG_COMPOSITE
R704 1K_s 1%
3
3
R702 20_s
D
1%
1 AUDIO_RIGHT_NEG
22P_s 2
L700 6.8uH_c_0805
2
R735 100K_s
2
R734 8.25K_s 1%
D
2
C723 1
8
R733 8.25K_s 1%
1%
C718 0.1U_s
C724 22P_s 1 2
AUDIO_RIGHT_POS
1
R732 100K_s
Q702 2sc2712
1
D
Place no traces or parts between AUDIO_LEFT_POS and AUDIO_LEFT_NEG. Keep traces close in length and route traces next to one another. Surround the pair of traces with digital ground plane.
2
R731 100K_s
D R738 100K_s
Place no traces or parts between AUDIO_RIGHT_POS and AUDIO_RIGHT_NEG. Keep traces close in length and route traces next to one another. Surround the pair of traces with digital ground plane.
C
D
1%
C
C726 22P_s 1 2
Video/Audio RF Modulator (Remod) L803 4.7uH_c_0805 1
REMOD_VIDEO R806 150_s RES\1%\0603
10% 2
F800 1 3
3
C810 0.01U_s R804 2 2K_POT 118874-513-14
2
tps4_5mb2 R805 560_s
B
B
1
A
Loop Filter must be as close as possible to pins 14&15 C808
R807 10K_s
R803
A 0.047U_s
CH3/4_SEL C815 0.1U_s
2.2K_s
C809 0.022U_s U800
R741 2K_s 1% Y800 R810 1K_s
R743 1.3K_s 1%
6 7 8 9
A
2 50K_POT
C818 Must be X7R 1U
3
2 Vrms at 0 dBFS.
1 2 3 4
A
27P_s
X7R
R809
C820 0.1U_s C821 1000P_s
DAC_AUD_RIGHT
C816
PREEM AUDIO SPLFLT PS/LO
SFS PLLFLT TVOUT VIDEO TVOVCC VCCA GND GND
C807 0.01U_s
16 15 13 10
1
L801 120nH_c_0603 2
L800 150nH_c_0603 1 2
C805 9P_s
14 11 5 12
R801 27_s
REMOD_OUT
C803 7P_s R802 470_s
+5V C804 36P_s
mc44bc375u
L1119 10uH_c_1008
A
C800 0.01U_s
R800 470_s
C802 43P_s A
A
L804 3.3uH_c_1210
A
A
C817 750P_s 5%, NPO
A
C819 0.022U_s
R808 7.5K_s
A
MC44BC375U data sheet: 85% FM modulation at 1 kHz with 205 mVrms input at pin 7, with pre-emphasis. Pre-emphasis gain at 1 kHz = 0.87 dB. 100% modulation = +/- 25 kHz. To achieve +/- 50 kHz FM modulation (200%) without pre-emphasis, the nominal input level at pin 7 is: 2*(205 mVrms)*(0.87 dB)/(85%) = 534 mVrms. The digital audio level at the top end of R853 must be greater than 534 mVrms in order to achieve alignment. Target value = 566 mVrms for analog channel and 1132 mVrms for digital channel.
1
Lowpass filter, F3dB = 159 kHz D
A
CHS PSS LOP XTAL
A
Change to surface mount. TDK part NLFV25T-100K.
C814
C813
1000P_s
0.01U_s
C812 0.1U_s
C822
C1142 +
D800 smbj13
10uf_01
0.1U_s 2
1.132 Vrms at 0 dBFS R742 2K_s 1%
4MHz
1
2 Vrms at 0 dBFS.
1
REMOD_AUDIO
2
DAC_AUD_LEFT
A
A A
A
San Diego, California, USA.
Taipei, Taiwan, R.O.C.
Title
AUDIO_VIDEO.SCH Size C
File Name
Document Number
Date: Friday, September 26, 2003 5
4
3
2
Rev A
864684-049 Sheet 1
12
of
14
A
B
C
D
E
+5VA_OOB +5V
L1106 10uH_c_1008 1
501442-002 10V Y5V 0805 See table page 1.
C1109 +
10uf_01
60 MHz Lowpass Filter
2 4
IF_IN-
11
AGC_IN
x6964m A 1
QAM_AGCI
3
C1110 0.1U_s
C1105 0.01U_s 1 2
R1102 499_s 1%
8
AGC_OUT1
13
AGC_OUT2
6
C1103 5P_s
1
1 9
7
GND 2
A
4
IB_IF_POS TP1100
L1100 1.5uH_c_0603 10%
IB_IF_POS 1
12
14
469774-001-28
IF_OUTIF_OUT+
L1102 1.5uH_c_0603 10%
C1102 9P_s
C1101 9P_s
L1105 1.5uH_c_0603 10%
C1100 5P_s
R1100 1K_s 1%
L1103 1.5uH_c_0603 10%
IB_IF_NEG
L1101 1.5uH_c_0603 10% TP1101 IB_IF_NEG
Inductors are TDK MLF1608 series
DELAY_ADJ
2
TP1103 QAM_AGCI
AGC_SW
4
LA7783
R1101 499_s 1%
2
IF_IN+
VCC
1 16
C1104 0.01U_s 1 2
2
SAW_IF_NEG
GND
4 5
A
L1104 1.5uH_c_0603 10%
Table 1 C1100 C1102 L1100 L1102 L1104
C1101 Do not install C1103 Do not install L1101 0 ohm resistor L1103 0 ohm resistor L1105 0 ohm resistor R1100 1000 ohms 1% R1101 R1102 499 ohms 1%
TP1102 AGND
15
POUT1 POUT2
SAW_IF_POS
AGC_VCC
ING
3
GND
CHIP
VCC
2
QAM_IF-
U1100
IN
DRV_AMP_VCC
1
5
F1100 TUNER_IF
QAM_IF+
10
TP1104
2
2
2
C1108 0.01U_s
1
C1107 0.1U_s
2
1
1
+5VA_IB
QAM IF SAW Filter and AGC Amp
A
+5VA_OOB
+5VA_OOB 3
3
149188-018 F1101
OOB Tuner
5 4
POUT2 POUT1
3
SOUT
CHIP
2
IN
1
saf49_10mc220z
L1108 100nH_c_0603 L1109 100nH_c_0603
A 1
17
LO_IN2
22
21
14
1
A
1 1
C1130 6P_s
R1105 75_s
1
2
C1132 12P_s
2
A
C1140 27P_s
See note 3
OOB_VCO_NEG
C1139 47P_s
C1138 47P_s
C1137 27P_s
R1110 23.7_s 1% L1118 27nH_c_0603
L1116 27nH_c_0603
L1114 27nH_c_0603
R1107 49.9_s 1%
12
OUT2
13
GND 28
GND
NC_GND
C1126 0.1U_s 1 2
25
18
GND
GND 15
11
NC_GND 10
NC_GND
GND 7
C1135 0.01U_s 1 2
6
L1113 27nH_c_0603
GND
L1115 27nH_c_0603
NC_GND
L1117 27nH_c_0603
1
R1109 23.7_s 1%
AGC_IN
3
9
180 MHz Lowpass Filter
OOB_VCO_POS
OUT1
C1125 0.1U_s 1 2
A
NC_GND
A
2
C1134 11P_s
2
C1122 0.1U_s 2
471105-001-32
C1123 0.1U_s 2
LO_IN1
20
1
U1101 LA7784
2
RF_IN2
C1124 1000P_s
VCC_POST_AMP
2 24 C1129 0.01U_s 16
VCC_LNA
RF_IN1
VCC_LNA
MIX_OUT2
23
VCC_DRIVER
MIX_OUT1
27
C1128 0.01U_s 1 2
19
8 VCC_IF
26
VCC_MIX_LO
5 IF_IN2
4
A
L1110 should be changed by new part number
A
1
A
2
L1112 should be changed by new part number
Keep the bypass capacitors very close to the pins of the LA7784
2 R1104 51_s C1127 0.01U_s
L1110 120nH_c_0603
L1111 100nH_c_0603
C1120 0.01U_s
2
C1131 5P_s 1 2
IF_IN1
1
OOB_TAP
C1121 0.01U_s
2
L1112 220nH_c_0603
R1103 51_s
1
C1133 9P_s 1 2
1
70 to 130 mhz LPF. Helps to reduce LO leakage and also reject signals above 130 MHz.
TP1105 OOB_IF_POS 2
OOB_IF_POS
Note 3 OOB_IF_NEG TP1106 OOB_IF_NEG
TP1107 AGND
See note 3 A
C1136 0.01U_s 1 2
Notes :
Inductors are TDK MLG1608 series
TP1108 OOB_AGC
1. Use 0603 chip caps and resistors. 2. LA7784 Batwings must be connected to ground.
1
OOB_AGC
3. Keep these 2 traces very close to each other. Don't route under bypass caps. Don't place any trace between them.
2
C1141 0.1U_s
1
1
A
San Diego, California, USA.
Taipei, Taiwan, R.O.C.
Title
AFE.SCH Size C
File Name
Document Number 864684-049
Date: Friday, September 26, 2003 A
B
C
D
Sheet E
Rev A 13
of
14
A
B
15.8, 1% 35.7, 1%
C
D
E
+5V_TUNER
R519 120_s
C525 1000P_s
R520 1.2K_s
A
L511 150nH_c_0603
C524 120P_s
2
1
1 1
Q501 2sc5227_5
3
L513 120nH_c_0603
L512
A
390nH_c_1008 4
2
C526 470P_s
2
4
A
2
1
R522 4.7_s
OOB_TAP
R521 470_s
C527 2P_s
A
70 MHz Highpass Filter C532 22P_s
R523 1M_2010
L517 100nH_c_1008
AGC OPEN
9
+5V
4
2 10 13 14 15 16
A
GND GND GND GND GND GND
12
IF+
2
2
3
16 15 14 13
1 2 L500 1uH_c_1008 C500 0.1U_s
GND GND GND GND
GND GND GND GND
12 11 10 9
GND GND GND GND
C501 0.1U_s
L516 120nH_c_1008
A
A
1K_s
Place close to the ALPS TUNER
1
1
C533 150P_s
RF_IN
A 5 6 7 8
R501
QAM_AGCT C535 390P_s
1 2 3 4
+5V_TUNER 1
1
C534 22P_s
Diplexer shield
2
C536 33P_s
RF_conn
A
QAM_IF+
A A
42 MHz Lowpass Filter 3
R500
SCLK SDA C538 27P_s
5 6 7
C540 18P_s
SCL SDA AS
150_s GND
E500
S501
GND GND GND GND
A TUNER1 TDEZ1X002A
11
IF-
QAM_IF-
3
2
1
L520 270nH_c_1008
2
1
L521 270nH_c_1008
2
1
A UPSTREAM
2 1
1
L519 390nH_c_1008
8
A
L518 390nH_c_1008
C537 100P_s
C539 100P_s
C541 82P_s
A
C542 39P_s
L522 27uH_r 21
A
2
D500 smbj13
A
470_s 470_s
R502 R503
+5V
470_s 470_s
+5V_TUNER L523 10uH_c_1008
SCLK SDA
1
TUNER_SCLK TUNER_SDA
R504 R505
Place these parts near tuner IC.
C560
C559
100P_s
100P_s
100P_s
100P_s
R603 R604
L608 L609
L606 L607
L604 L605
C614
C613
C612
C611
R600
C603
C604
35.7, 1% 13.0, 1% 15.8, 1%
180nH
220nH
180nH
56pF
100pF
100pF
56pF
15pF
270pF
56nH
56nH
56nH
120pF
330pF
330pF
120pF
100nH
82nH
120pF
220pF
220pF
120pF
6800 pF DNI
0.1uF
82nH
93.1, 1% 26.1, 1% 31.6, 1%
L606 56nH_c_0603
C616 0.01U_s TX_DAC-
L609 56nH_c_0603 SEE OPTION TABLE 1 R604 13_s 1%
L607 56nH_c_0603
C553 1000P_s
L604 56nH_c_0603
C612 330P_s
+5V_US
JET C602
L605 56nH_c_0603
5
/SHDN TXEN VIN+
R600 26.1_s
C611 120P_s
C609 0.01U_s
6 2
R602 0_s
Inductors are TDK MLG1608 series
R603 13_s 1%
A
U600 la7791t 12 18
TX_OEN
R601 0_s
TX_DAC+ C613 330P_s
C554 1000P_s
A
Upstream Amp
0.1uF
C608 0.01U_s C614 120P_s
C555 1000P_s
2
D
L608 56nH_c_0603
C556 0.1U_s
A
+5V_US
C615 0.01U_s
+ C557 470u_10v
R526 0_s
Option Table 1
GND2
20
VCC2
19
NC
17
VOUT+
16
VOUT-
15
VCM NC
14 13
DGND SCLK SDA /CS
7 10 9 8
VINVCC1
4
GND1
11 3 1
NC GND GND
+5V_US
1
0.1U_s A
C603 6800P_s SEE OPTION TABLE 1
A
1 T600 6 +5V_US
C604
2
0.1U_s
3
SEE OPTION TABLE 1
A
C600 1000P_s UPSTREAM
4 458pt_1087 463131-001
C601 0.1U_s A A 1
+5V_US
C607 0.01U_s
1
8 7 6 5
C606 0.01U_s
C605 0.01U_s 2
L610 10uH_c_1008
33_4_S C610 0.1U_s
1
+5V
US_CTL_CSB US_CTL_DATA US_CTL_CLK
1 2 3 4
1
A
2
A SEE OPTION TABLE 1
1
RP600
2
Anadigics ARA2018 Sanyo LA7791T Microtune MT1530
C558 10U_c
A
D
2
467639-001 6.3V X5R 1206
2
C563
2
C564
1
Place these parts near QUAKE.
A
DNI
A
+ C617 470u_10v
San Diego, California, U.S.A.
2
TUNER_UPSTREAM.SCH Document Number 864684-049
A
B
C
D
Rev A
File Name
Date: Friday, September 26, 2003 A
Taipei, Taiwan R.O.C.
Title
Sheet E
14
of
14
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