CST131 Tutorial3 usm

School of Computer Sciences Universiti Sains Malaysia CST131 – Computer Organisation Academic Session 2014/2015 Semester 1

TUTORIAL 3 (Answer) Computer Arithmetic 1.

Briefly explain the following representations: sign magnitude and twos complement. Sign–Magnitude Representation: In an N-bit word, the left-most bit is the sign (0 = positive, 1 = negative) and the remaining N – 1 bits comprise the magnitude of the number. Twos Complement Representation: A positive integer is represented as in sign magnitude. A negative number is represented by taking the Boolean complement of each bit of the corresponding positive number, then adding 1 to the resulting bit pattern viewed as an unsigned integer.

2.

What is the difference between the twos complement representation of a number and the twos complement of a number? The twos complement representation of a number is the bit pattern used to represent an integer. The twos complement of a number is the operation that computes the negation of a number in twos complement representation.

3. If we treat 2 twos complement numbers as unsigned integers for purposes of addition, the result is correct if interpreted as a twos complement number. This is not true for multiplication. Why? The algorithm for performing twos complement addition involves simply adding the two numbers in the same way as for ordinary addition for unsigned numbers, with a test for overflow. For multiplication, if we treat the bit patterns as unsigned numbers, their magnitude is different from the twos complement versions and so the magnitude of the result will be different.

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4.

Explain Booth’s algorithm for twos complement multiplication.

=01

=10 Q0, Q-1

A=A+M

A=A-M Arithmetic Shift Right: A Q, Q-1 count =count -1

NO

count=0?

YES END The multiplier and multiplicand are placed in the Q and M registers, respectively. There is also a 1-bit register placed logically to the right of the least significant bit (Q0) of the Q register and designated Q-1; its use is explained shortly. The results of the multiplication will appear in the A and Q registers. A and Q-1 are initialized to 0. As before, control logic scans the bits of the multiplier one at a time. Now, as each bit is examined, the bit to its right is also examined. If the two bits are the same (1–1 or 0–0), then all of the bits of the A, Q, and Q -1 registers are shifted to the right 1 bit. If the two bits differ, then the multiplicand is added to or subtracted from the A register, depending on whether the two bits are 0–1 or 1–0. Following the addition or subtraction, the right shift occurs. In either case, the right shift is such that the leftmost bit of A, namely A n-1 not only is shifted into An-2, but also remains in An-1. This is required to preserve the sign of the number in A and Q. It is known as an arithmetic shift, because it preserves the sign bit.

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5. Is the following a valid alternative definition of overflow in twos complement arithmetic? ‘If the exclusive-OR of the carry bits into and out of the leftmost column is 1, then there is an overflow condition. Otherwise, there is not.’ The overflow rule was stated as follows: If two numbers are added, and they are either both positive or both negative, then overflow occurs if and only if the result has the opposite sign. There are four cases:  Both numbers positive (sign bit = 0) and no carry into the leftmost bit position: There is no carry out of the leftmost bit position, so the XOR is 0. The result has a sign bit = 0, so there is no overflow.  Both numbers positive and a carry into the leftmost bit position: There is no carry out of the leftmost position, so the XOR is 1. The result has a sign bit = 1, so there is overflow.  Both numbers negative and no carry into the leftmost position: There is a carry out of the leftmost position, so the XOR is 1. The result has a sign bit of 0, so there is overflow.  Both numbers negative and a carry into the leftmost position. There is a carry out of the leftmost position, so the XOR is 0. The result has a sign bit of 1, so there is no overflow. Therefore, the XOR result always agrees with the presence or absence of overflow.

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6. Multiply -13 by -5 using Booth’s algorithm for twos complement multiplication. Each number is represented using 5 bits. M = -13 = 10011; Q = -5 = 11011;

+13 = 01101 +5 = 00101

A Q 00000 11011 (-5) 00000 01101 -(-13) = +13 01101 11011 00110 11101

Q-1 0

00011 01110 00011 10011 +(-13) 10110 01110 11011 00111 11011 01101 -(-13) = +13 01000 00111 00100 00011

1

00010

1

00001

M 10011 (-13)

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Remarks Initial values CYCLE 1 A = A – M (“10” @ Q0, Q-1) Shift A, Q, Q-1 to the right CYCLE 2 Shift (“11” @ Q0, Q-1) CYCLE 3 A = A + M (“01” @ Q0, Q-1)

0

Shift CYCLE 4 A = A – M (“10” @ Q0, Q-1)

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Shift A, Q, Q-1 to the right CYCLE 5 Shift (“11” @ Q0, Q-1)

A, Q = 00010 00001 = 65

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7. Use the Booth algorithm to multiply 25 by 30, where each number is represented using 6 bits. M = 25 = 011001; -25 = 100111 Q = 30 = 011110 A Q 000000 011110 000000 000000 001111 000000 100111 –(25) = -25 100111 001111 110011 100111

Q-1 0

111001

110011

1

111100

111001

1

111110 111110 011001 +25 010111 001011

011100

1

011100 101110

0

M 011001

0

1

Remarks Initial Values Cycle 1 Shift (“00” @ Q0, Q-1) Cycle 2 A = A – M (“10” @ Q0, Q-1 Shift A, Q, Q-1 to the right Cycle 3 Shift (“11” @ Q0, Q-1) Cycle 4 Shift (“11” @ Q0, Q-1) Cycle 5 Shift (“11” @ Q0, Q-1) Cycle 6 A = A + M (“01” @ Q0, Q-1) Shift A, Q, Q-1 to the right

A, Q = 001011 101110 = 750

- oooOooo -

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