Course Syllabus

June 14, 2019 | Author: Jaime Luis Estanislao Honrado | Category: Cmos, Very Large Scale Integration, Mosfet, Electronic Circuits, Semiconductor Devices
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Course Number:

CIE 130

Department/Program: Department/Program: ECCE Semester:


Title: Principles of VLSI with HDL School: Science and Engineering

School Year: 2011-2012

Instructor: Dr. Rosula S.J. Reyes

A. COURSE DESCRIPTION The course is an introduction to design, layout, and testing of Very Large Scale Integrated (VLSI) circuits for complex digital systems. The focus will be on the fundamentals of the VLSI fabrication process that will introduce the students to the fabrication method, circuits, logic design, architecture, and design tools. The course will also introduce the students to the VLSI system-on-chip (SOC) structured design and design verification topics and techniques. B. COURSE OBJECTIVES The objective of this course is to introduce the students to the concepts in digital VLSI circuits. The course also aims to provide students with the knowledge required to design, implement, and test digital VLSI circuits through nMOS, pMOS, and CMOS technologies and to integrate those VLSI circuits in complex digital systems. Upon completion of this course, the students should demonstrate the ability to: 1. Understand the VLSI fabrication and its impact on the VLSI design process. 2. Understand the VLSI testing process and design for testability techniques. 3. Understand the level of abstraction in the design and verification of VLSI system. 4. Understand the use of various Computer-Aided Design (CAD) tools for design.

C. COURSE OUTLINE 1. Introduction to VLSI Design Moore’s Law

Design Levels of Abstraction Logic to transistor Level Translation Survey of Silicon Semiconductor Technology Bipolar, CMOS, Bi-CMOS, Ga-As Technology 2. CMOS Fabrication and Processing Technology Crystal Growth; Water Preparation; Oxidation; Diffusion, Ion Implantation NMOS, CMOS technologies; Layout Design Rules 3. Circuit Characterization and Performance Estimation Introduction  – Review of MOS Transistor Theory

Transistor Physics  – Accumulation, Depletion, Inversion Threshold Voltage; V-I Characteristics; Body Effect Noise Margin; Latch-up; Resistance; Switching Characteristics Power Consumption; Yield; Scaling of MOS Transistor Dimensions 4. Current Trends of VLSI system-on-a-chip 5. Hardware/Software Co-simulation

D. TIMEFRAME 13 June 2011 Orientation; Introduction to Chip Fabrication 20 June 2011 No classes - Submission of Assignment 1- to be submitted on June 21, 2011 27 June 2011 Introduction to MOS Technology 27 June 2011 Basic Electrical Properties of MOS circuits (Part I) Submission of Assignment 2 and Presentation of Assignment 2 ( by draw lots, everyone 4 July 2011 must be ready to present) 11 July 2011 Basic Electrical Properties of MOS circuits (P art II) 18 July 2011 Long Quiz No. 1 25 July 2011 MOS Circuit Design Processes 1 August 2011 Submission of Assignment 3 and Presentation of Exercise 1 8 August 2011 No classes 15 August 2011 Submission and Presentation of Exercise 1 22 August 2011 Submission and Presentation of Exercise 2 29 August 2011 Presentation on Synopsis 5 September 2011 Long Quiz No. 2 12 September 2011 Submission and Presentation of Exercise 3 19 September 2011 Submission and Presentation of Exercise 4 26 September 2011 Submission and Presentation of Exercise 5 TBA Final-Hands-On Exam or Final Term Project

E. REQUIRED READING 1. Principles of CMOS VLSI Design: A System Perspective By Neil H.E. Weste and Kamran Eshragihan 2. Introduction to VLSI circuits and Systems, 2002, John P. Uyemura, 

F. SUGGESTED READINGS 1. Basic VLSI Design: Systems and Circuits (Supplementary Reading) By Douglas A. Pucknell, Kamran Eshraghian 2. CMOS VLSI Microelectronics By Stanley Hurst

3. Design of VLSI System  – A Practical Introduction By L.M. Brakenbury 4. Introduction to NMOS and CMOS VLSI System Design By A. Mukherjee 5. VLSI Technology By S.M. Sze 6. Microchip Fabrication By P.V. Zant

G. COURSE REQUIREMENTS 1. Assignment 1: Current Trends in VLSI 2. Assignment 2: Graphical Design Systems (GDS), CalTech Intermediate Format (CIF), SPICEs (LTSPICE, HSPICE) 3. Assignment 3: Stick Diagram 4. Exercise 1: MOSFET Characteristics 5. Exercise 2: DC Characterization and Sizing of Inverters 6. Exercise 3: Standard Cell Layout and Characterization 7. Exercise 4: Long-channel Device Layout Skill 8. Exercise 5: Two Phase Clock Generator 9. Long Quiz #1 10. Long Quiz #2 11. Final Exams or Project

H. GRADING SYSTEM Long Quiz#1 (Written and Close Books and Notes) 15% Assignments and Exercises Reports 30% Long Quiz#2 (Written and Open Books and Notes) Final-Hands-On Exam or Final Term Project 20% Class participation and attendance 10% Equivalent Grade A 92 – 100 A87 – 91+ I.

B+ B

81 – 86+ 76 – 80+

CLASSROOM POLICIES Strictly follow attendance policy  – maximum of 11 absence

J. CONSULTATION HOURS M-W: 1:30-2:30 Th : 1:30-2:30


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