Computer Architecture-CS2071 I Unit Notes

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CS2071_Computer Architecture

I.INTRODUCTION TO COMPUTER ARCHITECTURE 1. Why we study computer architecture? The purposes of studying architecture are  To gain knowledge about designing / building a new computer  To gain knowledge about designing / building a new version of computer  To improve software performance  To find solution with embedded computer system

 To purchase a new computer 2. History of computer Processor technology

Memory innovations

I/O devices introduced

Dominant look & fell

0 (1600s)

(Electro)- mechanical

Wheel, card

Lever, dial, punched card

Factory equipment

1 (1950s)

Vacuum tube

Magnetic drum

Paper tape, magnetic tape

Hall-size cabinet

2 (1960s)

Transistor

Magnetic core

Drum, printer

Room-size mainframe

3 (1970s)

SSI/MSI

RAM/ROM chip

Disk, keyboard, video monitor

Desk-size mini

4 (1980s)

LSI/VLSI

SRAM/DRAM

Network, CD, mouse

Desktop/ laptop

5 (1990s)

ULSI,SOC(system on chip)

SDRAM, flash

Sensor/actuator, point/click

Invisible, embedded

Present

Artificial intelligence

Parallel computing, biometrics

Moore’s Law:

  

Moore’s law gives the exponential increase in number of devices on a chip over years. There is an annual increase of 60%. i.e., 1.6 devices per year. Therefore 8 devices for every 5 years.

TIPS

Tb

Processor 1.6 / yr 2 / 18 mos 10 / 5 yrs

Processor performa nce



Memory

GIPS

80486

R10000 Pentium II Pentium 256Mb 68040 64Mb

Gb 1Gb

16Mb 80386 68000 MIPS 80286

4Mb 1Mb

Mb 4 / 3 yrs

256kb 64kb

kIPS 1980

2000

1990

Calendar year

2

CS2071_Computer Architecture

kb 2010

Memory chip capacity

Generation

3.

Basic units of a digital computer: Memory

The six main units of a digital computer 1. Input unit Arithmetic & logic unit 2. CPU (central processing unit) 3. Data path & Control 4. Memory system 5. Link (bus structure) 6. Output unit

}

Control

Processor

Input

Link

Datapath

CPU

Input/Output Output

To/from network

I/O

Fig.1. Basic units of a digital computer

4. COMPUTER LEVEL HIERARCHY & COMPUTER SYSTEM ENGINEERING 4. a. Computer level hierarchy: | Software | | Hardware |

Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 Level 0

user High level language Assembly language System software Machine Control Digital logic

Executable programs, software (.exe) C, C++, java, …. Assembly code OS, library codes ISA, instructions Hardwired control, microwired Circuits, gates. etc,..

4. b. Computer system engineering:

H ig h le ve l v ie w

C o m p u t e r o r g a n iz a tio n

Circuit designer

Logic designer

C o m p u t e r a rc h i t e c tu r e

Electronic components

H a rd w a re

Computer designer

System designer

Applicati on designer

Applicati on domai ns

S o ftw a r e

Low le ve l v ie w

Fig.2. Computer system engineering

4. c. Methods used to improve system performance. The methods used to improve system performance are 1. Processor clock 2. Basic Performance Equation 3. Pipelining 4. Clock rate 5. Instruction set 6. Compiler

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CS2071_Computer Architecture

5. COMPUTER ARCHITECTURE & COMPUTER ORGANIZATION Computer organization:  Computer organization deals with operational units and interconnections that realize computer architectural specifications.  Architectural specifications refers to control signal, interface between computers, interface between CPU, memory, input/output peripherals.  Microarchitecture, also known as Computer organization is a lower level, a detailed description of the system that is sufficient for completely describing the operation of all parts of the computing system, and how they are inter-connected and inter-operate in order to implement the ISA.

Computer architecture:  Computer Architecture is an area of study that deals with the computer at the interface between hardware and software.  Computer Architecture deals with the structure and behavior of a computer including the information formats.  Computer Architecture encompasses a set of ideas that are applicable to design or understand any computer virtually from tiniest embedded microprocessors to most powerful supercomputers  Computer architecture is more hardware oriented than computer systems.

6. VON NEUMANN ARCHITECTURE AC - Accumulator MQ – multiplier quotient MBR (DR) – memory buffer register / data register IBR – instruction buffer register PC – program counter IR – instruction register MAR (AR) – memory address register

Fig.3. Expanded model of von Neumann architecture or IAS (Institute For Advance Studies) computer

AC & MQ – registers for temporary storage for operand and results DR – holds the data o be written / read from addressed word of main memory PC – To monitor the sequence of instruction execution To store the address of next instruction to be executed IBR – holds the instruction that is to be executed next IR – holds the instruction that is currently executed MAR (AR) – holds the address of the main memory to / from which data is to be transferred. Control signals – to fetch the instruction, decode the opcode, routing information correctly

7. MIPS ARCHITECTURE & MEMORY AND PROCESSING SUBSYSTEMS FOR MINIMIPS 7. a. MIPS (Microprocessor without Interlocked 

 

Pipeline Stages

)Architecture :

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies (formerly MIPS Computer Systems, Inc.). The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32 and MIPS64 define a control register set as well as the instruction set.

Fig.4.

   



The first commercial MIPS model, the R2000, was announced in 1985. It added multiple-cycle multiply and divide instructions in independent on-chip unit. New instructions were added to retrieve the results from this unit back to the register file and these resultretrieving instructions were interlocked. It had thirty-one 32-bit general purpose registers, but no condition code register. Unlike other registers, the program counter is not directly accessible. The R2000 could be booted either big-endian or little-endian. The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision. MIPSel refers to a MIPS architecture using a little endian byte order. Since almost all MIPS microprocessors have the capability of operating with either little endian or big endian byte order, the term is used only for processors where little endian byte order has been pre-determined.

7. b. MEMORY AND PROCESSING SUBSYSTEMS FOR miniMIPS. ... m 2 32

Loc 0 Loc 4 Loc 8 4 B / location

Memory up to 2 30words

Loc Loc m 8 m 4

... EIU (Main proc.)

$0 $1 $2

$31

ALU

Execution & integer unit

Integer mul/div Hi

FPU (Coproc. 1)

FP arith

$0 $1 $2

Floating point unit

$31

Lo

TMU (Coproc. 0)

Design of mul & divide

BadVaddr Status Cause EPC

Trap & memory unit

Design of floating point ALU Fig. 5. Memory and Processing Subsystems for miniMIPS Execution and integer unit (EIU):  It is the EIU that understand and executes the basic miniMIPS instructions mostly ALU / logic operations.  EIU has 32 general purpose registers, each of which is 32 bits wide and can hold the content of one memory location is shown in fig.6.

Name Register number $zero 0 $v0-$v1 2-3 $a0-$a3 4-7 $t0-$t7 8-15 $s0-$s7 16-23 $t8-$t9 24-25 $gp 28 29 $sp 30 $fp 31 $ra

Usage the constant value 0 values for results and expression evaluation arguments temporaries saved (by callee) more temporaries global pointer stack pointer frame pointer return address

Fig.6. Registers of miniMIPS

7. C. MIPS REGISTERS. (NOTE: REFER FIG.6.) In MIPS, the operands must be registers. • 32 registers are provided • each register stores a 32-bit value • compilers associate variables with registers • registers are referred to by names such as $s0 and $t1 • we use the “s” registers for values that correspond to variables in our programs • we use the “t” registers for temporary values For example, consider this example from the text: f = (g + h) - (i + j); We choose registers to store the values of our variables: f in $s0, g in $s1, h in $s2, i in $s3, and j in $s4. We’ll also need to store temporary values, which we will store in $t0 and $t1. The MIPS code: add $t0, $s1, $s2 Floating point unit (FLU): In computing, floating point describes a method of representing an approximation of a real number in a way that can support a wide range of values. The numbers are, in general, represented approximately to a fixed number of significant digits (the mantissa) and scaled using an exponent. The base for the scaling is normally 2, 10 or 16.  The typical number that can be represented exactly is of the form: Significant digits × baseexponent Example: 152853.5047 = 1.528535047×105 summary: 

MIPS operands Name

Example $s0-$s7, $t0-$t9, $zero, 32 regis ters $a0-$a3, $v0-$v1, $gp, $fp, $sp, $ra, $at Memory[0],

Comments Fast locations f or data. In MIPS, data must be in registers to perf orm arithmetic. MIPS register $zero alw ays equals 0. Register $at is reserved f or the assembler to handle large constants. Accessed only by data transf er instructions. MIPS uses byte addresses, so

230 memory Memory[4], ...,

sequential w ords dif fer by 4. Memory holds data structures, such as arrays,

words

and spilled registers, such as those saved on procedure calls.

Memory[4294967292]

8. DATA SIZE AND DATA TYPES: Data size In miniMIPS, there are 3 datasize as follows, 1. Byte –8 bits 2. Word – 4 bytes (32 bits) 3. Double word – 8 bytes (64 bits) word  In computer architecture, word can be defined as a 32-bit data element stored in a register or memory location with an address.  A word is a unit of data of a defined bit length (32 bit in miniMIPS) that can be addressed and moved between storage and the computer processor. A word can hold  Instruction  Signed integer  Unsigned integer  Floating point number  Strings of ASCII characters ord length  Word length is defined as the total number of bits used to represent. In general 1 word equals 32 bits.  Usually, the defined bit length of a word is equivalent to the width of the computer's data bus so that a word can be moved in a single operation from storage to a processor register.  For any computer architecture with an eight-bit byte, the word will be some multiple of eight bits. 7

CS2071_Computer Architecture

Byte Addressability: Byte Addressability is used for assigning successive memory address to successive memory location. This type of assigning is used in modern computers. One byte=8 bits. Example:32bits Address:0,4,8.... Bid-Endian format The name big-Endian is used when lower byte addresses are used for the most significant bytes (the left most bytes) of the word. (most significant byte has lowest address) Little Endian format The name little-Endian is used when lower byte addresses are used for the less significant bytes (the right most bytes) of the word. (Least significant byte has lowest address) Data types

Example: Type

S.no. 1 2 3 4

Data types Signed integer Unsigned integer Floating point number Bit string

     

Datasize word word word doubleword word doubleword

8-bit number Value32-bit version of the number

Unsigned 0010 1011  43  Unsigned 1010 1011 171  Signed Signed

byte byte byte

0010 1011 1010 1011

+43 –85

0000 0000 0000 0000 0000 0000 0010 1011 0000 0000 0000 0000 0000 0000 1010 1011  0000 0000 0000 0000 0000 0000 0010 1011 1111 1111 1111 1111 1111 1111 1010 1011

In miniMIPS, signed integers are represented in 2’s complement format. 7 7 Signed Integer in 8-bit format (values) = [-2 , 2 -1] = [-128, 127] Signed Integer in 32-bit format (values) = [-231, 231-1] In machine representation, sign of signed integer from its most significant bit o 0 for “+” o 1 for “ – “ UnSigned Integer in 8-bit format (values) = [0, 28-1] = [0, 255] UnSigned Integer in 32-bit format (values) = [0, 232-1]

Decimal and hexadecimal constants Decimal 25, 123456, 2873 Hexadecimal 0x59, 0x12b4c6, 0xffff0000 9. MODELS AND ABSTRACTION IN PROGRAMMING (High-level vs. low-level programming) Abstraction: Abstraction is a process by which data and program are defined with a representation similar in form to its meaning.

t e mp= v[ i] v [ i]= v[ i+ 1] v [ i+1 ]= te mp

O n e tas k = m any s t at em ent s

A s se m b ly la ng ua g e instr uc tio ns , m ne m o nic Compiler

Sw ap v[ i ] an d v[i + 1]

H ig h- le ve l la ng ua g e s ta te m e n ts Interpreter

V e ry hig h -le ve l la ng ua g e o b je c tive s o r ta s k s

M ore c onc ret e, m ac hin e-s p ec ific , err o r -p ron e; har der t o w rit e, rea d, debu g, or m ai nt ain

ad d ad d ad d lw lw sw sw jr

O n e s ta tem e nt = s e ver al ins truc t ions

$2 ,$5, $ 5 $2 ,$2, $ 2 $2 ,$4, $ 2 $1 5,0( $ 2) $1 6,4( $ 2) $1 6,0( $ 2) $1 5,4( $ 2) $3 1

Assembler

M o re a bs t rac t , m ac hine -inde pe nde n t; eas ier t o w rit e, r ead, de bu g, o r m a int ai n

M a c hi ne la ng ua g e ins tr uc tio ns , b ina r y ( he x)

00 a5 102 0 00 42 102 0 00 82 102 0 8c 62 000 0 8c f2 000 4 ac f2 000 0 ac 62 000 4 03 e0 000 8

M o s t ly one-t o-on e

Fig.7. Abstraction in programming (High-level vs. low-level programming)

II.INSTRUCTIONS 1. INSTRUCTION FOR miniMIPS AND ITS EXECUTION (example) High -le vel lang uag e s tatem ent:

a = b + c

As sem bly languag e instruc tion:

ad d $t8 , $s2 , $s1

Machine lan gua ge ins truction:

00 000 0 10 010 100 01 1100 0 0 0000 10 0000 A LU-ty pe ins truc tion

Instruction c ache

Register file

P C

Regis ter 17

Regis ter Unus ed

24

A LU $24

Register rea dout

A ddition opc ode

Regis ter file

Data c ache (not us ed ) $17 $18

Instruction fetch

Regis ter 18

Ope ration

Data rea d/s tore

Regis ter writeb ack

Fig.8. A typical instruction for MiniMIPS and steps in its execution

2. INSTRUCTION SET ARCHITECTURE (ISA) & INSTRUCTION SET DESIGN AND EVOLUTION:

Instruction set design: The instruction set attributes are 1. Consistent, with uniform and generally applicable rules 2. Orthogonal, with independent features non-interfering 3. Transparent, with no visible side effect due to implementation details 4. Easy to learn/use (often a byproduct of the three attributes above) 5. Extensible, so as to allow the addition of future capabilities 6. Efficient, in terms of both memory needs and hardware realization

Processor design team

New m achine project

Ins truction-s et definition

Im plem entation

Performance objectives

Fabrication & tes ting

? Tuning & bug fixes Feedback

Fig.9. Processor design and implementation process

Sales & use

INSTRUCTION SET ARCHITECTURE (ISA):   



   

Instruction is a word/ language easily interpreted by machine/hardware Instructions are the language of the machine An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor

Combination of instruction set, parts of machine, its functionality will produce correct, compact, fast programs. The instruction set / instruction set architecture we are going to discuss is instruction set of miniMIPS Mini- minimal, MIPS – microprocessor without interlocked pipeline stages. Registers, memory location (data storage), machine instruction are concerned by the complier and assembly programmer.

 Instruction set design goals:  To maximize performance  To minimize cost  To reduce design time  Machine instruction: Machine instruction typically contains  an opcode  one or more source operands  possibly a destination operand Opcode:    Operand   

An opcode (operational code) is a binary code or bit pattern that defines an operation. An opcode (operation code) is the portion of a machine language instruction that specifies the operation to be performed. Example: opcode for Addition operation is 32  100010 in binary In computer programming languages, the definitions of operator and operand are almost the same. In computing, an operand is the part of a computer instruction which specifies what data is to be manipulated or operated on, whilst at the same time representing the data itself. In assembly language, an operand is a value (an argument) on which the instruction, named by mnemonic, operates. The operand may be a processor register, a memory address, a literal constant, or a label.

MiniMIPS add & subtract instructions; e.g., compute: g = (b + c) (e + f) add $t8,$s2,$s3 # put the sum b + c in $t8 add $t9,$s5,$s6 # put the sum e + f in $t9 sub $s7,$t8,$t9 # set g to ($t8) ($t9) Classification of instruction types. Computer must have instructions capable of performing four types of operations 1. Data transfer between memory and processor (Load & Store) 2. Arithmetic and logic operations (Integer, Floating Point, logical operations) 3. Program sequencing and control (Jump, Conditional Branch, Call & Return) 4. Input / output transfer (move, copy, read, write)

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CS2071_Computer Architecture

Classification of instruction sets.  A complex instruction set computer (CISC) has many specialized instructions, which may only be rarely used in practical programs.  A reduced instruction set computer (RISC) simplifies the processor by only implementing instructions that are frequently used in programs; unusual operations are implemented as subroutines, where the extra processor execution time is offset by their rare use.  Theoretically important types are the minimal instruction set computer (MISC) and the one instruction set computer (IISC) but these are not implemented in commercial processors.  Another variation is the very long instruction word (VLIW) where the processor receives many instructions encoded and retrieved in one instruction word. Features of RISC architecture  Small set of instructions, each of which can be executed in approximately same amount of time.  Load/Store architecture  Limited addressing modes that eliminate or speed up address calculations.  Simple, uniform instruction formats that facilitate extraction/decoding of various fields and allow overlap between opcode interpretation and register readout. Advantages of CISC architecture  Economy in the number of instructions used translates to smaller storage space requirements,  Fewer memory accesses and more effective use of cache space.  Closer correspondence between machine instructions and operations commonly found in high level languages  Facilitate program compilation, understanding, troubleshooting and modification. Disadvantages of CISC architecture  Complex instruction sets are undesirable because inclusion of mechanisms to interpret all the possible combinations of opcodes and operands might slow down even very simple operations.  Will be rarely used  Makes instruction set more complex.

3. miniMIPS INSTRUCTION FORMATS.  Simplicity and uniformity of instruction formats is common in modern RISC designs that aim to execute the most commonly used operations as fast as possible at less expense.  There are 3 instruction formats in miniMIPS. They are  Register  Immediate  Jump

Fig.10. Instruction formats

 3.1 REGISTER INSTRUCTION FORMAT in miniMIPS: 31

R

op

25

rs

rt

20

6 bits

5 bits

5 bits

Opcode

Source register 1

Source register 2

sh

rd

15

fn

10

5 bits Destination register

5

0

5 bits

6 bits

Shift amount

Opcode extension

Register instruction format is of 32 bits long that is divided into 6 fields Field No. of bits naming usage 1 6 fn Opcode extension 2 5 sh Shift amount 3 5 rd Destination register Result is stored 4 5 rt Source register 2 Input data 5 5 rs Source register 1 Input data 6 6 op opcode Operational code will be specified. Opcode for ADD – 32 - (100000) Fn- (Opcode extension) function field serves as an extension of opcode, to allow more than one operations to be defined. Sh – (Shift amount) field is used in instructions that specify a constant shift amount Example: sll $t0, $s1, 2 ---- this value 2 will be specified in “sh” field $to = ($s1) left –shifted by 2  3.2 IMMEDIATE INSTRUCTION FORMAT in miniMIPS: op 31

I

rs 25

rt 20

operand / offset 15

0

6 bits

5 bits

5 bits

16 bits

Opcode

Source or base

Destination or data

Immediate operand or address offset

Immediate instruction format is of 32 bits long that is divided into 4 fields Field No. of bits naming usage 1 16 Operand /offset Immediate operand or address offset 2 5 rt Source register 2 Result is stored (data) 3 5 rs Source / base register Input data 4 6 op opcode Operational code will be specified. Opcode for addi = 8  (001000) Opcode for Load (lw) = 35  Used in both Arithmetic and logic instructions and also for load/store operations  Operand /offset field o When used as immediate operand:  Holds an integer that is constant throughout the operation  Works same as rt in register format  Example: addi t0, s0, 61 (to = rt, s0 = rs and Operand = 61) Therefore, t0 = (s0) + 61  Operand field is only 16 bits long. So the valid range is (-32768 to 32767) for signed integer and [0 x 0000, 0x ffff] for hexadecimal contants o When used as offset:  In load, store, branch instructions 16 bit field (offset) is added to base value in “rs” to get memory address for read/write (transfer of control)  For branch instructions, offset work as “word”, instructions always occupy 32-bits memory  For data access, offset is used as  Number of bytes forward (positive) relative to base address  Number of bytes backward (negative) relative to base address  Data (rt) field : o Acts as data destination for load operation

 3.3 JUMP INSTRUCTION FORMAT in miniMIPS: 31

J

op

25

6 bits Opcode

Field 1

4



jump target address

0

1 0 0 0 0 0 0 0 0 0 0 0260 bits 0 0 0 0 0 0 0 1 1 1 1 0 1 Memory word address (byte address divided by 4)

jump instruction format is of 32 bits long that is divided into 2 fields No. of bits naming usage 26 Jump For memory word target address address 6 op opcode Operational code will be specified. Opcode for ADD – 32 - (100000) Jump target address o For unconditional transfer of control to instructions in specified address o Only 26 bits are available in address field o Used to carry a word address as opposed to a byte address

4.INSTRUCTION TYPES Classification of instruction types: Computer must have instructions capable of performing four types of operations 1. Data transfer between memory and processor (load and store instructions) 2. Arithmetic and logic operations 3. Program sequencing and control (jump and branching instructions) 4. Input / output transfer SIMPLE ARITHMETIC AND LOGIC INSTRUCTIONS: ARITHMETIC INSTRUCTIONS:  Arithmetic instructions follow R-format and I-format instruction.  The arithmetic instructions ADD and SUB have a format that is common to all two-operand ALU instructions. For these, the fn field specifies the arithmetic/logic operation to be performed. add $t0,$s0,$s1 sub $t0,$s0,$s1

# set $t0 = ($s0)+($s1) # set $t0 = ($s0)-($s1) R

op 31

rs 25

31

# set $t0 to ($s0)+61 I

op

 

sh 10

fn 5

0

S ou rc e reg is te r 1

25

rs

S o u rc e re g is te r 2

20

rt

D e s tin at io n re g is te r

15

Un u s e d

add = 32 s ub = 3 4

o p e ra n d / o ffs et

0

0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 addi = 8



rd 15

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 x 0 A LU in s tru c tio n

addi $t0,$s0,61

rt 20

S ourc e

D es tinat ion

Im m ediat e o pe ran d

Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small constant o When used as immediate operand:  Holds an integer that is constant throughout the operation  Works same as rt in register format  Example: addi t0, s0, 61 (to = rt, s0 = rs and Operand = 61), Therefore, t0 = (s0) + 61  Operand field is only 16 bits long.  So the valid range is (-32768 to 32767) for signed integer and  [0 x 0000, 0x ffff] for hexadecimal contants There is no SUBI instructions, but it can be accomplished by adding a negative value. miniMIPS has a 32-bit adder and all inputs should be 32 bit long. So, the 16-bit immediate operand must be converted to 32-bit value before it is given as input to adder. This is done by SE (sign extenion) by taking 2’s

Multiply & Divide instruction: Multiply Divide op

31

R

mult rs,rt - (rs)*(rt) = Hi, Lo div rs,rt - (rs)/(rt) = Hi, Lo rs

25

rt

20

rd

15

sh 10

fn 5

0

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 x 0 ALU instruction

Source register 1

Source register 2

Unused

Unused

mult = 24 di v = 26

mfhi and mflo instructions: MiniMIPS instructions for copying the contents of Hi and Lo registers into general registers op rs rt rd sh fn 31

R

25

20

15

10

5

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 x 0 ALU instruction

Unused

Unused

Destination register

Unused

mfhi = 16 mflo = 18

LOGIC INSTRUCTIONS:  Logic instructions operate on a pair of operands on a bit-by-bit basis  The key difference between andi, ori, xori and addi is that 16-bit operand of a logical instruction is 0extended from left to turn it into 32-bit format for processing. # set $t0 = ($s0)^($s1) and $t0,$s0,$s1 # set $t0 = ($s0)˅($s1) or $t0,$s0,$s1 # set $t0= ($s0) ($s1) xor $t0,$s0,$s1 # set $t0 = (($s0) ˅($s1))’ nor $t0,$s0,$s1 _ _ _ _ _ _ _ andi $t0,$s0,61 # set $t0 to ($s0)61 ori $t0,$s0,61 # set $t0 to ($s0)61 xori $t0,$s0,0x00ff # set $t0 to ($s0) 0x00ff

_

_

LOGICAL SHIFTS: MiniMIPS instructions for left and right shifting: sll $t0,$s1,2 srl $t0,$s1,2 sllv $t0,$s1,$s0 srlv $t0,$s1,$s0 31

R

op

25

rs

20

rt

15

rd

sh 10

fn 5

0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 x 0 ALU instruction

31

R

# $t0=($s1) left-shifted by 2 # $t0=($s1) right-shifted by 2 # $t0=($s1) left-shifted by ($s0) # $t0=($s1) right-shifted by ($s0)

op

Unused

25

rs

Source register

20

rt

Destination register

15

Shift amount

rd

sll = 0 srl = 2

sh 10

fn 5

0

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 x 0 ALU instruction

Amount register

Source register

Destination register

Unused

sllv = 4 srl v = 6

LOAD AND STORE INSTRUCTIONS:  

  

Load and store instructions follow I format Instructions that carry out data transfer between memory and processor (load and store instructions) o load instructions - data transfer from memory to processor o store instructions - data transfer from processor to memory Load and store instructions transfer whole word (32 bit) between memory and processor Each instruction specifies a register and a memory address. op rs rt operand / offset Example: lw $t0,40($s3) 31 25 20 15

I

0

1 0 x 0 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 lw = 35 sw = 43

Base register

Data register

Offset rel ati ve to base Note on base and offset:

Memory Address in base register

A[0] A[1] A[2] . . .

Offset = 4i Element i of a rray A

A[i]



The memory address is the sum of (rs ) an d an imm ediate value. Calling one of these the base and the other the offset is quite arbitrary. It would m ake pe rfect sense to interpret the address A($s3) as having the base A and the offset ($s3). Howeve r, a 16-bit base confines us to a small portion of m emory space.

Data (rt) field  $t0 register: o Acts as data destination for load operation o Acts as data source for store operation lw $t0,40($s3) sw $t0,A($s3)

# load mem[40+($s3)] in $t0 # store ($t0) in mem[A+($s3)] -- “($s3)” means “content of $s3”



For memory address: o Memory address is obtained by adding 16-bit signed integer (constant offset) and the base value in register “rs” . i.e., by adding 40 and content of $S3 we get the memory address.



To load the constant value: o If constant is small (< = 16 bit)  That can represented by 16-bit or less  Can be loaded into register by using “addi” instruction  The first operand is the constant value  The second operand is $zero register (1st register in 32 genral purpose registers of miniMIPS) o If constant is large (> 16 bit)  That can be represented by 32 bits  32 = 16 + 16  Upper half bit is added by lui instruction  Lower half bit is added by ori instruction MiniMIPS lw and sw instructions and their memory addressing convention that allows for simple access to array elements via a base address and an offset



lui $s0,61

# The immediate value 61 is loaded in upper half of $s0 with lower 16 bit set to 0’s op 31

I

rs 25

rt 20

operand / offset 15

0

0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 lui = 15

Unused

Destination

Imm ediate operand

0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

 o o

Load and store instructions for byte-size data elements. Bytes can be used to store ASCII characters or small integers. MiniMIPS addresses refer to bytes, but registers hold words. lb $t0,8($s3) # load rt with mem[8+($s3)] and sign-extend to fill reg lbu $t0,8($s3) # load rt with mem[8+($s3)] and zero-extend to fill reg sb $t0,A($s3) # LSB of rt to mem[A+($s3)]

op

31

I

rs

25

rt

20

immediate / offset

15

0

1 0 x x 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 lb = 32 lbu = 36 sb = 40

Base register

Address offset

Data register

JUMP AND BRANCH INSTRUCTIONS: 

Jump and Branch Instructions follow J, I, R format j verify # go to memory location named “verify”



The jump instruction causes program execution to proceed from the location whose numeric or symbolic address is provided, instead of continuing with the next instruction in sequence For the jump instruction, 26-bit address field in instruction is augmented with 00 to the right and 4 highorder bits of program counter (PC) to left to form a complete 32-bit address.



op

jump target address

31

J

25

0 0 0 0 1 0

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1

j= 2

x x x x 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 From PC

Effecti ve tar get address (32 bits)

# go to address that is in $ra; # $ra may hold a return address Jump register (jr) instruction specifies a register ($ra) as holding the jump target address. jr $ra is used to effect a return from a procedure to point from which the procedure is called. Follows R-instruction format op rs rt rd sh fn jr $ra

  

31

R

25

20

15

10

5

0

0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 ALU instruction

Source regis ter

Unus e d

Unus e d

Unuse d

jr = 8

 BRANCH INSTRUCTIONS:  Conditional branch instructions allow us to transfer control to given address when a condition of interest is met.  bltz $s1,L # branch on ($s1)< 0 (branch when less than zero) 31

I

op

25

20

rt

15

operand / offset

0

0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 bltz = 1

beq $s1,$s2,L bne $s1,$s2,L 31

I

rs

Source

Zero

Relative branch distance in words

# branch on ($s1)=($s2) (branch when equal) # branch on ($s1)($s2) (branch when not equal) op rs rt operand / offset 25

20

15

0

0 0 0 1 0 x 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 beq = 4

Source 1

Source 2

Relative branch distance in words

 slt $s1,$s2,$s3

# if ($s2)