PRIYANKA PANCHAL
Unit I COMPUTER ARCHITECTURE AND ORGANIZATION
CONTACT :
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B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Unit 1: Register Transfer And Micro Operations: Register Transfer Language, Register transfer Bus and Memory transfer, Arithmetic Micro-operations,
Micro-operations, Logic Micro-operations, Micro-operations, Shift Micro-operations,
Arithmetic Logic Shift Unit.
Computer Organization:
Computer Organization is concerned with the way the hardware components operate and the way they are connected together to form the computer system. Computer Architecture:
Computer architecture is concerned with the structure and behavior of the computer as seen by the user. It includes the information format, instruction set, and technique for addressing memory. The architecture design of a computer system is concern with the specification of the various function modules, such as processors and memories, and structuring them together into a computer system . Register
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A register is a group of flip-flop with each flip-flop capable of storing one bit of information. information. An n-bit register has a group of n flip-flops & is capable of storing any binary information of n-bits. In addition to the flip flops, a register may have combinational gates that perform certain data processing tasks. “Register consists of group of flip -flops and gates that effect their transition. The flip-flops hold the binary information and gates control when and how new information is transferred into register.” The individual flip-flops in an n-bit register are numbered in sequence from 0 through n-1, starting from 0 in the rightmost position & increasing the numbers towards the left. Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
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B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Register Transfer Language
A digital system is an interconnection of digital hardware modules that accomplish specific information-processing task. Digital systems are built from modules that are built from components such as registers, decoders, arithmetic elements and control logic. Those modules are connected with control and data paths. Digital modules are best defined by registers they contain and operations they perform on stored data. Micro operations: the operations executed on data stored in registers. An elementary operation performed in information stored in register(s). Examples of micro operations: shift, count, clear, increment, and load
But also it is interesting to know that the internal hardware organization of a digital computer is best defined by: Registers it contains and their functions Sequence of micro operations performed on data inside registers Control that ignites the sequence of micro operations It is time now to agree on a terminology to describe the sequence of transfer between registers and arithmetic and logical operations associated with those transfers. RTL (Register transfer language): is symbolic notations used to describe micro operation transfer among registers. RTL is a system for expressing in symbolic form the micro operation sequences among registers in a digital module.
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Register Transfer
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Designation of Registers: Registers are designated by capital letters; sometimes followed by numbers to denote the function of a register. Examples will as: o MAR for Memory Address Register o PC for Program Counter o IR for Instruction register o R1 for processor register The individual flip flops in n-bit register is numbered from 0 in right most to n-1 in left most A register can be viewed as a single entity or may also be represented showing the bits of data they contain. Registers can be designated by a whole register, portion of a register, or a bit of a register. Registers and their contents can be viewed and represented in various ways such as shown in next figure:
Register transfer: Register Transfer is defined as copying/transfer the content of one register to another. For register transfers, the data transfer from one register to another is designated in symbolic form by replacement operator R2 R1 Please note that: o In this case the contents of register R2 are copied (loaded) into register R1 o A simultaneous transfer of all bits from the source R1 to the destination register R2, during one clock pulse o Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying (loading) them to R2 4 e g a P
That register transfer also implies that: Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I o
o o
The data lines extend from the source register (R1) to the destination register (R2) with lines equal the bit numbers of R1 and R2. Parallel load occurs in the destination register (R2) Control lines are needed to perform this action
Control Function: We need the transfer to happen under a certain condition by means which looks if-then statement. In digital systems, this is often done via a control signal, called a control function. If the signal is “1” then a ction will take place. See next example for control statement P. P also could be a combination of Boolean variables which yields a single Boolean output. P: R2 R1 Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1) then (R2 R1). Hardware Implementation for control function: Look at next diagram which shows R1 transfer to R2. You will realize that the n outputs of register R1is connected to n input of register R2. Register R2 has a load control activated by P control function and the whole operation is synchronized with the central clock. The rising edge of the CLK input triggers activates P at t time and at t+1 time the transfer takes place.
Block Diagram 5 e g a P
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Timing Diagram
Also we assume that here the registers are comprised of DFF that acts on rising edge clocks.
Simultaneous Operations: If cases where two or more operations are to occur simultaneously, they are separated with commas as shown next: P: R3 R5, MAR IR Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR The basic symbols for register transfer is shown in next table and that summarizes the topic: Symbol Alphanumeric Subscript Parentheses( )
Description Register Names Bit positions in registers Portion/Part of Registers
Left Arrow Colon :
Transfer/Copying of info. Separates control function from expression Separate two Micro-Ops
Comma ,
Example MAR, R2,A A3, B7 MBR(8-15), R2(L) A B P: A B AB, R1R2
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I Bus and Memory Transfer There is a problem if we need to move data from and to multiple registers.
The number of wires will be so large if separate lines are used to connect all registers with each other. To completely connect n registers we need n(n-1) lines. So the cost is in order of O(n2). This is not a realistic approach to be used in a large digital system. The solution is to use a common “Bus”. Instead, take a different approach; have one centralized set of circuits for
data transfer the “bus”. Also have control circuits to select which register is the source, and which is the destination. bus: Bus is a path (of a group of wires) over which Definition of a bus: information is transferred, from any of several sources to any of several destinations. One way of constructing a bus is by using multiplexers. The next diagram shows how this works. The next figure shows how to implement data transfer from register to the bus. BUS R
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I In general, the bus system will multiplex k registers of n bits each to
produce an n-line common bus. o The number of multiplexers need is n o The size of each multiplexer is k X 1 S1 0 0 1 1
S0 Register Selected 0 A 1 B 0 C 1 D Functional Table
Three state table buffers
Another way of constructing a bus is by using buffers or 3-state gates. The next two figures show the buffers in use for constructing a bus system.
The first one shows the graphical symbol for 3-state buffer
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While the next one shows bus system using 4 by one selectors of buffers. A bus system can be constructed with three state gates instead of multiplexers. Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
A three states gate is digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third state is a high-impedance state. The high-impedance state behaves like an open circuit, which means that the output is disconnected and does not have a logic, such as AND or NAND. However the one most commonly used in the design of a bus system is the buffer gate.
Bus Transfer in RTL:
The transfer of information from a bus into one of many destination registers can be accomplished by connecting bus lines to the inputs of all registers and activating load control of selected destination. The symbolic statement for a bus transfer may mention the bus or may be implied in the statement. R2 R1 OR BUS R1, R2 BUS Memory Transfer:
Memory (RAM) can be thought as a sequential circuits containing some number of registers. These registers hold the words of memory. Each of the r registers is indicated by an address. These addresses range from 0 to r-1. Each register (word) can hold n bits of data. Now assume the RAM contains r = 2k words. It needs the following o n data input lines o data output lines o k address lines o A Read control line o A Write control line
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
The memory can be viewed at the register level as a device, M. And since it
contains multiple locations, then we must specify which address in memory we will be using. This is done by indexing memory references. Memory is usually accessed in computer systems by putting the desired address in a special register, the Memory Address Register (MAR, or AR). And when memory is accessed, the contents of the MAR get sent to the memory unit’s address lines.
Operation: when address of required location is transferred into For Read Operation: when
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address register AR then the content is loaded into data register DR. DR M [AR] operation: the content of data register DR is transferred into For Write operation: memory location addressed by address register AR. M [AR] DR Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
micro operation The operations executed on data stored in registers are called micro-
operations. A micro operation is an elementary operation performed with data stored in register. They are classified into: operations : Transfer binary information o Register transfer micro operations: from one register to another. operation: Perform arithmetic operations on o Arithmetic micro operation: numeric data stored in registers. o Logic micro operation: Perform bit manipulation operations on non-numeric data stored in registers. operation: Perform shift operation on data stored in o Shift micro operation: registers.
Arithmetic Micro operation Basic arithmetic micro operations are:
Addition o Subtraction o Increment o Decrement o Arithmetic Shift Short look on different arithmetic micro operations: o The Add micro operation is specified as: R3 R1 + R2. And it means add content of R1 to R2 and store result of addition in R3. Usually it is implemented using hardware full adders. o The Subtraction is usually implemented using complementation and addition o
R3
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R1 + R2 +1
And it means subtract R2 from R1 by adding the complement of R2 plus 1 to R1. Usually it is implemented using a full adder a complement circuit. Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
R2 is the symbol for the 1’s complement of R2. Adding 1 to the 1’s complement produces the 2’s complement. Adding the contents of R1 to the 2’s complement of R2 is equivalent to R1 – R2. The increment and decrement micro-operations are symbolized by plus
one and minus-one operation, respectively. These Increment and decrement micro-operations are implemented with a combinational circuit or with a binary Up and Down Counter. In most computers, multiplication operation is implemented with a
sequence of add & shift micro operations and division is implemented with sequence of subtract & shift micro-operation.
Binary Adder:
To implement binary adder we need registers that holds data and a full adder that performs arithmetic operation between 2 bits and previous carry. The digital circuit that forms the arithmetic sum of two bits and a previous carry is called a full-adder a full-adder . The digital circuit that generates the arithmetic sum of two binary numbers of any lengths is called a binary adder . Binary adders are constructed from full adders connected in cascade. An N-bit binary adder circuit needs N number of full adders.
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
The interconnections of four full-adders (FA) to provide a 4-bit binary adder. The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 to n-1. The carries are connected in a chain through the full adders. The input carry to the binary adders C 0 and the output carry is C4. The S outputs of the full-adders generate the required sum bits. The output carry from each full-adder is connected to the input carry of the next-high-order full-adder. The n data bits for the A inputs come from one register (such as R1), and the n data bits for the B inputs come from another register (such as R2). The sum can be transferred to a third register or to one of the th e source registers (R1 or R2), replacing its previous content.
Binary Adder-Subtractor:
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Subtraction of A – B can be done by taking 2’s complement of B and added to A. The 2’s complement can be done by taking 1’s complement then adding “1” to the result. And finally the 1’s complement is the binary inversion. The addition and subtraction operations can be combined into one common circuit by including Ex-OR with each full adder. By looking at next drawing you will notice that input mode M control addition or subtraction operations. o If M=0 then circuit is an Adder and o If M=1 then circuit is a Subtractor (can you observe why??).
Each exclusive-OR gate receives input M and one of the inputs of B. When M=0, we have B Ex-OR 0 = B o The full-adders receive the value of B, the input carry is 0, and o The circuit performs A plus B. Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
When M=1, we have B Ex-OR 1 =B’ and C0=1 o The B inputs are all complemented and 1 is added through the input carry, and o The circuit performs the operation A plus the 2’s complement of B.
Binary Incrementor:
The binary incrementor is defined as it always adds one to the number in a register. For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is incremented. The incrementor can be implemented in one way by a counter. When clock transition arrives the count is incremented. But in another way the incrementor can be done using half adders. Hardware Implementation: The next drawing shows in hardware an incrementor of 4 bits. It can be extended to n bits easily including n half adders. One of the inputs to the least significant half adder (HA) is connected to logic-1 and the input is connected to the least significant bit of the number to be incremented. The output carry from one half-adder is connected to one of the inputs of the inputs of the next-higher-order half adder. The circuit receives four bits from A 0 to A3, adds one to it, and generates the incremented output in S0 through S3. The output carry C4 will be 1 only after incrementing binary 1111. This also causes output S 0 through S3 to go to 0.
Arithmetic Circuit
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The arithmetic micro operations listed in table 4-4 can be implemented in one composite arithmetic circuit. This circuit comprised of full adders and multiplexers. Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
The multiplexer controls which data is fed into Y input of the adder. The diagram of a 4-bit 4 -bit arithmetic circuit is shown in following diagram. It has four full adder circuits that constitute the 4-bit adder and four multiplexers for choosing different operations. There are two 4-bit inputs A and B and a 4-bits output D.
The output of the binary adder is computed from D = A + Y +Cin The Y input can have one of 4 different values: B, B’, always “1”, or always “0”. The next table shows how this can be implemented.
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Logic Micro-operations Micro-operations Logic micro operation specifies binary operations on the strings of bits in
registers. Logic micro operations are bit-wise operations, i.e., they work on the individual bits of data. Those could be useful for bit manipulations on binary data and also useful for making logical decisions based on the bit value. There are, in principle, 16 different logic functions that can be defined over two binary input variables. However, most systems only implement four of these: AND ( ), OR ( ), XOR ( ), Complement/NOT The others can be created from combination of these. List of Logic Microoperations-16 different logic operations with 2 binary variables are shown next.
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
The hardware implementation of logic micro operation requires the
insertion of the most important gates like AND, OR, EXOR, and NOT for each bit or pair of bits in the registers.
Hardware Implementation: The next figure shows one stage of a circuit that generates the four basic logic micro operations. It consists of four gates and a multiplexer. The two selection lines of the multiplexer selects one of the four logic operations available at one time. The circuit shows one stage for bit “i” but for logic circuit of n bits the circuit should be repeated n times but with one remark; the selection pins will be shared with all stages. 7 1 e g a P
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Applications Of Logic Micro operations operations Logic micro operations can be used to manipulate individual bits or a portions of a word in a register Consider the data in a register A. In another register, B, is bit data that will be used to modify the contents of A Selective-set A A + B Selective-complement
A A B
Selective-clear
A A • B’
Mask (Delete)
AA•B
Clear
A A B
Insert
A (A • B) + C
Compare
A A B
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I o
o
o
o
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Selective-set In a selective set operation, the bit pattern in B is used to set certain bits in A 1100 At 1010 B 1110 At+1 (A A + B) If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps its previous value Selective-complement In a selective complement operation, the bit pattern in B is used to complement certain certain bits in A 1100 At 1010 B 0110 At+1 (A A B) If a bit in B is set to 1, that same position in A gets complemented from its original value, otherwise it is unchanged Selective-clear In a selective clear operation, the bit pattern in B is used to clear certain certain bits in A 1100 At 1010 B 0100 At+1 (A A B’) If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged Mask (Delete) In a mask operation, the bit pattern in B is used to clear certain bits in A 1100 At 1010 B 1000 At+1 (A A B) If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I o
o
Clear
A A B In a clear operation, if the bits in the same position in A and B are the same, they are cleared in A, otherwise they are set in A 1100 At 1010 B 0110 At+1 (A A B) Insert A (A • B) + C An insert operation is used to introduce a specific bit pattern into A register, leaving the other bit positions unchanged This is done as A mask operation to clear the desired bit positions, followed by An OR operation to introduce the new bits into the desired positions Example o Suppose you wanted to introduce 1010 into the low order four bits of A: 1101 1000 1011 0001 A (Original) 1101 1000 1011 1010 A (Desired) 1101 1000 1011 0001 1111 1111 1111 0000 1101 1000 1011 0000 0000 0000 0000 1010 1101 1000 1011 1010
A (Original) Mask A (Intermediate) Added bits A (Desired)
Shift Micro-operations Micro-operations Shift micro-operations are used for serial transfer of data beside they are
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used in conjunction with arithmetic, logic, and other data processing operations. There are 3 types of shift micro operations. What differentiates them is the information that goes into the serial input: o Logical shift o Circular shift o Arithmetic shift Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Logical Shift:
Logical shift is one that transfers 0 through the serial input. In a Register Transfer Language, the following notation is used o shl for a logical shift left o shr for a logical shift right
A
right logical shift operation
A
left logical shift operation:
Examples: R2 R3
shr R2 shl R3
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I Circular Shift:
The circular shift rotates of the register around the two ends without w ithout loss of information. This is accomplished by connecting the two ends of the shift register to each other. the t he following notation is used o cil for a circular shift left o cir for a circular shift right
A right circular shift operation:
A left circular shift operation:
Examples: R2 cir R2 R3 cil R3
Arithmetic Shift:
Arithmetic shift is a micro-operation that shifts a signed binary number to the left or right. Arithmetic shift must leave sign bit unchanged. An arithmetic shift is meant for signed binary numbers (integer) An arithmetic left shift multiplies a signed number by two An arithmetic right shift divides a signed number by two The main distinction of an arithmetic shift is that it must keep the sign of the number the same as it performs the multiplication or division Note that the arithmetic shift right is considered divide by 2 and left shift is considered multiply by 2. A right arithmetic shift operation:
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
A left arithmetic shift operation:
Arithmetic shifts must leave the sign bit unchanged just to preserve the sign of the resulted number. If that case happened then it will be an overflow.
An
left arithmetic shift operation must must be checked for the overflow
An overflow flip flop will be used to detect arithmetic shift left overflow as shown in next figure.
In a RTL, the following notation is used for arithmetic shifts: o ashl for an arithmetic shift left o ashr for an arithmetic shift right
Examples: o R2 o R3
ashr R2 ashl R3
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I Hardware Implementation:
One possible for a shift unit would be bidirectional shift register with parallel load as shown in chapter 2. But another solution can be constructed from multiplexers as shown in next figure.
The figure shows 4 2 by 1 multiplexers with 4 input lines A0 to A3 and 4 output lines H0 to H3. The upper (left) multiplexer can take its inputs from serial in (IR) or A0. The last multiplexer (bottom or right) can take its inputs from A3 or serial input (IL). the single line select will select for shift right or left operations. 4 2 e g a P
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
Arithmetic Logic Shift Unit Instead of having individual registers performing micro-operations
directly, computer systems employ a number of storage registers connected to a unit called Arithmetic Logic Unit (ALU). This unit has 2 operands input ports and one output port and a number of select lines to help in selecting different operations. The ALU is made of combinational circuit so that the entire register transfer operation from the sources to the destination is performed in one clock cycle. The arithmetic, logic, and shift circuits known previously will be combined in one ALU with common selection inputs. One stage (bit) of ALSU with its table is shown in next two figures. As shown the arithmetic and logic units will select their operations simultaneously when S0 and S1 are applied; while S2 and S3 will select one of those unit outputs or a shift left bit stage or shift right bit stage. Note that one stage arithmetic circuit used here is implemented from figure 4.9 and the one stage logic circuit is implemented from figure 4.10. The circuit shown provides 8 arithmetic operations, 4 logic operations, and 2 shift operations.
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
PROBLEMS
1) Show the block diagram of the hardware that implements the following register transfer statement: yT2: R2 ← R1, R1 ← R2 Explain why this can be done in the same clock cycle without using a temp register?
Note: This can be done in the same clock cycle without using a temp register because the registers are edge-triggered flip flop; at the same time the outputs are already on different buses to be the new input for the other register. 2) The outputs of four registers R0, R1, R2 and R3, are connected through 4-to-1-line multiplexers to the inputs of a fifth register R5, each register is 8 bits long. The required transfers are dictated by four timing variables T0 through T3 as follows: T0: R5←R0 T1: R5←R1 T2: R5←R2 T3: R5←R3 The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connections necessary from the four timing variables to the selection inputs of the multiplexers and to the load input of register R5. 7 2 e g a P
The truth table for the outputs:
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I T0
T1
T2
T3
S1
S0
Load
0
0
0
0
X
X
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
1
1
1
Use the “sum of product” technique to get the logic expressions for the selection lines and the load signal: S1 = T2 + T3 S0 = T1 + T3 Load = T0 + T1 + T2 + T3
3) Represent the following conditional control statement by two register transfer statements with control functions. IF (P= =1) then (R1 ← R2) else if (Q= =1) then (R1 ← R3) Solution: P P’Q
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: R1 R2 : R1 R3
4) A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers. a) How many selection inputs are there t here in each multiplexer?
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I b) What size of multiplexers is needed? c) How many multiplexers are the in the bus? Solution: a) 4 selection lines to select one of 16 registers. b) 16 × 1 multiplexers. c) 32 multiplexers, one for each bit of the registers.
5) The following transfer statements specify a memory. Explain the memory operation in each case: a. R2 ← M[AR] b. M[AR] ← R3 c. R5 ← M[R5] Solution: a) Read memory word specified by the address in AR into register R2. b) Write content of register R3 into the memory word specified specified by the address in AR. c) Read memory word specified by the address in R5 and transfer content to R5(destroy previous value). 6) Draw the block diagram for the hardware that implements the following statements: x + yz: AR ← AR + BR Where AR and BR are two n-bit registers and x, y, and z are control variables. Include logic gates for control the function. Solution:
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7) Consider the following register transfer statements for two 4-bit registers R1 and R2. xT: R1←R1+R2 x′T: R1←R2
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I Every time the variable T=1, either the content of R2 is added to the content of R1 if x=1, or the content of R2 is transferred to R1 if x=0. Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two 4bit registers, a 4-bit adder, and a quadruple 2-to-1-line multiplexer that selects the inputs to R1. In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1. Solution:
8) Show the hardware that implements the following statement. Include the logic gates for the control function and a block diagram for the binary counter with a count enable input. xyT0 + T1 + y’T2 : AR AR + 1
9) Design a 4-bit combinational circuit decrementer using 4 full-adder circuits. Solution: 0 3 e g a P
A-1 A-1 = A + 2’s complement of 1 = A + 1111
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
10) Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages.
Solution:
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I
11) Register A holds the 8-bit binary value 11011001. Determine the B operand and the logic micro- operation to be performed in order to change the t he value in A to: a. 01101101 b. 11111101 Solution:
12) The 8-bit registers AR, BR, CR , & DR initially have the following values: AR = 1111 0010 BR = 1111 1111 CR = 1011 1001 DR = 1110 1010 Determine the 8-bit values in each register after the execution of the following sequence of micro-operations. AR ← AR + BR CR ← CR DR, BR ← BR + 1 AR ← AR – AR – CR CR 1.
AR : 1111 0001 0001 2. 2 3 e g a P
AR : 1111 0010 BR : 1111 1111 AR + BR : 1111 0001
BR : 1111 1111 1111
CR : 1011 1001 DR : 1110 1010 CR DR : 1010 1000
CR : 1011 1001 1001
DR : 1110 1010 1010
BR
: 1111 1111 : 1 BR + 1 : 0000 0000
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I AR : 1111 0001 0001
BR : 0000 0000 0000
3.
AR : 0100 1001 1001
CR : 1010 1000 1000
DR : 1110 1010 1010
AR : 1111 0001 CR : 1010 1000 AR - BR : 0100 1001
BR : 0000 0000 0000
CR : 1010 1000 1000
DR : 1110 1010 1010
13) An 8-bit register contains the binary value 10011100. What is the register value after arithmetic shift right? Starting from the initial number 10011100, determine the register value after an arithmetic shift left, and state whether there is an overflow. Solution: R = 10011100 Arithmetic shift right: ri ght: 11001110 Arithmetic shift left: 00111000 overflow because a negative number changed to positive.
14) Starting from an initial value of R = 11010111, determine the sequence of binary values of R after a logical shift left, followed by a circular shift-right, followed by a logical shift right and a circular shift right. Solution: R = 11010111 Logical shift left: 10101110 Circular shift-right: 01010111 Logical shift right: 00101011 Circular shift right: 10010101 15) What is wrong with the following register transfer t ransfer statements? a. XT : AR ← (AR)′ , AR ← 0 b. YT: R1 ← R2, R1 ← R3 c. ZT: PC ← AR, PC ← PC+1
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Solution: a. Cannot complement and clear the same register at the same time. b. Cannot transfer two different values (R2 and R3) to the same register (R1) at the same time.
Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
2140707 – COMPUTER ORGANIZATION
B.E Semester: 4 – 4 – IT/CE/CSE IT/CE/CSE (GTU) UNIT- I c. Cannot transfer a new value into a register (PC) and increment the original value by one at the same time. 16) Design a digital circuit that performs the four logic operations of exclusive-OR, exclusiveNOR, NOR and NAND. Use two selection variables. Show the logic diagram of one typical stage.
QUESTION BANK What is register transfer language? Clear it with example. Explain the operation of three state bus buffers and show its use in design of
common bus. Define: RTL, Computer Organization, Micro-operation Explain selective set, selective complement and a nd selective clear Explain 4-bit incrementer with necessary diagram. Explain 4-bit decrementer with necessary diagram.
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Prof. Priyanka Panchal Assistant Professor, IT Dept. MBICT, New V.V.Nagar.
