Cmos Rf Modeling,Characterization and Applications

ected Topics in Electronics and Systei

OS RF MODELING, CHARACTERIZATION AND APPLICATIONS

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS

SELECTED TOPICS IN ELECTRONICS AND SYSTEMS Editor-in-Chief:

M. S. Shur

Published Vol. 6: Low Power VLSI Design and Technology eds. G. Yeap and F. Najm Vol. 7:

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Current Research and Developments in Optical Fiber Communications in China eds. Q.-M. Wang and T. P. Lee

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Selected Topics in Electronics and Systems - Vol. 24

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS

Editors

M. Jamal Deen McMaster University, Canada

Tor A. Fjeldly Norwegian University of Science and Technology, Norway

, © World Scientific !•

New Jersey • London • Singapore • Hong Kong

Published by World Scientific Publishing Co. Pte. Ltd. P O Box 128, Farrer Road, Singapore 912805 USA office: Suite IB, 1060 Main Street, River Edge, NJ 07661 UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE

British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library.

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS Copyright © 2002 by World Scientific Publishing Co. Pte. Ltd. All rights reserved. This book or parts thereof, may not be reproduced in anyform or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permission from the Publisher.

For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission to photocopy is not required from the publisher.

ISBN 981-02-4905-5

Printed in Singapore by Mainland Press

PREFACE CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS M.JAMALDEEN Department of Electrical and Computer Engineering McMaster University, Hamilton, Ontario, Canada L8S 4K1

TOR A. FJELDLY UniK - Center for Technology at Kjeller, Norwegian University of Science and Technology, N-2027 Kjeller, Norway

The rapid evolution of semiconductor electronics technology is fueled by a never-ending demand for better performance at reduced cost, combined with a fierce global competition. For CMOS technology, this evolution is often measured in generations of three years, the time it takes for manufactured memory capacity to be increased by a factor of four and for logic circuit density to increase by a factor of between two and three. Technologically, this trend is made possible by a downscaling of transistor feature size (i.e., gate length) by a factor of two per two generations. Traditionally, the highfrequency properties of silicon MOSFETs have been considered inferior to other technologies, including silicon bipolar transistors and transistors based on III-V materials such as gallium arsenide. However, the CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cut-off frequencies of about 50 GHz have been reported for 0.18 urn CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of the popular wireless products today, such as cell phones, GPS (Global Positioning System), and Bluetooth. Of course, the great interest in RF CMOS comes the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. Circuit design is an integral part of electronics technology, as important as the fabrication itself. Advances in the fabrication process always pose new challenges to the circuit designers. In order to be able to take full advantage of the new technology, the designers need to update their CAD (Computer Aided Design) tools with precise

V

vi

Preface

descriptions of the new devices in terms of models that can be implemented into circuit simulators. To be able to scale the devices for different operations, the models must be physics based to account for the complex dependence of the device properties on dimensions and other processing variables. The model parameters are derived from measurements and characterization of the devices. For RF CMOS, both the modeling and the characterization are challenging tasks that will be especially emphasized in this volume. Next follows a survey of the six contributions included in the first issue. Reliable measurements are a prerequisite for any sensible work on device modeling, especially so for high frequencies where the subtleties of the device behavior are plentiful. In the first chapter of this volume, F. Sischka and T. Gneiting discuss a wide range of issues related to RF MOSFET measurements, most of which also apply to RF device characterization in general. A thorough discussion of S-parameters, Smith charts, polar plots, network analyzer measurements, de-embedding techniques, and MOSFET test structures are included, and may serve as a valuable high-level tutorial on the subject of RF measurements. In the second chapter, M. Je, I. Kwon, H. Shin, and K. Lee discuss MOSFET modeling and parameter extraction for RF applications. They review several existing techniques, many of which are based on earlier work on three-terminal III-V devices, and examine the problems and shortcomings encountered in adapting these techniques to RF MOSFETs. The fact that the MOSFET is a four-terminal device and that the silicon substrate is lossy represent major challenges. The authors emphasize the importance of using charge conserving models, especially in conjunction with parameter extraction. They also present a new four-terminal modeling approach for handling RF MOSFETs. Finally, many of the remaining challenges in RF CMOS modeling and parameter extraction are discussed. RF MOSFET modeling is also the topic of the third chapter by Y. Cheng. Equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain physics-based RF models. Procedures for parameter extraction are also discussed. The analysis emphasizes the importance of certain capacitive and resistive components at high frequencies, in particular, the polysilicon gate resistance, the distributed channel resistance, and the components associated with the lossy substrate. An RF MOSFET model based on BSIM3v3 is presented, and good correspondence is obtained with experimental data obtained for different device geometries. Non-quasistatic effects are discussed in conjunction with this model. The modeling of flicker noise and thermal noise, and existing challenges in this area, are also discussed as part of this presentation. The fourth chapter by C.-C. Chen and M. J. Deen is dedicated to RF CMOS noise characterization and modeling. From small-signal models, such as some of those discussed above, it may be difficult to find analytical expressions for the fundamental noise parameters. As an alternative, the authors present techniques for calculating the noise parameters numerically. De-embedding techniques for extraction of RF MOSFET noise parameters and scattering parameters from experiments are also presented in detail, along with procedures for obtaining the frequency and bias dependencies of the extracted

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vii

noise sources. Finally, this chapter includes some considerations for design of low-noise circuits, and a comparison of different noise models reported in the literature. Silicon-on-insulator (SOI) CMOS technology offers exceptional advantages in terms of low-power/low-voltage applications in digital as well as in RF and microwave circuits. In the fifth chapter, D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier present many aspects of the SOI CMOS technology, including SOI materials, devices and circuits, MOSFET properties, passive elements, and last but not least, the RF and microwave modeling and characterization of SOI MOSFETs. A fully developed SOI MOSFET macro model valid from DC to RF is presented, which includes transmission line effects related to both the gate and the channel. Comparisons with experiments show that this model is accurate up to 40 GHz for feature sizes down to 0.16 urn. Some examples of RF SOI CMOS applications are also presented. CMOS operating frequencies in the GHz range have been achieved through the down-scaling of device feature sizes into deep sub-micrometer dimensions. However, this has not come without penalties. Among these are the deleterious effects of hot carrier transport, brought on by a concomitant increase in the MOSFET channel electric field. The high field problem is, of course, rooted in the need for keeping the supply voltages relatively high to maintain high speed and reduce the subthreshold leakage current. Basically, the hot-electron effects lead to device degradation and, hence, represent a serious reliability problem. In the sixth chapter on RF CMOS reliability, S. Naseh and M. J. Deen consider the important issues of hot-carrier effects, and illustrate them by experimental results and simulations.

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Preface

M. Jamal Deen is professor of Electrical and Computer Engineering at McMaster University. He also holds the Canada Research Chair in ? •tSU't' Information Technology. He has also been professor of Engineering ; 'N ', Science at Simon Fraser University since 1993. Previously, he was "" ""* & with the CNRS Laboratory of Physics of Semiconductors Devices (LPCS), Grenoble (Visiting Scientist, summer 1998), faculty of Elec* trical Engineering (ECTM Lab), Delft University of Technology (Visiting Professor, summer 1997); Herzberg Institute of Astrophysics, National Research Council, Ottawa (Visiting Scientist, summer 1986); and Lehigh University, Bethlehem, Pennsylvania (Assistant Professor, 1985-86). His industrial experience includes a one-year visiting scientist position (1992-93) with the Device Technology Group, Northern Telecom, Ottawa, and several years of consulting and joint research with Northern Telecom, Bell Northern Research, Conexant, D&V Electronics, IBM, Mitel, National Semiconductor and Rockwell Semiconductor Systems. Dr. Deen holds the Ph.D. and M.S. degrees from Case Western Reserve University, Cleveland, Ohio, U.S.A. in Electrical Engineering and Applied Physics, and the B.Sc. degree from the University of Guyana, Guyana, S. America in Physics/Mathematics. As an undergraduate student, he won the Dr. Irving Adler's Prize for the best graduating mathematics student, and the Chancellor's Medal for the second best graduating student in the University in 1978. He was also a Fulbright Scholar from 1980 to 1982, an American Vacuum Society Scholar from 1983 to 1984, an NSERC Senior Industrial Fellow in 1993. He was given a Reward of Recognition Award, Silicon Technology Division, Northern Telecom in 1993, and won the IEEE 1993 Outstanding Branch Councillor and Advisor Award for Canada. Most recently, he was awarded a Canada Research Chair in Information Technology at McMaster University. Dr. Deen is a member of Eta Kappa Nu (the Electrical Engineering Honor Society, U.S.A) and the Electrochemical Society, a life member of die American Physical Society, and a Senior Member of the IEEE. Dr. Deen is also Editor, IEEE Transactions on Electron Devices; Executive Editor, Fluctuation and Noise Letters; and Member, Editorial Board, Interface — An Electrochemical Society Publication. Dr. Deen is the co-editor of six books or conference proceedings and the co-author of thirteen book chapters and one encyclopedia article. He has authored or co-authored more than 220 peer-reviewed scientific papers, 68 conference abstracts and extended abstracts, and 48 commissioned technical reports. He is also named an inventor in five patents.

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ix

Tor A. Fjeldly received the M. Sc. degree in physics from the Norwegian Institute of Technology, 1967, and the Ph.D. degree from Brown University, Providence, RI, in 1972. From 1972 to 1994, he was with Max-Planck-Institute for Solid State Physics in Stuttgart, Germany. From 1974 to 1983, he worked as a Senior Scientist at the SINTEF research organization in Norway. Since 1983, he has been on the faculty of the Norwegian University of Science and Technology (NTNU), where he is a Professor of Electrical Engineering. He is presently with NTNU's Center for Technology at Kjeller, Norway. He was Head of the Department of Physical Electronics at NTNU, and he also served as an Associate Dean of the Faculty of Electrical Engineering and Telecommunication. From 1990 to 1997, he held the position of Visiting Professor at the Department of Electrical Engineering, University of Virginia, Charlottesville, VA, and from 1997 he has been Visiting Professor at the Electrical, Computer and Systems Engineering Department, Rensselaer Polytechnic Institute, Troy, NY. His research interests have included fundamental studies of semiconductors and other solids, development of solid-state chemical sensors, electron transport in semiconductors, modeling and simulation of semiconductor devices, and circuit simulation. He has written about 150 scientific papers, several book chapters, and is a co-author of the books Semiconductor Device Modeling for VLSI (Englewood Cliffs, NJ: Prentice Hall, 1993) and Introduction to Device Modeling and Circuit Simulation (New York, NY: Wiley & Sons, 1998). He is also a co-developer of the circuit simulator AIM-Spice. Since 1998, he has been a Co-Editor-in-Chief of the International Journal of High Speed Electronics and Systems, Singapore. Dr. Fjeldly is a Fellow of IEEE and a member of the Norwegian Academy of Technical Sciences, the American Physical Society, the European Physical Society and the Norwegian Society of Chartered Engineers.

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CONTENTS

Preface M. J. Deen and T. A. Fjeldly

v

RF MOS Measurements F. Sischka and T. Gneiting

1

MOSFET Modeling and Parameter Extraction for RF IC's M. Je, I. Kwon, H. Shin, and K. Lee

67

MOSFET Modeling for RF IC Design Y. Cheng

121

RF CMOS Noise Characterization and Modeling C.-H. Chen and M. J. Deen

199

SOI CMOS Transistors for RF and Microwave Applications D. Flandre, J.-P. Raskin, and D. Vanhoenacker-Janvier

273

RF CMOS Reliability S. Naseh and M. J. Deen

363

International Journal of High Speed Electronics and Systems, Vol. 11, No. 4 (2001) 887-951 © World Scientific Publishing Company

RF MOS MEASUREMENTS FRANZ SISCHKA Agilent Technologies GmbH, Munich, Germany THOMAS GNEITING admos, Frickenhausen, Germany

The trend to higher integration and higher transmission speed challenges modeling engineers to develop accurate device models up to the Gigahertz range. An absolute prerequisite for achieving this goal are reliable measurements, which have to be checked for data consistency and plausibility. This is especially true for RF data, and also for checking and verifying the applied de-embedding techniques. If this is not the case, RF modeling can become quite time consuming, with a lot of guesswork and ad-hoc judgements, and, basically, frustrating and not correct. If, however, the underlying measurements are flawless and consistent, and provided the applied the models are understood well, RF modeling becomes very effective and provides accurate design kits which will satisfy the chip designer's main goal: right the fist time.

1

Characterizing Devices From D C To High Frequencies

While the characterization of electronic components in the DC domain is relatively simple and only requires a voltmeter and an amperemeter, the frequency performance of the device is affected by magnitude dependence and phase shift of the currents and voltages. Furthermore, nonlinearities will lead to a spectrum of frequencies, although the device is only stimulated with a single, sine frequency. Last not least, inevitable capacitive and inductive parasitics, with values close to those of the very device under test (DUT), will contribute to the measurements and degrade the measured performance of the 'inner' DUT. [1,2]

In this paper, we will go step by step through the individual characterization issues and develop measurement strategies which will provide the base of accurate device modeling.

2

DC Measurements As A Prerequisite For RF Setups

Large signal modeling of a nonlinear component always begins with the characterization of its DC performance. Instead of power supplies, DC parametric analyzers with sourcemonitor-unit plugins (SMU) are applied. This allows to fully characterize the DUT (device under test) from fempto-Ampere up to its maximum current, and in all four i-v quadrants. I.e. forward and reverse currents and voltages, are measured with the same SMU unit. l

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Gneiting

Usually, in case of a transistor, all 4 terminals (including substrate) are connected to individual SMUs in order to avoid recabling during the forward and reverse measurements.

SMUs apply a Kelvin measurement to avoid parasitic series resistances. This measurement procedure, also known as the four-wire method, consists of a stimulating line (Force) with a second one in parallel (Sense) for every pin of the DUT. Fig. 1 illustrates this. Ohmic losses on the Force line are eliminated by the main operational amplifier (OpAmpl) in voltage follower mode. This means this OpAmpl output will exhibit a somewhat higher voltage than the desired test voltage at the DUT, because the test current generates some ohmic losses along the Force line. The Sense line, connected to the minus input of the OpAmpl, assures that the DUT is biased with exactly the desired test voltage.

SMU

OpAmp2 External Shielding

* L

Ohmic Losses

±

d

OpAmpl

r

•AM/v^-

-r

Dielectric Losses

I desired I voltage

Measurement Instrument

F

Inner Shielding Force

Sense Test Potential

Metering Lines

Fig. 1: The principle of Kelvin measurements (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

While this method compensates the DC errors, it does not cover dynamic measurement problems. For example, to avoid external electro-magnetic influences, both the Force and Sense cables are shielded. Such cable shieldings exhibit parasitic capacitances. Due to charging problems, these capacitances will affect the measurement speed and accuracy of our Kelvin measurement. As a simple example: assume we want to measure the reverse characteristics of a semiconductor diode. This means we need measure very low currents. Before the voltage steps to, e.g. -20 V, the quiescent voltage at the diode is zero. That is, the cable capacitors are not charged. When the negative voltage step occurs, these capacitances have to be charged, and the required current is provided by the OpAmpl. This could lead to either a mis-measurement (DUT current plus charging current) or a delay in the triggering of the actual current measurement (by some intelligent firmware in our measurement). To solve this problem, an extra inner shielding is applied between the hot metering lines and the outer cable shielding, called 'Guard'. This extra shielding is connected to a separate,

2

RF MOS Measurements

889

second 0pAmp2 which follows exactly the value of the desired test voltage. Now it is this auxiliary OpAmp2 which supplies the charging current for the test cables, while the main Op Amp 1 can start current measurements independently of this charging problem. That is, the inner measurement loop does not see the charging problem any more. Of course the point where Force and Sense are tied together must be as close as possible to the DUT. In case they aren't connected, an internal lOkOhm resistor at the . of the SMU acts as the Kelvin point. Another important fact is that the Guard comae i should never be connected to Force or Sense. Otherwise, the inner loop OpAmpl of the SMU would measure the DUT current plus the charging current of the auxiliary, second OpAmp2! In order to maintain the DC measurement accuracy, SMUs perform periodically an autocalibration. This means that the SMU disconnects its outputs from the DUT, measures possible offset voltages and currents and corrects it. This type of calibration does not require any action from the user. See publications [3] and [4] for details.

3

Capacitance Measurements At 1MHz

As discussed in the previous chapter, the DC voltages and currents can be measured directly. The calibration is periodically auto-executed by the instrument. After such a DC characterization, modeling engineers usually perform a so-called CV (capacitance versus voltage) measurement in order to characterize the device capacitances at a standard frequency of 1MHz. This frequency is high enough to allow a resolution down to a few fempto-Ampere (provided shielded probes are applied for e.g. on-wafer measurements), yet still low enough to neglect second order parasitics like resistors in series with the capacitors, or like inductances. For such CV measurements, the DC-bias is swept, a test frequency (1MHz) is applied to the DUT, and the instrument calculates the capacitance between the 2 pins of the DUT from the magnitude and phase of the device voltage and current. For CV meters, an auto-balancing method is typically applied. Fig. 2 depicts the simplified measurement scheme. The DUT is inserted in the feedback loop of an operational amplifier, and the system is stimulated with a 1MHz sine signal plus a DC bias. The feedback resistor R is precisely known, and the complex voltages VI and Vdut are measured. From the formula given in Fig. 2, the capacitance of the DUT can be calculated, assuming an equivalent schematic of either a resistor in series with the capacitor, or, commonly for modeling, a capacitor in parallel with a resistor (which is the bias-dependent diode resistance for example).

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CV meter applying the auto-balancing method DUT

V

V

Zx

sine frequency + DC bias

R

Hint: LOW potential is virtual ground !

Fig.2: schematic measurement principle of a CV meter (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Again, test cables and fixtures contribute and affect the device characterization. Here, the measurement calibration consists of unconnecting the DUT, assuming an ideal OPEN condition and measuring the cables and their OPEN parasitics. The corresponding capacitance is then automatically subtracted from the subsequent DUT measurement. Note: If we are interested in the inner DUT's CV curves, i.e. without its surrounding test pads capacitances, we need to connect to an OPEN dummy structure during CV meter calibration. Such an OPEN dummy consists of all connection pads, lines to the DUT etc, but without the inner DUT itself. See Figures 34 and 46 for examples. When characterizing the capacitances of transistors, the open 3rd transistor terminal can be connected to the shielding potential, eliminating the effect of the unwanted capacitor. See Fig. 3, and also publication [5] for details.

taffies

w ©53®

QOSH

Measurement of CDG With the auto-balancing method, connecting the Source to the cable shielding potential, eliminates the effect of CGS

Fig. 3: measuring transistor capacitances with a CV meter (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

4

RF MOS Measurements

4

891

From Y-, Z-, And H-Parameters To S-Parameters

While the CV measurement is considered as a specific two-pin test condition, the situation changes for frequencies above 100MHz. The modeling device is now operated under its originally intended environment conditions: DC bias is applied to all the pins, and an additional small-signal RF excitation is applied. Now, the sine currents and voltages at all pins of the DUT are to be measured, with magnitude and phase. A natural choice for such characterizations would be Z-, Y- or H-parameters from linear two-port theory. These two-port parameters can be used to completely describe the electrical behavior of our device (or network), including any source and load conditions. For such parameters, we have to measure the voltage or current as a function of frequency and bias at the ports of the device. At high frequencies, however, it is very hard to measure voltage and current at the device ports. One cannot simply connect a voltmeter or current probe and get accurate measurements due to the impedance of the probes themselves and the difficulty to place the probes at the desired positions. Furthermore we have to apply either (AC-wise) OPEN or SHORT circuits as part of the Z-, Y- or H-parameter measurement. Active devices may oscillate or self-destruct with such terminations.

4.1

Introducing S-Parameters

Clearly, some other way of characterizing high-frequency networks is required that doesn't have these drawbacks. That is why scattering or S-parameters were developed. These parameters relate to familiar measurements such as gain, loss, and reflection coefficient. They are relatively simple to measure, and do not require connection of undesirable loads to the DUT. Different to Y and Z, however, they relate to the traveling waves that are scattered or reflected when a network is inserted into a transmission line of a certain characteristic impedance ZO. The measured S-parameters of multiple devices can be cascaded to predict overall system performance. S-parameters are readily used in both linear and nonlinear CAE circuit simulation tools, and Z-, Y- or H-parameters can be derived from S-parameters when necessary. To help with becoming familiar with linear S-parameters, we want to give a short example on characterizing components using power measurements, the lightwave analogy for Transmission and Reflection. Since a circuit described by S-parameters can be thought of like inserted into a uniform characteristic impedance (ZO) environment, we can compare Sparameters to reflection and transmission of an optical lens, surrounded at both sides by air. When light interacts with a lens, as in the photograph of Fig. 4, part of the light incident on the eyeglasses is reflected while the rest is transmitted. The amounts reflected and transmitted are characterized by optical reflection and transmission coefficients. By performing such a measurement, your optician is able to characterize your eyeglasses completely.

5

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F. Sischka

& T.

Gneiting

Fig. 4: reflection and transmission with eyeglasses (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Similarly, scattering parameters are measures of reflection and transmission of voltage waves through a two-port electrical network, inserted into a uniform characteristic impedance environment. Definition of S-parameters Referring once again to the spectacles examples from above, i.e. power-wise, the S-parameters are defined as: 2\

Pi I

I

2

i

I ajl 2 ibjl

|2 §2 I

i2

I—22 I

with

f

*

,

J

power wave traveling towards the two-port gate

2

power wave reflected back from the two-port gate

and I SnI2

power reflected from portl

ISi2l2

power transmitted from portl to port2

2

power transmitted from port2 to portl

IS.21I

IS22I2

power reflected from port2

This means that S-parameters relate traveling waves (power) to a two-port's (DUT) reflection and transmission behavior. Since the two-port is imbedded in a characteristic impedance of ZO, these 'waves' can be interpreted in terms of normalized voltage or current amplitudes. This is sketched below.

6

RF MOS Measurements

la,!2

893

-

lb, I2 « Zh

tWt*[

._ , f iiin'niiii

Starting with power

normalized toZo V*V

P=v*i

gives normalized amplitudes for voltage and current V

- VP =

3)

a,

^

•*

1-7

-o = I JZc

In other words, we can convert the power towards the two-port into a normalized voltage amplitude of towards _ twoport

VZo"

(1)

and the power away from the two-port can be interpreted in terms of voltages like L.

away _ from _ twoport

(2) See Fig. 5 for details.

Fig. 5: S-parameter definition (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

7

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Looking at the S-parameter coefficients individually, we have: v

_ b1

0

reflected at portl

211 £1

_ b2 _

Q

Vtowards portl

v

o u t of port2

—21 ^1

^towards portl

(3) S l l and S21 are determined by measuring the magnitude and phase of the incident, reflected and transmitted signals when the output is terminated in a perfect ZO load. This condition guarantees that a2 is zero. Sll is equivalent to the input complex reflection coefficient or impedance of the DUT, and S21 is the forward complex transmission coefficient. Likewise, by placing the source at port 2 and terminating port 1 in a perfect load (making al zero), S22 and S12 measurements can be made. S22 is equivalent to the output complex reflection coefficient or output impedance of the DUT, and S12 is the reverse complex transmission coefficient. The accuracy of S-parameter measurements depends greatly on how good a termination we apply to the port not being stimulated. Anything other than a perfect load will result in al or a2 not being zero (which violates the definition for S-parameters). When the DUT is connected to the test ports of a network analyzer and we don't account for imperfect test port match, we have not done a very good job satisfying the condition of a perfect termination. For this reason, two-port calibration, which corrects for source and load match, is very important for accurate S-parameter measurements. In order to become more familiar with S-parameters, we will now discuss some specific Sparameter values.

SllandS22 value -1 0 +1

interpretation all voltage amplitudes towards the twoport are inverted and reflected (Oil) impedance matching, no reflections at all (50 Q) voltage amplitudes are reflected (infinite Q.)

The magnitude of Sll and S22 is always less than 1. Otherwise, it would represent a negative ohmic resistor (!). On the other hand, the magnitude of S21 (transfer characteristics) respectively S12 (reverse) can exceed the value of 1 in the case of active amplification. Also, the starting

RF MOS Measurements

895

points of S21 and S12 can be positive or negative. If they are negative, there is a phase inversion. As an example, S21 of a transistor starts usually at about S21 = -2 ...-10. This means signal amplification within the ZO environment and phase inversion.

S21andS12 magnitude 0 0...+1 +1 >+1

interpretation no signal transmission at all input signal is damped in the Z0 environment unity gain signal transmission in the ZO environment input signal is amplified in the ZO environment

The numbering convention for S-parameters is that the first number following the S is the port at which energy emerges, and the second number is the port at which energy enters. So S21 is a measure of power emerging from Port 2 as a result of applying an RF stimulus to Port 1.

4.2

Smith Chart And Polar Plot

The Smith chart for Sxx What makes Sxx-parameters especially interesting for modeling, is that S11 and S22 can be interpreted as complex input or output resistances of the two-port. That's why they are usually plotted in a Smith chart. NOTE: do not forget that included in Sxx is the termination at the opposite side of the twoport, usually ZO !! The Smith chart is a transformation of the complex impedance plane R into the complex reflection coefficient T (rho) , following the formula:

^R-Z0 ~ R + zo r

(1)

with the system's characteristic impedance ZO = 50 Q. This means that the right half of the complex impedance plane circle in the r-domain. The circle radius is '1' (see Fig. 6).

9

R

is transformed into a

896

F. Sischka & T.

Gneiting

R-50 R

r=

R + 50

j50 Ohm

50 Ohm

Fig. 6: the relationship between Sxx and the complex impedance of a two-port. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

On the other hand, using a network analyzer with a characteristic system impedance of ZO, the parameter S11 is equal to

S„=2.^-1 v01

(2)

where vl is the complex voltage at port 1 and vOl the stimulating AC source voltage (which is typically normalized to 'I'). Fig. 7 depicts the corresponding circuit schematic. twoport ZO

ZO

V01

Fig. 7: about the definition of SI 1

V1

(S22 is analogous) (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Under the assumption that R is the complex input resistance at port 1 and ZO is the system impedance, we get using eq.(2) and the resistive divider formula for Fig. 7:

R-ZO S»11 n = 2--=— -1 = = R + ZO R + ZO And this is the reflection coefficient T from(l)!!

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RF MOS Measurements

897

NOTE: see also the chapter called 'Calculating S-Parameters From Complex Voltages' further down. After all, if the reflection coefficient T resp. Sj j or S22 is known, we get for the complex

i+r 1+s-n R = ZO • —-=• = ZO • — 1-T 1-S1 11

resistor R:

, with usually ZO = 50 Q

This explains how we can get the complex input/output resistance of a two-port directly from S11 or S22, if we plot these S-parameters in a Smith chart. Let's go back to Fig. 6 and consolidate this context a little further: it shows a square with the corners (0/0)Q, (50/0)Q, (50/j50)Q and (0/j50)ii in the complex impedance plane and its equivalent in the Smith chart with ZO=50£2. Please watch the angel-preserving property of this transform (rectangles stay rectangles close to their origins). Also watch how the positive and negative imaginary axis of the R plane is transformed into the Smith chart domain ( T ), and where (50/j50)Q is located in the Smith chart. Also verify that the center of the Smith chart represents ZO, i.e. for ZO = 50Q, the center of the Smith chart is (50/j0)Q. This allows us to make the following statements: > Sxx on the real axis represent ohmic resistors > Sxx above the real axis represent inductive impedances > Sxx below the real axis represent capacitive impedances > Sxx curves in the Smith chart turn clock-wise with increasing frequency. Fig. 8 depicts this graphically.



— K>

CD ED

Fig. 8: Location of ohmic, inductive and capacitive components in the Smith chart (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

11

898

F. Sischka

& T.

Gneiting

As an example for interpreting Smith charts, Fig. 9a shows the S l l plot of a bipolar transistor. In this case, the locus curve stars with S l l = 1 = ° ° * Z Q at low frequencies corresponding to R g g ' + R^j 0( j e + beta*Rr£. For increasing frequencies, the curves then turn into the lower half-plane of the Smith chart, the capacitive region. Here, the C g g shorts R(jiode' anc* beta = 1- F ° r infinite frequency, when the capacitors represent ideal shorts, the end point of S] j lies on the middle axis, i.e. the input impedance is completely ohmic, representing Rgg> + Rr£- Since Rgg> is bias dependent, and decreasing with increasing iB, the end points of the curves represent this bias-dependency. NOTE: For incrementing frequency, the Sxx locus curves turn always clockwise! Fig. 9b shows the S l l curve of a capacitor located between the two ports of the network analyzer (NWA). The capacitor represents an OPEN for DC, thus S11 = 1 = °°*Z0. For highest frequencies, it behaves like a SHORT, and we see the 50 Q of the opposite port2 (!). The transition between the DC point and infinite frequency follows a circle, and the increasing frequency turns the curve again clockwise.

S11

Fig. 9a: Si i of a transistor with increasing Base current iB. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

12

RF MOS Measurements

899

-F i™ e CI

Fig. 9b: Si ^ of a capacitor between port 1 and port 2

7%e PoZar diagram for Sxy

Fig.10: The polar diagram for S12 and S21 (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

The S21 parameter represents the power transmission from port 1 to port 2, if the two-port is inserted into a matching network with characteristic impedance Z0 of e.g. 50 Q. This means, if no signal is transmitted, then S21=0 (located in the center of the polar plot). If the signal is transmitted, then MAG(S21)>0. The magnitude of the S21 curve will be below T for damping between the port 1 and port 2, and above 1' for amplification. If the phase is inverted, we are basically in the left half-plane of the polar plot (REAL[S21]

\

How to proceed with the de-embedding of lossless delay lines: Provided we know the delay times TDl and TD2, we can use the 'port shift' properties of Sparameter multiplications (shift of reference planes), and obtain:

45

932

F. Sischka & T.

'S11'DUT n,rr S21,DUT

Gneiting

S12-DUT ^ S22,DUT

f

01 -i

0 1

'total

* p j-2Plf 2TD1 e

S21total expj2Plf

(TD1+TD2)

S12total*exp j2Plf 99? * °"total

(TD1+TD2)\

J-2PI-«-2TD2 pvn e x P

f : frequency TD1: delay time at port 1, TD2: delay time at port 2

with:

De-embedding

applying the

ABC-matrix

By definition, ABC matrices are best suited to describe a chain of two-ports. This feature makes them an ideal starting point for parasitics de-embedding related to measurement conditions where we have considerably long connection lines to the device, and a separation into parallel and serial parasitics cannot be achieved. I.e. situations where the parasitic components are more distributed than lumped. ABC matrix de-embedding can be applied for example to packaged or insertable devices like a connector etc.. It can also be applied to special on-wafer components line spiral inductors, which occupy a large area on the chip and whose parasitics are therefore distributed. For a classical ABC matrix de-embedding, let's start with an example of a packaged device. Besides the test fixture for the DUT, which consists basically of a substrate with a strip line for each port of the DUT, we also need a special test structure to characterize these strip lines. This means we need another strip line on the same substrate like the test fixture, and this strip line is exactly as long as the strip lines of the test fixture. See the sketch below.

(L - AL)/2 —location 7 of the DUT AJine

Ajine

AL test fixture to measure the DUT

auxiliary fixture to characterize AJine

With the assumption that the A j m e ABC matrix is identical to the connection strip lines of the test fixture, the total performance of the device-under-test (DUT) including the test fixture can be expressed in A matrices as:

46

RF MOS Measurements A

933

total = A line * A DUT * A line

or solved for the DUT ABC matrix AQJJT; : A _ A - l * A * A _1 • ^ DUT ~ " • line ** total ^ line

How to proceed: The measured S-parameters S. ^ i are converted to A t

taj

. The same applies to the

measured S j m parameters. Then the matrix calculation from above is applied in order to obtain the de-embedded

AQTJX-

As a special case, the ABC matrix can be applied to de-embedding from lossy delay lines. First, we have to define the ABC matrix A j m e of a strip line, with: ZO y ct B or TD

characteristic impedance of the strip line propagation coefficient of the line loss phase shift resp. delay time of the strip line,

r , lossless line Y (freq)- L = |a( fre q) + j • B(f re q) J • L ~

j • B(f) • L = j • 2PI • freq • T D

Note: roughly TD=10ps per mm strip line can be assumed on a ceramic substrate. In case of a lossy line, we calculate first for every frequency point [i] the auxiliary term: aux[i] = (j2 * PI * freqlij * oc + j * 2 * P I * f req[i] * p)* L

and in case of a lossless line (ct=0), we calculate first:

aux[i]=j*2*PI*freq[i]*p*L or aux[i]=j*2*PI*freq[i]*TD which gives for the ABC matrix of the delay line (per frequency point index i): Aline 10 =

cosh(aux[i]) ZO*sinh(aux[i]p —-sinh(aux[i]) cosh(aux)[i]

This matrix is then introduced in the ACB matrix de-embedding formula A

DUT

=

A|j"ne * A t o t a | * AjTne, and we can calculate the de-embed matrix ArjTjj.

47

934

F. Sischka

& T.

Gneiting

Note: in case of a lossless delay line, the formula simplifies to

Mine lossless [i]

( cos(p*l_) = -^sin(p*L)

and

ZO*sin(P*L)^ cos(p*L)

with

p = coVCL

ZO = J —

6.4

De-Embedding The OPEN Dummy Device

The most simple, but very often used de-embedding method is the simple de-embedding from an OPEN device. The underlying prerequisite for this method is, however, that all the circuit components of the OPEN dummy structure can be represented exclusively by lumped circuit components only which are altogether in parallel with the DUT. Only in this case, the well-known Y-matrix subtraction method Y_DUT = Yjxrtal - Y_OPEN can be applied. Fig. 33 depicts this condition. Y DUT

^^•^rDUT^^H infflHHn,t.,.-'M~ ilHIMiiij L"

•••••

- parallel-v. / parasitic;: Y_parallel Fig. 33: For OPEN dummy device de-embedding using Y-matrix subtraction, the OPEN subcircuit has to be completely in parallel with the DUT. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

In order to successfully applying this Y-matrix subtraction, this prerequisite condition of parallel parasitics has to be verified. Otherwise, the de-embedded curves of the inner DUT may look ok, but they may be wrong. The best way to check this is to model the open. If we are able to achieve a fit with a subcircuit consisting of lumped devices which can be interpreted as being completely in

48

RF MOS Measurements

935

parallel with the DUT, (independent of how complex the inner structure of this sub-circuit is !), we can be sure to perform a correct OPEN de-embedding. Fig. 34 shows an OPEN dummy layout, and its S-parameter performance. Referring to the physical layout given in Fig. 35, we can assume a simple RC TEE structure for low frequencies. For higher frequencies, also crosstalk between the ground-signal-ground GSG contact pads of the dummy and coupling across the pads from port 1 to port 2 comes into play. See Fig. 34 and components CIO, RIO, C12, C20 and R20, where the resirtors again represent the losses of the silicon substrate. This effect happens usually for frequencies above -10 GHz, and can be seen in the S-parameter measurements as a deviation from the low-frequency half-circles. See the typical measured S-parameters in Fig. 34. Of course, this 2nd order high-frequency dependency varies with the layout of the OPEN and also with the wafer process. OPEN DUMMY

R£«»

CE-33

Fig. 34: Modeling the OPEN dummy device (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

49

936

F. Sischka

& T.

Gneiting

Fig. 35: physical representation of the OPEN dummy structure for low frequencies (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

If we did not require e.g. inductors to model the OPEN dummy, or other components which can be assumed to be in series with the inner DUT, we can now perform the de-embedding. The measured S-parameters of the OPEN and the total DUT are transformed to Yparameters and then, the Y-parameters from the OPEN are subtracted from the total DUT's Y-parameters. De-embed from Open: •DUT

=

^Total - Y 0 p w i

Convert to S: SDUT

6.5

~

S(YQUT)

De-embedding The OPEN And The SHORT Dummy Device

A method to also strip off the series parasitic influence from the measured data is to deembed the inner DUT from both the OPEN and SHORT dummy device. The idea behind this method is, that the electrical behavior of the pads around the DUT can be described by a combination of exclusively parallel (OPEN) and exclusively serial (SHORT) circuit elements as described in Fig. 36.

50

RF MOS Measurements

937

SERIAL PARASITICA

; i Di

•

,_

i -'

r

i

;

)

:

. ' •-* t

V*y"' : *

—c

c i..

••- , 7 ^ - ^

isf-M1*)

I'AHALLEL PARAS!TICS • r-i'Hi'u!

Fig. 36: For OPEN and SHORT dummy device de-embedding using Y- and Z-matrix subtraction, the OPEN subcircuit has to be completely in parallel with the DUT, and the SHORT subcircuit completely in series with the DUT. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Once the two-port matrices of the serial and parallel parasitic elements are known, they can be subtracted very easily from the total measurement data set. To determine these matrices, the S-parameters of the OPEN and the SHORT dummy test structure are used.

51

938

F. Sischka

& T.

Gneiting

OPEN DUMMY: o

1

o

o-

PARALIEL PAOASITICS Y pu*!let

SHORT

i—ID-

DUMMY: SERIAL PARASITICS ;

._—o-

'^T*•••»"^•i,

--«•?! "••J1."" v i » i l -• rv-1

. o

{seies i;

•O

<

I

SHORT

^feaih 1 o

• Z i w i ' s t 2\

! PARALLEL PARASITICS i

"j . . . .

Fig. 37:

-

.

. •

Y parftUet

Y- and Z-matrix components of me OPEN and the SHORT dummy device (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

Looking at Fig. 37, the schematic of the SHORT dummy device, it is clear, how the matrices of the serial and parallel parasitic elements can be determined:

52

RF MOS Measurements

939

parallel elements: the S-to-Y converted S-parameters of the OPEN dummy give the Y-parameters of the parallel elements. serial elements: the Z-parameters of the serial elements can be determined from the SHORT dummy when the Y-parameters of the parallel elements are known and de-embedded. SHORT DUMMY layout

1

.J ZJ Z]

Sxx

equivalent circuit R1

L1

L2

R2

°-W—MYT*—|—rrrrrr •AAA-o Rp1

Sxy

Rp2 R3 . fWCF*„

' L3

CE—33

Fig. 38: Modeling the SHORT dummy device, de-embedded from the OPEN (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

53

940

F. Sischka & T. Gneiting

With this pre-assumption, the de-embedding can be performed following these matrix operations:

De-embed from Open: • Short/Open "

'Short " 'Open

Convert fo Zs ^Short/Open ~ MT$|,ort/0|Mit}

De-embed from Short: Zour

= Z D U T / 0 p o n - Zshoit/Op»n

Convert fo S: SDUT

= S(ZDUT)

In a first step, the influence of the parallel parasitic elements is removed from both the SHORT and the device under test (DUT). This is done by subtracting the Y-parameters of the OPEN from the Y-parameters of the SHORT and DUT. In the following step, the resulting Y-parameters are converted to Z-parameters and in this representation, the influence of the serial parasitic elements is removed by subtracting the de-embedded Zparameters of die SHORT from the de-embedded Z-parameters of the DUT. The resulting Z-parameters of the DUT are then finally converted back to S-parameters.

6.6

Verifying The De-Embedding

Verifying the de-embedding procedure is very important before applying it to the very DUT, i.e. die transistor etc. Wimout this step, errors or problems with the de-embedding will result in distortions of the inner, de-embedded device, and, thus, to a wrong device model. This is especially true when de-embedding the complete Y and Z matrices of the OPEN and SHORT dummy. Therefore, it is suggested to - model every dummy structure in order to verify its de-embedding prerequisites and to - verify the de-embedding witii a well-known 'golden device' before applying it to the modeling DUT. This means: - After the OPEN and (if available/required) SHORT dummy measurements have been modeled,

54

RF MOS Measurements

941

- and it is assured that circuit components of the OPEN are all in parallel with the DUT, - and the circuit components of the SHORT can be interpreted as being completely in series with the DUT, we can check the de-embedding procedure with a known 'golden device'. In practice, however, the problem is the availability of such a 'golden device'. Provided we have a THRU dummy, we can use this device for a verification of the de-embedding procedure. The idea is that the THRU should look like a simple delay line, with a certain characteristic impedance ZO, and a delay time TD. Additionally, the delay line can be lossy. In any case, the model parameters must represent physical meaningful values, and the deembedded trace must be simple without resonances etc. Just a simple delay line! Fig. 39 depicts such a dummy device layout, the measurement and the simple model.

THRU DUMMY

Fig. 39: measurement result and model of a THRU dummy, de-embedded from both, the OPEN and SHORT (with the SHORT itself de-embeded from the OPEN). (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

6.7

Over- And Under-De-Embedding

If under-de-embedding occurred, i.e. we de-embed 'not enough parasitics', the traces of the de-embedded device will not be 'turned back' sufficiently, se Fig. 40. The de-embedding error will add up to the inner device and make its model useless. Unfortunately, this effect is usually not directly visible from inspections of the data.

55

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The better recognizable effect, however, is over-de-embedding. If this happens, the deembedded DUT curves will 'turn backwards' for higher frequencies or show some other non-physical effects. They may even turn outside the Smith chart!

un-deembedded DUT

deembedded DUT

under deembedded

correctly deembedded

over deembedded Fig. 40: under and over de-embedding effect (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

7

Checking RF Measurement Data Consistency

For a successful device modeling, it is very important to check the RF measurement results before proceeding with the parameter extraction. Without going into the details, here some checkpoints: > > > >

> > >

Check for the DC bias losses due to the resistors in the bias TEEs. check the contact resistance of the RF probes to the aluminum pads on the wafer. check the RF-signal power if it is low enough for measuring linear S-parameters. DC bias currents from S-parameters measurements must match the DC curves, otherwise either self-heating, too much RF-signal, or oscillation etc. may have occurred. compare S-parameters (by Y-matrix conversion) against the CV curves. every de-embedding step must make the signal look more ideal. check if there are enough DC bias conditions available for transit time modeling.

56

RF MOS Measurements

8

943

Test Structures For MOS Transistors

This paragraph gives some information about the physical layout of: • • •

8.1

high frequency transistors as used in integrated CMOS circuits test structures to measure these transistors dummy structures to eliminate the influence of the parasitic pads from the real transistor behavior

Pad Layout Suggestions For A Uniform Test Stucture

DC And

S-Parameter

Fig. 41 gives and idea, how a uniform transistor layout could look like to cover both, highresolution DC current and also S-parameter measurements. Source and Bulk are shorted by the probes!

S-par Fig. 41: Uniform layout suggestion for DC and S-parameter measurements of transistors (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

For DC measurements, a low-current resolution is required down to sub-pico-Amperes. This can best be achieved using special shielded DC needles, and connecting these needles directly to the DC analyzer. It is not recommended to measure DC through the S-parameter testset of the network analyzer. For S-parameter measurements, a good grounding is essential, and ground loops must be avoided. Therefore, the Bulk and Substrate contacts are reliably connected to Ground when the GSG probes (Ground-Signal-Ground) are connected to the above layout.

57

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Gneiting

If an individual DC bias is required for the Bulk or Substrate contact, it is recommended to use GS probes (Ground-Signal), and to use a 3rd GS probe to bias the 3rd DC contact. Using a 3rd GS probe for the DC contact and not a DC needle reduces possible device oscillation considerably. to Bulk SMU

S-par with individual DC bias Fig. 42: Layout suggestion for S-parameter measurements and individual DC bias for Bulk or Substrate, using Ground-Signal probes. (C) Copyright 2001 by Franz Sischka, Agilent Technologies, Munich

NOTE: the distance between the centers of the pads is called pitch. Typical pitches for onwafer transistor modeling is about or below lOOum.

8.2

Layout For High Frequency MOS Transistors

Depending on the target application, there are different layout schemes possible for RF MOS transistors [20]. These layouts depend on the application in RF circuits. Fig. 43 depicts three basic possibilities for a layout of such devices.

58

RF MOS Measurements

RF transistorl design

one single

Top view

Device geometry

drain

gate

1 Gate 1 Drain 1 Source

transistor source

3 drain I gate,

945

p-Si

0

via

metal

n parallel transistors

gate

3 Gates 3 Drains 3 Sources idrain

H

• gate, p-Si

CZ~~J> metal

source

multi finger

O via

o o

transistors

6 Gates 3 Drains 4 Sources

^1

gate

^^^Bmm •2 drain I gate, p-Si

I source „

Q

via

metal

Fig. 43: Test structures for S-parameter measurements. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

The use of one of these designs depends on the functionality of the transistor in the designed circuit. However, most designs are using the multi finger transistor approach. It is very compact and because of a minimization of parasitic capacitance due to shared drain/source regions, it provides the best RF performance (e.g. cut-off frequency fT). A detailed layout of such a multi finger transistor is given in Fig. 44 below. The gate fingers are contacted from both sides to minimize the gate resistance which results in a better high frequency noise behavior.

59

946

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Gneiting

M drain §§ g a t e , p - S i

c;

H source — metal

Q

via

Fig. 44: Layout of a multi finger transistor. (C) Copyright 2001 ThomasGneiting, admos, Frickenhausen, Germany

Test devices should be designed so that they can drive enough current to get a reasonable gain for the measurement with the network analyzer. E.g. using a 'normal' short device with W/L = 10um/0.5um would result in a small starting value of IS21I = 0.2. Such small RF signal levels can be affected by the measurement noise and therefore become distorted. A multi-finger device with 6 gates, 3 drain and 4 source areas would exhibit a higher gain of about IS21I = 1.0 with much less measurement resolution problems. Fig. 45 finally depicts a three-dimensional representation of such a multi-finger MOS transistor. It is interesting to note how 'high' the metal planes are relative to the active silicon area and that the size of the transistor itself is very small compared to the size of the pads.

60

RF MOS Measurements

947

Fig. 45: High frequency MOS transistor layout. (C) Copyright 2001 ThomasGneiting, admos, Frickenhausen, Germany

For more information see publication [20].

8.3

Additional dummy structures for de-embedding

The pre requisite for a correct de-embedding is that certain test structures are available on a wafer together with the device under test (DUT) itself. Depending on the selected deembedding method, an OPEN and SHORT dummy structure is required and must be measured. For the proposed de-embedding verification from above, also a THROUGH dummy structure is necessary. The principle layouts of these structures are given in Figures 46 - 48. These layouts are for Ground-Signal-Ground Probes (GSG).

61

948 F. Sisckka & T. Gneiting

cal.plane after de-embedding

OPEN DUMMY

Fig. 46:

Layout of an OPEN dummy structure. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

cal.plane after de-embedding

SHORT DUMMY Fig. 47: Layout of a SHORT dummy structure. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

62

RF MOS Measurements

949

THRU DUMMY cal.plane after de-embedding

strip line of the THRU which has to be modeled and what must be representable by a simple SPICE stripline !! Fig.48:

Layout of a THRU dummy structure. (C) Copyright 2001 Thomas Gneiting, admos, Frickenhausen, Germany

9

Conclusions

"The modeling of electronic devices in the Gigahertz range can be troublesome, requiring a lot of guesswork and ad-hoc judgements..." These statements are certainly true if the device engineer does not have a thorough knowledge about the models he is applying, the effects involved in the RF characterization measurements and if he has not tested and verified the RF measurement conditions. On the other hand, if he is well aware of - the features of his measurement equipment (e.g. specifications and instrument calibration), - the limitations of the applied measurements (e.g. device self-heating due to the applied DC power levels), - the boundary conditions during characterization (e.g. small RF power levels for network analyzer measurements) - the performance of the RF test fixture or the on-wafer RF probes (e.g. contact resistance, ground loops etc.)

63

950 F. Sischka & T. Gneiting

- the quality of his RF dummy structures (e.g. verification using a THRU dummy on the wafer), - and permanent checking of data consistency (e.g. bias conditions for S-parameter measurements identical to the DC only measurements), RF device modeling is a very clean and reproducible science.

This chapter attempted to illustrate the main issues of these modeling pre-considerations. During the daily RF modeling work, it was found that once these issues are satisfyingly resolved and the data are consistent and o.k., reliable and accurate device models can be obtained. In order to make a thorough modeling job, it is clear that the modeling engineer has to know the selected device models. But without a clear picture of the basics, i.e. the underlying measurements and their quality, he might easily end up with phrases like the ones above! However, and underlining once again, this can be avoided when giving some extra thoughts to the measurement and characterization of the modeling devices.

References [1] F.Sischka, "Device Modeling and Measurement for RF Systems", VLSI conference proceedings 1999, Lisbon, Kluwer Academics. [2] F.Sischka, "RF Measurements And Modeling with Special Emphasis on Test Structures", Tutorial Short Course at the ICMTS 2000 Conference, Monterey, CA. [3] Agilent 4155B/4156B Product Note No. 3: "Prober Connection Guide", Agilent Technologies Literature Number 5966-4185E, 1998 [4] "Ultra Low Current dc Characterization of MOSFETs at the Wafer Level", Agilent Technologies Application Note 4156-1, 1/1998, Lit.Nr. 5963-2014E [5]..Hiroshi Haruta, "Agilent Technologies Impedance Measurement 2nd edition, Agilent Technologies product number 5950-3000

Handbook",

[6] R.W.Anderson, "S-Parameter Techniques for Faster, More Accurate Network Design", Agilent Technologies Application Note 95-1, PN 5952-1130. This is a reprint of the article in the Feb, 1967 Hewlett-Packard Journal, vol.18, no.6 [7] _Understanding the Fundamental Principles of Vector Network Analysis, Agilent Technologies Application Note 1287-1

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[8] P. van Wijnen, "On the Characterization and Optimization of High-Speed Silicon Bipolar Transistors", PhD Thesis University of Delft, 1992, published 1995 by Cascade Microtech, Inc., Beaverton, Oregon [9] Paul Schmitz, "Vector Measurements of Hewlett-Packard, Publication HP5958-0387, April 1989

High

Frequency

Networks",

[10] Agilent Technologies Application Notes 1287-1: "Understanding the Fundamental Principles of Vector Network Analyzers", Pub.No. 5965-7710E, 1997 [11] Agilent Technologies Application Notes 1287-2: "Exploring the Architectures of Network Analyzers", Pub.No 5965-7708E, 1997 [12] Agilent Technologies Application Notes 1287-4: "Network Analyzer Measurements: Filter and Amplifier Examples", Pub.No5965-7710E, 1997 [13] "Hewlett-Packard 1997 Back to Basics Seminar", D.Ballo, Network Analyzer Basics, Pub.No. 5965-7917E [14] Hewlett-Packard Application Note 8510-5A: "Specifying Calibration Standards for the HP8510 Network Analyzer", Publication HP5956-4352, February 1997 [15] Cascade Microtech, "Microwave Wafer Probe HP8510 Network Analyzer Input Instruction Manual, 1990

Calibration

Constants",

[16] Cascade Microtech Application Note: "On Wafer Vector Network Analyzer Calibration and Measurements", 1997, Pub Name PYRPROBE-0597 [17] Cascade Microtech Application Note: "Layout Rules for GHz Probing", 1992, Pub.Name LAYOUT19 [18] CascadeMicrotech Technical Brief: "A Guide to Better Vector Network Analyzer Calibrations for Probe-Tip Measurements" [19] F.Sischka, "IC-CAP Modeling Reference", Agilent Technologies publ.no.8519090109, May 2000 [20] T. Gneiting, "Documentation of the BSIM3v3 Modeling Package", HP Part No. 85190-90082, October 1998, included in: IC-CAP Modeling Software Documentation, Agilent Technologies Prod.Nr. 85199D

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International Journal of High Speed Electronics and Systems, Vol. 11, No. 4 (2001) 953-1006 © World Scientific Publishing Company

MOSFET MODELING AND PARAMETER EXTRACTION FORRFIC'S MINKYU JE, ICKJIN KWON, HYUNGCHEOL SHIN, AND KWYRO LEE Dept. ofEECS, KAIST Also with MICROS Research Center, KAIST 373-1 Kusong, Yusung, Taejon, 305-701, Korea E-mail:krlee@ee. kaist. ac. kr After reviewing the basic concept and general strategies, we have examined a variety of examples of modeling and parameter extraction methods for RF MOSFET's. Modeling and parameter extraction techniques popular in III-V FET modeling were reviewed and recent efforts to model the RF MOSFET and extract the model parameters were examined in light of the differences between the MOSFET and the III-V FET. A very simple and accurate parameter extraction method studied in our laboratory for three-terminal modeling considering charge conservation is also introduced. Our works have two important implications. One is that the consideration for charge conservation is important not only for accurate device modeling and circuit simulation but even more for proper parameter extraction. Another is that one accurate large-signal /- V model is enough to be used for DC, low-frequency analog, as well as RF circuit simulation. Four-terminal modeling based on new equivalent circuits to address the high-frequency effects arising in a MOSFET is very complicated and not practical for CAD applications, even without considering the substrate coupling terms. As a temporary alternative, the macro-modeling approach is examined with various examples.

1. Introduction Until recently, most RF circuits and systems have been implemented with either compound semiconductor transistors, such as GaAs MESFETs, HEMTs, HBTs, or silicon BJTs. The microwave properties of silicon MOSFET's were inferior to those of other high-frequency transistors. However, over time the continuous down-scaling of the CMOS technology has made it a candidate for RF applications." As shown in Table 1, the 0.\&-/jm CMOS technology easily available today exhibits nearly 50 GHz offT (cut-off frequency) and fmax (maximum oscillation frequency), and 0.35 dB of NFml„ (minimum noise figure) at 2-GHz operation frequency.5 These figures indicate excellent potential of the current CMOS technology for RF applications operating at several GHz. As the channel length of a MOSFET shrinks to 100 nm, the/?- of the device comes to about 100 GHz.

67

954 M. Je, I. Kwon, H. Shin & K. Lee Table 1. RF characteristics of n-MOSFET's with decreasing channel lengths.5

Gate Length, L [nm]

250

180

140

120

100

MGHz]

33

49

70

84

112

fmox [GHZ]

41

47

51

52

60

NFmin [dB] @ 2 GHz

0.5

0.35

0.23

0.2

0.15

In addition to its sufficient potential, the CMOS technology is very attractive as an RF technology because CMOS provides such advantages as low cost, high-level integration, and easy access over other technologies. Above all, using the CMOS technology it becomes possible to integrate RF circuits, low-frequency analog circuits, and digital circuits in a single chip, which makes an ultimate one-chip system. This strength of the CMOS technology has resulted in a large amount of research directed toward replacing the conventional highfrequency transistors in RF circuits with RF MOSFET's and integrating the RF front-ends into a single chip.6* However, differences between the RF MOSFET and conventional high-frequency transistors make the proper modeling of RF MOSFET complicated and difficult and, in turn, prevent the successful development of robust commercial RF circuits using CMOS technology. There are two major differences: one is related to the substrate material and the other arises from the device structure of the MOSFET's. These differences complicate not only the device modeling but also the implementation of the integrated RF CMOS circuits. 1.1. Large and lossy parasitic components due to the semi-conducting rather than semi-insulating nature of the silicon substrate The MOSFET's are fabricated on a silicon substrate. Silicon is a semi-conducting material rather than a semi-insulating material like gallium-arsenide. As shown in Table 2, the resistivity of silicon is much lower than that of gallium-arsenide, especially for the practical case. Essentially, the intrinsic resistivity of silicon is smaller than that of gallium-arsenide due to more plentiful carriers in the intrinsic condition. Adding to this, in a practical CMOS process, the silicon substrate is typically doped to have the carrier concentration ranging from about 1015 cm3 to about 1018 cm3, which corresponds to the resistivity of 0.01 ~ 10 ohm-cm. The resistivity value of the silicon substrate is closely related to the ease of device fabrication. In the CMOS process, it is not easy to maintain either p-type or n-type substrate in a high resistivity condition.

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Table 2. Electrical properties of Si and GaAs at 300 °K.

Properties

Si

GaAs

11.7

13.1

• Ultimate intrinsic resistivity

2.3 x 105ohmcm

108 ohmcm

• Practical resistivity range

0.01 ~ 10 ohmcm

108 ohm-cm

\.SW/cm-°C

0.46 W/cm-°C

Dielectric constant Substrate resistivity

Thermal conductivity

The lower resistivity of the silicon substrate results in larger and lossier parasitics related to the substrate. The performance of the integrated CMOS RF circuits is often dominated by these parasitics, not by intrinsic MOSFET's. The substrate parasitics have an important effect on the characteristics and performance of RF CMOS circuits in several aspects, which can be summarized as follow: A. On MOSFET's In RF MOSFET's, the influence of the distributed substrate resistance becomes significant as the operation frequency increases.815 At low frequencies, the impedance of the junction capacitance is so large that the substrate resistance may not be seen from the drain terminal. However, with increasing frequency, the impedance of the junction capacitance reduces and the effects of the substrate resistance start to be seen. At high frequencies, combined with the fact that the MOSFET is a four-terminal device, the signals in RF MOSFET's are coupled through the substrate R-C network in a complex way. The substrate signal coupling mainly affects the small-signal output characteristics, which are important for RF design. This will be discussed in detail in section 3.2. B. On passive circuit elements The semi-conducting substrate also affects the performance of the passive circuit elements such as inductors and capacitors, and makes the modeling of the passive elements complicated.1'1-21 Above all, the energy dissipation through the ohmic loss of the silicon substrate significantly degrades the performance of the on-chip inductors, which is one of the most important components for RF IC's."" The lack of an accurate model for on-chip inductors presents one of the most challenging problems for silicon RF IC designers."" C. On interconnection elements On lossy substrates, complex signal propagation characteristics are exhibited along the interconnection lines and thus it is much harder to model the interconnection lines on the silicon

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substrate."24 For the typical resistivity of the silicon substrate, as the operation frequency increases, a transition from the "slow-wave" propagation mode (no electric field in the substrate) to the "dielectric quasi-TEM" propagation mode (electric field in the substrate) occurs. Furthermore, a longitudinal current component is induced in the silicon substrate by the magnetic field. D. On bonding/probing pads The bonding/probing pads on the silicon substrate constitute considerable parasitics. Most of the loss is associated with the coupling from the signal pads to ground pads that originates from the pad-to-substrate capacitance and the semi-conducting nature of the silicon substrate.25 The S-parameters of the pads have a strong dependence on the substrate resistivity.26 Besides, the substrate carried coupling between the input pad/lead and the output pad/lead is significant.27 All of these parasitics should be carefully considered not only for the actual circuit but also for de-embedding to obtain the accurate characteristics of the intrinsic MOSFET. E. On signal/noise coupling in mixed-signal IC's As various kinds of circuit blocks are integrated on a single-chip, such as digital, analog, and RF circuitry, the signal and noise coupling between blocks through the semi-conducting substrate becomes an important issue for successful system design.18" For example, the great amount of harmonics in the switching noise generated from the digital block may be coupled to the adjacent RF block whose signal level is very weak, to significantly degrade the signal-tonoise ratio of the system. Thus, an efficient isolation technique preventing the substrate coupling should be devised. Also, accurate substrate coupling models that can be incorporated into the circuit simulator are required for the accurate simulation of the designed circuits. 2.2. Three-port/four-terminal rather than a two-port/three-terminal

device

The conventional high-frequency FET's have three terminals: a gate, a source, and a drain. Bipolar transistors are also three-terminal devices, having an emitter, a base, and a collector as their terminals. However, the MOSFET has a fourth terminal, the "body", as shown in Fig. 1. The body is doped opposite to the source/drain regions to isolate these two regions by reversebiased p-n junctions. For reliable operation of a MOSFET, the body terminal should be connected to a certain terminal with a fixed potential. It is typically connected to ground (the lowest potential used in the circuit) for an n-MOSFET and Vdd (the highest potential used in the circuit) for a p-MOSFET to prevent the source/drain junctions from being forward-biased in any case.

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Fig. 1. Simplified cross-section of a MOSFET.

The basic concept of FET operation is to control the current flow between the source and the drain by adjusting the voltage applied to the gate terminal. The carriers - electrons for an nMOSFET and holes for a p-MOSFET - start from the source where they have a higher potential energy and move through the channel region below the gate and sink into the drain where they have a lower potential energy. The number of carriers participating in a current flow is controlled by the field induced from the gate voltage. In a MOSFET, the change in the body potential can also cause the change in the number of channel carriers. This control mechanism by body voltage is very similar to that by gate voltage, although the body voltage is much less efficient than the gate voltage in controlling the current flow. Thus the MOSFET is essentially a four-terminal device. In many cases, the source and the body of the MOSFET are tied together. Even for this configuration, however, a MOSFET cannot be treated as a three-terminal device because the potential of the intrinsic body node (Fig. 1), which can affect the device operation, is neither the same as the (extrinsic) body terminal nor as the source. With DC excitations, the intrinsic body potential is the same as the extrinsic one, which is also identical to the source terminal. However, with AC excitations, the AC body current becomes significant as the excitation frequency increases. The distributed R-C network composed of the depletion capacitances and the substrate resistances, and the AC current flowing through this R-C network directly coupled from gate, drain, and source terminals make the potentials of the extrinsic body and the intrinsic body different. It is much more difficult to explain and predict the behavior of the four-terminal device than that of the three-terminal device. A three-terminal device can be treated as a two-port network, where four complex numbers (eight real numbers) are enough to characterize the device. However, nine complex numbers (eighteen real numbers) are required to characterize a fourterminal device. The complexity increase due to this difference is significant. The highfrequency modeling and parameter extraction is even more difficult considering the signal coupling between various terminals through the substrate. In addition, the measurement of the four-terminal device is harder to perform and more time-consuming. Additional DC /-K curves are needed to characterize the effects of the body terminal in DC operation, and, ideally a threeport S-parameter measurement is needed to fully characterize the small-signal behaviors of the four-terminal device at high frequencies in AC operation. However, there is no established

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measurement technique to perform an on-wafer three-port ^-parameter measurement. Even if three-port measurement is possible, the number of measurement ports is increased and there are many more bias combinations for the AC characteristics to consider; thus the measurement becomes much more time-consuming. As a result, the data handling and the parameter extraction procedure become very complicated. 1.3. Difficulties in CMOS RF modeling/parameter extraction As discussed above, the modeling and the parameter extraction of RF MOSFET's are different from and more difficult than those of conventional high frequency transistors mainly due to the lossy silicon substrate and the four-terminal device structure of MOSFET's. The difficulties can be summarized as follows: • A more complicated model with a larger number of parameters is required to describe the behavior of the four-terminal MOSFET. • The parasitic components for both active and passive devices as well as for pads and interconnection lines, originating from the semi-conducting substrate, should be included and the effects of signal coupling through the substrate parasitics should be considered properly. • The lossy silicon substrate causes large parasitics of the probing pads and interconnection lines. Accurate measurement and careful de-embedding of these parasitics should be performed using well-designed de-embedding fixtures to obtain the real characteristics of intrinsic MOSFET's. • An on-wafer three-port S-parameter measurement technique has not yet been wellestablished, although it is needed to obtain full small-signal characteristics of four-terminal MOSFET's. Until now, the well-established two-port measurement has been used to characterize MOSFET's, which gives insufficient information to model the four-terminal device. • The measurement of three-port/four-terminal devices requires more measurement points and longer time, and produces a large amount of data. • The manipulation of the large amount of data and the extraction of a large number of model parameters are difficult and time-consuming. Despite these problems, intensive efforts have been spent in the field of MOSFET modeling and parameter extraction, and partial solutions have been exhibited. In the next section, we will introduce basic strategies for RF modeling and parameter extraction of two-port networks. Then, in section 3, various three-terminal models and parameter extraction methods for conventional high-frequency transistors and RF MOSFET's, including the work we performed recently, are extensively described. We briefly comment on four-terminal MOSFET modeling and parameter extraction in section 4, followed by conclusion.

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2. RF Modeling Approaches and Parameter Extraction Strategies for Two-Port Network At high frequencies above about 1 GHz, S-parameter measurement is the easiest and the most reliable way to measure the network characteristics of a certain functional block. A great number of models and corresponding parameter extraction methods from S-parameter measurement data have been proposed for various kinds of two-port networks such as passive devices20 and transistors.™1 In this section, we will discuss the concept and useful interpretations of S-parameters in section 2.1; the basics of modeling and parameter extraction in section 2.2; adequate modeling and parameter extraction strategies for linear/reciprocal and nonlinear/nonreciprocal two-port networks in sections 2.3 and 2.4, respectively; and, finally, requirements for RF FET modeling in section 2.5. 2.2. Physical, mathematical, and engineering interpretations circuit design and measurement

of S-parameters for

An Alport device can be represented in many ways. At low frequency, this is usually done by Z, Y, or H matrices. This is because it is easier to force or measure terminal voltage (or current) with open (or short) circuit. However, there are many problems with this at high frequency. Firstly, accurate high frequency measuring of voltage or current is very hard. In addition, an active device may oscillate or self-destruct with open or shorted connections. Secondly, the voltage or current depends on the cable length, which is always needed to connect a DUT (device under test) and a measurement system. This is equivalent to saying that they are position dependent along the cable. Thirdly, it is not easy to achieve truly open/short termination at high frequency. On the other hand, terminating the port with a cable of characteristic impedance ZQ is much easier. Instead of voltage or current, it is physically and mathematically much easier to work with power (or equivalent voltage) waves propagating into and being reflected from or transmitted through the device. Note that this propagating equivalent voltage wave is position invariant along the cable. Moreover, incident power is fully absorbed, or equivalently there is no reflected power, when the cable corresponding to the force/measure port is terminated by Z0. S-parameters, or scattering parameters in an Alport network are defined as the complex reflection coefficients at each port and complex transmission coefficients of the equivalent voltage wave between each pair of ports. An Alport network has A/2 S-parameters, among which N parameters indicate the reflection coefficients and the remaining N2-N parameters, the transmission coefficients." The S-parameter measurement technique overcomes all of the above drawbacks in characterizing high-frequency networks." The S-parameters relate to familiar measurements such as gain, loss, and the reflection coefficient. The measured S-parameters of multiple devices can be cascaded to predict overall system performance. They are analytically convenient for CAD programs and flow-graph analysis, and mathematically, H, Y, and Z- parameters can be derived from S-parameters when necessary. It should be noted, however, that S-parameters are measured with a particular Z0-system, i.e., 50 O. For example, S2| is the forward gain when terminal 2 is terminated by Z0. This gives insight for a hybrid circuit but not for an integrated

73

960 M. Je, I. Kwon, H. Shin & K. Lee circuit, because usually the output impedance for the former is matched to Z0, while it is very far from Z0 for the latter. Thus S2\ can be interpreted as the rough gain of the device only when its input/output impedance level is around ZQ. 2.2. Basic concepts of modeling and parameter extraction Only when both a proper model and a good set of model parameters are used together, can we obtain accurate and meaningful circuit simulation results. Thus, it is important to develop both a mathematically well-conditioned model to effectively describe the device characteristics and its associated parameter extraction method to find the correct parameter set. The model and the extracted parameter set should be able not only to fit the measured data well but also to predict the correct device behavior under conditions where no measurement is made. Because a correct and efficient parameter extraction is as important as the model itself, we should carefully consider the parameter extraction strategy and method at the same time as when the model is developed. Prior to discussion of the practical modeling and parameter extraction strategies, we should explain modeling and parameter extraction. Most of the device models have their own equivalent circuits, which consist of resistances, capacitances, inductances, voltage-controlled current sources, and so on. This equivalent circuit, having the proper values for each circuit element, generates the device characteristics, or predictions. The value of each element in the equivalent circuit is determined either by examining the data table for table models or by solving the physical or empirical equations for physical models. The model parameters indicate either the values of elements themselves for the table model or the physical and empirical constants and coefficients that appear in the equations describing the behavior of elements for the physical model. In the case of the table model, developing the model of a certain device means that we construct the equivalent circuit that can explain the device behavior in the operation region of interest and devise an appropriate interpolation scheme that can give values of elements when the device does not operate at measurement points. Sometimes, the equivalent circuit of the table model may not be physical, but just mathematical and the element values may be just measured 5-parameter values themselves like the Root model.,4*' The set of measurement conditions should be carefully designed to efficiently cover the whole range in which the device operates. On the other hand, in the case of the physical model, modeling implies constructing the equivalent circuit and formulating the suitable equations that are solved for the element values when the device operating conditions are given. When we extract the model parameters of the physical model, we first extract the element values that fit the measurement data under various conditions, and then find the best values of the constants and coefficients in the equations that describe the characteristics of elements in the operation range of interest. Parameter extraction is not needed for some simple physical models because all of the element values can be calculated from the physical equations without extracting the constants and coefficients experimentally if the process parameters and the device geometries are given. With a physical understanding of the device operation, we can construct the equivalent

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circuit by choosing and arranging the proper elements. We may further develop the set of equations, each of which describes the behavior of each element. All of the elements and all of the constants and coefficients in the equations must ideally have the corresponding physical origins. However, some of them may be added by empirical experience to enhance the model accuracy. Note that with increasing the number of elements (and/or constants and coefficients), the model accuracy may be improved, but it scarifies the computational efficiency and complicates the parameter extraction. A good model should give satisfactory predictions within the target error tolerance with a minimum number of elements, constants, and coefficients. If the model is physically correct and the model parameters are extracted well, the values of the elements such as resistances, capacitances, and inductances should usually be frequencyindependent by definition. However, like the current source, transconductance and conductance with non-quasi-static"M orfrequency-dispersion40-"characteristics, some elements may be frequency dependent. We assume that the S-parameter measurement is made to extract the model parameters and the measurement at one discrete bias-frequency generates A" independent S-parameters. Since Sparameters are complex numbers, each S-parameter has a real part and an imaginary part, or magnitude and phase, ^measurement data is obtained for one set of S-parameter measurement. If we make measurements at / discrete frequency points without changing bias voltages, 1XY measurement data are generated. The parameter extraction is simply the procedure to find the best set of model parameters fitting the measurement data set. In principle, 1XY data points can be exactly fitted using 1XY independent elements. However, the number of the elements in the practical equivalent circuit is usually and should be much less than 2XY, and it is impossible to model all of the detailed physical phenomena. Besides, there always exist measurement errors. Due to these reasons, the model predictions cannot fit the measurement data perfectly. Thus, the best set of parameters does not give an exact fitting of the measurement data but best approximates it with minimum error under certain criteria. There are various methods to obtain the best set of model parameters and the methods can be classified into three categories: optimization-based approach,'2-" decomposition-based approach,4'-" and direct extraction:4"50 A. Optimization-based approach We assume that the properties of the model are accurately represented with its K characteristics. Let p = [Pi,P2,- • ;PN]Z RN be the vector of model parameters to be extracted, y' =LVj'>J;2'''"'>.>v']e RM > ' = 1,2,- -.AT , the vector of model performance of the i-th characteristics, and zl =[zt',z2',--,zM']e RM , i = \,2,---,K , the vector of measured performance of the »'-th characteristics. A general device model of the i-th characteristic can be written as y' = y'{p). Given the known device model y' = y'{p) for all i"s, pointwise error of the model can be defined as ej'(p) = y]'(p)-zj'{p), M

i = \,2,---,K, j = \,2,---,M . Given

a set of weights W = [w, vv2>- • -,wM]e R , i = 1,2,- • ,K, a scalar measure of partial model

75

962 M. Je, I. Kwon, H. Shin & K. Lee accuracy is assumed as

under the well-known least squares criterion. The global optimization is to find the parameter vectors p^ e R" that minimize the total error function e(p) given as

e(p) = ie'(p).

(2)

Various optimization techniques, such as a gradient-based Levenberg-Marquardt algorithm," a simulated annealing algorithm," and a simulated diffusion algorithm," are used to solve the given optimization problem, like (2). It is generally believed that global optimization is needed to extract the "best" set of parameters to fit the measured performances. However, it is also the most problematic one. The false convergence to a local minimum is frequent if the initial approximations to model parameters are not sufficiently accurate, and substantial computing resources might be needed. This approach cannot provide any intuition to model users. B. Decomposition-based approach Detailed knowledge of model functions is used to design measurements and transform data in such a way as to make the error functions e'(p) in (1) dependent only on a small subset of model parameters. If the parameter subset for different characteristics were disjoint, K independent regressions could be used instead of the global optimization problem or minimization of (2). Furthermore, simplifications of the model in properly selected parts of the characteristics are typically employed, resulting in reduction of the extraction problem to a sequence of some simple curve fittings. The advantage is a simple and fast extraction (with model simplification). Model users can also get some sense of the relationships between parameter values and generated model characteristics. However, because interactions between characteristics are ignored, quality of total fit suffers. Additional model simplifications reduce accuracy even further. C. Direct parameter extraction For some simple models with a relatively small number of parameters, an adequate set of parameters can be solved analytically. In many cases, like the decomposition-based approach, the model is simplified and solved to obtain the model parameters in the selected parts of the characteristics. Direct parameter extraction requires that the analytical expressions are formulated for a particular model based on the separation of model parameters and a few selected parts of the characteristics. The extracted results from direct parameter extraction are sensitive to the device models. Obviously, the measurement accuracy of the selected data points must be very high to reduce the extraction errors. The accuracy of the model with directly extracted parameters may not be the "best." In addition, the development cost involved in such an approach is high. However, the extraction procedure is very straightforward and needs very short computation time. The greatest virtue of this approach is to give users a useful intuition

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during the parameter extraction. In practice, the above three approaches are properly combined according to the features of the model. We can easily find cases where the decomposition-based successive curve fitting method and the direct extraction method are used together. Even if the decomposition-based method and/or direct extraction method are sufficient to extract the parameters, often the global optimization step is followed to enhance the model accuracy. 2.3. Modeling and parameter extraction strategies for a linear/reciprocal network

two-port

We will focus on the modeling and parameter extraction strategies for linear/reciprocal two-port networks in this section. Most of the passive devices can be treated as linear networks under normal conditions, or when too high voltage is not applied and too large current doesn't flow through the devices. A linear network doesn't have dependence on the applied bias voltages. On the other hand, a passive device is a reciprocal network because no amplifying activity takes place. Thus, most passive devices are modeled as linear and reciprocal networks in practice. The equivalent circuit of the linear/reciprocal device consists of linear/reciprocal passive elements, such as resistances, inductances, and capacitances. There is no transconductance and no transcapacitance because of the reciprocal characteristics and the passive elements in the equivalent circuit have no or negligible bias dependence because of the linear characteristics. For the linear network, there is no distinction between a small-signal model and a large-signal model. If the model is physically correct and the model parameters are extracted well, the values of the elements should usually be frequency-independent and bias-independent as the ideal resistances, inductances, and capacitances show neither frequency dependence nor bias dependence. In the physical model, the equations should not be functions of bias voltages or operation frequencies but of process parameters and geometric parameters of the passive devices only. The operation of passive devices is relatively simple although some parasitic components must be considered adequately. In addition, the number of significant technology parameters for passive devices is smaller than those of transistors and technology parameters, including the substrate doping concentration, are much simpler for passive devices than for transistors. As a result, there are only a few elements in the equivalent circuit, and the physical modeling based on equations is relatively easy. In most cases, parameters can be extracted directly or by using very simple curve fitting such as linear regression. For convenience, a simple optimization technique might be used without severe convergence problems. To characterize a passive device, S-parameter measurements are also made to extract the model parameters and evaluate the model accuracy. Due to the linear characteristics, however, the 5-parameter measurements at only one bias point sweeping the frequency is sufficient. The measurements generate four J-parameters - Sn, Sn, S2\, and S22 - as functions of frequency. Making a distinction between the real part and the imaginary part of each S-parameter, or the magnitude and the phase of each J-parameter, results in eight measured characteristics.

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However, considering that 5, 2 and S2i of the reciprocal network have the same value due to reciprocity," the number of independent measurement characteristics reduces to six. These characteristics, or the converted characteristics in the form of//, Y, or Z-parameters, are used to evaluate the model performance and extract parameters. As an example of passive device modeling and parameter extraction, we will briefly review the model and parameter extraction method for silicon on-chip spiral inductors presented in a paper by Yue and Wong:'8 Example.

Modeling and parameter extraction for a silicon on-chip spiral inductor."

4"Bfc:

(a) Layout of a square-type spiral inductor. MSM4-¥2 • M2

:S m m m ; L

i-V3

Oxide

Silicon substrate

B

(b) Cross-section along A-B. Fig. 2. Layout and cross-section of a typical on-chip spiral inductor. The on-chip inductors are fabricated using a microstrip transmission line wound in a spiral. In addition to the rectangular geometry as shown in Fig. 2, octagonal and circular geometries are also widely used to implement microstrip spiral inductors. Figure 2(b) shows a crosssectional view of the square-type spiral inductor. Multiple metal layers are often stacked and connected together through via to reduce the ohmic loss resulting from the resistivity of the metal line. A metal layer passing under the spiral is used to access the inner port (point B in Fig. 2(a)) of the inductor. Note that a lower-level metal (Ml) is not used in Fig. 2. By including Ml,

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we can decrease the coupling to the lossy substrate, which significantly degrades the inductor performance at high frequencies. Although the inductor is a device intended for storing magnetic field energy, inevitably parasitic resistances dissipate energy through ohmic loss, lowering the inductor quality factor Q appreciably. In addition, the parasitic capacitance limits the operating frequency of the integrated inductor drastically. Since these counter-productive parasitics limit the inductor performance, it is very important to include and model them accurately, as well as to predict the inductance value correctly. The physical model of a spiral inductor on silicon is v ~g. 3. The inductance and resistance of the spiral and underpass are represented oy aie series inductance, Ls, and the series resistance, Rs, respectively. The overlap between the spiral and the underpass allows direct capacitive coupling between the two terminals of the inductor. This feed-through path is modeled by the series capacitance, Cs. The oxide capacitance between the spiral and the silicon substrate is modeled by COT. The capacitance and resistance of the silicon substrate are modeled by C$i and Rsi-

1c

c£

..

Fig. 3. The lumped physical model of a spiral inductor on silicon."

Ls can be calculated as a sum of all the self and mutual inductances. The self inductance of a line with a rectangular cross-section and the mutual inductance between two parallel lines can be calculated from geometric parameters of lines using adequate formulas summarized by Graver." Based on Graver's formulas, Greenhouse developed an algorithm for computing the inductance of planar rectangular spirals." The Greenhouse method states that the overall inductance of a spiral can be computed by summing the self inductance of each wire segment and the positive and negative mutual inductance between all possible line segment pairs. When a conductor is subjected to a time-varying magnetic field, the eddy current effect occurs. Eddy currents manifest themselves as skin and proximity effects. In the case of the skin effect, the time-varying field due to the current flow in a conductor induces eddy currents in the conductor itself. The proximity effect takes place when a conductor is under the influence of a time-varying field produced by a nearby conductor carrying a time-varying current. The skineffect eddy current and the proximity-effect eddy current superimpose to form the total eddy current distribution. Regardless of the induction mechanism, eddy currents reduce the net current flow in the conductor and hence increase the AC resistance. The series resistance of each line segment caused by the skin effect can be expressed as

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(3)

W-ttf

where p, /, and w represent the resistivity, the length, and the width of the line, respectively, t^ denotes the effective thickness of the line and is defined as 5 (4) teff=S-(\-e-" ) where t is the thickness of the line and 5 is the skin depth, which is a function of frequency. Thus, in fact, Rs depends upon frequency. Despite that the skin effect is more severe than the proximity effect in typical cases, if we want to include the resistance resulting from the proximity effect, it can be computed using a numerical electromagnetic field solver and added XoRs. Based on the inductor's structure, both the crosstalk between adjacent turns and the overlap between the spiral and underpass contribute to Cs. However, since the adjacent turns are almost equipotential, the effect of the crosstalk capacitance is negligible. Therefore, for most practical inductors, it is sufficient to model Cs as the sum of all overlap capacitances, which is equal to S„

..2

Cs=n-w<

^ —

(5)

t0x,M2-M3

where n is the number of overlaps and taxMi-Mi is the oxide thickness between the spiral and the underpass. eox denotes the oxide permittivity. In this model, a MOS microstrip structure is modeled by a three-element network comprised of CM, Rs,, and CSi. Cox represents the oxide capacitance, whereas RSi and Q, represent the silicon substrate resistance and capacitance, respectively. The physical origin of RSi is the silicon conductivity, which is predominately determined by the majority carrier concentration. CSi models the high-frequency capacitive effects occurring in the semiconductor and its value increases with frequency. The substrate capacitance and resistance are approximately proportional to the area occupied by the inductor and can be approximated by Cox=yl-W^,

(6)

CSi=\-l-wCsub,

(7)

and Rsi=,

2 r

'•W-Gsub

(8)

where Csub and Gsub are capacitance and conductance per unit area for the silicon substrate. The factor of two accounts for the fact that the substrate parasitics are assumed to be distributed equally at the two ends of the inductor. Csub and Gsub are functions of the substrate doping and are extracted from measurement results using a simple optimization technique. With all the extracted parameter values, the small-signal characteristics of the equivalent circuit can be simulated using a CAD tool such as SPICE, and then compared to the measured results. For inductors, the quality factor calculated from the 5-parameters should also be

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verified to validate the developed model and parameter extraction procedure. The on-chip spiral inductor on the silicon substrate is one of the most complicated passive devices. We should consider and model the electromagnetic phenomena dominating the device operation correctly. We have reviewed an example" for this topic. The equivalent circuit composed of elements having their own physical origins was developed and the parameter values were extracted using several equations, a simple optimization, and a numerical solver, if it were needed. 2.4. Modeling and parameter extraction strategies for a nonlinear/nonreciprocal twoport FET Conventional RF FET's have been modeled as nonlinear/nonreciprocal two-port networks. The characteristics of FETs exhibit strong dependence on bias as it is intended to: for example, as the gate voltage increases and comes to exceed a certain threshold value, significant current starts to run through the channel. Thus, a FET is a nonlinear network and both a small-signal model and a large-signal model are needed to completely describe the device operation. The most important aspects of the FET features are amplification and switching operation. The amplification occurring in the FET implies that the FET must be a nonreciprocal network and thus needs transconductances and transcapacitances in its small-signal equivalent circuit. The transconductance represents the amplifying activity itself and the transcapacitance represents the phenomenon where the charge between two given nodes in the active device is controlled not only by the voltages across the two nodes but also by the voltages applied at other nodes, which is unlike the operation of a passive capacitor such as a simple parallel plate capacitor. The transcapacitance is indispensable in guaranteeing charge conservation, especially when the transient behavior of the FET is simulated.57*0 More about this will be discussed in 3-1. The device physics of FETs is not simple and a large number of process parameters and geometric parameters affect the operation. The equivalent circuit requires numeruous elements to describe the device behavior accurately and it is hard to develop equation-based physical models that provide sufficiently accurate predictions. Usually, the equations are augmented by several empirical constants or functional terms. Furthermore, for high-frequency application of the FET model, phenomena such as non-quasi-static effects and frequency dispersion effects must be modeled correctly. The modeling of these effects results in frequency-dependent elements" "•" in the frequency domain description, or equivalently, elements with delayed response in the time domain description. The amount of the delay is often represented by a time constant"" or numerically determined by solving partial differential equations." For most of the conventional RF FET models, the S-parameters are measured sweeping frequency and used to extract small-signal parameters. Since the FET has bias dependence, the S-parameter measurements are made at a set of bias points that effectively covers the operation region of interest and parameters are extracted at each bias point. The S-parameter measurements at each bias point generate four S-parameter characteristics - S,u S\2, S2I, and S22 - varying with frequency. No pair of these characteristics is identical when the device is on and operates in an active mode, while S,2 and S2, coincides when the device is off and passive. The elements in the equivalent circuit can be divided into two groups: the extrinsic parasitic

81

968 M. Je, I. Kwon, H. Shin & K. Lee elements and the intrinsic ones. The extrinsic elements are not related to the intrinsic FET operation, whereas the intrinsic elements represent the active operation of the intrinsic FET. For example, the interconnection parasitics and overlap capacitances are the extrinsic elements and the transconductance and gate capacitances are intrinsic ones. The different nature of the extrinsic elements and the intrinsic elements is often used to extract parameters more easily. The extrinsic elements have no or negligible bias dependence while the intrinsic elements have strong bias dependence. Taking advantage of this difference, it is common practice to apply zero drain bias to the FET,6' where the behavior of the intrinsic FET is much simpler. This coldFET method reduces the number of elements and the values of the remaining extrinsic elements can be extracted without difficulties. With the values of the extrinsic elements determined, then parameters related to the intrinsic FET are extracted to complete the parameter extraction. When the parameter values at an arbitrary bias point are needed during a simulation, the values are obtained using proper interpolation functions such as a polynomial function or a spline function. Also an interpolation function connecting the small-signal measurement data points is integrated to generate the large-signal parameters." Although a lot of parameters are extracted from the S-parameters, sometimes DC I-V characteristics are also measured to extract the DCrelated parameters." Until recently, somewhat different approaches have been applied to model MOSFET's and to extract MOSFET parameters until recently. This is because the MOSFET is a four-terminal, or three-port device and thus the approach used for the III-V FET could not be effective, on one hand, and because the high-frequency characteristics have not been as important for MOSFET's as for III-V FET's, on the other hand. It was only a few years ago that the high-frequency modeling of the MOSFET began to generate extensive interest. The modeling of MOSFET's has been mainly focused on the DC I-V and low-frequency C-V characteristics, and thus most MOSFET models are based on complicated large-signal equations describing the drain current and charge at each terminal - gate, drain, source, and body - as functions of terminal voltages.63 While the equations stem from the MOSFET device physics basically, many empirical constants, coefficients, and functional terms enhance the performance of the model equations. Typically, the DC I-V and low-frequency C-V characteristics are measured and a fairly complex extraction sequence follows to obtain reasonably good fitting to the measurement data. The extraction routine consists of decomposition-based extraction steps followed by global optimization steps with multiple targets to refine the model performance.6* Recently, as the high-frequency modeling of MOSFET's attracts growing interest, new approaches are being applied to MOSFET modeling and parameter extraction. In this section we have discussed the basic strategies of modeling and parameter extraction for FET's. We will review actual examples to make the concepts more tangible in sections 3 and 4, with emphasis on the modeling and parameter extraction of RF MOSFET's, or new approaches. Before examining the modeling examples, the requirements for successful RF FET modeling will be discussed to elucidate RF FET modeling.

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969

2.5. Requirements for RF FET modeling The requirements for RF FET modeling should be considered from several points of view: Which measurement method is the most reliable at high frequencies? What performances are important and should be predicted accurately in RF circuit and system design? What conditions should be satisfied to guarantee a robust and efficient circuit simulation? As mentioned previously, S-parameter measurements are the only practical method to characterize the high-frequency performance of devices, circuits, and systems. Thus a RF model and its parameter extraction scheme had better be based on a small-signal model because the Sparameter measurement is a small-signal measurement. Note that by the S-parameter measurement one obtains / ' (= dl/dV) and C (= dQ/dV) at the frequencies of interest. Making an accurate measurement and using the results for parameter extraction is desirable for successful modeling without doubt. Table 3. Required quantities for RF circuit design.

LNA • Bias ( / ) • Gain(/', C) • Linearity

(I",I'",C) • Thermal noise

Mixer

Oscillator

• Bias(/) • Conversion gain (7",C) • Linearity (/"",C)

• Bias (7) • Oscillation frequency (/\C) • Oscillation amplitude (/",/"',£) • Phase noise (///"noise)

Power Amp.

• Bias (I) • Gain(/', C) • Linearity

(I'",C)

Table 3 shows the list of quantities that a successful RF FET model must predict accurately for the important building blocks of RF systems, which indicates that RF models should be able to simulate /, /', /", and /'" very accurately. This is an extremely challenging task. Compared with low frequency analog circuits, a RF system requires much better accuracy of higher harmonics. Besides, the most efficient RF simulation is based on harmonic balance. Thus RF circuit simulation needs much higher-order continuity to improve numerical accuracy as well as simulation convergence speed. It can be easily inferred that starting from / ' modeling/extraction with the help of S-parameter measurement and then constructing /, /", and /'" is a more efficient way than starting from modeling and extraction of / itself. Because / should be uniquely determined for a given Vgs, Vds bias condition, where Vgs is the gate-to-source voltage and V& is the drain-to-source voltage, respectively, all of the / ' are not independent. Similarly, we measure C (=Q") first then extract parameters and construct Q. As all / ' are not independent, so are Q', such that Q is uniquely determined at a given bias condition. This is needed for charge conservation. One of the very important requirements for FET modeling and parameter extraction is that charge conservation is absolutely required for accuracy and simulation convergence. To accomplish this, we should model the current and charge of FET's as path-independent

83

970 M. Je, I. Kwon, H. Shin & K. Lee

quantities.57 In other words, after controlling voltages are allowed to vary and then return to their original values, the values of the current and charge should remain unchanged regardless of the variation history. Details on the charge conservation will be discussed in the next section. 3. Three-Terminal RF MOSFET Modeling and Parameter Extraction Examples As mentioned in 1.2, a MOSFET is a four-terminal device rather than a three-terminal device, unlike other RF FET's. In spite of this fact, in many works, the MOSFET has been modeled as a three-terminal device in the RF range. A three-terminal modeling approach makes the problem quite simple and there are good solutions to this simplified problem devised for conventional III-V FET's already. One wants to use the well-established RF modeling and parameter extraction methods for the conventional III-V FET's. The source and the body terminals of a MOSFET are tied together in many applications, and the MOSFET configured in this way can be handled as a three-terminal device without large errors. In this section, we will examine and discuss the three-terminal modeling approach of RF MOSFET's after the III-V FET modeling/parameter extraction techniques are introduced. 3.1. Brief review of small- and large-signal modeling and parameter techniques for III-V FET's

extraction

The differences between III-V FET models and MOSFET models result from the fact that III-V FET's were originally modeled for high-frequency applications whereas in the past MOSFET models were intended to simulate digital circuits and low-frequency analog circuits. Thus, in studies on III-V FET modeling/parameter extraction, high-frequency modeling issues such as de-embedding of pads and interconnection parasitics, non-quasi-static effects, and nonlinear characteristics including high-order harmonics have been intensively addressed for a long time. Many techniques were developed to address the high-frequency modeling and parameter extraction problems efficiently, and unique features of III-V models were formed during the process. For MOSFET's, physical models that describe the device behavior with a set of equations have mostly been based on large-signal model. This is because it provides the necessary accuracy as well as computation efficiency required by the digital and low-frequency analog VLSI. In contrast to this, it is not difficult to find table models for III-V FET's containing a collection of small-signal measurement data for later retrieval. Actually, the Root model, one of the most widely accepted III-V FET models, is a table-model. There are several reasons why the table models have been applied to III-V FET circuit simulation extensively. The table model can provide quite accurate predictions required for high frequency circuit design without a complete understanding of the physical mechanisms of problematic issues such as non-quasi-static effect, nonlinear characteristics, and frequency dispersion effect, especially for III-V FET's. This is possible because the table model is basically based on measurement; thus, if measurements are made carefully and proper data handling is guaranteed, relatively accurate modeling results can be obtained.

84

MOSFET Modeling and Parameter Extraction for RF IC's 971 Another reason to use table models for III-V FET's is that in many cases, the simulation of RF circuits with III-V FET's has been performed using a harmonic balance simulator, which simulates the circuit performance in the frequency-domain. This harmonic balance simulation is most efficient in simulating circuits including components that have frequency-dependent characteristics. The modeling approach using a set of data measured varying frequency is a very natural one considering the harmonic balance simulation. The other type of circuit simulators are time-domain circuit simulation programs such as SPICE, which has been very popular for MOSFET circuit simulations. For this type of simulation, equation-based physical modeling is a natural approach because the equations can give the current value at each branch as a function of node voltages varying with times. There also exist several III-V FET models for the timedomain simulation such as the Curtice model," the Staz model,66 the Materka model,6' and TriQuint's own model (TOM),68 all of which are based on physical and empirical equations. Popular models for MOSFET's include the BSIM3v3 model,6' the MOS Model 9,6' and the EnzKrummenacher-Vittoz (EKV) model.™ Although table models can provide accurate results for high-frequency circuit simulation, they have problems and shortcomings. In table models, interpolation functions are used to generate continuous data at points between measurement data points. The continuity of the measured characteristics is guaranteed by using interpolation, but the first-order and higherorder derivatives of the characteristics might not be continuous if a proper interpolation function is not chosen. Discontinuities increase the time to converge and even make the simulation fail to converge. Furthermore, because the measurements always contain some errors, the numerical integration of the measured data to find the current or charge values might cause a charge non-conservation problem. However, the most important disadvantage of the table model is that the model is not predictive. This is simply because the table model is not based on device physics. The table model is only valid for devices under the same conditions as the device on which actual measurements were made. Performance of devices with different dimensions or technology parameters cannot be predicted effectively. Thus, all devices with different dimensions used in the circuit should be measured and it is practically impossible to analyze the yield of IC's accounting for process variations. We will now examine examples of RF III-V FET models and parameter extraction methods. The conventional small-signal equivalent circuit for III-V FET and its well-known parameterextraction method will be introduced, and the principles of nonlinear active device modeling studied by Root and Hughes will be reviewed with a resulting physical/empirical model topology.

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M. Je, I. Kwon, H. Shin & K. Lee

6o-'rn

Fig. 4. Conventional small-signal equivalent circuit of a 1H-V FET.

The conventional small-signal equivalent circuit of a III-V FET is shown in Fig. 4. Dambrine, Cappy, Heliodore, and Playez have suggested an efficient method to determine the parameters of this equivalent circuit directly from the measured 5-parameters." Basically, this equivalent circuit can be divided into two parts: • the intrinsic elements, gm, gjs, Cgs, Cg-^vw-r

Fig. 5. Small-signal equivalent circuit of a cold FET.71 The series parasitic elements can be extracted using these expressions. Ls can be extracted from Im(Zl2), Lg from Im(Zn), and Ld from In^Z^). In addition, the linear extrapolation of the plot Re(Zn) versus \llg to the ordinate gives the value of Rs + Rg + RJ3. Therefore the Zparameters' real parts provide three relations between the four unknowns, R„ Rg, Rd, and Rc. At this step, an additional relation is needed to separate the four unknowns. This additional relation can be the value of the sum Rs + Rd determined by the conventional method using the real part of Z22 and the concept of channel opening factor," the value of Rg provided from the resistance measurement, the values of Rs and Rd provided by DC measurement, or the value of Rc if the channel technological parameters are known. Therefore, the determination of the four parameters, Rs, Rg, Rd, and Rc, does not constitute a real problem since some redundant relations are available in most cases.

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M. Je, I. Kwon, Hr Shin & K. Lee

B. Determination of the shunt parasitic elements Intrinsic device

Fig. 6. Small-signal equivalent circuit of a cold FET at gate voltage lower than the pinch off voltage.71

At zero drain bias and for a gate voltage lower than the pinch-off voltage Vp, the intrinsic capacitance (i.e., under the gate) cancels, as does the channel conductance. Under these biasing conditions, the FET equivalent circuit is shown in Fig. 6. In this figure, Cb represents the fringing capacitance due to the depleted layer extension at each side of the gate. For frequencies up to a few giga-hertz, the resistances and inductances have no influence on the imaginary part of the /-parameters, which can be written lm{Yu) = MCpg+2Cb)

(13)

Im(yI2) = Im(y2I) = -yfflCA

(14)

Im(y22) = yo»(C /x/ +C A ).

(15)

Thus, the three unknowns, Ch, Cpg, and C^, can be calculated using (13)—(15). C. Determination of the intrinsic Y-matrix The remaining problem is to determine the y-matrix of the intrinsic device from experimental data. When all the extrinsic elements are known through the previous steps A and B, the following procedure can be used to solve this problem: (a) transformation of the as-measured S-parameters to impedance (Z) parameters and subtraction of Lg and L,t that are series elements; (b) transformation of Z to /-parameters and subtraction of Cpg and C^ that are in parallel; (c) transformation of Yto Z-parameters and subtraction of Rg, Rs, Ls, Rd that are in series; (d) transformation of Zto y-parameters that correspond to the desired matrix. Therefore, the determination of the intrinsic admittance matrix can be carried out using some simple matrix manipulations with the known values of extrinsic elements.

88

MOSFET Modeling and Parameter Extraction for RF IC's 975 D. Extraction of the intrinsic elements Since the intrinsic device exhibits a n topology, it is convenient to use the admittance (Y) parameters to characterize its electrical properties. These parameters are Yu= 11

a>2R(CA+Cjl/).

(23)

Expressions (20)-(23) show that the intrinsic small-signal elements can be deduced from the Yparameters as follows: Cgli from Yn, Cgs and /J, from Yu,gm and rfrom Y2X, and lastly, gds and Crfs from y22Through steps A to A all the elements of the FET shown in Fig. 4 are extracted in a direct manner. This method is now well known and has been widely used to extract small-signal parameters of III-V FET's with or without modifications. The extraction of small-signal model parameters is used in the generation and verification of large signal models. The equivalent circuit and parameter extraction procedure introduced above are only for small-signal modeling. For obtaining the corresponding large-signal model, additional large-signal model construction method should be devised. However, as the equivalent circuit in Fig. 4 does not contain a complete set of intrinsic capacitances for charge conservation, we cannot build a successful large-signal model guaranteeing the charge conservation from this small-signal model. Note that in this work, all the parasitics including C w and Cpj are extracted without using separate test fixtures. However, it is also common practice to determine and de-embed pad parasitic elements using separate patterns: open and short patterns for the two-step method," and open, short, and thru patterns for the three-step method." Root and Hughes are the pioneers who addressed the possible problems of equivalent circuits such as that shown in Fig. 4 and presented the principles of nonlinear active device modeling for circuit simulation in SPICE and harmonic balance programs, motivated by an examination of three common problems of standard nonlinear GaAs MESFET models." Here

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M. Je, I. Kwon, H. Shin & K. Lee

we will focus on the first and second problems and their solutions, which introduce the concepts of a voltage controlled charge source (VCQS) and a transcapacitance. These concepts are so important that we review the original ideas of Root and Hughes here. The first problem is that simulations done in large-signal analysis don't fit the measured imaginary parts of the v-parameters versus bias. On the other hand, good fits to the measurements can be obtained in linear (small-signal) analysis. The solution is to use nonlinear VCQS elements in place of two-terminal capacitors in the nonlinear model. A VCQS is a reactive analogue of the familiar voltage controlled current source. This improves the accuracy and convergence properties of the large signal reactive FET model. Linearizing the resulting equations produces an accurate small-signal model, consistent with the large-signal simulations in the appropriate limit. Linearizing a VCQS element produces another unfamiliar quantity, the transcapacitance. A transcapacitance is a reactive analogue of a transconductance. G O

SO

( ^

OD

I* Fig. 7. Voltage controlled current source element.

The nodal equations solved by SPICE in transient (large-signal) analysis are given in (24). There are similar equations, written in the frequency domain, which characterize the harmonic balance based circuit simulators." It is possible in principle to formulate active device models starting directly from the quantities of (24). However, it is often much easier to begin from basic nonlinear elements, and use them as building blocks to construct full models.76 Ii{V\{t\--;VN{t)) + ^-Qi{V,(t),--;VN{t)) = Q, i = \,--,N where N = number of nodes. (24) at Corresponding to each of the terms of the left hand side of (24), there is a nonlinear branch element which we consider. The first is a familiar element, the voltage controlled current source (VCCS). It defines a branch current as a nonlinear function of one or more controlling voltages. A schematic of a three-terminal VCCS element is given in Fig. 7. This example can be considered the most elementary nonlinear model of a FET. The model drain-source current Ids depends on the gate-source voltage Vgs as well as the drain-source voltage Vds. Ifi'UiVr'V*) (25) A nonlinear element related to the second term on the left hand side of (24) is the VCQS. It is a multi-terminal reactive analogue of a VCCS. The VCQS defines a branch charge as a nonlinear function of one or more controlling voltages. The branch current is defined to be the total time derivative of the charge. A schematic of a three-terminal VCQS element is given in Fig. 8. The charge associated with the gate-source branch Qgs depends on the gate-source voltage Vgs and also on the drain-source voltage V^ as given in (26). This is a generalization of

90

MOSFET

Modeling and Parameter

Extraction for RF IC's

977

the familiar two-terminal capacitor, where the charge associated with a branch depends only on the single voltage difference across the element. The branch current of a VCQS element is defined, in (27), by the total time derivative of the charge. The associated reference direction for current to flow is chosen to be from the positive to the negative sign of the symbol in Fig. 8. Notice that the gate-source branch current of this element has a term proportional to the time derivative of the drain-source voltage. The coefficient of proportionality cQsJdVds is a 'so a function of Vgs and Vds. This is called a transcapacitance Cm, which is a reactive analogue of the transconductance. (26) Qgs=Qgs(vgs,vds) jVCQS ' gs

=

-

d_Q

_

i. « g s

df

= c„

dt

dQgs dVgs dv„gs dt •+c„

d

Qg* dVds

dvH, dt

dKis dt

(27)

G Q

o„© SO

OD

Fig. 8. Voltage controlled charge source element.

The model current /rfs of the VCCS nonlinear element of Fig. 7 is plotted versus the two controlling bias voltages Vgs and Vds in Fig. 9. Ids describes a two-dimensional surface. The slope of the Ids surface in the direction parallel to the Vgs axis defines the model transconductance gm(Vgs, V&). The slope of this surface in the direction parallel to the V^ axis defines the model conductance gds(Vgs> VYds) = -dI"s BV. gs gds(Vgs,V*)

91

=

2Lt dV,ds

(28) (29)

978 M. Je, I. Kwon, H. Shin & K. Lee

Fig. 9. Model current /* vs. two controlling bias voltages V& and V&. 2 Taking the partial derivative of (28) with respect to Vds, and noting 8 L

dlL

ur dVgs 0,dV, ds we obtain a relationship between the model conductance and model transconductance given in (30). A mathematically equivalent statement (derived using Stokes's Theorem) is given by (31). The indicated contour is any closed loop on the surface defining the model current Jds.

w*wv

5K„,

dV„

< j k Wv. V* )dVgs + gds (Vgs, Vds )dVds ]= 0

(30)

(31)

A key consequence of (30) and (31) is that the model conductance gaJi,Vgs, Vds) and the model transconductance gm(Vg$, Krfs) are not independent functions of bias! Extraction of model gm and gds separately versus bias, which is standard practice in linear analysis, can result in a path-dependent model Ids. That is, the right hand side of (31) may be different from zero. A nonzero result for the right hand side of (31) represents the net (positive or negative) current supplied by the VCCS to the circuit after its controlling voltages are allowed to vary and then return to their original values. This is not a problem in small-signal analysis, where the bias point remains fixed, but it is extremely dangerous in large-signal analysis. Disaster can result in large-signal simulations even if the right hand side of (31) is only slightly different from zero. Under the conditions of large signal periodic input waveforms, the FET model controlling voltages can traverse closed loops in voltage space at the rate of billions of times a second (at microwave frequencies). The error (excess current) generated with each loop traversal accumulates, ultimately becoming large enough to cause the simulation to crash, or else cause a spurious result, such as a runaway voltage on a capacitor plate elsewhere in the circuit. The two properties of path independence and time (frequency) independence of current modeled by VCCS element are hallmarks of a network variable. Exactly the same considerations apply to the network variable charge as applied to the network variable current. The model charge Qgs of the VCQS nonlinear element of Fig. 8 is

92

MOSFET Modeling and Parameter Extraction for RF IC's 979 plotted versus the two controlling bias voltages Vgs and Vj, in Fig. 10. Qgs describes a twodimensional surface. The slope of this surface in the direction parallel to the Vgs axis defines the model capacitance Cgs(Vgs, Vds). The slope of the Qgs surface in the direction parallel to the V& axis defines the model transcapacitance Cm(Vgs, Vds). This is precisely the quantity we met in (27).

Fig. 10. Model charge Q^ vs. two controlling bias voltages VJS and V&. The statement of path independence of the model charge is given in (32). An equivalent statement is given by (33). Mathematically, (32) and (33) show that Cgs(Vgs, Vds) and Cm(Vgs, Vds) are components of a conservative vector field. #

h* (Vs. • V * )dVss + Cm (Vgs, Vds )dVds ] = 0 8Ces

dC„

(32) (33)

dV„ dV„ ds "• gs Again the important point is that the model capacitance and model transcapacitance are not independent functions of bias! Specifying the model capacitances and transcapacitances separately versus bias can result in a path-dependent model Qgs. That is, the right hand side of (32) may be different from zero. Such a situation can result in the same fatal errors as described for the VCCS case. The transient (large-signal) analysis simulations don't fit the ^-parameters versus bias data well. On the other hand, good fits to the measurements can be obtained by using a simple AC (small-signal) model. However, the poor fit to the data in the transient analysis (TA) mode means the TA and AC simulations are inconsistent. Such inconsistencies mean AC simulations over a wide range of bias, no matter how accurate, cannot be used to reliably extrapolate the true large signal model performance. The solution to this problem is to start directly from three-terminal VCQS elements such as Qgs(Vg$, Vds) and QgdiVg,, Vds). Despite the innocent appearance of capacitor symbols in the equivalent circuit of the FET model, the intrinsic capacitors are not two-terminal capacitors. A two-terminal capacitor has a capacitance (and also a charge) that depends only on the single

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M. Je, I. Kwon, H. Shin & K. Lee

voltage difference between the terminals. However, the intrinsic capacitors and charges in

FET's depend on two voltage differences. The consistency between TA and AC modes can now be guaranteed by taking the AC admittance matrix to be given by the linearized TA equations. G

o

G O

9ds -JvW-

9ds SO-

•©•

-OD

9m

(b)

(a)

Fig. 11. Time delay implementation in linear analysis: (a) using a frequency dependent element (b) using a transcapacitance.

The second problem is that large-signal FET models do not simulate time delays of the FET. In linear analysis, time delays are typically introduced via the multiplicative frequency dependent factor gme~J°". In a linear FET model, this factor often appears with the transconductance element at the output. The key point is that in linear analysis only, quantities such as conductances and transconductances can be assigned arbitrary frequency dependences. The objective is to try to represent time delays, at least approximately, using the nonlinear elements. We can start from the standard expression gme'i 10 GHz) cannot be explained.'-'2 On the other hand, without the intrinsic body node, the substrate parasitics cannot be modeled physically. The Rsub connected in series with the drain junction capacitance in Fig. 16 may be just enough to fit the measured K22 or S22 up to about 10 GHz, but its location in the equivalent circuit is not physically correct.81-82 As a result, it is difficult to make the value of Rsub in this model be scalable and predictable from the technology parameters. Above all, all the models examined in this section are three-terminal models, and thus their application is limited to a specific circuit configuration. 3.3. KAIST three-terminal model with simple and accurate parameter extraction technique

Drain

6 Source Fig. 17. Small-signal equivalent circuit of a three-terminal MOSFET model without an intrinsic body node.

We have proposed a simple and accurate parameter extraction method for a small-signal MOSFET model including the substrate-related parameters and a complete set of non-reciprocal capacitors.83 This work focuses on a charge-conserving and physical small signal equivalent

100

MOSFET Modeling and Parameter Extraction for RF IC's

987

circuit of the RF MOSFET and an accurate parameter extraction approach by K-parameter analysis from measured S-parameters. The small signal equivalent circuit of a three-terminal MOSFET model is shown in Fig. 17. Non-reciprocal capacitance and substrate-related parameters are included in the model. In a three-terminal configuration, the source-to-body junction capacitance Cjs and the source-tobody spreading resistance Rsubs can be excluded if the intrinsic body node is assumed to be short-circuited to the source directly. This approximation makes a simple direct extraction of all the elements possible. However, Cjd and Rsubd extracted with this assumption do not provide physically correct values, although they provide excellent fit of Y-n up to 10 GHz, as pointed out in 3.2.80 Four intrinsic capacitances, Cgs, Cgd, Cdg and Csd, are required for the three-terminal model. The overlap capacitances are merged with the correspondent intrinsic capacitances. Cgd and Cdg are the two non-reciprocal capacitance components for the three-terminal model.57*0 The capacitive effect of the drain voltage on the gate charge is represented by Cgd, and the capacitive effect of the gate voltage on the drain charge is represented by Cdg. In general, Cdg is different from Cgd. C„ = Cdg - Cgd is a transcapacitance representing the different effect of the gate and the drain on each other in terms of charging currents, just as gm is a transconductance representing the different effect of these two terminals on each other in terms of transport currents. If Cgd and Cdg are set to be equal, as in most conventional models, large error can be introduced since charge conservation does not hold. In the AC simulation, the transcapacitance has to be included for accurate prediction of the transadmittances v 2 i and Yn. Without the nonreciprocal gate-drain capacitance, it is impossible to model I m ^ i ) and I m ^ u ) accurately at the same time. In the case of a four-terminal model with a separate substrate terminal, a similar approach can be extended by including other non-reciprocal capacitances. The resistance Rg represents the effective gate resistance that consists of the distributed channel resistance and the gate electrode resistance." These effects are approximated by a single effective lumped gate resistance, as shown in the equivalent circuit of the MOSFET shown in Fig. 17. Direct extraction using a linear regression approach is performed by K-parameter analysis on the equivalent circuit of the MOSFET for high frequency operation. In our approach, an optimization process, which may have uncertainties in obtaining physical parameters, is not required. The small-signal equivalent circuit shown in Fig. 17 can be analyzed in terms of Yparameters as follow: ja>(Cgs + Cgd) a>2 (Cgs + Cgd )2 Rg + ja>(Cgs + Cgd) "

\+2Cgd (Cgs + Cgd )Rg - jwCgd

- jwCgd

y 12

Yix

\+a>2{Cgs+Cgd)2Rg2

\+jco{Cgs+Cgd)Rg 1 + MCgs 2

+ Cgd )Rg

8 m -°> Cdg(Cgs

1 + ja(Cgs

+Cgd)Rg l+

+ Cgd )Rg -jccCdg-jcogmRg{Cgs+Cgd)

2

a, (Cgs+Cgd?Rg2

101

988

M. Je, I. Kwon, H. Shin & K. Lee

y22 -_gds

2

*** \+jojCjdRsubd

+

+j(oCsd

**» \ + jcoCjdRsubd

= gdj +

**

, (Cgs+Cgd)Rg

s

"

«

a

u^.,^r

j.r

+Cgd)R2g

2

\ i

(54) For operation frequency up to 10 GHz, by using the assumption that a2 (Cgs + Cgd)2 Rg2 « 1, the K-parameters can be approximated as follows: y,, * w2 (Cgs +Cgd)2Rg+ jo>(Cgs + Cgd)

(55)

2

Yl2 * -w Cgd(Cgs + Cgd)Rg - jcoCgd

(56)

»2i * 8m ~0}2Cdg{Cgs +Cgd)Rg -jwCdg -jojgmRg(Cgs+Cgd)

(57)

2 >-22 * * * +,°)C2*2S:bd 1^ CgdCdgRg \+a> Cjd Rsuhd JWCjd

i ,

l + O) 2C^Jd 2 DRsubd2

+

a>2gmR2gCgd(Cgs +Cgd)

+ jaCsd + jcoCgd + jcogmRgCgd - ja>>CgdCdg(Cgs + Cgd)R2g.

(58) The validity of the assumption that a} (Cgs + Cgd)2 Rg2 « 1 will be checked after each parameter is extracted. All the components of the equivalent circuit are extracted by the Yparameter analysis and analytical equations are derived from real and imaginary parts of the Yparameters. gm is obtained from the ^-intercept of Re(K21) versus of and gds is extracted from the ^-intercept of Re(y22) versus of, at the low frequency range. Rg, Cgd, Cgs and Cdg can be obtained by (61H74).

< 59 >

gm=Re(r2.)Uo /? g =Re(y n )/(Im(K n )) 2

(61)

Cgd=-\miXxl)loj

(62)

Cgs=(lm(Yn)

(63)

+ lm(Yn))/co

Cdg =-lm(Y2l)/o>-gmRg(Cgs+Cgd)

(64)

For the extraction of substrate components Rsuhd and Cjd, Ysub is first defined as follows: ysub = hi ~gds ~-.—

«i

101-

1.S

-.

102-

A,..

subd fl

-»

—I

'

1

1.0

2.5

(a)

—•

—•

B-

r~

(

•—

a

r-

1.5

2.0

(b)

Fig. 22. The drain-bias dependence of small signal parameters for an n-MOSFET having 100 fan width and biased to Vjs= 2 V: (a) capacitances, (b) Rs and /?»«. In Fig. 22, drain-bias dependence of the extracted small-signal parameters for the nMOSFET biased to Vgs= 2V\s shown. The drain-bias dependence of the extracted capacitances are shown in Fig. 22(a). The vertical line at Vds = 0.81 Kis the boundary between the linear and saturation regions. When the transistor is biased in the linear region with low Vds, the intrinsic behavior of the transistor becomes symmetric in terms of drain and source. Thus the intrinsic capacitances Cgsi and Cgdi are almost the same at V^ = 0 V. In Fig. 22(a), the difference between Cgs and Cgd at Vds = 0 Vis due to the parasitic Cgb which is included in the Cgs. Cgb of the gate contact pad component and the poly-to-well capacitance in the field oxide become the major parts of the parasitic capacitance. At V& = 0 V, Cdg is the same as Cgd and Cm = 0. Cm increases with J ^ in the linear region and is almost constant for high Vds in the saturation region. Csd becomes negative in the linear region because the raising the drain voltage will increase the effective reverse bias at the drain end and will cause the magnitude of the inversion layer charges to decrease. In the saturation region for higher Vds, the gate-to-drain capacitance Cgd is almost the same as Cgdo. The extracted capacitance parameters correctly model the bias dependence of intrinsic capacitance. Because the conventional C-V measurements using large C-V test structure are less sensitive to extraction of small capacitance values in short-channel

106

MOSFET

Modeling and Parameter

Extraction for RF IC's

993

RF MOSFET's, measuring S-parameters of the RF MOSFET in the high frequency GHz range is a better alternative. The proposed parameter extraction method can be applied to accurate intrinsic capacitance modeling at GHz operation. The extracted Rg and RsuM with drain bias are shown in Fig. 22(b) and they are almost constant with drain bias.

20 -

W / L * 100/0.35 V*-2V ———_

W/Ls 100/0.35 V. - 2 V • On,

/

(0

•

-

Extraction rwult DC inm urwmnt

Extraction raault DC measurement

E _? 20

/ 8*. \

i . .a

(a) Fig. 23. gm and g& extracted from the S-parameter measurement and those obtained from DC measurement: (a) varying the gate bias for Vis = 2V, (b) varying the drain bias for Vg, = 2 V.

In Fig. 23, gm and gds extracted from the S-parameter measurement and those obtained from DC measurement are compared. Extracted gm and gds as a function of Vgs with gate bias for Vds -2 V are shown in Fig. 23(a), and extracted gm and g* as a function of Vj, with drain bias for Vgs = 2 V are shown in Fig. 23(b). They match very well with each other, verifying the validity of the equivalent circuit and the extraction method. The extraction results correctly modeled the bias dependence of gm and && in the linear and saturation regions. Figure 23 shows that RF conductance data agree well with those from derivatives of measured DC I-V characteristics. This has very important implications, that a large-signal model for I-V characteristics is accurate enough to be used for DC, low-frequency analog, as well as RF circuit simulations. 4. Four-Terminal RF MOSFET Modeling and Parameter Extraction We have examined several trials to model the RF MOSFET as a three-terminal device. As mentioned previously, the three-terminal models are only valid for devices with source-body tied configuration and the complex signal coupling through the intrinsic body node cannot be described. To overcome these important limitations, four-terminal modeling of the RF MOSFET is required as essentially it is a four-terminal device. In this chapter, four-terminal modeling examples will be reviewed.

107

994

M. Je, I. Kwon, H. Shin & K. Lee

4.1. Equivalent-circuit-based

modeling approaches

1

OB

Fig. 24. Complete small-signal model for a four-terminal intrinsic MOSFET proposed by Bagheri and Tsividis.37

In Ref. 37, Bagheri and Tsividis presented a four-terminal physical model of a MOSFET with the equivalent circuit shown in Fig. 24. It includes a "transmission-line effect" which is another name for the non-quasi-static effect, and its parameters are given by functions of terminal voltages, process parameters, and device geometry. The parameters vary continuously in value with bias from strong, through moderate to weak inversion. The equations were derived for the long-channel device using a charge-sheet approximation. Two differential equations the current transport and charge continuity equations -with appropriate boundary conditions were solved using iterative methods for obtaining the small-signal terminal currents. In general, each terminal current has the form of a power series numerator over a common denominator series. From this result, the small-signal /-parameters can be calculated using the definition Y

»P =

L

(69)

v

fr

K=O,y*0

where the subscripts a, fl, and y can stand for drain (d), gate (g), and substrate (b). The Yparameters that were evaluated and truncated to second order in Ref. 37 are shown below. 1 + jcoa{ Y (70) gs = -J®0* D(ja>) 1 + jcoa2 Y (71) gd = -JvCgd D(jco) 1 + j coai (72) hs = -JoCbs D{ja>) 1 + jcoa2 Y 0 (73)

M = -J*" ,bd'

108

MOSFET Modeling and Parameter Extraction for RF IC's

-JoC.«*"

igb

*m

Sti

(74) D(jo>)

\-jcoa4-U

r10

Frequency (GHz)

Fig. 2 The model without the substrate resistances cannot predict the measured Yu characteristics.

Another important component that almost all of the compact models implemented in commercial circuit simulators did not account for is the substrate resistance. Actually, substrate-coupling effects through the drain and source junctions and these substrate resistance components play an important role in the contribution to the output admittance so the inclusion of these substrate components in a RF model is needed. This effective admittance of the substrate network can contribute 50% of the total output admittance.9 As shown in Fig. 2, a MOSFET model without the substrate resistance components cannot predict the frequency dependency of the output admittance of the device so the simulation with such a model will give misleading simulation results of the output admittance when the device operation frequency is in gigaherze range. 1.3. The status of the RF MOSFET modeling Compared with the MOSFET models for both digital and analog application at low frequency, compact models for HF applications are more difficult to develop due to the additional requirements of bias-dependence and geometry scaling of the parasitic components as well as the requirements of accurate prediction of the distortion and noise behavior. A common modeling approach for RF applications is to build sub-circuits based on the intrinsic MOSFET that has been modeled well for analog applications.,0, "' 2 The accuracy of such a model depends on how to establish sub-circuits with the correct understanding of the device physics in HF operation, how to model the HF behavior of intrinsic devices and extrinsic parasitics, and how to extract parameters appropriately for the elements of the sub-circuit. A reliable and physics-based parameter extraction methodology based on the appropriate characterization techniques is another important

124

MOSFET Modeling for RF IC Design 1011 portion of the RF modeling to determine the model parameters and generate scaleable models for circuit optimization. Currently, most RF modeling activities focus on the above subcircuit approach based on different compact MOSFET models developed for digital and low frequency analog applications, such as EKV, 13 MOS9, 6 and BSIM3v3.5 Several MOSFET models for RF applications have been reported.11,12'1415 With added parasitic components at the gate, at the source, at the drain and at the substrate, these models can reasonably well predict theHF AC small signal characteristics of short channel (SB

RSI:UB

B Fig. 7 (e) One resistor substrate network.1

(Gm-j>*Cm)K»

r~

-e— -e— -e-

(QK+j»CsDi)vas/ ^/W

O

v

(Gmb-j»Cmb) s#

RDSB

Fig. 8 An equivalent circuit with both intrinsic and extrinsic components.

132

MOSFET

Modeling for RF IC Design

1019

2.2.4. Implementation ofa subcircuit RF model in circuit simulators The equivalent circuit shown in Fig. 8 can be used to understand and analyze the HF behavior of a MOSFET. In order to implement this equivalent circuit in a Spice simulator, a subcircuit approach has to be used. In the subcircuit, the characteristics of the intrinsic device is described by a MOS transistor compact model implemented in the circuit simulator, and all the extrinsic components have to be located outside the intrinsic device, so that the MOS transistor symbol in the subcircuit only represents the intrinsic part of the device \ For example, (1) the source and drain series resistors have been added outside the MOS intrinsic device to make them visible in AC simulation (in most compact models, since the internal series resistances are only "virtual" resistances embedded in the I-Vmodel to account for the dc voltage drop across the source and drain resistances in calculating the drain current, they do not add any poles and are therefore invisible for AC simulation); (2) The gate resistance should be added to the subcircuit model (usually RG is not part of the MOS compact model, but plays a fundamental role in RF circuits as we discussed in Section 1); (3) The substrate resistors should be added to account for the signal coupling through the substrate; (4) Two external diodes should be added in order to account for the influence of the substrate resistance at HF (the source-to-bulk and drain-to-bulk diodes are part of the compact model but their anodes are connected to the same substrate node, which will short the AC signal at HF12 so the diodes internal to the compact model should be turned off). With the above considerations, a subcircuit that represents a RF MOSFET in a circuit simulator can be given in Fig. 9. Note that the intrinsic substrate node should be connected at some point along the resistor RDSB, but simulations have shown that connecting the intrinsic substrate to the source or the drain side has little influence on the simulated AC parameters. In some RF models,9-" the intrinsic substrate has been connected to the source side of in order to save one node and one component for the subcircuit model. Two external overlap capacitances, CGSP and CGDP as shown in Fig. 9, with bias dependence can be added but this is not always required, depending on the compact model used. For example, BSIM3v3 accounts for bias dependent overlap capacitances that, if extracted correctly, have shown a sufficient accuracy. However, by adding these external capacitances, the inaccuracies of the intrinsic capacitance model appearing for short-channel devices can be corrected. In the next section, we will discuss the modeling of these intrinsic and extrinsic components shown in Fig. 8. 2.3. Modeling of the intrinsic MOSFET Compared with the MOSFET modeling for digital and low frequency analog applications, the HF modeling of MOSFETs is more challenging. All of the requirements for a MOSFET model in low frequency application, such as continuity, accuracy and scaleability of the

It may include the overlap capacitances at the source, at the drain and at the bulk, depending on the intrinsic compact MOSFET model used in the implementation.

133

1020

Y. Cheng

DC and capacitance models should be maintained in a RF model." In addition, there are further important requirements to the RF models: (1) The model should accurately predict bias dependence of small signal parameters at HF operation; (2) The model should correctly describe the nonlinear behavior of the devices in order to permit accurate simulation of inter-modulation distortion and high-speed large-signal operation; (3) The model should correctly and accurately predict HF noise which is important for the design of, e.g., low noise amplifiers (LNA); (4) The model should include the NQS effect so it can describe the device behavior at very high frequency range in which NQS effect cannot be ignored for a model to behave correctly and will degrade the device performance significantly; (5) The components in the developed equivalent circuit model should be physics-based and geometrically scaleable so that the model can be used in predictive and statistical modeling for RF applications.

Core/Intrinsic MOSFET • Ro

CGSPJ_ • Rs

J:

-AA/V

_iL.

• .I^J_CGDP

JV CSB

l—AA/V RSB

' Substrate Network /

W\r RDSB

B

AAAr-i RDB

B

fig. 9 A subcircuil that can be implemented in a circuit simulator.

To achieve the above, the model for the intrinsic device should be derived with the inclusions of most (if not all) important physical effects in a modern MOSFET, such as normal and reverse short-channel and narrow width effects, channel length modulation, drain induced barrier lowering (DIBL), velocity saturation, mobility degradation due to vertical electric field, impact ionization, band-to-band tunneling, polysilicon depletion, velocity overshoot, self-heating, channel quantization." Also, the continuities of small signal parameters such as transconductance Gm, channel conductance G&, and the intrinsic trancapacitances must be modeled properly. Many MOSFET models, including MOS9,6 EKV,20 and BSIM3v35 have been developed for digital, analog and mixed signal

134

MOSFET

Modeling for RF IC Design

1021

applications. Recently, they all are extended for use in RF applications. We do not present any new models in this work. Instead, in the following, we give a brief discussion on the concept of deriving a compact model of the intrinsic device for RF applications. A compact model includes many mathematical equations for different physical mechanisms. The most important and essential parts are DC and capacitance models. It has been found that the model accuracy in fittings of HF small signal parameters and large signal distortion of a RF MOSFET is basically determined by the DC and capacitance models.21 2.3.1, DC model In general, a DC MOSFET model is derived based on the following Jn = qiimE + qDn V«

(8)

JP = q^pE-qDpVp

(9)

where J„ and Jp are the current density for electrons and holes respectively; q is the electron charge; n, and /j, are the mobilities for electrons and holes, respectively;« is the electron concentration in the channel; p is the hole concentration in the channel; £ is the electric field; D„ and Dp are the diffusion coefficients for electrons and holes, respectively. D„ and .Dp link tojn and y, with the following equations: Dn = V,Hn

(10)

Dp = viflP

(11)

where v, is the thermal voltage. The first terms in Eqs. (8) and (9) describe the drift current components due to the electric filed E. The second terms describe the diffusion current component due to the carrier concentration gradient. In the strong inversion region, the total current is dominated by the drift current. In the subthreshold region, the diffusion current component dominates. However, in the transition region (moderate inversion region) from subthreshold to strong inversion, both drift and diffusion currents are important, and need to be included in the model. As shown in (8) and (9), the electric field E, carrier density, and mobility are the basic factors determining the current characteristics. The electric field E can be obtained by solving the Poisson equation V>=—£-

135

(12)

1022

Y. Cheng

where 0is the electrostatic potential; p i s the charge density including electron, holes, and other charges in the interesting region of the device. However, to get analytical solutions for I-V models, simplified approaches are needed to consider the influence of the electric field in compact modeling." Besides the proper consideration of the electric field, the channel charge and mobility need to be modeled carefully to describe the current characteristics accurately and physically, based on which, different physical effects can be added in the I-V model. In modeling the channel charge, physical effects such as short channel effect, narrow width effect, non-uniform doping effect, and quantization effect etc. should be accounted for in order to describe the charge characteristics accurately in today's devices. There are two types of charge models, one can be called threshold-voltage (Vlh)based models, another can be called surface-potential (y*)-based models, yf-based charge models are based on the analysis of the surface potential that will appear in the I-V model to describe charge characteristics with the influence of many physical effects.22 F,A-based charge models are derived also by solving the surface potential with the consideration of those physical effects, but finally V,h is used instead of 1/4 in the charge (and hence I-V) model to account for the influence of some process parameters such as oxide thickness and doping and device parameters such as channel length and width.5'6,20 In both models, the continuities of the charge and its derivatives should be modeled carefully for the I-V model to have good continuity and to predict correct distortion behavior of the devices. A F,A-based charge model used in BSIM3v3 is given in Eq. (13) as an example. As shown in Fig. 10, the model fits the measured data of the channel charge and ensures the continuity of the channel charge from strong inversion to the subthreshold regions.23 Fig. 11 shows the continuity of the ^ ^ ( a n d hence the charge model as given in Eq. (13) and its first and second derivatives.19

Qchs o = Cox Vpieff

(13a)

VGS-V,H,

VgsKff =

2nv/ln l+exp(— ) 2nvi 1 + 2nCox l„CoX\^.I—-—exp( ^ qe,iN ^iNd, 2nvi

(13b) —)

Here Cox is the unit area oxide capacitance; n is the subthreshold swing factor; Nch is the doping concentration in the channel; Voff\s a fitting parameter; " Vas is the gate voltage; V,h is the threshold voltage; vt is the thermal voltage; q is the electron charge; £,, is the dielectric permittivity of the semiconductor; and $ i s the surface potential when Vgs=Vlh, and is given by 0s=2v,ln(-^-)

where Nch is the doping concentration in the channel;«, is the intrinsic carrier density.

136

(13c)

MOSFET Modeling for RF IC Design 1023

l O itt

N =axiaie

10-"•

.2 o o

GJ

io- 1 3 ;

10-

10-'

OS

OO

OS

1.0

1-5

2X1

3 0

2.5

35

V G S (V) Fig. 10. The charge model covers the weak, moderate, and strong inversion regions of MOSFETs.23

The second derivative of VgsUff vs. VGS

The first derivative of Vgsiaff vs. VGS

Vgstsff .

ft********

•1.0

-0.5

0.0

0.5 1.0 yos(V)

*****

1.5

2.0

2.5

Fig. 11. The continuities of the charge model and its derivatives are needed in different operation regimes." Mobility is another key parameter in MOSFET modeling. It will influence the accuracy and distortion behavior of the model significantly.19,24 The relationship between the carrier mobility and the electric field in MOSFETs has been well studied.25,26 Three

137

1024

Y. Cheng

scattering mechanisms have been proposed to describe the dependence of mobility on the electric field.27 Each mechanism may be dominant under specific conditions of doping concentration, temperature and biases as shown in Fig. 12.

Effective Field Eeff

Fig. 12 Mobility behavior influenced by different scattering mechanisms, depending on the bias and temperature conditions.27

In strong inversion, mobility depends on the gate oxide thickness, doping concentration, threshold voltage, gate and substrate biases. In weak inversion, it is usually modeled as a constant. Thus, continuity of the mobility model is also required to ensure the continuity of the /-K model. In BSIM3v3, a mobility expression based on the V^eff given in Eq. (13) is used, fJ, 1+(U.+UCVBSX

(14) ) + Ub{

J ox

) I ox

where ^& Um Ub and Uc are fitting parameters extracted from measured data; V,h is the threshold voltage; Tox is the gate oxide thickness." With Vg5leff\n Eq. (13), the mobility model given in Eq. (14) is continuous from strong inversion to weak inversion. It has been known that the I-Vmodel based on Eq. (14) can predict the distortion behavior of the devices.21 Recently, other detailed analysis of the influence of the mobility model on the distortion behavior of the 7-Kmodel has also been reported.24 In Fig. 13, is shown the comparison of characteristics of Gm and its derivatives versus gate bias between the model and measured data for a device of 5fim

138

MOSFET

Modeling for RF IC Design

1025

channel length, with the consideration of the distortion behavior of the mobility model.24 It has been realized that an accurate and physical description of a mobility model in compact MOSFET RF models for circuit simulation is essential for distortion analysis. It is also suggested that different models for electron and hole mobilities should be developed because of the difference in quantum-mechanical behavior of electrons and holes in the inversion layer in today's MOSFETs.24

*

6*

%. "

l«

•90 r " " • " • ^ «•»»•.-/}----

3.00

--:•

3.30

.if *M

4.50

5.00

5.50

6.00

VcsCV) Fig. 13 Measured (symbols) and modeled (lines) behavior of Gm and its first and second derivatives as a function of VGS for an n-channel MOSFET with a width of lOum and length of 5\im at fis=0V.24

Based on the charge and mobility models, complete I-V equations can be developed with further inclusions of many important physical effects such as short channel and narrow width effects, velocity saturation and overshoot, poly-depletion effect, quantization effect, and so on. In order to meet the requirements for both AC small signal and larger signal applications, the continuity and distortion behavior of the I-V model should be ensured in deriving the equations when including these physical effects. 2.3.2. Capacitance model In real circuit operation, the device operates under time-varying terminal voltages. Depending on the magnitude of the time-varying signals, the dynamic operation can be classified as large signal operation and small signal operation. Both types of dynamic operation are influenced by the capacitive effects of the device. Thus, a capacitance model is another essential part of a compact MOSFET model for circuit simulation.

139

1026

Y. Cheng

Many MOSFET intrinsic capacitance models have been developed. Basically, they can be categorized into two groups. (1) Meyer and Meyer-like capacitance models and (2) charge based capacitance models.28,29 The advantages and shortcomings of the two groups of model have been well discussed and both of them have been implemented in circuit simulators. The Meyer and Meyer-like models are simpler than charge-based models so they are efficient and faster in computations. But they assume that the capacitances in the intrinsic MOSFET are reciprocal, which is not the case in real device,"and earlier models based on this assumption cannot ensure the charge conservation.19'30 Charge-based models ensure the charge conservation and consider the non-reciprocal property of the capacitances in a MOSEFT. These features are required to describe the capacitive effects in a MOSFET, especially for RF applications where the influence of trans-capacitances are critical and should be considered in the model. But usually the charge-based capacitance models require complex equations to describe all of the 16 capacitances in a MOSFET with four terminal, as given in the following, Q=^SL d/,j

i*j,ij=G,D,S,B

(15)

Cj = - ^ L

i=j

(16)

The development of an intrinsic capacitance model of modern MOSFETs is another challenging issue in RF modeling. To meet the needs in RF applications, besides ensuring charge conservation and non-reciprocity, an intrinsic MOSFET capacitance model should at least have the following features such as (1) guaranteeing model continuity and smoothness in all the bias regions, (2) providing model accuracy for devices with different geometry and different bias conditions, and (3) ensuring model symmetry at the bias of VDs=(N. Some comparisons between the MOSFET capacitance models and the measured data have been reported.31 However, a complete verification of the bias and geometry dependencies of those capacitance models has not been seen. It has been found that some engineering approaches have to be used to improve the accuracy of the capacitance model if the intrinsic capacitance model cannot describe the device behavior accurately.32 Recently, the model continuity has been improved greatly. Many discontinuity issues in earlier capacitance models have been fixed.33 However, most capacitance models still cannot ensure the model symmetry when VDs=0. In Fig. 14 and 15, the asymmetries of the capacitance model in BSIM3v3 are shown for CGs=CGD, Q>0 and C^, and for CBD and CBS.i9 It has been known that a MOSFET should be symmetric for some capacitances at VDs=0, i.e. CDD=Css and CBD=CBS. The asymmetric issue in the capacitance model is apparently non-physical and may cause convergence and accuracy problem in the simulation. This issue may become more critical in the model for RF applications because the devices are often biased in the region of KDS=0V in some applications such as switching. Efforts have been made based on the source-referenced approach, the bulkreferenced approach and surface potential oriented approaches to improve the symmetry property of the models.34 The development of advanced capacitance models with good

140

MOSFET

Modeling for RF IC Design

1027

continuity, symmetry, accuracy and scalebility is still a challenge for the model developers.

V D S (V)

Fig. 14 Simulated Css and CDD as a function of VDS- Css *€DD when VDS-0. "

0.2 0.1 -

^

8 O

• \T \

0.0 -

1

y

-0.1 "

£

'a

-0.2-

o B o

-0.3-0.4-0.5-

Oss

....

f

W/L=10/0.5 1

t/SD

1 0.0

VBS=OV

1.0

1.5

2.0

2.5

V D S (V) Fig. 15 Simulated Css and CDD as a function of VDS. CBS ^BD when VDS~0.'9

141

1028

Y. Cheng

2.4. Modeling of the extrinsic

MOSFET

For an AC small signal model at RF, the modeling of parasitics is very important. The models for these parasitic components should be physics-based and linked to process and geometry information to ensure the scalability and prediction capabilities of the model. Also, simple sub-circuits are preferred to reduce the simulation time and to make parameter extraction easier. Besides a development of a physical and accurate intrinsic model discussed above, the following issues should be considered in developing a MOSFET model for deep submicron RF applications: 1) The gate resistance should be modeled and included in the simulation. 2) The extrinsic source and drain resistances should be modeled as real external resistors, instead of only a correction to the drain current with a virtual component. 3) Substrate coupling in a MOSFET, that is, the contribution of substrate resistance, needs to be modeled physically and accurately using approriate substrate network for the model to be used in RF applications. 4) A bias dependent overlap capacitance model, which accurately describes the parasitic capacitive contributions between the gate and drain/source, needs to be included. 2.4.1. Modeling of gate resistance At DC and low frequency, the gate resistance consists mainly of the poly-silicon sheet resistance. The typical sheet resistance for a polysilicon gate ranges between 20-40 £2/square, and can be reduced by a factor of 10 with a silicide process, and even more with a metal stack process. At HF, however, two additional physical effects appear, which will affect the value of the effective gate resistance. One is the distributed transmission line effect on the gate, and another one is the distributed effect or NQS effect in the channel.8,35 The distributed transmission line effect on the gate at HF has been studied.7 It will become more severe as the gate width becomes wider at higher operation frequency. So multi-finger devices are used in the circuit design with narrow gate width for each finger to reduce the influence of this effect. A simple expression of gate resistance, R0, based on that in DC or low frequency has been used to calculate the value of gate resistance with the influence of the distributed gate effect (DGE) at HF. However, a factor of a is introduced, which is 1/3 or 1/12 depending on the layout structures of the gate connection to account for the distributed RC effects at RF, as given in the following,

Rc.^^XZL^+Ot) N/Lf

(17)

a

where RGsh is the gate sheet resistance, ffyis the channel width per finger, Lf is the channel length, and A^is the number of fingers, Wex, is the extension of the poly-silicon gate over the active region.

142

MOSFET

Modeling for RF IC Design

1029

Complex numerical models for the gate delay have been proposed. However, the simple gate resistance model with the a factor for the distributed effect has been found accurate up to VfTfov a MOSFET without significant NQS effects." The NQS effect or the distributed RC effect in the channel is another effect that should be accounted for in modeling the HF behavior of a MOSFET. For the devices with NQS effects, additional bias and geometry dependences of the gate resistance are needed to account for the NQS effect.8,35 It has been proposed that an additional resistive component in the gate should be added to represent the channel distributed RC effect.8 As discussed above, when a MOSFET operates at high frequencies, the contribution to the effective gate resistance is not only from the physical gate electrode resistance but also from the distributed channel resistance, which can be "seen" by the signal applied to the gate, as shown in Fig. 16. Thus, the effective gate resistance RG consists of two parts: Ra

=Ra.

poly +Ra,

mis

(18)

where Ra.poiy is the distributed gate electrode resistance from the poly-silicon gate material and is given by Eq. (17), RG.^ is the NQS distributed channel resistance seen from the gate and is a function of both biases and geometry.8,35

Fig. 16 Equivalent gate resistance consists of the contributions from the distributed gate poly resistance and distributed channel resistance.S3S

The HF characteristics of the gate resistance have been studied.35 In Fig. 17, it is shown that RG decreases first as Lf increases while showing a weak bias dependence in this region, then starts to increase with £/as Lf continue to increase above 0.4um while showing a strong bias dependence. The Lf dependence of Ra varies for different VGS. At lower VGS, the Lf dependence of Ra is stronger. Also, RG for the devices with longer Lf increases significantly and has stronger VGs dependence. Fig. 18 shows the Wf dependence of RG. It demonstrates that Ra increases as W^-decreases when Wfl

circuit of the substrate

network.17

Ysub

- r CP"

Rsub

—

B

Fig. 32 (c). One resistor EC for the substrate network

161

[37].

parameters-

1047

-i L f 0.36mm W(=12p W f12Mm 1^=10 OOO

Vf

•

r-

_ov R«.»«>»>f/>«">»">»»

100

Cffi rjctyiJrcajijrtmijpr^ranqmmrprar^ 8

9

10

11

Frequency (GHz)

Fig. 34 Extracted values ofCcc Cos, and C0D at a given bias condition.

162

MOSFET

Modeling for RF IC Design

1049

K

dam v~?ov

E O

Q?

V

=O.0V. 0.2V, 0.4V, 0.6V

50

tf§^AS»S*&& —i—•—i2

4

10

12

Frequency (GHz) Fig. 35. Extracted values of substrate resistance at several different bias conditions.37

2.6. Simulations and comparisons with measurements According to the methodologies discussed above, a subcircuit model based on different core models can be developed. In this section, as an example, we present some results of the RF MOSFET model based on BSIM3v3.10'43 The model has been examined with devices of different geometries at different bias conditions from several technologies. Here we shown the results by using devices fabricated with a 0.25|im RF CMOS technology. Multi-finger devices with lengths Lf from 0.36|lm to 1.36fXm and width per finger (Wj) from 2.5|lm to 12|im are characterized with a HF measurement system consisting of a HP8510 network analyzer and a HP41421-Vtester. S-parameters are measured and are then converted to Y-parameters to facilitate the parameter extraction. The measured raw data are de-embedded with the two-step (open and short) procedure discussed in Section 2.5.1.38 The model parameters for the intrinsic devices as well as for the series source/drain resistances are extracted from the measured DC data. Other parameters for the extrinsic components such Ra, RDB, RSB etc. and some parameters for the capacitance model are extracted from the measured HF and AC data. The simulations with the subcircuit model show satisfactory agreement with experiments. As an example, Figure 34 shows a comparison of the Y-parameter characteristics between measurements and the model for devices with different geometries at VG=VD=W. Y-parameters in liner scale plots instead of Smith-chart plots are presented to clearly show the fitting of the model against measurements. The good match between the model and data proves that the simple subcircuit model can be accurate up to 10GHz. Figure 37 gives a comparison offj-ID characteristics between the model and measurements for several devices. Together with the plots in Fig. 36, it demonstrates that the subcircuit

163

1050

Y. Cheng

model can predict the HF characteristics of the devices with different geometries at different bias conditions.

„^

2

1.5X10- -

O o D

2x12u,mx0.36^01 10x12umx0.56um 10x12|imx0.36^101

C 0)

E v (/J

1.0x10-2.

Solid lines: Model Symbols: Measure data

£

5.0x10-3-

I ... Frequency (GHz)

Fig. 36 (a). Measured and simulated real and imaginary parts ofY,, characteristics for several different devices.4i

„

-5.0x10 4 ' -1.0X10-3 "BS" -1.5X10-3

°8

Solid lines: Model Symbols: Measure data

-2.0x10- 3

-2.5x10-3-

Q:

10x12nmx0.36nm 10x12pnnx0.56nm 2x12nmx0.36ujn

-3.0x10- 3

Frequency (GHz)

Fig. 36 (b). Measured and simulated real and imaginary parts of Yn characteristics for several different devices.4>

164

MOSFET

6x10-2 5x10-2 4x1tr2

T

O O °

~

~

2x12|imx0.36nm 10x12|imx0.36(im 10x12(imx0.56)im

Modeling

~\ • 1 ' Solid lines: Model

for RF IC Design

1051

r

Symbols: Measura data V

DS= V CE= 1 V BS

ov

3x10-2

52-

2x10-21x10-2

If

0

=8.

-1x10-2CD -2x10-2 -3x10-2

F r e q u e n c y (GHz)

Fig. 36 (c) Measured

and simulated

real and imaginary

parts of Yn characteristics for several

different

devices.4

~r

o c E

2x12jjmx0.36prn

°

10x12nmx0.56(j.m

o

10x12)jmx0.36nm

Solid lines: Model Symbols: Measure data v

txfvaf1v

V=.

1

-T—'

'

tOSO-

V

DS=1V

V

BB=0V •

• 2.5-

•

2.0-

•

•

Finger numbers*1G Width per finger s 6^m Length=0.18jim

1.5LO-

•

•

•

-

OS0.03

4

5

Frequency (GHz)

Fig. 48 An example of measured NFmi„ versus frequency for a MOSFET.

4.035-

1

i

|

.

-1

•

1

•

Finger numbers=10 •

Width per finger=€lirn Length~0.18um

.

ID•

S' S

25•

J Z

•

•

Z0VBS=0V

1.5-

Frequency = 3 G H z

1.010

20

mA

los( ) Fig. 49 An example of measured NFmin versus IDS for

a

MOSFET.

As mentioned above, circuit designers prefer to use the parameters re lated to a two-port network to describe the noise performance of a device and a circuit. Universal

183

1070

Y. Cheng

noise models have been developed for any two-port network. A noisy two-port network shown in Fig. 50 (a) can be represented by a noise-free two-port network with two noise current sources, one at the input port (i,) and the other at the output port (i2) as shown in Fig. 50 (b). Figure 50 (b) can also be transformed to a noise-free two-port network in Fig. 50 (c) with a noise current source, Sm=4KBTGin, and a noise voltage source, S™ = 4KBTRW at the input port, where the v„ and i„ are correlated to each other and the correlation relationship is described by a correlation admittance Yc = Gc + JBc The noise source /'„ can be further separated to a noise source /„„ that is uncorrelated to v„ and a noise source /„cthat is fully correlated to v„ in = irm + Inc

(62)

inc = YcVn

(63)

and

The above relationship can be expressed in terms of noise power spectral density as follows: + S,nc

Sinc=\Y(S™

(64)

(65)

According to the two-port network given in Fig. 50, we further have the following relationships, v» =

h

(66)

Y21

in =h + Y\\Vn

(67)

Si 2

&2

S» = - ^ 7 = 4KaTR,

(69)

N2

Sm=4KBTGm

184

(70)

MOSFET

Modeling for RF IC Design

1071

(a)

(b) Ii

+ InQ

Noise-free two port

(c) Fig. 50. Noisy two-port and its ABCD-parameter representation.

Based on the above relationships, the four noise parameters discussed earlier can be calculated, (71)

Xtrt — IYv<

[G7 * VA"

G, -

&2

(72)

Bopi ——Be

(73)

NF mi. = 1 + 2Rn(Gc + G,p'!

-'jun.d

D

W

A fV-jnn^

^fron ^* at T2i versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10 fingers of width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

0.01-1.0x10 • -2.0xl0 : jf

-3.0x10"

1

-4.0xl0":

>> -5.0xl0": -6.0xl0": -7.0xl0":

1

2

3

4

5

6

Frequency (GHz) Fig. 33. Measured (symbols) and simulated (lines) imaginary parts of y^ and y^\ versus frequency characteristics for the n-type MOSFET with the channel width W = 10 x 6 um (10fingersof width 6 um) and length L = 0.18 um biased at VDS = 1.0 V and VGS = 1.2 V.

Figures 34 to 37 show the extracted gm, RDS, CGS and CGD versus gate bias VGS respectively, for devices with different channel lengths. These extracted parameters give similar fitting accuracies as the y-parameters versus frequency characteristics shown in figs. 30 to 33 at all the gate biases shown in figs. 34 to 37.

235

1122

C.-H. Chen & M. J. Deen

30 r

W=10x6nm

%

L=0.18um • I^0.27nm L=0.42nm

1ou

L=0.64um • L=0.97um

2.0

Fig. 34. Transconductance (gm) versus VGS characteristics extracted from the measured Re(y2i) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 (im (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 urn, 0.42 urn, 0.27 nm and 0.18 urn, respectively, biased at VDS = 1.0 V.

L=0.97um L=0.64u.m L=0.42um L=0.27um L=0.18nm

Fig. 35. Output resistance (#DS) versus VGS characteristics extracted from the measured Re(y2i) at the low frequency region for the n-type MOSFETs with channel width W = 10 x 6 um (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 urn, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

236

RF CMOS Noise Characterization and Modeling 1123

400

I V^l.OV

W=10x6nm

• - • - • - -•-•-•-i

• L=0.97um

300

fe

. _ , - • - • - • - • - • — - • — • — • - - • L=0.64um

200

^ ^ - A - A - A - A - A — A — A — A _ A L=0.42nm

100

^ • ^ - » • • • • — • — • — • L=0.27nm • ^ • - • • • — • — • — T — T L=0.18um

T-T

0

0.5

1.0 1.5 V^CVolt)

2.0

Fig. 36. Gate-to-source capacitance (CGS) versus VGS characteristics extracted from the measured lm(yn) at the lowfrequencyregion for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 um) and lengths L = 0.97 urn, 0.64 um, 0.42 um, 0.27 um and 0.18 urn, respectively, biased at the drain voltage VDS = 1.0 V.

160

L=0.97um

W=10x6um 120

V =1.0V

• L=0.64um

DS

£

80

. L=0.42um

40

< ^ I ^ - - * L=0.27um "^T—•L=0.18uni

m*$$^ 0.5

1.0

1.5

2.0

V ra (Volt) Fig. 37. Gate-to-drain capacitance (CGD) versus VGS characteristics extracted from the measured Im(yn) at the lowfrequencyregion for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at the drain voltage VDS = 1.0V.

The gate resistance (RG) used in the simulation for different channel lengths is obtained from *G

=

(90) 3 • « •L

237

1124 C.-H. Chen & M. J. Deen where RQSH = 5.17 Q and n is the number of fingers. In fig. 34, the VG$ bias for the peak gm decreases as the channel length is reduced, and this results in the shift of the peak / T shown in fig. 26. Although the peak gm increases when the channel length is reduced, the output resistance (Rps) m fil- 35 decreases at the same time, and this results in the amplification factor (Ay(Hy= gm x RDS) remaining about the same at the V G S where the peak gm occurs. Based on the element values extracted from the measured y-parameters and noise parameters, figs. 38 and 39 show the extracted channel noise and induced gate noise versus frequency characteristics for n-type MOSFETs with different channel lengths biased at V DS = 1.0 V and V GS = 1.2 V. It is shown that the channel noise, in general, is frequency independent and increases when the channel length decreases because of the higher drain current at the same V DS and V GS bias. The solid lines in fig. 38 are the extracted channel noise based on the method described in section 5.1 which provides an alternative way to verify the channel noise extracted by the proposed method. The small increase in the channel noise at low frequencies for deep sub-micron devices might be caused by the inaccuracy of the measurement system at low frequencies. In fig. 39, the induced gate noise is proportional t o / 2 (solid lines in the figures) where/is the operating frequency. In addition, when channel length decreases, the induced gate noise also decreases because of the decrease of gate-to-source capacitance Q J J , as shown in fig. 36. Therefore, the strength of the induced gate noise is mainly determined by the gate-to-source capacitance instead of the voltage or current fluctuation in the channel.

V =1.0V V =1.2V DS

GS

1E-21

-w-* L=0.18um

• • •

* • • • • • • » » • • I^0-27um &.

A

A A

L=o.42um

A A A A A A A A

— • • • • • • • • • • L=0.64um • • • • • • • , • • •

I^0.97um

W=10x6um 1E-22 0

1 2

3

4

5

6

Frequency (GHz) Fig. 38. Extracted channel noise (ij) versusfrequencycharacteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10 fingers of width 6 |im) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V. The solid lines are the extracted channel noise based on the method in section 5.1.

238

RF CMOS Noise Characterization and Modeling 1125

1x10

L=0.97um L=0.64um

1x10

> L=0.27um

L=0.42uin L=0.18um

h~« lxl0_24 1x10 Frequency (GHz) Fig. 39. Extracted induced gate noise (i-?) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V.

Figure 40 shows the extracted noise correlation between the channel noise and induced gate noise versus frequency characteristics for n-type MOSFETs with different channel lengths biased at V D s = 1.0 V and V G S = 1.2 V. It shows that the noise correlation between the channel noise and the induced gate noise is proportional / In addition, when channel length decreases, the noise correlation also decreases because of the decrease in the gateto-source capacitance CGS.

8x10 r L=0.97um

6x10"" •

L=0.64um 4x10"" L=0.42nm 2x10"

L=0.27um L^.18um

2

3

4

5

6

7

Frequency (GHz) Fig. 40. The noise correlation between i* and i\ ( ' „ ' / ) versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V and VGS = 1.2 V.

239

1126

C.-H. Chen & M. J. Deen

Another useful parameter that is sometimes used to describe the relationship between the channel noise, induced gate noise and their correlation is the cross-correlation coefficient c, which is defined as,

y/

(91)

W Figure 41 shows the extracted cross-correlation coefficient c versus frequency characteristics for the devices with different channel lengths. In general, c is frequency independent and decreases when the channel length is reduced. This implies that the channel noise and the induced gate noise are less correlated for the shorter channel length devices. These results show an opposite trend to the simulated results presented in Refs. 49 and 50

0.6 r V^l.OV

W=10x6nm

§ 8 u S o o

s

-* b=0.97um 0.4-

• L=0.64um

*-*-r A A

L=0.42um

A A

0.2

L=0.27|xm

•

-*-*0.0

1 2

T •

b=0.18um

T

3

4

5

6

7

Frequency (GHz) Fig. 41. The cross-correlation coefficient c versus frequency characteristics for the n-type MOSFETs with channel width W = 10 x 6 urn (10fingersof width 6 um) and lengths L = 0.97 fim, 0.64 \xm, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDs = 1.0 V and VGS = 1.2 V.

For the V G S bias dependence of the extracted noise sources, figs. 42 and 43 show the extracted i| and fl versus V G S characteristics for the n-type MOSFETs with channel width W = 10 x 6 um and lengths L = 0.97 ^.m, 0.64 \im, 0.42 |am, 0.27 um and 0.18 um respectively, biased at V D s = 1.0 V. The channel noise is caused by the voltage or current fluctuation in the gradual channel region which is from the intrinsic source terminal to the pinch-off point, and from the saturation region which is from the pinch-off point to the intrinsic drain terminal. For long channel devices, the channel noise mainly comes from the gradual channel region. However, for short channel devices, the noise from both regions has to be taken into account. It is shown that the channel noise has a strong V G S dependence and it increases, but then tends to saturate when V G S increases. On the other

240

RF CMOS Noise Characterization

and Modeling

1127

hand, the induced gate noise has a weak VQS dependence because it is mainly determined by the gate-to-source capacitance CGS instead of the voltage or current fluctuation within the channel of the transistor.

1.5xl0'2

T

W=10x6|am V =1.0V DS

1.0x10"'

P-

5.0x10"'

•

•

A'

•

A

L=0.18um

T

I

u

• L=0.27um

A

A L=0.42um

•

• L=0.64um

•

• L=0.97|xm

A.

O.OL

li

0.5

1.0

1.5

2.0

V^CVolt) Fig. 42. Channel noise (i? ) versus V GS characteristics for the n-type MOSFETs with channel width W = 10 x 6 \im (10 fingers of width 6 fim) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 urn, respectively, biased at V D S = 1.0 V.

1x10"

I '•••,

I

I

'••

| L=0.97um L=0.64|im

AA,

••

••

A •

2

!§ lxlO"

TT

TTT

10"

T

A A L=0.42Lim • • L=0.27Mm

A

Ty

•

V^l.OV W=10x6nm 0.5 1.0

1.5

• L=0.18um 2.0

V^CVolt) Fig. 43. Induced gate noise (ij;) versus V G S characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10 fingers of width 6 um) and lengths L = 0.97 um, 0.64 |im, 0.42 um, 0.27 um and 0.18 um, respectively, biased at V D S = 1.0 V.

Figures 44 and 45 show the extracted correlation noise i Jd* and the cross-correlation coefficient c versus V G S characteristics for the n-type MOSFETs with channel width W = 241

1128

C.-H. Chen & M. J. Deen

10 x 6 Lim and lengths L = 0.97 Jim, 0.64 Lim, 0.42 iim, 0.27 Lim and 0.18 Lim respectively, biased at V D s = 1.0 V. For the correlation noise, it increases, then tends to saturate when V GS increases. This follows the V G S dependence of the channel noise. However, the correlation noise decreases when the channel length is reduced and this follows the channel length dependence of the induced gate noise. On the other hand, the cross-correlation coefficient tends to decrease when V G S increases. It is because of the faster increase in the channel noise compared to the correlation noise, and it follows the trend predicted in Ref. 17. 3x10 W=10x6um

L=0.97um

v K =i.ov 2x10 F L=0.64um :•

2 lxHT

•

• L=0.27um . • , T .l>0.18nm 2.0 1.5

,••••••• JTTTTTTT

0

0.5

L=0.42um

*

.••:*

C3

T

1.0 V„

c s ^

Fig. 44. The correlation between fl and A ('J/ ) versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

0.6 a 'o 0.5

8 u

vDS=i.ov W=10x6um 1

0.4

a o 0.3

1

A

0.2

! u 0.1

***•••••

I CO

a

T

0.0

L=0.97um

0.5

T T

•

•

T,

1.0

1.5

•

L=0.64um ' L=0.42um • L=0.27um L=0.18um 2.0

V Fig. 45. The cross-correlation coefficient c versus VGS characteristics for the n-type MOSFETs with channel width W = 10 x 6 um (10fingersof width 6 um) and lengths L = 0.97 um, 0.64 um, 0.42 um, 0.27 um and 0.18 um, respectively, biased at VDS = 1.0 V.

242

RF CMOS Noise Characterization and Modeling 1129

For the V D S dependence, figures. 46 and 47 show the extracted channel noise versus V GS characteristics at different V D s biases for the devices with 0.97 |im and 0.18 jam channel length, respectively. For the long-channel devices, because the channel noise is mainly contributed from the gradual channel region, it is not sensitive to different V D s biases. However, for the short-channel devices, the saturation region contributes considerable noise power to the overall channel noise. Therefore, the channel noise will increase when the V D s bias is increased because of more noise current contributed from the saturation region than the decrease of the noise current contributed from the gradual channel region. 3.0x10

1.0x10 5.0x10

V GS (Volt) Fig. 46. Channel noise (/^ ) versus VGS characteristics for the n-type MOSFET with channel width W = 10 x 6 um (10fingersof width 6 um) and length L = 0.97 um biased at VDS = 1.0 V, 1.2 V, 1.5 V, 1.8 V and 2.0 V, respectively.

1.8xl0'21 r L=0.18um W=10x6um 1.2xl0"21 h

6.0x10"

0.0 VGS (Volt) Fig. 47. Channel noise (ij) versus VGS characteristics for the n-type MOSFET with channel width W = 10x6 M.m (10fingersof width 6 um) and length L = 0.18 um biased at VDS = 1.0 V, 1.2 V, 1.5 V, 1.8 V and 2.0 V, respectively. 243

1130 C.-H. Chen & M. J. Deen In order to verify the accuracy of the extracted noise sources, and compare the simulation results against the measured data and those based on van der Ziel's model which is suggested for long channel devices, figs. 48 to 51 show the measured (symbol) and simulated (lines) noise parameters versus frequency characteristics. The simulations are performed using the direct calculation technique described in section 3.1 • for the n-type MOSFET with the channel width W = 10 x 6 Jim and length L = 0.97 Lim biased at V D S = 1.0 V and V G S = 1.2 V. In these figures, the solid lines are the simulated results based on the extracted noise sources (solid lines in figs. 38 to 40) and the dashed lines are the simulated results based on van der Ziel's model in which the power spectral density of the noise sources are given by 'J =

(92)

ySatn4kTSdo 2_2

i2

co C0

g

= 5satn4kT-r-

(93)

and

°do

(94)

V 7 = *satn4kTJ

V/////'//////77777? Wafer B

Polishing

SOI Wafer

Fig. 2. Fabrication process for SIMOX (A), BESOI (B) and Smart-Cut (C) SOI wafers.

n+ poly gate

KflaETTraas

N

j

Lb .iu)'ffvn"rri"'

P B: Fully depleted

*—1 Source/ i ^ J drain Depletion

A: Partially depleted

HH Inversion Hill Accumul. C: Accumulation mode D: Volume inversion

^

Neutral

Fig. 3. Types of SOI MOSFET's (for sake of conciseness, only the Si film and active gate material and oxide are represented, not the buried oxide and underlying Si substrate).

278

SOI CMOS Transistors for RF and Microwave Applications

1165

VGf t»y/yc-';y y "-^'•••'•'";-]

Kink effect

vD

vs -W-

*

v

B

•*•

Drain voltage

Gb

Fig. 4. Typical PD SOI MOSFET structure and ID-VD curves for various gate biases.

Substrate j contact c ©

p+

\ Source \

N?_. .

•

-•.

,

§»'•

=•3

3

P+

as ©

i

>•?

Drain

-Cl

a

03

Gati

H-gate contact

'normal" lateral contact Fig. 5. Typical body tie layouts.

On the contrary, MOS transistors realized on SOI films thin enough to allow the depletion region to extend across the whole film (Fig. 3.B) feature dramatically reduced FBEs due to the reduction of the source barrier. Furthermore they exhibit superior device characteristics with respect to bulk MOSFET's: sharper subthreshold slope close to an ideal 60 mV/decade value at room temperature, improved drive capability due to smaller body effect and mobility degradation with gate voltage19. These properties result from the front-to-back gate coupling through the Fully-Depleted film capacitance as will be detailed in Section 3. The main drawback of Fully-Depleted or FD devices is-the sensitivity of the threshold voltage to the film thickness and buried oxide parameters, the latter ruling out the use of thin-film FD SOI devices for total-dose radiation-hardness applications. Threshold voltage dependence on the film thickness can however be minimized holding the film total dose constant rather than the doping concentration . Threshold voltage standard deviations similar to bulk devices have indeed been achieved for FD SOI MOSFET's. The use of thin-film SOI substrates, in which, by definition, the lateral isolation field oxide extends down to the buried oxide providing complete dielectric isolation of neighbor devices, considerably eases the fabrication of deep-submicron MOS devices 279

1166

D. Flandre, J.-P. Raskin & D.

Vanhoenacker-Janvier

either FD or PD. When compared to conventional bulk process, threshold voltage roll-off is indeed minimized, reliable ultra-shallow junctions are easily processed, wells and latchup are suppressed and complicated lateral isolation process can be avoided. In addition, although defect densities may be higher in SIMOX films than in bulk substrates, SOI process yield may actually be higher than that of bulk since SOI devices and circuits are much more tolerant to defects1. Unique buried-channel MOS devices, such as p-channel transistors featuring P + source and drain and P" uniformly doped channel regions, can be built on thin-film SOI substrates9 (Fig. 3.C). No current flows as the device is turned off because of the full depletion of holes in the channel region. When the device is turned on, an accumulation current flowing in a surface channel adds to the buried current that flows in the undepleted part of the film. As a result, so-called accumulation-mode or AM devices (Fig. 3c) show low leakage currents, almost ideal subthreshold slopes, as well as excellent drive capability due to the combination of several conduction mechanisms and the use of low doping levels which favors higher mobility. P-type AM devices are of particular interest because -0.7 to -0.4 V threshold voltages are easily achieved using hT-polysilicon gate material, thereby avoiding the problem of boron penetration into the gate oxide when using P+-doped polysilicon. Various processes using p-channel AM transistors have been proposed21, as well as processes with both n- and p-AM devices22. However, originally, AM devices were not candidates for deep-submicron ULSI integration due to shortchannel effects and punchthrough characteristics not as well controlled as in enhancement-mode FD transistors. Nevertheless the feasibility of 0.2 urn AM MOSFET's has been demonstrated23. Double-gate (DG) thin-film MOSFET's may be regarded as the ultimate FD devices24'25 (Fig. 3.D). Also called volume-inversion devices due to the extension of the inversion layer across the whole Si film, these transistors feature very high drive currents, ideal subthreshold characteristics and totally suppressed body effect. The threshold rolloff is moreover much reduced. However, although several fabrication processes for DG devices have been proposed26'27 and some circuits have shown very promising performances, in particular for total-dose radiation-hardness ' ' ' , the fabrication unfortunately remains non-standard which presently jeopardizes the use of DG devices for ULSI applications. Nevertheless the 1999 SLA roadmap and numerous publications clearly point out the need for DG devices to simply and efficiently control the shortchannel effects below 70 nm of channel lengths32'33

2.4. High-speed low-power digital circuits SOI CMOS is already considered as a very attractive technology for the realization of low-voltage low-power (LVLP) digital ULSI circuits and has a number of well-known advantages over conventional bulk Si CMOS34'1. The power and speed performance of simple logic gates are usually characterized by means of the following relationships: Power = Delay ~

fC{vddf

cvdd K{VM-VJ

280

CD

SOI CMOS Transistors for RF and Microwave Applications

1167

where / is the frequency, C the total capacitance of the logic gate, VM the supply voltage, Vth the threshold voltage and K a constant which is inversely proportional to me body factor. These relationships clearly show that simultaneous reduction of power and delay can only be achieved by reducing the capacitance, which is a long-known advantage of SOI. It has been recognized for a long time that the SOI dielectric isolation provides much reduced parasitic capacitances with respect to bulk CMOS. In the latter case, the source/drain loads indeed correspond to junction capacitances, which depend on substrate or well doping and bias voltage (Fig. 6). The technological trend towards reduced dimensions and supply voltages inherently leads to an increase of die source/drain junction capacitances per unit area. In thin-film SOI, die source/drain capacitances are mainly defined by the buried oxide mickness and hence are tremendously reduced when compared to bulk, both regarding the bottom area (Cj„, Cjp) and sidewall components (Cjswn. CjSWp) (Fig. 6). In recent deep submicron CMOS processes, the SOI source/drain junction capacitance reduction even achieves factors on the order of 10 when compared to bulk. The parasitic capacitances of polysilicon and metal interconnection layers are also reduced in SOI due to the presence of die thick buried oxide, but to a lesser extend depending on the technological stack height.

c

jswn - '

-

-

• ""

~jswp

CVitau bulk /SOI -1.3

Fig. 6. Comparison of bulk and SOI junction capacitances for a typical 1 \xm CMOS process (Q and Qsw denote the bottom area and sidewall peripheral junction components at zero bias).

Overall, the typical speed increase and power decrease related to SOI reduced parasitic capacitances amount to about 30 to 40 % versus comparable bulk CMOS circuits. From Eq. (1), another obvious way to preserve the speed performance while reducing the supply voltage is to decrease the threshold voltage. In bulk implementations this can only done at the expense of an increase in the leakage current and hence in static power dissipation. Fully-depleted SOI transistors offer the opportunity to limit that degradation owing to their almost ideal subthreshold slope, as well as to further increase die drive current owing to their smaller body factor. These characteristics all add up to significantly increase the power times delay capability, in particular for reduced supply voltages, as discussed below.

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2.5. Perspectives Years of worldwide research and development in universities and industrial research centers were necessary to demonstrate the benefits and manufacturability of SOI. The industrialization phase towards mainstream production started in August 1998 with the announcement of IBM's plans to ramp-up its SOI technology towards, firstly, the fabrication of commercial high-speed microprocessors6. IBM chose to rely on its ownfabricated SIMOX material and on a PD SOI CMOS process which at this time, proved to be more straightforward and reliable to scale to sub-0.2 um channel lengths, than FD devices requiring very thin SOI films in order to control the short-channel effects . Inherent PD floating-substrate effects are controlled at the design level by proper simulation and timing of critical digital paths36. Nevertheless the FD process has been proved to be the best option for 0.25 um and above SOI CMOS and its controllability is improving at a rapid pace. Scalability towards sub-0.13 um dimensions has been demonstrated on 30 nm-thin SOI films37. The cost issue has long been said to delay the use of SOI for commercial applications. SIMOX or Smart-Cut substrates are still about 3 times more expensive than identical size and comparable quality bulk Si wafers. Nevertheless a past Sematech study demonstrated that if the higher starting cost could be reduced by a factor of 2, the revenues to be made from mass production of 64 Mb SRAM could be substantially higher using a SOI instead of a bulk CMOS process. The reasons are: fewer processing steps, better fabrication yield, smaller chip size and enhanced performance38. More recently, IBM claimed that, even considering the present cost of their SIMOX substrates, the total "SOI wafer + CMOS process" fabrication is only 10 % more expensive than the corresponding bulk Si CMOS process. The SOI material cost decrease could be driven by the development of a high-volume application such as DRAMs. SOI implementation of DRAMs was not considered at first because the SOI film thickness drastically limited the depth of the buried storage capacitor thereby increasing the required cell area. However with the advent of stacked memory capacitors built atop the cell transistors, DRAMs on SOI have been tested and showed considerable improvements over bulk counterparts in cell area and access time39. Nevertheless, there currently remains a critical problem to be overcome regarding SOI use for high-volume applications, namely wafer availability, which in year 2000 does not exceed 2 million pieces per year. The challenges for low-power low-voltage analog and microwave SOI CMOS circuits, however, have not been as widely investigated. Preliminary theoretical results nevertheless showed that analog circuits, in particular operational amplifiers, benefit from the lower body effect and load capacitances in FD SOI CMOS40-41'42'43. On the other hand, preliminary experimental results also showed that submicron FD SOI MOSFET's may achieve transition frequencies in excess of 20 GHz for supply voltages on the order of 3 V . Combined with the ability to realize low-loss matching or interconnection lines on high-resistivity SOI substrates45 and the drastic reduction of substrate crosstalk figures46, these properties may lead to the future development of single-chip mixed digital/analog/microwave solutions. A recent development of SOI applications is related to the field of integrated sensors. High-precision thin membranes can indeed be easily processed on SOI substrates owing to the good control of the film and buried oxide thickness. High-performance pressure sensors as well as accelerometers for use in airbag electronic systems have already been produced.

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3. Properties of Fully-Depleted SOI MOSFET's 3.1. Introduction With SOI emerging as a key technology for the realization of future low-voltage lowpower (LVLP) CMOS circuits, the impact of the improved characteristic* of SOI MOSFET's on speed and power consumption has already received a lot of attention in digital circuitry1. The challenges for analog SOI CMOS circuits, however, have not been as widely investigated. The reduction of parasitic capacitances and the feasibility of diffusion resistors and capacitors free of junction effects have however long been recognized as advantages for the realization of analog circuits on SOI substrates48. Nevertheless, few SOI analog circuits have been reported, presumably because the occurrence of the kink effect in thick-film partially-depleted (PD) SOI MOSFET's severely degrades the output conductance characteristics in saturation1 and thereby the performance of analog circuits. Solutions to the kink effect such as the use of body contacts49 or twin-gate devices50 have been implemented in operational amplifiers but the results showed little improvement of the performances over bulk CMOS counterparts, exception for the ability to withstand elevated temperatures in excess of 300°C51. The kink effect is known to be greatly reduced in thin-film fully-depleted (FD) SOI MOSFET's. Moreover FD devices provide much smaller subthreshold swing and substrate factor than bulk or PD SOI MOS transistors1. This might offer interesting opportunities for LVLP analog circuits. The present section will present the major properties of FD SOI MOSFET's, of interest for the analog circuit design and operational amplifiers (opamps) in particular, i.e. the I-V characteristics of MOS transistors in saturation and principally, the ratio of transconductance over drain current, the output conductance and the intrinsic gate capacitances. Noise, linearity and dynamic range performance will be briefly treated as well. In addition, an engineering model, efficient for opamp design, will be validated.

3.2. I-V characteristics and body effect - impact on digital circuits The main interesting feature of FD SOI MOSFET's is the low value of the body-effect coefficient, which influences both the current drive of the device and its subthreshold swing. The body-effect coefficient, denoted n, is an image of the ideality of the coupling between the gate voltage and the surface potential. It is well known that FD SOI devices offer near-ideal coupling, which yields a value of n close to unity, contrary to bulk Si MOSFET's. This can be intuitively explained by relating the body effect to the capacitive division between channel, gate and substrate potentials (Fig. 7).

283

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D. Flandre, J.-P. Raskin & D. Vanhoenacker- Janvier Bulk Si MOSFET

mmmsmm;3®is!s& S//////J//JWM'f'(

i

Fully-depleted SOI MOSFET

i C Vs^r T

CH

'B

Fig. 7: Comparison of bulk and SOI MOSFET space charge regions and body effect models.

In a bulk transistor, n is then given by n =l+-

£„•

(2)

where COT is the gate oxide capacitance per unit area, esi is the permittivity of silicon and ^dmax *s m e m a x i m u i n depletion width in strong inversion. In a bulk CMOS process with channel lengths around 1 um (i.e. corresponding to a gate oxide thickness of about 30 nm), n is equal to 1.4-1.6 typically. In a 0.25 um processes, the scaling down of the gate oxide to about 5 nm is partly counterbalanced by the Xdmax reduction due to doping level increase which yields typical n values of 1.2 - 1.3. In a SOI FD MOS transistor, on the other hand, the body effect is given by

« = 1+-

(3)

Cjcsi/(

+Coxb

where Coxb and tsj are the buried oxide capacitance and the silicon film thickness, respectively. Typical n values reduce to 1.05 - 1.1 for a 1 um processes with oxide thickness tm, silicon thickness tsj and buried oxide mickness tmb equal to 30, 80 and 400 nm respectively and even reduce to 1.01 - 1.02 for a 0.25 um processes with tgx, r and roxb equal to 5,40 and 400 nm respectively. The influence of the body-effect coefficient on the current drive of the device can be best understood by using a simple device model. The saturation drain current of a MOSFET is given by the following expression:

tDsa,=^Cox^-(Vg5-Vlhf

(4)

H being the effective mobility, V the gate-to-source bias, Vth the threshold voltage and W and L the width and length of the device respectively. From the above equations, it follows that the saturation drain current may be 30-40% higher in a FD SOI device than in a bulk device with similar parameters, depending on body effect.

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A more accurate model for submicron devices would include velocity saturation and series resistance effects52. These tend to somewhat degrade the superior current drive capability of FD SOI MOSFET's as short channel lengths are considered. It has been shown however that non-optimally designed FD SOI transistors still present a 25% current drive improvement over comparable bulk devices for gate lengths down to 0.2 um which could be restored to even better values with optimization of the device structure . In addition, the subthreshold swing (inverse subthreshold slope) of a MOSFET is also affected by the body effect. Indeed, the subthreshold swing is given by the following expression1: S(mV/dec.)=n—In(l0) 1

(5)

if the influence of the interface traps is neglected. The low value of n in FD SOI devices yields an improvement of the subthreshold slope over bulk devices. Almost ideal subthreshold swings of 60 mV/dec at room temperature corresponding to the predicted n values have been experimentally demonstrated for optimally designed FD SOI MOSFET's with channel lengths down to 0.2 um54. As a result, a lower threshold voltage can be used in SOI devices without jeopardizing the OFF leakage current (Fig. 8a), and ON drive current much higher than in bulk devices can be obtained, in particular for reduced supply voltage (Fig. 8b).

Gate Voltage (V)

Supply voltage (V)

(a)

(b)

Fig. 8. (a) Subthreshold slope of bulk and fully depleted SOI MOSFET's, (b) Ratio of fully depleted SOI to bulk saturation drain currents.

Fig. 9 validates these concepts comparing the Id-Vd curves of short-channel nMOSFET's, from SPICE model results of three available 0.25 um CMOS processes: bulk, PD SOI with body tied to source or not, FD SOI. The impact of the improved FD SOI CMOS characteristics on speed and power consumption has already received a lot of attention in digital circuitry. ASIC's and gate arrays have been realized showing speed improvement factors over bulk counterparts by up to 1.7, with a 3 V power supply ' . Circuits built on a 0.5 um FD SOI CMOS IM gate array showed twice the speed or half the power consumption of similar bulk CMOS circuits when operated at 2 V supply voltage.

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1.40E-03

1.20E-03 1.00E-03 ^

/^^M--~"~

"""

8.00E-04

<

Q —

6.00E-04

BULK 4.00E-04 •

PD-SOI with body contact

/

PD-SOI with floating body

2.00E-04 -

FD-SOI O.OOE+00 •

' 0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

VD(V) Fig. 9. Comparison of bulk, PD and FD SOI n-MOSFET drain currents for W = 10 um, L = 0.25 |jm, Vgs = 1 V and VbS = 0 V. In the PD-SOI case with body contact, the latter is tied to the source.

It can be shown that around 40 % of the improvement results from the capacitance reduction and the other 60 % from the drive current increase. A threefold enhancement of the power times speed figure of merit has been demonstrated for 1 V supply voltage, in particular in the case of a 512K SRAM57. A 0.25 um 625 MHz 1.5 V fully-depleted SOI CMOS 64-b microprocessor recently demonstrated an increase of speed by 30 % and a decrease of power by a factor of 3.3 when compared to the bulk equivalent58. Regarding very high-frequency circuits, 0.25 um FD SOI CMOS circuits had already been processed in 1987 with frequency dividers achieving a record 2 GHz input frequency59. Further improvements lead to 6.2 GHz frequency dividers comparable in speed to bulk Si bipolar or GaAs implementations but with considerably smaller power dissipation60. Frequency dividers operating at 1 GHz with a 1 V supply voltage have been realized in a 0.12 (am SOI CMOS process, consuming only 50 uW61.

3.3. CAD models Several analytical modeling alternatives exist for the electrical simulation of FD SOI CMOS circuits. The best-known SOI SPICE model62 was originally developed for 5 Vdigital applications. It has been proved efficient for the reliable simulation of LVLP digital circuits down to a 1 V-supply voltage63. However, as it is a strong inversion-based model, it is inadequate for reliable analog design. It indeed suffers from the troubles common to this family of models such as improper modeling of moderate inversion current, discontinuous transition from triode to saturation, discontinuities of the current and charge derivatives (i.e. the small-signal conductance and capacitance parameters) between the different regions of operation, unphysical overshoot of the transconductance/drain current ratio in moderate inversion64, etc. On the contrary, efficient analog design, and especially for LVLP applications, requires a model valid from weak to strong inversion and non-saturation to saturation conditions with smooth continuous transitions. The EKV model initially developed for bulk MOSFET's provides such properties65. It has been proved that it can successfully be extended to FD SOI MOSFET's56,43. A dedicated FD CMOS model which features infinite continuity of both 286

SOI CMOS Transistors for RF and Microwave Applications

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current and charge expressions as well as their derivatives (i.e. conductance and capacitance) has also been proposed, initially for channel lengths down to 1 urn , then extended down to 0.16 um effective channel lengths68 as well as towards RF simulation up to more than 20 GHz69. The latter will be further used in the next sections on microwave devices and circuits. In the next paragraphs of this section, we will mostly exploit the EKV modeling as a simple and efficient empirical engineering model for the design of analog blocks. Occasionally we will also refer to charge-sheet models when the EKV model reaches its limitations. Charge-sheet models such as presented in Ref. 70 for bulk Si MOSFET's and in Ref. 71 for FD SOI MOSFET's also fulfill the conditions of validity and continuity from weak to strong inversion and non-saturation to saturation conditions with smooth continuous transitions. However charge-sheet models rely on the resolution of a set of highly non-linear implicit equations and are not computationally efficient, nor widely available in SPICE.

3.4. Analog properties In the case of analog circuit design, operational amplifiers (opamps) in particular, we are mostly concerned with the characteristics of MOS transistors in saturation and principally, the ratio of transconductance over drain current, the output conductance, the intrinsic gate capacitances and the noise performance. We will then focus our discussion on these parameters and their modeling in the EKV formulation. The extension of the EKV model to fully-depleted SOI MOSFET's will be presented and supported by measurements on both bulk Si and SOI MOSFET's. Two special cases of MOSFET operation of interest in analog applications, i.e. as a linear resistor in continuous-time filters and as a CMOS switch in switched-capacitor structures, will be briefly treated as well regarding their linearity and dynamic range performance.

3.4.1. Ratio of transconductance to drain current The transconductance-to-drain current ratio directly affects the open-loop gain of operational amplifiers as will be discussed in Section 7. As far as analog micropower circuits are concerned, it is known that the maximum performance may be obtained when the value of the transconductance/drain current ratio (gUh) is the largest. This condition appears in the weak inversion regime for MOS transistors72. The value of gjlo can be rewritten as: gm= ID

dID IDdVa

=ln(!0)=

S

q nkT

The low body-effect coefficient of SOI devices allows for obtaining near-optimal micropower designs (g„/Io values of 35 V"1 are obtained close to the maximum physical value at room temperature, while g„/lo reaches only values of 25 V"1 in bulk MOSFET's). In strong inversion, the gjlo becomes (for long-channel devices):

287

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D. Flandre, J.-P. Raskin & D. Vanhoenacker- Janvier

(7)

nlr,

and remains higher in FD SOI than in bulk MOSFET's with similar technological characteristics. Experimental SOI and bulk n-MOSFET %JID characteristics are compared in Fig. 10. The good agreement between measured and modeled gjlo characteristics, using the EKV model, is also demonstrated for both bulk and SOI devices. This model proposes an analytical expression for the gJID in saturation, which is continuous from weak (WI) to strong inversion (SI) and simplifies to the well-known expressions presented above in WI and SI, when the corresponding conditions are applied: 1-e ID

nU

T

{-JhJh (8)

vw 7

= 2nnCoxi^/LyT where Is a normalization current, n is the mobility, Cox the gate oxide capacitance per unit area, W the width and L the length of the device, and UT the thermal voltage. This expression is valid and mathematically identical for both the bulk and FD SOI MOSFET's but the SOI n body factor is constant from weak to strong inversion according to Eq. (3), whereas in bulk, it is slightly dependent on V Q according to Eq. (2). However as a first approximation, this variation can usually be neglected7 .

10"

10" 10" V(M-C OX .W/L) (v2)

10"

Fig. 10. Experimental (symbols) and modeled (lines) transconductance over drain current ratios vs. normalized drain current in saturation: Bulk (x) and SOI (o) measurements, EKV model with n - 1.1 for SOI (—) or 1.5 for bulk case (—).

Rewriting Eq. (8) as

288

SOI CMOS Transistors for RF and Microwave Applications

l-e

1175

h/^n (Q\

ID J C

_Ip_ Is

(W/L) 2nnCmU}

I c is also called the inversion coefficient65. Denoting ID/(W/L)=I', the "adimensional" current normalized to the aspect ratio, we may deduce that the gjlo versus /' characteristic does not depend on the actual device sizes, but only on device type, technology and temperature. Hence, it appears as a universal curve that characterizes all the devices of a given type (either nMOS or pMOS) for a given technology, at constant temperature. As will be shown in Section 7, such a curve proves very efficient for topdown analog design in which device dimensions are unknowns of the problem and very difficult to guess a priori. This analysis has been extended to deep-submicron SOI CMOS processes and our results demonstrates that optimized sub-0.25 urn-effective length FD MOSFET's still present significantly larger gjlo ratios than PD and bulk devices thanks to their wellknown much better subthreshold slope and body effect. However, for the nominal 40 nm film thickness, the longer channel devices show an unexpected degradation of the g„/Io under weak inversion conditions. This has been related to non-fully-depleted conditions due to the low gate voltage applied. Whereas in shorter channel devices, the source/drainto-body depletion regions start to interact with channel depletion and fully deplete the film even at zero gate voltage. As will be discussed into full details in Section 7, the combination of this gJlD improvement with the reduction of the parasitic capacitances can be exploited to boost the performances of SOI CMOS amplifiers over bulk implementations by a factor between 3 to 10, in terms of either the transition (unity-gain) frequency, the circuit area, the dc openloop gain or the stand-by current.

3.4.2. Early voltage The EKV model incorporates the non-zero output conductance (i.e. gd =dID/dVD ) of MOS transistors in saturation by introducing the concept of channel-length modulation7 and multiplying ID by the appropriate factor. We may also define an Early voltage parameter73,74 Vea so that in saturation, gd is equal to ID IVea . This second formulation will be preferred for the opamp small-signal analyses to be discussed further. Vea indeed appears as a figure of merit for each technology since, to the first order, it does not depend on the drain current amplitude as does the output conductance. Measurements have shown that our FD SOI MOSFET's exhibit mean Vea values proportional to L as is usual and on the order of 7-10 (V/um) times the length for 2 < L < 20^/w . Such figures are similar to those of comparable bulk devices. More detailed analyses of Vea have shown strong dependence on biases and technologies75 (Fig. 11), i.e.: • an increase of Vea from WI to SI corresponding to enhanced vertical gate coupling and lesser lateral drain influence on the drain current, 289

1176 D. Flandre, J.-P. Raskin & D. Vanhoenacker-Janvier

•

an increase of Vea in FD SOI when compared to bulk MOS technology which can be intuitively explained by a reduction of the penetration of the drain depletion charge into the channel region when compared to bulk (Fig,

0.5

1.0

1.5

2.0

2.5

VdsW Fig. 11. Early voltage as a function of diain-to-source voltage, with gate bias referred to threshold (GVO - VcV„i) variedfromweak to strong inversion, for n-MOSFET's from a 2.4 \tm bulk technology ( ) and from a 2 Mm FD SOI process ( ).

BolkSiMOSFET

SOIMOSFET

Kg. 12. Intuitive interpretation of the Early voltage improvement in FD SOI MOSFET's due to a relatively smaller drain charge penetration (dark area), when compared to bulk equivalent.

Table 1 presents Veo extraction for 0.25 |im FD SOI CMOS process and shows that improved full depletion in thinner devices also tends to slightly better Vea, due to reduced 290

SOI CMOS Transistors for RF and Microwave Applications

1177

short-channel effects. But more importantly, it demonstrates that full depletion maintains a linear relationship between Vea and L, on the order of 10 V/um, from very short to long channel lengths, contrary to recently reported sublinear degraded trends in bulk Si transistors with Halo pocket implants7 . L

vD=vG 0.4 V 0.6 V 0.8 V 1.0 V L

vD=vG

0.4 V 0.6 V 0.8 V 1.0 V

0.25 urn fs,=30 nm 1.16V 2.43 V 4.37 V 9.05 V

0.25 jim r„=40 nm 0.78...0.86 V 1.81...1.84V 3.44...3.57 V 7.71V

1 um tsi =30 nm 10.05 V 13.71V 18.37 V 25.63 V

1 Jim tsi = 40 nm 6.79... 10.74 V 12.75...13.21V 15.05...16.10 V 26.97 V

Table 1. Early voltage as a function of length (L) and silicon film thickness (f„), for gate voltage equal to drain voltage and Vgbs= 0 V.

3.4.3. Intrinsic gate capacitance The intrinsic capacitances are important elements of the small-signal dynamic model of the MOS transistor73. They do not correspond however to actual physical capacitors, but are mathematical elements conveniently describing the variations of the different charges stored within the device as a function of the voltages applied to the different terminals. Considering that a MOS transistor has four terminals and that a charge is referred to each of them, we will face a complex model of sixteen intrinsic capacitances, noted Cy and defined as:

C = x-

3V,

,Xii

~U

+ 1 if

i= j

if

i*j

(10)

with i and j suffixes corresponding to either gate, source, drain or substrate terminal. As they depend on applied bias, the intrinsic capacitances are non-linear components, furthermore non-reciprocal since C„ corresponding to the variation of the charge associated to terminal i with the voltage applied to terminal j does not have to be equal to Cjj which corresponds to the variation of the charge associated to terminal j with the voltage applied to terminal i. In OTA design, the two most important intrinsic capacitances are Cgg and Css, which respectively correspond to the two basic amplifier configurations, i.e. the common-source where the device is seen from the gate and the common-gate where the device is seen from the source. The complete Cy model may therefore be reduced, for sake of simplicity, to two elements, the gate-source Cgs and gate-bulk Cgb capacitances. Since in saturation the gate-drain Cgd and non-reciprocal drain-gate Cdg capacitances both tend to be identical 291

1178 D. Flandre, J.-P. Raskin & D. Vanhoenacker-Janvier and equal to zero, Cgg indeed reduces to Cgs+Cgb = Csg+Cbg. Following Ref. 77, a worstcase approximation for Css in saturation will be to take it equal to Cgs approximately, although it is generally slightly lower. The EKV model proposes empirical analytical expressions for Cgb and Cgs, which are valid in and continuous between all regimes of operation65. Figure 13 illustrates this behavior as a function of Vc, showing that in moderate inversion, the intrinsic gate capacitances strongly depart from their well-known strong inversion values, e.g. Cgs equal to two thirds of Cox. The lower values are obviously related to the progressive build-up of the inversion layer from WI to SI and should be taken into account in efficient opamp synthesis in order to reliably locate the associated poles and zeros. Measurements16, 2-D numerical device simulations16,40 and modeling78 have shown that the intrinsic gate-to-source Cgs and gate-to-drain Cgd capacitance characteristics of FD SOI MOSFET's are similar to those of bulk devices. The source/drain-to-gate coupling through the conducting inversion channel and the gate oxide is indeed similar in both cases.

TTTryr

.& & See-* »«w-»-»-w

o 9b

^ C u ° - (.0_PJ?

i >

10 -12 *Ut_ 10 -13

30 nm

10 -14 10 -15 10



0.0

0.5 1.0 1.5 Amplitude (Vpk) Fig. 17. Second- and third-order harmonic distortions in the drain current of bulk and FD SOI MOSFET's driven as resistors, with DC gate bias set 1 V above threshold voltage and DC source/drain set to 1 V in bulk, 0 V in SOI, as a function of the ac signal amplitude superposed to the source terminal.

Experimental evidence supporting the superiority of FD SOI over bulk MOSFET's regarding linearity properties is presented in Ref. 85 (Fig. 17).

3.4.6. The CMOS analog switch The CMOS analog switch combining parallel nMOS and pMOS transistors with complementary inverted gate signals is a key block of sampled-data analog circuits (Fig. 18). A well-known problem of this structure is that the switch on-resistance increases when the supply voltage is lowered. It may even peak to very high values for mid-range input signals when VDD is decreased below a value which can be estimated by 2Vlt/(2-n), assuming identical threshold voltage and body effect parameters for n- and pMOSFET's74. FD SOI CMOS featuring reduced values for" these parameters clearly allows for correct switch operation at much lower voltages than in bulk43 (Fig. 18). /

n

V

T

v

dd,min

Bulk

1.5

0.7

3.0

SOI

1.1 1.1

0.7 0.4

1.7 1.0 J

Fig. 18. CMOS switch schematic and minimum VDD table computed from 2.VaJ(2-n).

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We have refined the analysis using the EKV model, with similar bulk and SOI parameter sets as above and minimal switch dimensions (i.e. (W/L)n = 1, (W/L)p = 2.5), in order to compute as a function of VJJ, first the maximum permissible threshold voltage which keeps the on-resistance below 50 k£2 (Fig. 19), then the resulting switch off-current (Fig. 20). A 50 k£i maximum on-resistance is a typical value corresponding to a maximum settling error of 0.01 % for a 500 kHz clock frequency and a 2 pF capacitance. We observe that the required bulk threshold voltages become extremely low for reduced VDD. The corresponding bulk off-current then exceeds the maximum admissible current, which limits to 0.01 % the relative error due to the discharge of the capacitance during the holding phase. Therefore we believe that low threshold bulk CMOS processes do not represent a viable solution for sampled-data analog circuits. Double threshold processes are required with charge-pump circuits to boost the switch gate signal above the supply voltage. On the contrary, FD SOI CMOS technology offers the simplest solution to the problem of the low-voltage CMOS switch, when using a threshold voltage of about 0.33 V compatible with both maximum on-resistance and off-current switch typical specifications for a supply voltage of 1.2 V.

3.5. High-temperature characteristics Up to now, room temperature operating conditions have only been addressed whereas circuits will generally run at a higher junction temperature due to environmental issues or just self-heating. In particular, rapid burn-in tests for IC lifetime prediction are generally conducted at 125 °C. The present paragraph will compare the temperature dependences of bulk and SOI MOS transistors. 1.2

SOI Bulk

1

fc

** s

01

8P 0.8 o

>

•

•

•

0.6

cQ 0.4 bt ^H

0.2

y

•

*

•

+

•

•

•

•

x

^

t

^

^^****^

'

0

1.5 2 2.5 3 Supply voltage V D D (V) Fig. 19. Maximum admissible symmetrical threshold voltage of n-/p-channel devices for minimal-dimension CMOS switch with maximum on-resistance of 50 k£2, as a function of VDD-

The drift of MOS transistor current-voltage curves with temperature significantly affects the correct operation of Si MOS integrated circuits. Typical static device characteristics (Fig. 21) clearly show that contrary to SOI, bulk Si MOSFET's present, above 200°C, drastically reduced ON-to-OFF current ratios and threshold voltage values which are not compatible with acceptable noise margins in digital circuits or with bias stability in analog circuits.

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1.5 2 2.5 Supply voltage V D D (V)

3

Fig. 20. Bulk and SOI CMOS switch off-currents resulting from the threshold voltages of Fig. 19 as a function of the supply voltage. Also represented is the limit corresponding to a relative error of 10"4 due to the discharge of a 2 pF-capacitance during a 1 us-holding phase.

-2

-1

0

Gate Voltage (V) Fig. 21. Drain current versus gate voltage curves of SOI (solid line) and bulk (dashed) 20/5 p-MOSFET's with Vo=3V.

Fig. 22. Simplified bulk Si MOSFET cross-section depicting depletion region extension (gray) under channel (dark) and total drain junction area contributing to leakage (large dashed line). Note that other source and wellsubstrate junctions could also contribute to leakage if reverse biased.

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The increase with temperature of MOSFET OFF leakage currents (/;«,*), defined for OFF gate bias condition typically equal to 0 V, is related to the degradation of important MOS electrical parameters: the threshold voltage (V,/,), the subthreshold slope (5) and the reverse-biased junction saturation current (Ijs). These are linked to the increase with temperature of the intrinsic carrier concentration (n/) and of the thermal voltage (U, = kT/q). In a bulk Si MOSFET (Fig. 22): • Vth decreases as the Fermi potential (ty) and the depletion width and charge under channel reduce with temperature. • IjS is proportional to n, and the total bottom and sidewall drain junction area (AjD) below 150°C when generation mechanisms in the junction depletion region dominate, and is proportional to AjD and n,2 above 150° when diffusion mechanisms of excess carriers in the quasi-neutral transition regions become dominant. The temperature behavior of a thick-film PD SOI MOSFET is very similar to bulk. Since the channel depletion region does not extend across the whole active film thickness, it changes with temperature modifying V,h and leaves a quasi-neutral region in the film contributing to junction leakage by diffusion mechanisms. However when the film is thin enough so that the junctions extend down to the buried oxide, A]D reduces to a single sidewall component proportional to the channel width (W) and film thickness (*„•) thereby drastically limiting Ijs. In a thin-film FD SOI MOSFET, the channel depletion extension being equal to the film thickness, it remains constant with temperature and V,h only depends on f. Furthermore, as quasi-neutral regions are suppressed, only generation mechanisms may contribute to Ijs, which is now proportional to «/ and the depletion region volume, i.e. W.L.tsi where L is the channel length. These basic physical behaviors are confirmed by measurements of IJs and V,h as a function of temperature, and performed on bulk and FD SOI MOSFET's (Fig. 23). It may be observed that: • bulk Iis may be up to 1 uA/um of device width at 300°C, and almost three orders of magnitude lower in FD SOI; • bulk Vth may shift by 2 to 5 mV/°C depending on doping, temperature86, etc., whereas FD SOI V,h only shifts by 0.7 to 1.5 mV/°C as long as the device remains fully depleted. Indeed, as the maximum depletion width is reduced when temperature increases, there exists a critical point, typically between 200 and 300°C depending on device optimization, above which FD SOI transistors feature a bulk-like dependence of the threshold voltage and leakage current because the film becomes partially depleted87'88'89. Three more problems of bulk Si CMOS structures1 related to leakage current and threshold voltage variations with temperature should be pointed out: • previous data did not take into account the significant leakage current of the reverse-biased well-to-substrate junctions which are required to isolate e.g. n-MOS devices realized in the P-doped bulk Si substrate from p-MOS devices located in very large-area N-doped wells contacted to the positive supply voltage.

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0

100

200

300

(°C)

Janvier

0

100

200

300

Fig. 23. ljs and V,h evolutions with temperature for bulk (+) and FD SOI (o) MOSFET's (W = 20 Jim).

•

the isolation of individual bulk Si MOSFET's also involves a thick field oxide structure which may give way to lateral parasitic transistors. Their threshold voltages are normally set much above the maximum supply voltage by field implantation, but this is usually not guaranteed for very high-temperature operation due to threshold voltage lowering. • N-P-N-P thyristor-like parasitic structures and related latch-up problems are then unavoidable in bulk Si CMOS circuits. Latch-up may potentially be triggered at lower voltages for temperatures higher than at room temperature, due to the dramatic increase of thermally generated substrate leakage currents. All these three process-related problems are totally suppressed by buried oxide isolation in SOI CMOS structures'. The basic electrical behaviors previously described explain the unavoidable physical limitations of bulk and PD SOI CMOS digital circuits operated at high temperature. Measurements on bulk Si CMOS logic gates show leakage currents per elementary gate on the order of 1 uA at 250°C even though their design was fully optimized for hightemperature operation90'91. On the other hand, FD SOI CMOS logic gates demonstrate leakage currents per inverter lower than 10 nA at 300°C without any design optimization. Similarly the measured standby currents of bulk Si and PD SOI CMOS 64 kb SRAM's 92 increase with temperature following a n,2 dependency. The latter is almost two orders of magnitude lower than the former due to drain junction area reduction (Fig. 24). However extrapolating these values for a 1Mb SRAM of interest for future VLSI applications, we end up with a static power dissipation under 5 V operation larger than 1 W at 300°C even with PD SOI technology! This seems to definitely prevent the use of bulk Si and even questions PD SOI CMOS for VLSI integration at elevated temperature, contrary to FD SOI. Furthermore, the lower temperature dependence of the FD SOI MOSFET characteristics is not only of interest for very high-temperature conditions above 200 °C, but also in the usual range of operation for IC rated up to e.g. 125 °C according to standard burn-in test conditions. Also note that starting at 125-150°C, the leakage current in PD SOI MOS is already reduced by about one order of magnitude when compared to bulk. Fig. 25 compares theoretically a conventional bulk CMOS technology with 0.7 V threshold voltage and 90 mV/dec subthreshold swing to a FD SOI CMOS featuring 0.5 V and 60 mV/dec values respectively, chosen for equal leakage at room temperature. At 300

SOI CMOS Transistors for RF and Microwave Applications

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125°C, both the bulk and FD SOI threshold voltages are lowered to approximately 0.4 V, but the better SOI subthreshold swing yields a leakage current figure more than one decade below bulk. Also note that low threshold voltage bulk CMOS results almost unpractical under such conditions. 1Mb SRAM

64Kb

10

1

> 10 0

in

® 10" o PL,

10

>-> c

CO

10" 150 200 250 Temperature (°C)

350

Fig. 24. Bulk Si and PD SOI CMOS 64 Kb SRAM standby current dissipation vs. temperature and extrapolation of standby power dissipation for 1 Mb SRAM under 5 V supply operation.

-4 v

T.bult - 0.5 - 0.3 V

= 0.5 - 0.1 V Viibulk-0-7-0-^1

0.5 1.0 Gate Voltage (V)

'

'

•

•

2.0

Fig. 25. Extrapolation of bulk and FD SOI MOS characteristics at 400 K.

This theoretical extrapolation has recently been demonstrated comparing the experimental leakage currents of 0.25 \im bulk and FD SOI MOSFET's which feature Ioff values of about 20 pA/fim93 and 2.2 pA/u.m, respectively94. This may be of tremendous importance regarding the stand-by or static power dissipation of portable systems, as well as die possibility to run IDDQ testing methodologies for rapid production validation. Reciprocally, FD SOI CMOS circuits could be tested under more severe burn-in 301

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conditions, approximately 50 to 75 °C higher than in bulk for similar leakage currents, leading to reduced testing time and costs by a factor of about X according to the classical Arrhenius law.

3.6. Conclusion SOI CMOS can now be regarded as a very attractive and mature technology for the realization of low-voltage low-power (LVLP) digital ULSI circuits owing to a number of well-known advantages over conventional bulk Si CMOS: • dielectric isolation provides reduced parasitic capacitances and leakage currents when compared to junction isolation. • full-depletion (FD) operation of thin-film SOI MOSFET's may yield quasiideal device properties such as sharper subthreshold slope, lower body effect and smaller vertical field mobility degradation. Improved subthreshold slopes in turn allow for the use of lower threshold voltages for identical subthreshold leakage current values. These characteristics all add up to significantly increase the drive capability, in particular for reduced supply voltages. • thinned films and dielectric isolation result in simplified submicron CMOS processes: threshold voltage roll-off is minimized, reliable ultra-shallow junctions are easily obtained, wells and latch-up are suppressed and complicated lateral isolation process can be avoided. • the low temperature dependence of FD SOI MOSFET's drastically minimizes the increase of the leakage currents for typical ratings above 70100 °C, thereby reducing the stand-by power consumption in this range of temperature or enabling rapid IDDQ or burn-in testing above 125 °C. Regarding analog properties, available models for the important small-signal conductance and capacitance characteristics of fully-depleted SOI MOSFET's have been discussed and validated. These have been exploited to investigate the impact of the improved device characteristics of FD SOI MOSFET's, i.e. smaller subthreshold swing, body factor and parasitic capacitances, on the performances of several basic analog cells. We have found that: • CMOS analog switches can still be operated at a supply voltage as low as 1.2 V when optimized in FD SOI CMOS. • FD SOI CMOS has the potential to boost the speed, accuracy, power and area performances of 1- and 2-stage operational amplifiers well over bulk implementations, especially when moderate inversion operation of the active devices is considered, as is common in LVLP circuits. • the linearity properties of FD SOI MOS resistors could be much better than those of bulk counterparts, which is of high interest for LVLP filter implementations. By demonstrating the great potential of FD SOI CMOS for high-performance analog and mixed-mode analog-digital low-voltage low-power applications, this study has opened a whole new field of applications for this technology. In the next sections, the analysis will be extended to microwave performances and finally applied to high-performance circuit design.

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4. Microwave Characterization of Passive Elements on the SOI Substrate This section is devoted to the analysis and modeling of passive elements on SOI substrate, starting with a preliminary analysis of the behavior of the SOI substrate at high frequencies. This model is used afterwards for the transmission lines and integrated inductors.

4.1. High frequency behavior of the SOI substrate The fundamental difference between the Si substrate and the GaAs substrate is the fact that the silicon resistivity is lower then the GaAs one, so that Si cannot be considered as a dielectric for microwave applications. The behavior of the substrate is a function of bias conditions and frequency and will be analyzed for the microstrip structure represented in Fig. 26. The microstrip transmission line is considered as a quasi-TEM transmission line, the transverse lineic (i.e. per unit length) elements are a capacitor and a conductance accounting for the substrate losses. The behavior of the MIS (Metal-InsulatorSemiconductor) capacitor illustrated in Fig. 27, has been reported in the literature for some years. Some models are based on the behavior of the charges in the structure but most of them are limited to a few MHz, assuming that the majority carriers in the semiconductor are responding to voltage variations without delay95,96'97'98' 10°. The relaxation time of the majority carriers is neglected. On the other hand, some authors had a special interest in the distribution of electromagnetic fields in planar lines on semiconductor substrate. Hasegawa101 defines three fundamental modes in such structures: • the dielectric quasi TEM mode • the skin-effect mode • the slow-wave mode.

I Sl(»,

Metal

>*~*—• • •—•"—• • — • — • • • • ' » dielectric mode -6

? o 0|0 -2

o"poop

0 2 dc Bias Condition [V]

Fig. 28. Small-signal characteristics of SOI capacitive structure versus applied dc voltage for various frequencies, d0I = 1 (im, ds, = 500 |im and psi = 4000 Q.cm.

The classical theory explains the low frequency curves: • for positive bias conditions, there is an abundance of electrons below the oxide. For a p-type substrate, this is called an inversion layer. At low frequencies, the minority carriers follow the excitation. This is not the case anymore when the frequency increases (see Fig. 28 in the kHz range). The inversion layer charge cannot keep up with fast variations of the voltage and the required charge changes are provided by covering or uncovering acceptor atoms at the bottom of the depletion region, just as in the case of depletion operation. When the frequency increases above 1 kHz, the inversion layer cannot follow the variations because it is isolated from the outside world. Thermal generation and recombination only can change its electron concentration; those phenomena are very slow. • for negative bias conditions, there is an abundance of holes below the oxide (accumulation), forming the "bottom plate" of the capacitor. As a consequence, the total capacitance is approximately equal to the oxide capacitance. The 2D-Medici simulator gives results in agreement with the above-mentioned theory for low frequencies. It however takes into account the distribution of the potential and the carrier concentration, as well as their evolution with frequency, so that the simulation shows a rapid decrease of the equivalent capacitance for positive and negative bias conditions, at frequencies above 1 MHz. A further decrease happens between 1 MHz and 1 GHz. The section below will briefly explain the behavior of the capacitive structure versus the relaxation time of the carriers.

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4.1.2. Influence of the relaxation time of the minority and majority carriers on the parameters of the MOS capacitor The relaxation time of the minority carriers expresses the inertia of the inversion layer under the oxide layer. For a p-type substrate, the minority carriers are the electrons. Three sources can supply minority carriers to the inversion layer: an electron diffusion current from the bulk silicon, a volume generated current within the depletion region or a surface generated current directly related to the surface states at the insulator-semiconductor interface. Sah et al"°. have demonstrated that the finite generation-recombination within the space charge region is the dominant factor controlling the frequency response of the inversion layer. The generation and recombination of electron/hole pairs carry out the charging and discharging of the inversion layer through traps in the depletion region. These traps may be crystal lattice dislocations, impurity atoms located interstitially or substitionally in the crystal lattice, or surface defects. Hofstein and Warfield96 define for the strong inversion layer regime, a resistance Rgr associated with this generationrecombination: Rgr=^h

(16)

where \j/s, X& n, and x0 are, respectively, the surface potential, the thickness of the depletion region, the density of electrons or holes in an intrinsic semiconductor, and the time carrier density fluctuation to decay to its equilibrium concentration by recombination through traps. This lifetime is typically the order of 10"6 sec. This equivalent resistance allows taking into account the frequency response of the inversion layer. The relaxation time of the minority carriers is given by Tgr = RgrCb,

where Cb is the capacitance

associated to the depletion region under the oxide layer. The simplified equivalent circuit for SOI capacitive structure represented in Fig. 29 is valid in the strong inversion regime. The limits of the equivalent capacity Cgb are

Cgb —> Cox

for

co«x~gr

and

C +C Cgb —» —^ — for co > r~ . In weak or moderate inversion and in depletion regime C

oxCb

C C this model is not valid for co « T~r]. Cgb tends to — o x c

with Cc - C, + Q,.

Cox + Cc

Tsividis104 gives a general expression of Cc valid in all regimes. The depth of the depletion layer depends on the substrate doping, so it is with the capacitor Cb. As a direct consequence, the relaxation time of the minority carriers depends strongly on the substrate resistivity: the minority carriers react up to higher frequencies for higher resistivity silicon substrates. The inertia of the majority carriers is often neglected in the literature. The 2-D Medici simulator however shows that this hypothesis is not valid anymore for frequencies higher than a few MHz. When frequency increases up to GHz, neither minority neither 306

SOI CMOS Transistors for RF and Microwave Applications

1193

majority carriers follow the variation of the applied potential. The silicon substrate is then considered as a dielectric with losses. The final model for inversion mode, taking into account the minority and the majority carrier inertia, is represented in Fig. 29; Csi and Rsi represent the inertia of majority carriers.

Oxide layer

Minority carriers inertia

Majority

carriers inertia

T Fig. 29. Complete model for capacitive structure valid for inversion mode.

Measurements have been performed up to 500 MHz, to check the validity of the model (Fig. 30). The measured capacitor has been made on a SOI wafer with an oxide thickness of 0.4 u\m and a silicon substrate thickness of 500 urn. The capacitive structure has an area of 900x1200 um2. 100 C„

inversion • O Model Measurements

ilr iimffiiiil ^— 0

Frequency [Hz]

307

(a)

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D. Flandre, J.-P. Raskin & D.

Vanhoenacker-Janvier

/

where Vlh0 is the long-channel zero-drain bias threshold voltage, dvM accounts for the charge sharing effect and aD/BL accounts for the DIBL effect. The total charges are obtained by integrating the charge densities along the channel. Analytical expressions are obtained as functions of qnfiS and qnfj. The intrinsic capacitances are obtained by differentiation of total charges with respect to the applied voltages. When we split the device into several sections, we apply the above equations of drain current and charge to each section. This means that we define a source and a drain for each section, which correspond to the two ends of the section. In each section end, we consider a channel charge density. Therefore, the expressions of the current and charges in each section have the same form as in a real transistor, but they are written in terms of the channel charge densities corresponding to the source and the drain defined for each section (these are now qnfj and q„fj), which in turn, depend on the front and back gate voltages, and the voltage difference between the drain and the source of the section. It is the simulator, by iteration, which obtains the values of the voltages between the section drains and sources. However, note that the drain of the section next to the source, the source of the section next to the drain, and the source and the drain of the middle section are artificial sources and drains; this implies that the parameters defined for these sections do not follow the scaling rules in the same way as a real transistor. Therefore, parameters dvM and aDIBL will not have the same parameters in these sections as in a real transistor of the same channel length. By definition, the total gate capacitance cg, used in the calculation of the lumped element cge,

includes both the extrinsic and intrinsic gate capacitance elements.

However, in order to use our equivalent circuit in a circuit simulator it is necessary to derive cg in a closed-form expression. For simplicity we have made cg equal to the total extrinsic gate capacitance. We have proven that this approximation gives a sufficient improvement of the S-parameters phase values under all practical bias conditions.

5.3. Extraction Procedure 5.3.1. Intrinsic Part The parameters of the model used for the intrinsic transistors are extracted under DC conditions by combining direct algorithms with global optimization144. In Fig. 44a and b, we show comparisons of the measured and modeled DC characteristics (drain current

322

SOI CMOS Transistors for RF and Microwave Applications

1209

versus VGS and VDs) for deep-submicron transistors. These transistors come from a 0.25 |im process developed at LETT, Grenoble, France138. The front and back gate oxides are, respectively, toxf = 4.5 nm and toxb = 400 nm. However, because of the quantum effect, it is necessary to consider in the model an effective oxide thickness, tOXfeff, which is larger than the real one, since the distance between the channel and the interface is not negligible compared to the oxide thickness. This quantum effect has been confirmed by RF measurements of the gate oxide capacitance, from which we have extracted the value of the effective oxide thickness (t0^,eff= 5.8 nm)148. The Si film thickness is tb = 30 nm. The transistors are composed of 16 fingers of 6.6 urn width (W) each connected in parallel. 14 VGfS = 0.9V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Drain Voltage [V] (a) • L e fr=0.16 nm x L e ff=0.26|im a Leff=0.41 nm c 8 u i—

3 6

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Gate Voltage [V] (b) Fig. 44. Comparison of measured (symbols) and modeled (a) ld-Vos and (b) /d-Vq/s of a SOI nMOSFET with L,j = 0.16 urn. Solid line: three-section model; dashed line: one section model.

When we split the transistor into three shorter transistors, a few parameters related to the short-channel effect have to be changed in order to obtain the same I-V c :jtics of the single transistor. The standard scaling rules cannot exactly be applied to these 323

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shorter transistors, since it is just the transistor closest to the drain, which comprises most of the longitudinal field effects. The transistor closest to the source and the one in the middle have a more "long-channel" behavior despite they may be very short. As a result, we only consider the DIBL effect in this drain-side transistor and neglect it in the other two transistors. The charge-sharing effect does not depend on the longitudinal field. However, the scaling rule of the charge-sharing in the real transistor should not be followed in these shorter transistors and we observed that in each section the reduction of threshold voltage because of charge-sharing is smaller than for the single transistor; the charge sharing is modeled in the three transistors using the same parameter value for all of them. Anyway, because of the physical basis of the model, these two parameters are the only ones that have different values for different numbers of sections. The rest of the parameters are the same in the three shorter transistors as in the single one. 35 30 S 25

=8). This OTA experimentally achieved a 103 dB-DC open-loop gain and a 271 kHztransition frequency over a 12.3 pF-load capacitance with a 60c-phase margin and a total bias current of only 2 uA under a 3 V-supply voltage, in accordance with the targeted and simulated specifications. 347

1234 D. Flandre, J.-P. Raskin & D. Vanhoenacker-Janvier

(W/L) 1.2 (W/L) 3.4 (W/L) 5.6 (W/L) 7.8 (gn/lD) 1-2

(gJh) 3-6 (gnflu) 7-8 /DD (MA)

/r(kHz) Avo (dB) phase margin (degrees) output swing (V)

SOI 30/3 33/3 66/3 30/3 25.8 22.3 22.7 3 350 44 85.6 0.9

BULK 27/3 23/3 46/3 17/3 18 14.5 14 4.32 350 41 85.4 0.75

Table 5. Experimental SOI and simulated bulk design parameters and performance of the 1-stage CMOS OTA of Fig. 66 (CL = 10 pF, B - 2). The bulk simulations used the same technology parameters as the SOI simulations in good agreement with the measurements, except for the body effect and junction capacitances, as given by the values of Table 4.

Fig. 69. Cascoded CMOS OTA architecture.

The output swing was almost equal to 2 V. Using our gJID procedure again with the bulk parameters, we simulated that to achieve a similar fT performance with same CL and phase margin, the bulk implementation could only have used gjlo ratios of 19 and 17 for the input differential pair and output cascode devices respectively, and would then have dissipated 45 % more supply current for a DC open-loop gain reduced by 8 dB. Furthermore, the simulation showed that for higher transition frequencies, the FD SOI benefits over bulk increase up to a reduction of the supply current by a factor larger than 3.5 and an improvement of the gain by more than 20 dB, for/ r equal to 10 MHz (Fig. 70). Even though the active device gJID values have to be reduced towards strong inversion

348

SOI CMOS Transistors for RF and Microwave Applications

1235

(13 and 3.5 V"1 in SOI and bulk respectively at 10 MHz). In these estimates, the gJID ratios of both SOI and bulk current mirrors were taken constant and equal to 5 V . Concerning the output swing and noise performance, the results of the above analysis, as a function of fT were used to compute the total input-referred thermal noise power spectral density in bulk and SOI from equations (52) - (53). The bulk to SOI noise ratio ranges from 1.54 at 100 kHz to 3.11 at 10 MHz. To achieve the same thermal noise performance, lower gn/Ip values could be used in bulk for the current mirrors according to (53): the higher the transition frequency, the higher the bulk to SOI bias current ratio, the lower the bulk mirror gJID for the same noise and the larger the output swing reduction in bulk when compared to SOI. In our case this output swing reduction in bulk may attain several volts, even for l o w / r resulting in unpractical designs.

c) High-frequency applications We demonstrate here the potential of SOI CMOS technology on high-resistivity substrate towards the implementation of operational amplifier classical architectures with transition frequency above 1 GHz, without the need for extra compensation technique (e.g. feed forward) to boost the frequency performances. Such wideband amplifiers may be required for analog signal processing at intermediate RF frequencies in communication systems. 25

20~

3 n 15 %

< io 5

} 100K

1M Transition frequency (Hz)

5 10M

Fig. 70. Comparison of simulated total current dissipation and DC open-loop gain performance of the bulk and SOI cascoded CMOS OTA's of Fig. 69 (with fl-mirror ratio equal to 2) as a function of the transition frequency. The computations were based on the EKV model using the set of parameters of Table 4.

In these applications the opamps are capacitively loaded, locked in closed loop and have to be stable in unity-gain feedback. Consequently, behavioral models of opamp performances and device parameters valid in a large frequency range are required to extend usual OTA design based on the phase margin criterion to the GHz range. Two opamp architectures have been considered. In both cases, behavioral analytical expressions of the gain-bandwidth product (GBW) and phase margin performance are derived from the device transconductances and capacitances as discussed in previous sections. For frequencies above about 100 MHz, the transconductances and source/drainto-substrate capacitances become frequency dependent and influence the opamp transition

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Vanhoenacker-Janvier

frequency and internal poles and zeros. High frequency opamp design then requires the correct modeling of both the transconductance and substrate capacitances as presented above. Several opamp implementations have been realized with 1 \im gate length SOI MOSFET's. The opamp voltage gains (Av), total transconductances G and output impedance ZgM were extracted from on-wafer scattering parameter measurements. The transition frequency (fT) and the phase margin •

0

i

~t'

i

10

o . 03 •

1010

10 Frequency (Hz)

Fig. 71. One-stage OTA simulated (-) and measured (o) total transconductance as a function of frequency. 40

:- -.. 30

a 20 O 10

k "

,

"

•

iid.-... x

0

1

-10 10°

10'

v

-

10°

i_; HT

10 10

Frequency (Hz) Fig. 72 Measured voltage gain of the one-stage with G=2pF (- -) and 6pF (-) and the folded-cascode opamps

withCi=6pF(-).

The quite low DC voltage gains Av are due to the device short channel length and the strong inversion operation. Nevertheless for second order sigma-delta converters with low 350

SOI CMOS TYansistors for RF and Microwave Applications

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over sampling rate or using reduced gain sensitivity technique e.g., these gain values are sufficient. They may also be sufficient for other high-frequency switched-capacitor filtering applications.

7.1.3. Conclusion Our OTA synthesis methodology has further been exploited to investigate the impact of the improved device characteristics of FD SOI MOSFET's, i.e. smaller subthreshold swing, body factor and parasitic capacitances, on the performances of several basic OTA architectures. We have found that FD SOI CMOS has the potential to boost the speed, accuracy, power and area performances of 1- and 2-stage operational amplifiers well over bulk implementations, especially when moderate inversion operation of the active devices is considered, as is common in LVLP circuits. By demonstrating the great potential of FD SOI CMOS for high-performance analog and mixed-mode analog-digital low-voltage low-power applications, our study has opened a whole new field of applications for this technology. Furthermore, our synthesis procedure has been successfully extended, in other works, to a number of other CMOS OTA architectures (two-stage Miller OTA43, folded-cascode 2-stage OTA, regulated-cascode 3-stage OTA171, multipath hybrid nested Miller 4-stage OTA, etc.), considering a variety of small- and large-signal specifications (gain, transition frequency, phase margin, settling time, noise, slew rate, distortion, PSRR, CMRR, etc.), and operating conditions (high-temperature169; high-frequency80; capacitive and resistive loads ) as well as applications (instrumentation opamp173; MOSFET-C continuous-time filter172; SC L-A modulator174175, RF carrier detector176, current-mode structures177, capacitive pressure transducers178, radiation-hardness179180). The validity of the synthesis procedure has been successfully demonstrated by the experimental realizations of several of those circuits.

7.2 Microwave oscillators Two basic oscillator families are used in the microwave frequency domain: series and feedback oscillators181. They are represented in Fig. 73. Due to high substrate losses and source biasing difficulties, parallel feedback structures were chosen: the first one with active feedback and the second one with passive feedback (inductance). The active feedback structure is represented in Fig. 74. It can be viewed as 2 inverters face to face, with a tank inductor in parallel. The oscillation criteria imposes that the impedance of the inductance ZL should meet the following conditions Re(Z L +Z o „,) 4. These performances can be easily achieved on SOI with a spiral inductor136. The circuit schematic is shown in Fig. 74 and, with more details, in Fig. 75. VI

Z2

I

ir

Y3

Y2 Z3

Fig. 73. Microwave oscillators structures (a) series feedback, (b) parallel feedback.

w

•**0W

T

Si

1

a) Silicon dangling bond

Si

I

—Si

o

Si--Si O

\)

j

J

Si

b) Oxygen dangling bond

O—Si

Si

c) Oxygen vacancy V 0

Fig. 2. Atomic structures of defects in the bulk of silicon dioxide.

At the silicon-silicon dioxide interface, a family of traps generally known as Pj, centers exist which are silicon dangling bonds where silicon is bonded to three other silicon

366

RF CMOS Reliability

atoms, Si3=Si-, and the other three silicon atoms are in the substrate. is shown in Figure 3.

1253

This interface traps

oxide / 1 x.

—Si

substrate

P SiSi

I

Fig. 3. Atomic structures of defects at silicon-silicon dioxide interface.

In the following section, some of the different mechanisms by which hot carriers can damage the device are explained in more detail.

2.1. Channel hot-electrons (CHE) As mentioned before, one of the damages caused by hot carriers is trapped charges in the gate oxide. These charges are carriers in the channel, which on their way from source to drain gain high enough energy so that they can overcome gate oxide potential barrier 4>6 and penetrate into the gate oxide. The event of a carrier gaining energy and entering the gate oxide is a statistical phenomenon. A model called lucky-electron model, has been developed.17 This model takes into account several probability factors in order to calculate the gate current Ig which is representative of hot carriers entering the gate oxide.'7 According to this model, as carriers are accelerated by the lateral electric field in the channel, their move is hindered by scattering caused by the lattice. Some types of scattering called optical phonon and impact ionization scattering cause the carriers to loose their energy and are called inelastic scattering. The probability of a carrier traveling a distance d without experiencing any energy robbing scattering is exp(-dfk) in which X is called the scattering effective mean free path. Some other types of scattering called acoustical phonon scattering, do not cause the carriers to loose their energy significantly. The acoustical phonon scattering, also called elastic scattering, only causes redirection of carriers. Similar to inelastic scattering, a parameter Xr is defined as the redirecting scattering mean free path, and the probability of a carrier redirection over the differential distance dx is dx/ Xr In the redirection process carriers can isotropicly be redirected to all directions and part of them will be directed toward the silicon-silicon dioxide interface. Again, for carriers directed toward the interface, there is a probability involved that some of them reach the interface without any energy robbing scattering. Finally, the probability for carriers which have entered the gate oxide to reach the gate terminal is P(E0X) in which Eox is the electric field inside the oxide. Since the events involved for a carrier to reach the gate terminal are independent from each other, the over-

367

1254 S. Naseh & M. J. Deen

all probability for one carrier reaching the gate terminal is the product of probabilities of each single event. The final result of this analysis can be expressed as:

/ „

=

/

1 * * ( ox>r J/** p E

d]

(3)

dx

b

0

r

in which P^b is the probability of a carrier gaining energy higher than b and retaining its momentum when it reaches the interface and is a function of electric field in the channel, L 11

is the channel length, Id is the drain current and / is the gate current. graphical exhibition of channel hot electron mechanism.

Figure 4 shows a

v„ VH

JTX

^

p substrate

drain

Fig. 4. Channel hot electron generation. The dashed line shows the border between depletion region and neutral bulk.

-9

io r -10 10

10

a

3>

io

10

10

0

J 2

L 4

6 V

8

J 10

c>V

Fig. 5. Measured gate current versus gate voltage (from reference 18).

368

L 12

RF CMOS Reliability 1255 Experimental verification of this model has been reported and shows good agreement with measurement.17 The gate current /„ can be an indicator for the amount of charge trapped inside the gate oxide. A sample measurement of/„ versus gate voltage V„ for constant Vds is shown in Figure 5. The shape of the Ig versus Vds can be qualitatively explained as follows. At low values of V the transistor is in deep saturation which means there is a pinch-off region formed near drain where a high lateral electric field is present. But at low values of Vg, the electric field in the oxide near drain is in a direction which inhibits collection of carriers. As Vg increases, the vertical electric field in the gate oxide near drain becomes favorable for collection of carriers, but at the same time transistor moves toward the linear region from the pinch-off region, and therefore the lateral electric field in the pinch-off region gradually disappears. Since variation of lateral and vertical electric fields are opposite to each other there is a point where Ig has a maximum. The value of Vg at which this maximum happens

is V^Vfr As mentioned in the introduction, however, there have been observations of hot carrier effects even when power supply is low enough so that qVdd is less than both threshold energy for impact ionization and Si-Si0 2 barrier height.7'8 This is not possible according to the simple lucky electron model explained above. Therefore a new model was introduced which assumes that electrons are in quasithermal equilibrium with the electric field and therefore energy distribution of electrons follows the Fermi-Dirac statistics.19 This energy distribution can be approximated by Maxwell-Boltzmann distribution as in the case of hot carriers we are mostly interested in the high energy region of the distribution. According to these energy distributions, there is a certain probability that the electron may gain any energy. Therefore it is possible that electrons have energies above the impact ionization threshold energy or Si-SiC>2 barrier height. The improvement provided by quasithermal equilibrium approach has been incorporated into the lucky electron model.20

2.2. Drain avalanche hot-carriers (DAHC) Another effect that can be caused by energetic carriers in the channel is that carriers on their way toward drain collide with the lattice atoms and generate new electron and hole pairs. These electron and hole pairs can also gain high energy in the electric field and produce new electron-hole pairs, similar to avalanche process in a reversed biased p-n junction. This process is shown in Figure 1 b in the avalanche plasma. During the same process, the energetic carriers can impinge on the atomic bonds at the interface of the substrate and gate oxide or inside the oxide, and break them, thus creating dangling bonds. As a result, new electronic states Nit are created at the interface and these Nit can affect the electrical performance of the device.18

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In a NMOS transistor, the extra electrons which are generated by the avalanche process are absorbed by drain, and the generated holes are absorbed by substrate terminal which form the substrate current component Isub. Typical measurement results of Isub versus Vg at various Vjs a NMOS transistor are shown in Figure 6.

0.30

0.40

0.50

0.60

0.70

v g oo Fig. 6. Measured substrate current versus gate voltage.

As is shown in Figure 6, the variation ofIsub versus V„ for a constant V^s has a maximum. The explanation is as follows. It is known that generation of electron-hole pairs in an avalanche process is proportional to both strength of electric field and the number of primary carriers initially flowing in the channel, that is, carriers which originally flow in the channel and generate new electron-hole pairs by colliding with the lattice atoms. For low values of Vg above threshold, the transistor is in deep saturation and a pinch-off region is formed near the drain which results in a strong lateral electric field in that region. Also, at low values of V the drain current Id is low. As V increases Ij increases but transistor comes out of saturation region gradually. In other words, the variations of the number of primary carriers and the strength of the electric field in the channel with respect to Vg are opposite to each other. This causes that a maximum value for Isub appears at some particular value of Vg It has been observed that this maximum usually happens at about Vg=VJ2. It is reported that the biasing condition which causes maximum Isub is where maximum damage is generated in NMOSFETs.18

370

RF CMOS Reliability

1257

2.3. Substrate hot electrons (SHE) Unlike the cases of CHE and DAHC, which were caused by lateral electric field in channel, SHE are caused by the vertical electric field between gate and substrate. The electrons which are thermally generated in the region below the gate, drift toward the silicon-silicon dioxide interface and gain kinetic energy in the electric field below the gate.

^

^

^_^^ i _ ^ _ _ _ ^ _ ^

p substrate

-* v d

!_?^__

drain

Fig. 7. Substrate hot electron generation.

This is shown in Figure 7. Some of these electrons penetrate into oxide and cause a uniform distribution of trapped charge in the oxide. SHE is not a major problem in short channel devices as most of the electrons are absorbed into source and drain region and a smaller fraction them reaches the device surface, compared to the long channel devices.

2.4. Fowler-Nordheim tunneling (F-N) A mechanism by which electrons can be injected into the gate oxide is tunneling. If a strong electric field is applied between metal plate (gate in a MOSFET), and bulk or substrate of a MOS structure so that direction of electric field is in favor of attracting electrons from bulk toward the gate, electrons may tunnel from the conduction band of the silicon to the conduction band of the silicon dioxide. This mechanism of tunneling is called Fowler-Nordheim tunneling (F-N). The comparison of F-N tunneling and direct tunneling is shown in Figure 8. The current density between gate and substrate is shown both experimentally21 and theoretically to be in the following form: A

-B/E

J = Ks

(4)

in which constants A and B depend on the electron's effective mass and the potential barrier height at silicon-silicon dioxide interface, and Eox is the electric field in the gate oxide.

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This current is shown to cause degradation of the gate oxide and eventually its breakdown.22 Fowler-Nordheim tunneling

Metal

Si02

direct tunneling

Si

Metal

Si02

Fig. 8. Comparison of Fowler-Nordheim tunneling and direct tunneling.

In MOS transistors, as the gate oxide becomes thinner, F-N tunneling can be important. Unlike CHE and DAHC mechanisms which were caused by the lateral electric field in the channel, F-N tunneling is caused by the vertical electric field between the gate and the channel. Therefore, if a large voltage is applied to the gate, this mechanism of current can be important especially near the source which the highest electric field between gate and substrate exists.

2.5. Hot carrier degradation

ofMOSFETs

Different opinions has been suggested about the mechanism of device degradation as result of hot carriers. In some researches, only trapped charges are considered as the source of device degradation.10'11'23'24'25 In some others, interface trap generation is considered as the reason for device degradation. 13 ' 18 ' 26 ' 27 ' 28,29 ' 30 ' 31 ' 32 ' 33 ' 34 There are as well reports where both kinds of damages are considered to be involved in device degradation.35'36'37 Although the idea that only electron injection being responsible for NMOSFET degradation has been reported,27'28 in most of the researches, it has been proposed that hot holes as well as hot electrons are involved in the process of interface states generation at the silicon-silicon dioxide interface.13'29'30'38 It is observed that the maximum interface state generation in NMOSFETs coincides with the maximum Isub condition, and in PMOSFETs the maximum interface traps generation happens at the condition V^Vj which coincides with maximum hot hole injection into the gate oxide.29 This observation confirms that hot holes are important in interface state generation.

372

RF CMOS Reliability

1259

2.6. Lightly doped drain MOSFETs In order to reduce the hot-carrier effect in the MOS transistors, the doping profile of the drain and source are modified in a way that electric field in the pinch off region is reduced. By introducing a narrow, lightly doped n-type region between the channel and the n+ drain and n+ source diffusion regions the so called Lightly Doped Drain (LDD) MOSFET is created. In this structure the high electric field in the drain pinch off region is reduced by spreading it into the n- region, similar to spreading of electric field in a lightly doped p-n junction. Therefore, it is possible to have shorter channel length with the same Vds voltage, or use higher power supply voltages, without having too high electric field in the pinch off region. This structure is shown in Figure 9. t

gate

n+ LDD regions p substrate

Fig. 9. LDD MOSFET structure.

As a result of reduction of electric field, the impact ionization is reduced in LDD MOSFETs compared to the conventional MOS transistor structure. For the same reason, avalanche breakdown also happens at higher Vds voltages. The LDD structure also provides an improvement in the punchthrough voltage of the device, and alleviates the fall off in the threshold voltage due to short channel effects. On the other hand, the introduction of the lightly doped region adds to the ohmic resistance in series with drain and source, but this effect is not seriously affecting the device performance.39

3. Experimental Tools for Hot Carrier Damage Detection For the purpose of studying effects of hot carriers on MOS transistors, experimental tools are required to investigate the damage caused by hot carriers. One of the important experimental technique used in the study of the hot carrier damage in MOS transistors is the charge pumping measurement. Charge pumping is a powerful technique applied to a MOS transistor which is used for determining the interface traps distribution in the energy band gap and also their spatial profile in the channel. Two other types of measurements, C-V measurement and floating-gate measurement, will also be discussed briefly. C-V measurement, a technique for investigation of the sili-

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con-silicon dioxide interface quality in MOS capacitor, can also be used to study the effect of hot-carriers on the MOSFETs by measuring the device parasitic capacitors Cgd and Cgs. Floating-gate measurement is a technique by which the gate current is measured and it is possible to distinguish whether it is caused by hole injection or electron injection.

3.1. Charge pumping method Charge pumping technique as a mean to study the interface traps at the interface of the silicon substrate and gate oxide of a MOSFET was reported for the first time by the authors of.40 The experimental setup and circuit connection for charge pumping experiment is shown in Figure 10.

pulse generator

JL /\

/\

V

ISL.

^

£J

p substrate

XT ^reverse

DC AMMETER

Fig. 10. Charge pumping measurement setup.

In this experiment, the drain and the source of the MOS transistor are connected together and a reverse voltage is applied between drain/source and substrate terminals. A pulse generator applies voltage pulses between the gate and the substrate in a way that it switches the surface underneath the gate between inversion and accumulation. During inversion, a layer of charge made of substrate minority carriers appear underneath the gate. These charges mainly originate from the source and drain diffusion regions. Some of these carriers fill the fast electronic states at the interface of the substrate and the gate oxide. When the gate voltage changes so that surface underneath the gate returns into the accumulation state, the free minority carriers which form the inversion layer return to the source and drain diffusion regions. The charges trapped in the interface states recombine with the substrate majority charges. Also, a small fraction of the free carriers in the inversion layer may recombine with the majority charges of the substrate too. These two com-

374

RF CMOS Reliability

1261

ponents are called interface trap component and geometric component, respectively, and together, they form a current which flows from substrate to the drain and the source. Therefore, this current, which is called charge pumping current, can be written as: 40 hp=MGWit-aC0X(Vgh-Vth))

(5)

in which: / =charge pumping current, / = frequency of the applied gate pulse, AG = gate area, q = electron charge Nit = fast interface states density, a = fraction of free carriers under gate which recombine with substrate majority carriers, Cox = gate oxide capacitance per unit area, Vgh = gate voltage during the inversion and, Vth - threshold voltage. Usually the waveform of the pulse applied to the gate is chosen in a way that the free carriers have enough time to return to the source and drain, and therefore geometric component of the charge pumping current is small compared to the interface trap component. Therefore, / can be a measure of the density of the fast interface traps under the gate. This forms the basis of the charge pumping technique for studying the interface traps in MOS transistors. In interpreting the result of charge pumping experiment, it is important to consider the kinetics of the charging and discharging of the interface traps.41 Therefore, in the following section, the capture and emission processes are briefly explained. Interface traps can be acceptor type or donor type. Acceptor traps are the traps which are either in neutral state or negatively charged, and donor traps are traps which can be either in neutral state or positively charged. A trap can charge or discharge through both emission and capture processes at the same time. For example, a neutral acceptor trap can capture an electron or emit a hole, i. e., receive an electron from the valence band and it becomes negatively charged. A negatively charged acceptor state can emit an electron or capture a hole, i. e., send an electron to the valence band, and it becomes neutral. The probability per unit time that an interface state can emit (e„ ) or capture (c ) a charge using the Shockley-Read-Hall model is: 42 ' 43 C

n

=

a v

(6>

*n

=

a v

n thnl>

(?)

a V

p ,hPs

(8)

% = apvthPi

(9)

c

p

=

n thns'

and:

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in which o~n and a p are the capture cross section of electrons and holes, respectively; v^, is the thermal velocity of the carriers; given by: vth = (3kT/m*)W2

(10)

in which m* is the effective mass of carrier, and ns andps are the density of electrons and holes at the surface; and: -{E'-E-)/kT . ( * , - * • > / « •

(11) (

i

2

)

in which nt is the intrinsic density of electrons, E{ is the intrinsic Fermi energy and E, is the energy of the trap in the band gap. ny is the electron concentration in the conduction band and p] is the hole concentration in the valence band that would exist, if the trap energy E, coincided with the Fermi energy EF, and the Boltzmann approximation of the Fermi function is used. If an is much larger than crp, then the trap has a much higher tendency to capture electrons than to capture holes. These sort of traps are considered as electron traps. If o n is much smaller than o p , then the trap is considered as a hole trap, and if 0 n and d p are comparable to each other, then the trap is called generation-recombination center. Using the expressions (6) to (9), it can be shown that if the surface conditions are suddenly changed so that interface states change their charge state, the transition from neutral to negatively charged states occurs exponentially with the time constant:

and the time constant for the transition from the negative state to neutral state will be: t = l/(c„ + e n ).

(14)

in which traps are considered as acceptor type. In the charge pumping experiment, if Ton and T0jr defined as the length of time gate that voltage is kept at V h and Vgi, respectively, are sufficiently long, then the interface traps will reach to an equilibrium with the free carriers in the channel. Also, if rise time Tr and fall time Tf of the pulse applied to the gate are short enough, the interface traps will not have time to emit any charge. In this case, the charging and discharging of traps are done by capture of electrons in inversion and capture of holes in accumulation, respectively. However, if the rise time of the gate voltage is not short, then the interface traps may emit holes during the rise time. The traps which charge this way will not be able to capture electrons as the inversion layer forms in the channel, and therefore they do not contribute to the charge pumping current. In order to simplify the analysis, it may be assumed that free carriers in the channel are in equilibrium with the gate voltage, that is, free electrons

376

RF CMOS Reliability 1263 and holes in the channel are only a function of gate voltage and independent of time. But the interface states are not in equilibrium with the free carriers in the channel and their charge exchange process has the time constants explained before. As the gate voltage varies, when it is slightly above the flat band voltage, it can be assumed that the hole emission process is dominating, and as gate voltages increasingly becomes closer to the threshold voltage, then electron capture becomes dominant. It can be assumed that the interface traps below a certain level Eemh which have a short time constant are negatively charged by emitting holes, and therefore, they do not contribute in the charge pumping. Therefore Eemh sets a lower limit for the energy levels which can be covered in the charge pumping process. During the fall time, as the gate voltage becomes less than the threshold voltage the inversion channel gradually disappears. The interface traps which emit electron before the channel has disappeared will not contribute to the charge pumping current as these charges are collected by the drain and the source terminals. But the interface traps which emit their electrons after the channel has disappeared will contribute to the charge pumping because the emitted electrons recombine with the majority carriers (holes) in the substrate. Similar to the rise time, an energy level can be assumed above which the electron emission time constant is so short that they emit electrons before the inversion layer disappears, and therefore, they do not contribute in the charge pumping current. This sets an upper limit for the energy level which contribute to the charge pumping current. A similar analysis can be performed for the case of donor traps at interface. The charge emission and capture by interface traps which was explained need to be considered in order to be able to consistently explain the observations in charge pumping measurements. The basic experimental setup which now is used for charge pumping measurement has stayed the same. But different schemes for applying the gate voltage have been suggested by different groups in order to improve the measurement. 4 In one class of charge pumping experiments known as variable amplitude mode, the base level voltage applied to the gate, Vgi, is kept constant and the high value of the voltage pulse, Vgh, is increased gradually. In the case of NMOSFET, Vgj value is chosen below flat-band voltage Vpg so that channel is in accumulation. By gradually increasing the amplitude of the pulse, so that Vgh becomes greater than the flat-band voltage, the transistor moves into depletion and as Vgh increases to values above threshold voltage, the channel goes into inversion. A typical charge pumping current versus Vgh is shown in Figure 11. The regions 1, 2 and 3 specified on the plot correspond to values of Vgh 7T + cLL'

sL + L +

S

^gs

(41)

^gs

It is seen that by choosing the value of Ls properly, the real component of the input impedance can be adjusted to the desirable value. Also, the imaginary component of the input impedance disappears at the frequency at which the reactances of s(Lg+LJ and 1/ sCgs cancel each other. The inductor Lg at the gate of Ml provides a degree of freedom in determining the frequency at which input impedance becomes purely real, and by adjust-

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ing its value, this frequency can be adjusted. Capacitors Cc are coupling capacitors and their values are large enough that at the frequency of interest, they will have a small impedance. It should be emphasized that in real circuits and devices, the presence of gateto-drain capacitor Cgcj and drain-source resistor Rds means that the load at the drain of the transistor Mj also affects the input impedance of the amplifier. However, simulation of the input impedance, using the small signal model of Figure 25, shows that essence of the inductive source degeneration technique for amplifier's input matching is still valid and by choosing a proper value for Ls, it is possible to satisfy the matching conditions. The feasibility and performance of the circuit in Figure 30 for RF signal amplification has already been confirmed and reported by measurement on a similar circuit. In order to analyze the performance of the circuit, the operating point of each transistor and their small signal model at those operating point should be known. The biasing current of each transistor for the biasing voltages shown in Figure 30 before hot carrier stress is obtained from the previously measured DC characteristics of the transistors and is 3 mA.

D 0.005 0.003 0.001 -0.001 -0.003

2

4

6

1

8

10

8

10

-

-0.005 I

:

8

0.05 0.04 0.03 0.02 0.01 0.00

0.002 0.000 0

2

4

6

8

0

10

Frequncy (GHz)

2 4 6 8 Frequency (GHz)

10

Fig. 32. Comparison of the Y-parameters of the small signal model (dashed line) and measurement (square symbols). The squares almost completely overlap the dashed lines, and this indicates good agreement between model and measurements.

398

RF CMOS Reliability

1285

The parameters of the small signal model of the transistors at this biasing point are extracted from their S-parameter measurement using the procedures similar to that of. In order to make sure that the extracted small signal model is valid, a comparison of the Yparameters calculated from the small signal model and the Y-parameters derived from measured S-parameters of the transistors before hot-carrier stress are shown in Figure 32. In these plots model parameters are shown by dashed line and measurements by squares. There is a good agreement between the model and measurement and therefore the graphs almost completely overlap and cannot be distinguished from each other. To investigate the effect of hot-carrier on the performance of this amplifier, it can be assumed that both transistors Mj and M2 follow the same degradation pattern, as both of them are biased at the same operating point. By setting both the input source impedance Zs and load impedance RL equal to 50 Q, as happens in many practical cases,83 the voltage variation at the drain of the transistors M[, assuming a 1 mV p-p signal at the amplifier's input, can be shown by simulation to be about 30 mV p-p. Almost the same amount of variation appears at the gate and drain voltage of M2. This level of variation compared to the gate and drain biasing voltages of the transistors are very small and negligible. Therefore, the DC bias voltages across the transistors can be used to determine what mode of hot carrier stress (e. g., CHE, DAHC, etc.) exists in the transistors. For the biasing voltages shown in Figure 30, the DAHC mechanism is dominant. Therefore, the accelerated aging condition specified in Figure 16 is used to do the analysis. It can further be assumed that all the other elements and biasing voltages in the circuit are not affected by the hot carrier stress. Therefore, for the purpose of this investigation, it is enough to replace each of the MOS transistors in the circuit with their small signal model before and after stress. The inductors in the circuit are considered on chip inductors and in the simulation, the inductors are replaced with their 7t-model equivalent circuit obtained from S-parameter measurement of the real spiral inductors which had been fabricated with the same technology. It is assumed that Rb and C c can be modeled by a single resistor and capacitor, respectively. It should be mentioned that since after hot carrier stress, the I-V characteristics of the device changes, then the biasing current of the transistors change to 2 mA for the biasing voltages shown in Figure 30. The small signal model used for the transistors in the simulation are extracted at the new operating point. One important issue in the LNA is the matching at the input of the circuit. The reflection coefficient at the input of the amplifier defined as: Z

-Z

r .in = - ^ — i

(42)

z. +z in

s

and it can be a considered as the criteria for measurement of mismatch at amplifier's input. Zs is the signal source impedance. In Figure 33, the magnitude of r / n versus frequency is

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0.3 before stress after stress

^ °

2

I 0.1

0.0 2.00

J

I

I

I

L

2.05

2.10

2.15

2.20

2.25

2.30

Frequency (GHz) Fig. 33. Reflection coefficient of the input of the LNA before and after hot carrier stress. Stress condition: Vg = 0.65 V and Vd = 3.7 V.

plotted. It is assumed that both the signal source and the load impedances are 50 Q . It is clearly seen that after the hot carrier stress the matching at the LNA's input is disturbed. There are two points which need to be explained. First, it was observed that the value of the load connected to the output of the amplifier affects the value of the input impedance of the amplifier. This means that the NMOSFETs used in the circuit are not unilateral devices. By considering the small-signal model of the transistors, it can be stated that the gate-to-drain capacitor Cg(j, which has an impedance less than 2 kQ at 2 GHz, provides a path between output and input of each transistor. Also, the output resistance of the MOSFETs Rfc provides another connection between output and input of the device. This is to be expected as device channel length becomes shorter, which causes a more pronounced channel length modulation effect. This is especially important in the design of the first stage of the LNA where the presence of the inductor at the transistor's source provides feedback from the output to the input. This importance can be further confirmed by the trend of variation of input impedance versus frequency, before and after stress. As mentioned before, the gate-to-source capacitor Cgs increases with stress, which then may raise the expectation that the frequency at which input impedance of LNA, Zin, becomes a pure real resistance would shift to lower frequencies after hot-carrier stress. The result of simulations show the opposite trend. In fact, it can be shown by simulation that both the decrease in gm and the decrease in Rjs shift the minimum r i n to higher frequencies. Therefore, the effects of degradation of gm and Rds on the input impedance is more prominent than that of the degradation of C„s due to hot carrier stress.

400

RF CMOS Reliability

1287

The second point is that care should be taken in the use of r,-„ as a measure of mismatch. If the signal source impedance Zs has an imaginary part other than zero, a reflection coefficient r,„= 0 does not correspond to the conjugate matching of the signal source and LNA, which is the desirable condition at LNA's input. Another important parameter of the LNA is its power gain. The transducer power gain GT is defined as the ratio of the power dissipated in the load to the power available from the source, before and after stress, and it is shown in Figure 34. Clearly, this parameter has also decreased after stress and it shows a shift in frequency similar to that of the input reflection coefficient. The drop in the power gain is due to both the increase in input mismatch and the decrease in the overall voltage gain of each transistor. 25 CO •o

(9

I

20

-

15

-

after stress

/

10

/'"\\

/

1

/ i

i

3

4

1

1

2

2

3

\

4

Frequency (GHz) Fig. 34. Transducer power gain before and after stress. Stress condition: Vg = 0.65 V and ^ = 3 . 7 V .

Another important parameter of the amplifier is its stability. The parameter u has been shown to be an appropriate measure of two-port networks stability:84 1-IS,

(43)

Is^-iSj^l + |s12s21| in which: A

^ l 1^22 ~ ^ 1 2 ^ 2 1 '

(44)

If the value of \i is more than 1, then the two-port network is unconditionally stable, and also a higher value of [i indicates a more stable two-port. From Figure 35, it is seen that before stress the LNA has conditional stability but after stress it becomes uncondi-

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tionally stable. This probably can be attributed to the decrease in the gain of the LNA, as generally, higher gain is associated with lower stability. 1.80 1.60

§

1.40

2

1.20

S 1.00

0.80 1

2

3

4

Frequency (GHz) Fig. 35. Stability factor \i versus frequency before and after stress. Stress condition Vg = 0.65 V and Vd = 3.7 V.

6. Summary In this chapter, the effects of hot carrier stress on the NMOSFETs parameters and its electrical performance were presented. First, the operating mechanisms of a MOSFET was described. Using these mechanisms, it was shown that because of presence of strong electric fields, e. g., as in pinch-off region when device is operating in saturation mode, hot carriers are generated. Different mechanism of hot-carrier generation like channel hot electron (CHE), drain avalanche hot carriers (DAHC), substrate hot electrons (SHE) and Fowler-Nordheim tunneling were explained. Important experimental tools, such as charge pumping and C-V measurement which are used for studying the silicon-silicon dioxide interface in MOSFETs and MOS capacitors, and floating gate measurement which is used to measure the gate leakage current in MOSFETs were explained. The results of measurements of hot-carrier effects on the RF and DC electrical parameters and characteristics of NMOSFETS were presented using the accelerated aging process. Degradation of parameters like transconductance gm, threshold voltage Vth, output conductance gds and transit frequency fT of an NMOS transistor were demonstrated. It was shown that drop in transit frequency is caused by the decrease of gm and the increase of

402

RF CMOS Reliability 1289

And finally, using the results of measurements of hot-carrier effects on NMOSFETs, the effects of hot carriers on the performance of a LNA made of NMOS transistor were simulated. It was shown that matching at the input of the LNA is disturbed by hot carriers. The gain of the amplifier drops and also the frequency of the maximum gain is shifted due to hot carriers. And as a result of drop in amplifier's gain, its stability increases.

Acknowledgements We thank Dr. D. Landheer, National Research Council, Ottawa and Dr. N.R. Das, McMaster University, Hamilton, for their careful review of parts of this manuscript. We are also grateful to several of our current and previous colleagues for their interest and support, and for their comments and useful suggestions on our work over the past several years. Finally, we are grateful to the Natural Sciences and Engineering Research Council (NSERC) of Canada and Micronet, a federal network center of excellence in microelectronics for partial financial support of this work.

Reference [1] H. Iwai; "CMOS Technology-Year2010 an Beyond," IEEE Journal ofSolid State Circuits, Vol. 34, No. 3, pp. 357-366, March 1999. [2] R. H. Dennard, F. H. Gaensslen, H-N Yu, V. L. Ridout, E. Bassous and A. R. LeBlanc; "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions," IEEE Journal of Solid State Circuits, Vol. 9, No. 5, October 1974, pp. 256-268. [3] C. S. Kim, M. Park, C-H. Kim, Y. C.l Hyeon, H. K. Yu, K. Lee, K. S. Nam; "A Fully Integrated 1.9-GHz CMOS Low-Noise Amplifier," IEEE Microwave and Guided Wave letters, Vol. 8, No. 8, pp. 293-295, August 1998. [4] M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, N. Ito, T. Yashiomi. T. Ohguro, H. Sasaki Momose and H. Iwai; "0.15-um RF CMOS Technology Compatible with Logic CMOS for Low-Voltage Operation," IEEE Transactions on Electron Devices, Vol. 45, No. 3, pp. 737-742, March 1998. [5] J. N. Burghartz, M. Hargrove, C. S. Webster, R. A. Groves, M. Keene, K. A. Jenkins, R. Logan and E. Nowak; "RF Potential of 0.18-um CMOS Logic Device Technology," IEEE Transactions on Electron Devices, Vol. 47, No. 4, pp. 864-870, April 2000. [6] Y. Tsividis, "Operation and Modeling of the MOS Transistors." New York, McGrawHill, second edition, 1999, chapter 6. [7] J. E. Chung, M-C Jeng, J. E. Moon, P-K Ko and C. Hu; "Low-Voltage Hot-Electron Currents and Degradation in Deep-Submicrometer MOSFET's," IEEE Transactions on Electron Devices, Vol. 37, No. 7, July 1990, pp. 1651-1657. [8] L. Manchanda, R. H. Storz, R. H. Yan, K. F. Lee and E. H. Westerwick; "Clear Observation of Sub-Band Gap Impact Ionization at Room Temperature and Below in 0.1 um Si MOSFETs," IEDM Technical Digest, 1992, pp. 994-995.

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Selected Topics in Electronics and Systems - Vol. 24

CMOS RF MODELING, CHARACTERIZATION AND APPLICATIONS CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cutoff frequencies of about 50 GHz have been reported for 0.18 urn CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of today's popular wireless products, such as cell phones, GPS (Global Positioning System) and Bluetooth. Of course, the great interest in RF CMOS comes from the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. This book discusses many of the challenges facing the CMOS RF circuit designer in terms of device modeling and characterization, which are crucial issues in circuit simulation and design.

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