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Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Timing Analysis Dynamic Timing Analysis (DTA) Static Timing Analysis (STA)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Dynamic Timing Analysis
So-called Simulation ¾ ¾
Input vectors are applied during the simulation time Simulator calculates the logic value and delays
Disadvantages of DTA ¾
Virtually impossible to do exhaustive analysis • •
¾
¾
Vector creation takes too long Incomplete timing coverage
Hard to discern the cause of failure because the function and timing are analyzed at the same time Requires more memory and CPU resources over STA • •
Long simulation time Capacity limited
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Static Timing Analysis (1/2) A method for determining if a circuit meets timing constraints without having to simulate clock cycles Three main steps
¾ ¾ ¾
Break the design into sets of timing paths Calculate the delay of each path (create timing graph) Check all path delays to see if the given timing constraints are met
IN
D
Q QN
D
Q
OUT
QN
CLK
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Static Timing Analysis (2/2)
IN
D
Q QN
D
Q
OUT
QN
CLK
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Static Timing Analysis Reduction
IBM’s Hitchcock (70’s)
observed that you could exhaustively test all behaviors within a single clock cycle
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Advantages of STA Exhaustive timing coverage Does not require input vectors More efficient than DTA in memory and CPU resources
¾ ¾
Faster operation Capacity for millions of gates
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Disadvantages of STA For synchronous logic only Difficult to learn Tricky constraints beyond the boundaries of single clock flip-flop design chips:
¾ ¾ ¾ ¾
Multiple clocks False paths Latches Multi-cycle paths
Lack of consistent conventions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Review Main Steps of STA Break the design into sets of timing paths Calculate the delay of each path (create timing graph) Check all path delays to see if the given timing constraints are met
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Four Types of Timing Paths
Start Point: clock pin of sequential device End Point: data input pin of sequential devices
Start Point: primary input port End Point: data input pin of sequential devices
Start Point: clock pin of sequential device End Point: primary output port
Start Point: primary input port End Point: primary output port
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Timing Path Example How many start points are in this design? How many end points are in this design? How many timing paths are in this design?
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Create Timing Graph
Netlist is represented as directed acyclic graph (DAG) Delay values associated with links (Cells & Nets) are calculated Create the timing graph of arrival time (AT) Create the timing graph of required time (RT) Create the slack graph ¾
Timing is met when slack is greater than or equal to zero (RT should always be after AT)
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Timing Graph – Arrival Time 1.45
0.3 0.1 0.4
Tarr = 0.1
0.2
1.55 0.1 0.15
0.55
0.15
1.3 0.1
Timing Arc
0.1
1.2 0.65 0.20.85 0.1 0.2 0.7
0.3 0.4
0.2 0.9 1.0 0.1
0.2 0.1 0.2 0.6
0.1 1.3
Tarr = 0.1
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Timing Graph – Required Time
0.3 0.1 0.4 0.1
0.2
1.4
0.15
1.25 0.1
0.05
0.15 0.1
0.55
Treq = 1.5
0.1
1.15 0.65 0.20.85 0.1 0.2 1.4 0.65 0.2 0.95 0.25 0.35 0.1 0.2 0.1 0.2 0.55
0.1
Tarr = 1.5
setup time case Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Slack Graph 0
0
-0.05 -0.05
0 -0.05
0 0 -0.05
-0.05
-0.05
-0.05
-0.05 -0.05
0.2
-0.05 -0.55
Slack = Required Time – Arrival Time setup time case Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Block -based vs. Path -based STA (1/2) Block-based Path-based
Block-based: timing information is associated with discrete design elements (ports, pins, gates) ¾
Slack is calculated on every design element
Path-based: timing information is associated with topological paths (collections of design elements) ¾
Used in Primetime
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Block -based vs. Path -based STA (2/2) Block-based Path-based Path-based:
AT=2 3 1 AT=5
AT=2
2 1 3 2
RAT=10
3 1
AT=2 RAT=5
3 1 AT=5 AT=5 RAT=4
2 1
AT=7 RAT=7
Block-based: 3 2
AT=6 RAT=5
3 1
2+2+3 = 7 (OK) 2+3+1+3 = 9 (OK) 2+3+3+2 = 10 (OK) 5+1+1+3 = 10 (OK) 5+1+3+2 = 11 (Fail) 5+1+2 = 8 (OK)
AT=9 RAT=8
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
RAT=10 AT=11 RAT=10
Critical path is determined as collection of gates with the same, negative slack: In our case, we see one critical path with slack = -1
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Timing Arcs Describes the timing relationship between two nodes When traversing the design structure to update AT and RT, STA is actually traversing through timing arcs from node to node Defined in cell library
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Combinational Arcs
Combinational arcs (Timing delay) ¾ ¾ ¾
Combinational arcs are the default arcs Each combinational arc has one of three timing senses Timing senses are specified in the library or automatically derived from the logic function
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Setup Timing Arcs
Setup arcs (Timing check) ¾
Constrains the time before the active clock edge when the data needs to be stable • •
setup_rising setup_falling
CK
D
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Hold Timing Arcs
Hold arcs (Timing check) ¾
Constraints for the time after the active clock edge when the data still needs to be stable • •
hold_rising hold_falling
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Edge Arc Types
Edge arcs (Timing delay) ¾
After a launching clock edge, the clock node is converted to a data node • •
falling_edge rising_edge
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Preset and Clear Types
Preset and Clear arcs (Timing delay) ¾
After an active asynchronous signal occurs, the time the data appears at the output of the register • •
¾
positive_preset / negative_preset positive_clear / negative_clear
These arcs are often disabled
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Recovery Types
Recovery arcs (Timing check) ¾
The amount of time before an active clock edge an asynchronous signal needs to be inactive • •
recovery_rising recovery_falling
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Removal Arcs
Removal arcs (Timing check) ¾
The amount of time after an active clock edge an asynchronous signal needs to be inactive • •
removal_rising removal_falling
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Three State Arcs
Three state enable & disable arcs (Timing delay) ¾
Special timing relationship for three state activation • •
three_state_enable three_state_disable
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Minimum Pulse Width Types
Width arcs (Timing check) ¾
The amount of time a signal needs to remain stable • •
nochange_high nochange_low
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Timing Verification Items
Timing Checks ¾ ¾ ¾ ¾ ¾ ¾
Setup time Hold time Recovery time Removal time Minimum pulse width Glitch detection (clock gating) Å User-defined
Design Rule Checks ¾ ¾ ¾
Max capacitance Max transition Max fan-out
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Clock Gating Checks D
Q
D
QN
Q QN
Enable
U1
CLK Setup Margin
Hold Margin
CLK Enable Enable
Distorted Clock Waveform Gated_Clock Enable
Glitch due to late arrival time of Enable Gated_Clock Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Data Preparation for STA Gate-level Netlist
Back-annotated Parasitic
Design Data
Interconnect Data
Block Models
Estimated Wire Load Models
STA Descriptions of Clocks Cell Library Library Data
Timing Constraints Boundary Conditions
Operating Conditions Timing Exceptions
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Library Data
Cell Delay model ¾ ¾
Linear model Non-linear model
Operating conditions
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delay time (ns)
Linear Cell Delay Model
T0
Cell Delay = T0 + Ac * Cload
output capacitance load (pf) T0 : cell pin to pin intrinsic delay (delay without any loading) Ac : drive impedance
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Non -linear Cell Delay Model Non-linear Delay values are stored in the delay tables Delay tables
¾ ¾
Cell delay Transition delay
50%
Vin
50%
Vout 20%
I1 I2 Dtransition(I1)
Dc
Dtransition(I2) I3
Req
Dcell(I2) Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
80%
Ceq 33
Delay Tables Cell Delay
Dcell(I2) = f(Dtransition(I1), Ceq)
Transition Delay
Dtransistion(I2) = g(Dtransition(I1), Ceq)
Output Capacitance
Input Transition 0
0.5
1
0.1
0.123
0.234
0.456
0.2
0.222
0.432
0.801
Vin I1 I2 Dtransition(I1)
index1: input transition Index2: output capacitance
Dc Vout Dtransition(I2) I3
Req
Dcell(I2) Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Ceq 34
Select the Correct Delay Table
According to output transition direction ¾ ¾
rise table fall table
F
Output transition direction depends on unateness ¾ ¾ ¾
invert (positive_unate) noninvert (negative_unate) nonunate •
R
The worst case delay is selected
R or F R
Consider the clock edge for sequential cells ¾ ¾
edge_rising edge_falling
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Operating Conditions The process, voltage, and temperature (PVT) ranges a design encounters Specified in the technology library Cell and interconnect delays are scaled
Dscale = D (1 + ∆ P K P )(1 + ∆V KV )(1 + ∆ T K T ) ∆ P = Pr ocess − nom _ process / ∆V = Voltage − nom _ voltage ∆ T = Temperature − nom _ temperature delay
delay Worst
delay
Worst Typical
Worst
Best Typical
Typical Best
Best Process
Voltage
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Temperature 36
Data Preparation for STA Gate-level Netlist
Back-annotated Parasitic
Design Data
Interconnect Data
Block Models
Estimated Wire Load Models
STA Descriptions of Clocks Cell Library Library Data
Timing Constraints Boundary Conditions
Operating Conditions Timing Exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Define Timing Constraints
Design rule constraints ¾ ¾ ¾
Set fan-out constraints Set capacitance constraints Set transition time constraints
Design optimization constraints ¾ ¾ ¾ ¾
Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Define Clock Specification We need to accurately specify the clock including the clock routing details in the early design stage in order to achieve timing convergence What should be defined?
¾ ¾ ¾
Period Waveform Latency • •
¾
Uncertainty • •
Source latency Network latency Jitter Skew
All register-to-register path are constrained now
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Clock Period & Waveform Period: Clock cycle time Waveform: Clock rise and fall time Example:
¾ ¾ ¾
Period: 10ns Rise time: 0ns Fall time: 5ns
clock 0
5
10
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Clock Latency
A very important part of the clock is the routing effects: ¾
Off Chip cause: •
¾
Source latency (delay): the timing a clock signal takes to propagate from its ideal waveform original point to the clock definition point
On Chip cause: •
•
Budgeted network latency (delay) : the time the clock signal takes to propagate from the clock definition point to the clock pin of the sequential cells Actual insertion delay D Q QN
network latency source latency (min_rise : max_rise : min_fall : max_fall) Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Clock Uncertainty Definition
The maximum difference between the arrival of clock signals at sequential cells in one clock domain or between domains P1 FF
P4 FF
P2 P3
FF
Arrival(P1) Arrival(P2) Arrival(P3) Arrival(P4)
= = = =
0.5ns 1ns 1.2ns 1.3ns
uncertainty = 1.3 – 0.5 = 0.8ns FF
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Clock Uncertainty
A very important part of the clock is the routing ¾
Off Chip impact: •
¾
Jitter: typically a small value
On Chip impact: • •
Budgeted skew Actual skew
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Ideal and Computed Clocks
Off chip clock effects are fixed throughout flow: ¾ ¾
On chip routing is estimated till clock tree routing ¾ ¾
Source Latency Jitter Budgeted network latency Budgeted skew
On chip routing is calculated after clock tree routing ¾ ¾
Actual insertion delay (network latency) Actual skew
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Define Timing Constraints
Design rule constraints ¾ ¾ ¾
Set fan-out constraints Set capacitance constraints Set transition time constraints
Design optimization constraints ¾ ¾ ¾ ¾
Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
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I/O Constraints
After constraining clock, we still need to constrain the I/O ¾ ¾
Only comboin needs a "budgeted" arrival time Only combout needs a "budgeted" required time
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Boundary Conditions
Input driving cell Input transition time Output capacitance load Input delay Output delay D
Q
Driving Cell INV01
b 5pf
QN
Output Capacitance Load Input Transition Time
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Input & Output Delay An input delay is the specification of an arrival time at an input port relative to a clock edge An output delay represents an external timing path from am output or inout port to a register
Input delay = Delayclk-Q + a Q
a
Input Block
Q
My Design
b
c
Output Block Output delay = c
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Define Timing Constraints
Design rule constraints ¾ ¾ ¾
Set fan-out constraints Set capacitance constraints Set transition time constraints
Design optimization constraints ¾ ¾ ¾ ¾
Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Constraint Combinational Path Delay Set a target maximum delay for output ports Override the default single-cycle timing for paths Set a target minimum delay for output ports Override the default hold relation in a sequential path
IN
Logic
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
Out
50
Define Timing Constraints
Design rule constraints ¾ ¾ ¾
Set fan-out constraints Set capacitance constraints Set transition time constraints
Design optimization constraints ¾ ¾ ¾ ¾
Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions • •
False Path Multi-cycle path
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
Why are there false path constraints in a design? ¾
¾
¾
¾
¾
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Unexercised Path
A path may exist in the circuit but never be used in its normal functional operation ¾
A test register PROBE is inserted in the circuit to enable chip debugging in the field. Data can be read through the probe register. Data can be written from the probe register. Probing would not occur at speed. (An alternative to scan)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
Why are there false path constraints in a design? ¾
¾
¾
¾
¾
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Irrelevant Path
A functional path may exist but the timing is so slow or irrelevant ¾
The chip uses a synchronized synchronous reset. The reset cycle has a huge number of cycles before it needs to settle.
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Asynchronous Path
A functional path may exist but the timing is so slow or irrelevant ¾
I have metastabilization registers between those two asynchronous clock zones
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
Why are there false path constraints in a design? ¾
¾
¾
¾
¾
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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IP Reuse
A block may be reused and certain signal functions are no longer required ¾
This piece of logic is a custom adder. With design re-use, often the blocks contain all of the potentially useful functions. When the design is implemented in a chip, often particular signals are not implemented
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
Why are there false path constraints in a design? ¾
¾
¾
¾
¾
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Logically Impossible Path
A path may exist in the circuit but no combination of input vectors may ever exercise it ¾
¾
¾
A signal cannot travel from the Q output of a_reg through the two muxes to b_reg PrimeTime attempts to automatically detect "logically impossible false paths“ (requires many CPU cycles) These situations are quite rare
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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False Path
Why are there false path constraints in a design? ¾
¾
¾
¾
¾
A path may exist in the circuit but never be used in its normal functional operation A functional path may exist but the timing is very slow or irrelevant A block may be reused and certain signal functions are no longer required A path may exist in the circuit but no combination of input vectors may ever exercise it A combinational loop exists in the design that needs to be broken
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Combinational Loops
A combinational loop exists in the design that needs to be broken ¾
¾
Most STA’s can’t leave combinational loops in the design, as a race condition will occur PrimeTime dynamically breaks combinational loops.
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Break Combinational Loops Break any reset arc (unusually specified) Break a three-state enable arc Break at the first loop re-entry point Break arcs in the library
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Define Timing Constraints
Design rule constraints ¾ ¾ ¾
Set fan-out constraints Set capacitance constraints Set transition time constraints
Design optimization constraints ¾ ¾ ¾ ¾
Define clock specification Specify boundary conditions (I/O timing requirements) Specify combinational path delay requirements Specify timing exceptions • •
False Path Multi-cycle path
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Multicycle Paths
Multicycle paths occur because the designer knows that the particular logic function will not be used till a later cycle
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Data Preparation for STA Gate-level Netlist
Back-annotated Parasitic
Design Data
Interconnect Data
Block Models
Estimated Wire Load Models
STA Descriptions of Clocks Cell Library Library Data
Timing Constraints Boundary Conditions
Operating Conditions Timing Exceptions
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Interconnect Data Estimated delay information for nets based on a wire load model is used before P&R Back-annotated (Actual) delay information based on the P&R result is often described in the form of
¾
SDF (timing information) – Standard Delay Format •
¾ ¾ ¾
SDF triplet: (min:typ:max)
RSPF – Reduced Standard Parasitic Format DSPF – Detailed Standard Parasitic Format SPEF – Standard Parasitic Exchange Format •
SPEF also has syntax that allows the modeling of capacitance between different nets, so it is used by the crosstalk analysis tool
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Wireload Model
Very inaccurate!
500um x 500um 1000um x 1000um
wire_load (“500”) ( resistance : 3.0 capacitance: 1.3 area: 0.04 slop: 0.15 fanout_length ( 1 , 2.1 ) fanout_length ( 2 , 2.5) fanout_length ( 3 , 2.8) fanout_length ( 4 , 3.3)
/* R per unit length*/ /* C per unit length */ /* area per unit length */ /* extrapolation slope*/ /* fanout-length pairs */
Cwire = (fanout=3, length =2.8) x capacitance coefficient (1.3) = 3.64 load units Rwire = (fanout=3, length =2.8) x resistance coefficient (3.0) = 8.4 resistance units AreaNet = (fanout=3, length =2.8) x area coefficient (0.04) = 0.112 net area units Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Wireload Modes
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Parasitic Model During P&R
Compute wire length ¾ ¾ ¾
Compute parasitic value ¾ ¾
Ideal Manhattan Model Computed Manhattan Model Global Routing Model Linear parasitic model Table lookup parasitic model
Calculate wire delay ¾ ¾
Elmore Model Final Layout Model
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Ideal Manhattan Model
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Computed Manhattan Model
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Global Routing Model
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Table Lookup Parasitic Model
Table-Look-Up (TLU) Capacitance model ¾
CapTable •
¾
cap_value = f(configuration, width, spacing)
CapModel •
•
Assign CapTable to the reference layer according to the configuration Capacitances are categorized into bottom, top and lateral group
M2
top
air M1
lateral substrate
Poly configuration1
configuration2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
bottom
configuration3 74
Elmore Model
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Final Layout Model
AWE (Extraction Based) Model ¾ ¾
p1 , p2 – Poles r1 , r2 - Residues
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Perform Static Timing Analysis Gate-level Netlist Block Models Cell Library Operating Conditions
Descriptions of Clocks Boundary Conditions
Back-annotated Parasitic
Specify design data & libraries
Estimated Wire Load Models
Specify interconnect Specify timing constraints
Constraint Violation Reports
Path Timing Reports
Timing Exceptions
Check Timing Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (Assumptions)
Check setup time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (Timing Constraints)
Clock definition ¾ ¾ ¾ ¾
Clock period: 14ns (Dclkp) Clock source latency: 2ns (Dclks) Clock network latency: 3ns (Dclkn) Clock uncertainty: 1ns (Dclku)
IO constraints ¾ ¾
Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY)
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STA Example 1 (Timing Paths)
Timing Path 1 Timing Path 2 Timing Path 3 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (AT of Path1 - Rise)
Timing path 1: PI to clock data input ¾
Arrival time at end point: Da+2+3+2+3+2 = 13ns source clock (ideal)
launch edge 13 14
0
capture edge
target clock (ideal)
AT
R
2
Why are the delay values chosen?
AT = 13 3
R 2
R
2
3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (AT of Path1 - Fall)
Timing path 1: PI to clock data input ¾
Arrival time at end point: Da+2+2+2+3+2 = 12ns source clock (ideal)
launch edge 12
0
14 capture edge
target clock (ideal)
AT
F
2
Why are the delay values chosen?
AT = 12 2
F 2
R
2
3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (RT of Path1 - R/F)
Timing path 1: PI to clock data input ¾
Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns source clock (ideal)
launch edge 0
14 target clock (ideal) 16
target clock (source)
capture edge 19 target clock (source+network) 18 RT 17 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
target clock (source+network +uncertainty) setup time
83
STA Example 1 (Slack of Path1 - Rise)
Timing path 1: PI to clock data input ¾ ¾
Slack at end point: RT - AT = 17-13 = 4ns Timing is met since slack is greater than 0 R
2
AT = 13 RT = 17 3
R 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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2
3
84
STA Example 1 (Slack of Path1 - Fall)
Timing path 1: PI to clock data input ¾ ¾
Slack at end point: RT - AT = 17-12 = 5ns Timing is met since slack is greater than 0
F
AT = 12
2
RT = 17 2
F 2
R
2
3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (AT of Path2 - Rise)
Timing path 2: clock to clock data input ¾
Arrival time at end point: Dclks + Dclkn +3+2+3+2+3+2 = 20ns source clock (ideal) 0
19 20
14
5 launch edge
AT
Why are the delay values chosen?
AT = 20 3
R2
3
R 2 3
source clock (source +network)
2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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86
STA Example 1 (AT of Path2 - Fall)
Timing path 2: clock to clock data input ¾
Arrival time at end point: Dclks + Dclkn +3+2+2+2+3+2 = 19ns source clock (ideal) 0
19
14
5 launch edge
AT
Why are the delay values chosen?
AT = 19 3
F2
2
F 2 3
source clock (source +network)
2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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87
STA Example 1 (RT of Path2 - R/F)
Timing path 2: clock to clock data input ¾
Required time at end point: Dclkp + Dclks + Dclkn - Dclku - Ts = 14+2+3-1-1 = 17ns source clock (source+ network)
launch edge 0
5
14
target clock (ideal) 16
target clock (source)
capture edge 19 target clock (source+network) 18 RT 17 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
target clock (source+network +uncertainty) setup time
88
STA Example 1 (Slack of Path2 - Rise)
Timing path 2: clock to clock data input ¾ ¾
Slack at end point: RT - AT = 17-20 = -3ns Timing is not met since slack value is negative
AT = 20 3
R2
3
RT = 17 R 2 3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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R
89
STA Example 1 (Slack of Path2 - Fall)
Timing path 2: clock to clock data input ¾ ¾
Slack at end point: RT - AT = 17-19 = -2ns Timing is not met since slack value is negative
AT = 19 RT = 17 3
F2
2
F 2 3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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R
90
STA Example 1 (AT of Path3 - Rise)
Timing path 3: clock to PO ¾
Arrival time at end point: Dclks + Dclkn +3+2+3+2= 15ns source clock (ideal) 0
5 launch edge
14 15 source clock (source +network)
AT
3 R
AT = 15
2
R 3 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (AT of Path3 - Fall)
Timing path 3: clock to PO ¾
Arrival time at end point: Dclks + Dclkn +3+2+2+2= 14ns source clock (ideal) 0
14
5 launch edge
source clock (source +network)
AT
3 F
AT = 14
2
F 2 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 1 (RT of Path3 - R/F)
Timing path 3: clock to PO ¾
Required time at end point: Dclkp - DY = 14-3 = 11ns source clock (source+ network)
launch edge 0
5
11
14
target clock (ideal) output delay
RT
3 F
RT = 11
2
F 2 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Q
3
QN
2 93
STA Example 1 (Slack of Path3 - Rise)
Timing path 3: clock to PO ¾ ¾ ¾
Slack at end point: RT - AT = 11-15 = -4ns Timing is not met since slack value is negative This is the critical path
AT = 15
3 R
D
RT = 11
2
Q
3 R 3
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
QN
2
94
STA Example 1 (Slack of Path3 - Fall)
Timing path 3: clock to PO ¾ ¾
Slack at end point: RT - AT = 11-14 = -3ns Timing is not met since slack value is negative
AT = 14
3 F 2
F 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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RT = 11
Q
3
QN
2
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STA Example 2 (Assumptions)
Check hold time violations Assume all gates have 3ns max rise delay and 2ns min rise delay Assume all gates have 2ns max fall delay and 1ns min fall delay Assume all nets have 2ns max delay and 1ns min delay 3ns CLK-Q delay 1ns setup time (Ts) 1ns hold time (Th)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (Timing Constraints)
Clock definition ¾ ¾ ¾ ¾
Clock period: 14ns (Dclkp) Clock source latency: 2ns (Dclks) Clock network latency: 3ns (Dclkn) Clock uncertainty: 1ns (Dclku)
IO constraints ¾ ¾
Input delay of A, B, C: 1ns (Da , Db , Dc) Output delay of Y: 3ns (DY)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (Timing Paths)
Timing Path 1 Timing Path 2 Timing Path 3 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (AT of Path1 – R/F)
Timing path 1: PI to clock data input ¾
Arrival time at end point: Da+1 = 2ns source clock (ideal)
launch edge 14
0 2 capture edge AT Next Data
target clock (ideal) Why are the delay values chosen?
AT = 2 D
Q
R/F 1
1
QN
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (RT of Path1 - R/F)
Timing path 1: PI to clock data input ¾
Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns source clock (ideal)
launch edge 0
7 target clock (ideal) target clock (source) target clock (source+network) capture edge RT
target clock (source+network +uncertainty)
hold time Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (Slack of Path1 – R/F)
Timing path 1: PI to clock data input ¾ ¾ ¾
D
Slack at end point: AT - RT = 2-7 = -5ns Timing is not met since slack value is negative This is the critical path
Q QN
R/F 1
1 AT = 2 RT = 7
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (AT of Path2 - Rise)
Timing path 2: clock to clock data input ¾
Arrival time at end point: Dclks + Dclkn +3+1+2+1+2+1 = 15ns source clock (ideal) 0
19 20
14
5 launch edge
source clock (source +network)
AT
Next Data Why are the delay values chosen?
AT = 15 3
R1
2
R 1 2
1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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102
STA Example 2 (AT of Path2 - Fall)
Timing path 2: clock to clock data input ¾
Arrival time at end point: Dclks + Dclkn +3+1+1+1+2+1 = 14ns source clock (ideal) 0
14
5 launch edge
source clock (source +network)
AT Next Data
Why are the delay values chosen?
AT = 14 3
F1
1
F 1 2
1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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103
STA Example 2 (RT of Path2 - R/F)
Timing path 2: clock to clock data input ¾
Required time at end point: Dclks + Dclkn + Dclku + Th = 2+3+1+1 = 7ns source clock (ideal)
launch edge 0
7 target clock (ideal) target clock (source) target clock (source+network) capture edge RT
target clock (source+network +uncertainty)
hold time Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (Slack of Path2 - Rise)
Timing path 2: clock to clock data input ¾ ¾
Slack at end point: AT - RT = 15-7 = 8ns Timing is met since slack is greater than 0 AT = 15 RT = 7 3
R1
2
R 1 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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R
105
STA Example 2 (Slack of Path2 - Fall)
Timing path 2: clock to clock data input ¾ ¾
Slack at end point: AT - RT = 14-7 = 7ns Timing is met since slack is greater than 0
AT = 14 RT = 7 3
F1
1
F 1 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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R
106
STA Example 2 (AT of Path3 - Rise)
Timing path 3: clock to PO ¾
Arrival time at end point: Dclks + Dclkn +3+1+2+1= 12ns source clock (ideal) 0
5 launch edge
12 source clock (source +network)
AT Next Data
3 R
AT = 12
1
R 2 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (AT of Path3 - Fall)
Timing path 3: clock to PO ¾
Arrival time at end point: Dclks + Dclkn +1+1+1= 11ns source clock (ideal) 0
5 launch edge
11 source clock (source +network)
AT Next Data
3 F
AT = 11
1
F 1 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA Example 2 (RT of Path3 - R/F)
Timing path 3: clock to PO ¾
Required time at end point: - DY = -3ns source clock (source+ network)
launch edge -3
0
target clock (ideal) RT output delay
F
RT = -3
1
D
Q
3
F 1 Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
QN
1 109
STA Example 2 (Slack of Path3 - Rise)
Timing path 3: clock to PO ¾ ¾
Slack at end point: AT - RT = 12-(-3) = 15ns Timing is met since slack is greater than 0
AT = 12 R
RT = -3
1
R 2
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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3
1
Q QN
1
110
STA Example 2 (Slack of Path3 - Fall)
Timing path 3: clock to PO ¾ ¾
Slack at end point: AT - RT = 11-(-3) = 14ns Timing is met since slack is greater than 0
AT = 11 F
RT = -3
1
F 1
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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3
Q
1
1
111
QN
Handling Multiple Clocks
Determine the least common multiple (LCM) of the 2 clock periods first and then find the setup and hold relationship
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Setup Relationships Find the Setup Relationship between A rising to B rising The setup relationship is the closest distance between the launching clock edge (A) to the receiving clock edge (B)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Hold Relationships Find the Hold Relationship between A rising to B rising The hold relationship is the closest distance between the launching edge (A) to the previous receiving edge (B)
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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STA with Latches Latches and Flip-Flops are both registers or "storage devices“ Latches are level sensitive instead of edge triggered
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Time Borrowing Example 1 If these were flip flops, timing would not be met at b_reg With time borrowing, the middle latch can borrow time from the next stage and meet timing!
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Time Borrowing Example 2
Can time borrowing eliminate negative slack? ¾
No, the final data missed the active edge of c_reg.
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Time Borrowing Example 3
Can time borrowing eliminate negative slack? ¾
No, c_reg is a flip-flop and the data misses c_reg’s edge
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Time Borrowing Example 4
Can time borrowing eliminate negative slack? ¾
Yes! In fact there is extra time before the activating edge of c_reg
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Time Borrowing Example 5
Can time borrowing eliminate negative slack? ¾
No. The earliest b_reg can launch the data is at time 5. c_reg will receive the data too late
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Four Types of Analysis
Single operating condition analysis ¾ ¾ ¾
Worst operating condition Typical operating condition Best operating condition
Simultaneous best-case/worst-case analysis On-Chip variation Case analysis
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Single OC Analysis
Typically, you need to perform timing analysis for at least two operating conditions to ensure that the design has no timing violations ¾ ¾
Best case (minimum path report) (Hold Time Check) Worst case (maximum path report) (Setup Time Check)
CIC 0.18um library example ¾ ¾ ¾
fast.lib typical.lib slow.lib
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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Best/Worst Case Analysis
For most of STA tools, you can simultaneously perform timing analysis for the best-case and worstcase operating conditions. ¾ ¾
Max paths analyzed with worst case OC (Setup Time Check) Min paths analyzed with best case OC (Hold Time Check)
Min-max values can be also specified for ¾ ¾ ¾ ¾ ¾ ¾
SDF back-annotated delays Input and output delays Wire load models Net resistance-capacitance Clock latency/transition Driving cell
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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On -Chip Variation Analysis On-Chip Delays have uncertainty due to the variation of PVT across large dies On-chip variation allows you to account for the delay variations due to PVT changes across the die, providing more accurate delay estimates.
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Case Analysis Timing analysis with specified logic value conditions on pins or ports Logic constants are propagated to avoid unnecessary timing path analysis (3 paths in this example)
conditional combinational timing arc
3
1
F2
2
F 2 2 0
Chip Implementation Center / Design Service Division / Physical Design Section / C.S.Chen Static Timing Analysis
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F 0
125
STA in Cell -based Design Flow Cell-based
After each run of synthesis ¾ ¾
After each run of physical optimization ¾ ¾
Synopsys Physical Compiler / Synopsys Saturn Synopsys Astro / Cadence SE / Cadence SOC Encounter
After each run of P&R ¾ ¾ ¾
Synopsys Design Compiler / Cadence Ambit Magma Blast RTL / Blast Fusion
Synopsys Apollo / Astro Cadence SE / Cadence SOC Encounter Magma Blast Fusion
STA sign-off ¾
Primetime
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