Chapter 3C PIC18 Assembly Programming Part C

3.5 Register Re gister Indirect Addressing Modes in PIC18

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Outline •

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Immediate addressing mode Direct addressing mode Register Indirect addressing mode

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Immediate Addressing Mode •

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The operand is a literal constant The instruction has a !" #literal$ Can %e used in loading in&ormation and per&orming arithmetic and logic operations ONLY in the WREG r  egister  register  '(amples)  –

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mo*l+ ,(-5 load ,(-5 into /R'0 su%l+ D"-" su%tract /R'0 &rom addl+ ,(2, add /R'0 +ith ,(2, 3

Register Direct Addressing Mode •

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The operand data is in a &ile register in data memor. The address o& the &ile register is pro*ided as a part o& the instruction. '(ample)  –

mo*+& ,(2,4 A cop /R'0 into &ile reg location ,(,2,

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Destination Option in Direct Addressing Mode •

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Pro*ides an option to store the result either in /R'0 or in &ile register. '(ample)  movlw

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;[WREG] = 0

 movwf

0x20, A 

;[0x20] = 0, [WREG] = 0

incf

0x20, W, A  ;[0x20] = 0, [WREG] = 1

incf

0x20, W, A  ;[0x20] = 0, [WREG] = 1

incf

0x20, F, A  ;[0x20] = 1, [WREG] = 1

incf

0x20, F, A  ;[0x20] = 2, [WREG] = 1

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Register Indirect Addressing Mode •

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uppose ou +ant to cop *alue ,(55 to location ,(,2, to ,(,22. A &i(ed address must %e speci&ied in direct addressing mode as an operand. Thus4 using direct addressing mode4 one instruction copies to one register)  movlw  movwf  movwf  movwf  movwf  movwf

0x55 0x40, 0x41, 0x42, 0x43, 0x44,

A  A  A  A  A  6

Register Indirect Addressing Mode •

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Three registers 6no+n as file select registers  #7R(4 #7R(4 +here (  ,4 14 -$ store addresses o& the data memor location #i.e.4 pointers$. A 7R is a 1-9%it register +hich is split into t+o 89%it registers4 6no+n as 7R(! and 7R(:. To load a RAM address into a 7R4 use !7R)  –  –  –

!7R ,4 ,(,3, !7R 14 ,(,2, !7R -4 ,(,7

load 7R, +ith ,(3, load 7R1 +ith ,(2, load 7R- +ith ,(7 7

Register Indirect Addressing Mode •

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7R( is associated +ith a I;D7( register #+here (  ,4 14 -$. /hen reading &rom #+riting to$ the I;D7( register4 +e are reading &rom #+riting to$ the &ile register pointed to % the 7R '(ample) LFSR 0, 0x030  movwf '()F0

;FSR0 poin! o RA" #$$%&!! 0x30 ;cop* +& con&n of WREG ino RA" #$$%&!! 0x30

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'(amples e.g.4 /rite a program to cop the *alue ,(55 to location ,(2, ,(22 Directto Addressing Mode Indirect Addressing Mode

 movlw 0x55  movwf 0x40, A   movwf 0x41, A   movwf 0x42, A   movwf 0x43, A   movwf 0x44, A 

-.(/ & 0x00  movlw 0x05  movwf -.(/, A   movlw 0x55 LFSR 0, 0x040 Loop movwf '()F0 incf FSR0L, F $&cf! -.(/, F, A   %# %# Loop 9

Register Indirect Addressing Mode •

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Indirect addressing mode allo+s looping :o+e*er4 +e incremented onl 7R(! To deal +ith 7R(:4 +e need to use %ranching instructions conditioned on the Carr uals

to the content o& /R'0 %e&ore the mo*e operation. However, the content of FSR will not be modified 11 after o!eration "different from !revio#s three SFRs$

Pre*ious e(ample re*isited e.g.4 /rite a program to cop the *alue ,(55 to location ,(2, to & ,(220x00 -.(/  movlw 0x05  movwf -.(/, A   movlw 0x55 LFSR 0, 0x040 Loop movwf -S/'(0 $&cf! -.(/, F  %# %# Loop 12

Demonstration

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Introduce mo*&& %e&ore ne(t e(ample...

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'(ample •

Cop a %loc6 o& 5 %tes o& data &rom RAM locations starting &rom ,(,3, to RAM locations starting &rom ,(,,

-.(/ & 0x00  movlw movlw 0x05  movwf movwf -.(/, A  LSFR 0, 0x030 LSFR 1, 06070 Loop  movff -S/'(0, -S/'(1 $&cf! -.(/, F, A   %# %# Loop 15

'(ample Add the in data memor locations ,(,2,9,23 together and place the result in locations ,(,, and ,(,,? -.(/ & 0x00 L89:/E & 0x07 89:/E & 0x0< LFSR 0, 06040  movlw 0x04  movwf -.(/, A  cl%f 89:/E, A  cl%f L89:/E, A  Loop  movf -S/'(0, W, A; #$$wf L89:/E, F, A;  nc (&x incf 89:/E, F, A;  (&x $&cf! -.(/, F, A   %# %# Loop

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