Ceng355 Lab Report_1

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF VICTORIA CENG 355 – MICROPROCESSOR-BASED SYSTEMS LABORATORY REPORT

Experiment:

Project

Title:

Signal Monitoring System

Date of Experiment:

Nov 16, 2010

Report Submitted on:

November 30 , 2010

To:

Tony

Names: Ryan Key

V00482077

Cameron Smith

1

V00482018

Table of Contents Objective ......................................................................................................................................... 4 1

Design Solution ....................................................................................................................... 4 1.1

Square Wave Frequency Measurement ............................................................................ 4

1.1.1 Rising Edge Detection Using Edge Port ................................................................... 5 1.1.2 Timer Using the Programmable Interrupt Timer ...................................................... 7 1.2 Resistance Measurement .................................................................................................. 8 1.2.1 Initialization of the ADC .......................................................................................... 9 1.2.2 Displaying the Resistance ....................................................................................... 11 1.3 Saw-tooth Waveform ..................................................................................................... 12 1.3.1 External DAC.......................................................................................................... 12 1.3.2 Configuring the QSPI ............................................................................................. 13 1.4 Saw-tooth Waveform Frequency Update ....................................................................... 15 2

3

1.4.1 Detecting the Button Press ...................................................................................... 15 Discussion .............................................................................................................................. 17 2.1

Square Wave Frequency Measurement .......................................................................... 17

2.2

Resistance Measurement ................................................................................................ 18

2.3

Saw-tooth Waveform ..................................................................................................... 20

2.4

Improvements to the Saw-Tooth Waveform .................................................................. 21

Final Design Specifications Limitations and Errors .............................................................. 22 3.1

Specifications ................................................................................................................. 22

3.2

Limitations ..................................................................................................................... 23

3.3

Errors .............................................................................................................................. 23

4

Conclusions ........................................................................................................................... 24

5

References ............................................................................................................................. 24

6

Appendix ............................................................................................................................... 25 6.1

Pictures ........................................................................................................................... 25

6.2

Code ............................................................................................................................... 26

2

Table of Figures Figure 1-1 IRQ1_INIT .................................................................................................................... 5 Figure 1-2 IRQ1_handler ................................................................................................................ 6 Figure 1-3 PIT0_Init ....................................................................................................................... 7 Figure 1-4 PIT0_handler ................................................................................................................. 7 Figure 1-5 ADC Result Registers ................................................................................................... 8 Figure 1-6 ADC Initialisation Function ........................................................................................ 10 Figure 1-7 Polling In Main Function ............................................................................................ 11 Figure 1-8 External DAC Wiring ................................................................................................. 12 Figure 1-9 QSPI Initialisation Function ........................................................................................ 14 Figure 1-10 IRQ7_Init .................................................................................................................. 15 Figure 1-11 IRQ7_handler ............................................................................................................ 16 Figure 2-1 Graph of Frequency Measurements ............................................................................ 18 Figure 2-2 Graph of High and Low Resistance Measurements .................................................... 19 Figure 2-3 Graph of Saw-Tooth Frequency .................................................................................. 20 Figure 2-4 Output Filtering ........................................................................................................... 22 Figure 6-1 Lower Limit of saw-Tooth Frequency ........................................................................ 25 Figure 6-2 Upper Limit of Saw-Tooth Frequency ........................................................................ 25

Tables Table 2-1Square Wave Frequency ................................................................................................ 17 Table 2-2 Resistance Measurements ............................................................................................. 19 Table 2-3 Resistance Accuracy and Uncertainty .......................................................................... 19 Table 2-4 Saw-Tooth Frequency Predictions ............................................................................... 20

3

Objective To design and implement a system that:  

 

Measures the frequency of square wave signal from an external function generator. Measures the resistance of an on board potentiometer 5k thumb turn potentiometer via the potential difference between the reference ground and input value measured from the adjustable terminal. Generates a saw-tooth waveform using the Queued Serial Peripheral Interface (QSPI) to control a 12 bit Digital to Analog Converter (DAC). Modifies the frequency of the saw-tooth wave form as the resistance value of a 5k potentiometer on the MCU Project Board Student Learning Kit is changed

1 Design Solution 1.1 Square Wave Frequency Measurement To measure the frequency of a square wave it is necessary to detect either the rising or falling edges of the waveform. To do this the edge port was configured to detect the rising edge of the square wave signal applied to IRQ7 (PORT NQ). To determine frequency of the square wave it is necessary to measure the time between two consecutive rising edges. To do this a Programmable Interrupt Timer (PIT0) was used to count the number of internal clock cycles between the rising edges. PIT0 counted down from 0xFFFF, starting when the first edge was detected, until either the second edge was detected or the counter reached zero. If the counter reached zero an interrupt was generated. The interrupt causes an overflow counter to be incremented and the counter to restart counting down from 0xFFFF. Upon the second edge of the square wave the total number of clock cycles that occurred between the two edges was calculated. Then the square wave frequency was calculated according to the following equation: 1 𝐶𝑜𝑟𝑒 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑒𝑦 𝑆𝑞𝑢𝑎𝑟𝑒 𝑊𝑎𝑣𝑒 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑒𝑦 = 2 𝑇𝑜𝑡𝑎𝑙 𝐶𝑜𝑢𝑛𝑡

4

1.1.1 Rising Edge Detection Using Edge Port First the edge port was initialized in the function named “IRQ_Init()”. Initializing the edge port required first disabling all interrupts. Next the corresponding interrupt for pin 1 of port NQ (IRQ1) was unmasked. The priority and level were set to a value of 3 which was chosen arbitrarily as being lower than SW1 interrupt and higher than 1. The interrupt enable register was set to allow interrupts for EP0 pin1. The Data Direction Register (DDR) was marked to allow all pins on Edge port 0 to input. It is advisable to set pins as inputs even if not being used because this sets them as high impedance and reduces the risk of damage if an accidental short occurs. The edge port was set as rising edge sensitive. The ISR location in memory was marked and interrupts were re-enabled resuming regular program execution.

/* ======================================================================= * INTERRUPT CONTROLLER INITIALIZATION FUNCTION ======================================================================= */ VOID IRQ1_INIT(VOID) { MCF5XXX_IRQ_DISABLE(); //DISABLE INTERRUPTS MCF_INTC0_IMRL &=~ (MCF_INTC_IMRL_INT_MASK1|0X1); //UNMASK (IRQ1) INTERRUPT MCF_INTC0_ICR01 |= 0B00011011; //INTERRUPT LEVEL 3 PRIORITY 3 MCF_EPORT_EPIER0 = 0B00000010; //ENABLED INTERRUPT FOR EPORT0 PIN 1 MCF_EPORT_EPDDR0 = 0X0; //DATA DIRECTION (INPUT) MCF_EPORT_EPPAR0 = 0B0000000000000100; //RISING EDGE SENSITIVE MCF5XXX_SET_HANDLER(64+1,(UINT32) &IRQ1_HANDLER); //LOCATING ISR MCF5XXX_IRQ_ENABLE(); //ENABLE INTERRUPTS }

Figure 1-1 IRQ1_INIT

Next the interrupt service routine for rising edge detection was written. Upon a rising edge of the square wave signal EP0 generates an interrupt. The ISR checks if the timer is running already or not. If the timer is not already running the ISR starts the timer assuming this is the first rising edge. If the timer is already running the ISR stops the timer and adds [(0xfff) – (value of the counter)] to the overflow counter. The frequency is then calculated by dividing the reference frequency by the number of clock cycles counted. The flag for the EP0 is reset until the next rising edge occurs.

5

/* ======================================================================= * IRQ1 Handler ======================================================================= */ __interrupt__ void IRQ1_handler () { int count; int delay; mcf5xxx_irq_disable();

// Mask all IRQs

if(MCF_PIT0_PCSR & 0x0001) // Is this the first edge? { // 2nd Edge count = 0xffff-MCF_PIT0_PCNTR; // temporary variable MCF_PIT0_PCSR &=~MCF_PIT_PCSR_EN; // Disable Counter timer_pulses += count; // Calculate Total Pulses MCF_PIT0_PMR = 0xffff; // Reset the counter for(delay=1000000;delay>0;delay--){} // Delay to prevent overflow of buffer printf("Frequency = %d Hz\n\r",(int)(FREQ_Hz/timer_pulses)); // Calc & Display Frequency printf("ADC: %d ohms\n",(5000*(MCF_ADC_ADRSLT0/8)/4095)); // Calc & Display Resistance } {

// 1st Edge

else MCF_PIT0_PCSR |=MCF_PIT_PCSR_EN; timer_pulses =0;

// Start Timer // Reset the Overflow Counter

} // Clear Interrupt Flags // Un-Mask All IRQs

MCF_EPORT0_EPFR = 0xff; mcf5xxx_irq_enable(); }

Figure 1-2 IRQ1_handler

6

1.1.2 Timer Using the Programmable Interrupt Timer Configuring the programmable interrupt timer required enabling the overwrite enable bit and enabling interrupt generation when the counter reached zero. The initial value was set to the maximum of 0xFFFF. The corresponding interrupt for overflow was unmasked. The priority was set to level 2 and the location of the ISR in memory was marked.

/* ======================================================================= * Timer Initialization Function ======================================================================= */ void PIT0_Init(void) { mcf5xxx_irq_disable(); // Mask all IRQs MCF_INTC0_IMRH &=~ MCF_INTC_IMRH_INT_MASK55; MCF_INTC0_ICR55 |= 0b00010010; mcf5xxx_set_handler(64+55,(uint32) &PIT0_handler); MCF_PIT0_PCSR = 0x0 |MCF_PIT_PCSR_OVW |MCF_PIT_PCSR_PIE;

//Unmask PIT Interrupt //interrupt level 2 priority 2 // Set the location of the overflow ISR //Automatic Overwrite enable //Enable PIT interrupts //start count value at max // Un-Mask All IRQs

MCF_PIT0_PMR = 0xffff; mcf5xxx_irq_enable(); }

Figure 1-3 PIT0_Init

When the Programmable interrupt timer overflowed an interrupt was generated. Then the corresponding ISR was run which incremented the counter value by 0xFFFF. Then the interrupt flag in the PCSR for the PIT was cleared by writing a 1 to it. The PIT is already set to loop around so the timing sequence continues automatically.

/* ======================================================================= * Timer Overflow Interrupt Handler ======================================================================= */ __interrupt__ void PIT0_handler () { timer_pulses += 0xffff; // Increment Overflow Counter by 0xFFFF MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;

// Clear the Overflow Interrupt Flag by Writing 1 to it

}

Figure 1-4 PIT0_handler

7

1.2 Resistance Measurement The second objective was to measure the resistance of a 5kΩ potentiometer. This was accomplished by measuring the voltage at the wiper of the potentiometer with the processors’ 12 bit analog to digital converter. The voltage measured is proportional to the resistance between the wiper and ground (or the voltage supply). The relationship is given by: 𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 =

𝑉𝑤𝑖𝑝𝑒𝑟 𝑉𝑤𝑖𝑝𝑒𝑟 ∗ 𝑅𝑡𝑜𝑡𝑎𝑙 = ∗ 5𝑘𝛺 𝑉𝑠𝑝𝑝𝑙𝑦 3.3 𝑉𝑜𝑙𝑡𝑠

Because the analog to digital converters on the processor are 12 bit the voltage is readable as a number from 0x000 to 0xFFF corresponding to VRef_Low to VRef_High. In this program the lower reference voltage was set to 0 volts and the upper reference voltage 3.3 volts. The result from an analog to digital conversion is reported in a 16 bit result register were bits 0-2 are all zero and bits 3-14 are the result and bit 15 is the extension of the results sign where 0 indicated a positive result and 1 is negative.

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sign Extend Result 0 0 0 Figure 1-5 ADC Result Registers

Because the result reported in bits 3-14 it is shifted up by 3 bits effectively multiplying it by 8. Also because we will never have a negative number the 15th bit will always be 0. To obtain the 16 bit result the value in the 16 bit result register simply needs to be shifted down by 3 bits or equivalently divided by 8. This results in the following equation to convert the reported number to a voltage. 𝑉 = 3.3 ∗

𝑅𝑒𝑠𝑢𝑙𝑡𝑅𝑒𝑔𝑖𝑠𝑡𝑜𝑟 8 0𝑥𝐹𝐹𝐹

Then the resistance is given by the combination of the previous two equations as:

𝑅 = 3.3 𝑉𝑜𝑙𝑡𝑠 𝑅=

𝑅𝑒𝑠𝑢𝑙𝑡𝑅𝑒𝑔𝑖𝑠𝑡𝑜𝑟 8 0𝑥𝐹𝐹𝐹 ∗ 5𝑘𝛺 3.3 𝑉𝑜𝑙𝑡𝑠

𝑅𝑒𝑠𝑢𝑙𝑡𝑅𝑒𝑔𝑖𝑠𝑡𝑜𝑟 8 ∗ 5𝑘𝛺 0𝑥𝐹𝐹𝐹

8

1.2.1 Initialization of the ADC First the analog to digital converter needed to be initialized. This was accomplished by writing another dedicated initialization function. The first line of the ADC initialization function declares a new variable used by a for-loop which provides a delay to ensure the ADC successfully starts. Next the power configuration register is configured so that the ADC can be started and will not automatically power down. Next the loop sequential mode of operation was selected. Then the ADC clock was set by setting the system clock divider such that the ADC operated at less than 5 MHz. Then zero crossing detection was disabled as we do not need it. Next the sampling order was selected such that AN0, then AN1, AN2, …,AN7 were sampled in order. All samples above AN1 were disabled as we only needed to sample 2 different analog voltages. Next the lower limits and higher limits were set to the minimum and maximum values, effectively disabling them. Then the offset was set to zero for both ADCs. The calibration register was set to zero because the standard high and low reference voltages were used. Then a delay was added because there must be a delay after power up before the ADCs can be started. We found that at the low clock frequency of the boards in the lab this delay was not necessary. However if the clock frequency was increased, or there were less operations between the modification of the power register and the starting of the ADCs this delay would be necessary. An alternative is to poll the status bits in the power register until the ADCs are powered up before starting the first scan.

9

/* ======================================================================= * ADC Initialization ======================================================================= */ void ADC_init() { int n=0; MCF_GPIO_PANPAR = 0xFF; //sets port AN to primary function (ADC) MCF_ADC_POWER = 0b0000000011010100; //turns on the ADC and prevents auto power down MCF_ADC_CTRL1 = 0b0000000000000010; //loop sequential everything else disabled MCF_ADC_CTRL2 = 0b0000000000000100; //set divisor system clock/2(4+1) MCF_ADC_ADZCC = 0; //zero crossing disabled MCF_ADC_ADLST1 = 0b0011001000010000; //sampling each input value in order MCF_ADC_ADLST2 = 0b0111011001010100; //same thing for converter b MCF_ADC_ADSDIS = 0x0004; // Disable AN2…AN7 MCF_ADC_ADLLMT0 = 0; //lower limits=0 MCF_ADC_ADLLMT1 = 0; // MCF_ADC_ADHLMT0 = 0x7FF8; //higher limits = max MCF_ADC_ADHLMT1 = 0x7FF8; // MCF_ADC_ADOFS0 = 0; //offset to 0 MCF_ADC_ADOFS1 = 0; //ditto MCF_ADC_CAL = 0; //used Vref low and Vref high For(n=0;n