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Design for Testabilit Testability y and Built--I n S Built Sel Se elf l f --Te T Test est
Jin-Fu Li . Department of Electrical Engineering Jungli, Taiwan
Outline
Basics Design-for-Testability Design-for-Testability (DFT) Techniques
Ad Hoc DFT Structural Methods
Partial Scan BIST Boundary Scan Syndrome-Testable Design C-Tes esttable Des esii n
Built-In Self-Test (BIST) Techniques
Signature Analysis Pseudorandom Pattern Generator (PRPG) Built-In Logic Block Observer (BILBO)
ummary Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
2
Outline
Basics Design-for-Testability Design-for-Testability (DFT) Techniques
Ad Hoc DFT Structural Methods
Partial Scan BIST Boundary Scan Syndrome-Testable Design C-Tes esttable Des esii n
Built-In Self-Test (BIST) Techniques
Signature Analysis Pseudorandom Pattern Generator (PRPG) Built-In Logic Block Observer (BILBO)
ummary Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
2
Definitions
Definition
A fault is t e s t a b l e if there exists a well-specified , a reasonable cost using current technologies. A circuit is t e st s t a b l e w i t h r e sp s p e ct c t t o a f a u l t s et et w en eac an every au n s se s es a e
Definition design techniques that make test generation and test application cost-effective
Electronic systems contain three types of components: (a) digital logic, (b) memory , In this chapter, we discuss DFT techniques for
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
3
Ad Hoc DFT Guidelin es
Partition large circuits into smaller subcircuits to reduce test eneration cost usin MUXed and/or scan chains) T1 T2
1
1 0
C1
C2
Normal Test C1
0 0
2
0 1
1
0
0
1
Advanced Reliable Systems (ARES) Lab.
1
Jin-Fu Li, EE, NCU
0
4
Ad Hoc DFT Guidelin es
Insert test points to enhance controllability & observabilit
Test points: control points & observation points OP
C1 C2 CP1
CP2
Advanced Reliable Systems (ARES) Lab.
CP3
Jin-Fu Li, EE, NCU
C2
1
CP4
5
Ad Hoc DFT Guidelin es
Design circuits to be easily initializable
Partition large counter into smaller ones
Keep analog and digital circuits physically
Avoid the use of asynchronous logic Consi er tester requirements pin imitation, etc) Etc
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
6
Scan Design A pproaches
They are effective for circuit partitioning of internal state variables for testing combinational one
Shift-register modification
Level-sensitive scan design (LSSD)
Circuit is designed using pre-specified design .
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
7
Scan Design A pproaches
Consider a representation of sequential circuits (primary inputs)
(primary outputs)
Combinational Logic Y (next state)
(present state) y
clk
state
To make elements of state vector controllable ,
A TEST mode pin (T) A SCAN-OUT pin (SO) A MUX switch in front of each FF M
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
8
Ad ding Scan Structure
Combinational
SFF
logic
SFF
SCAN-OUT
SFF
T SCAN-IN Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
9
Scan Test Generation & Design Ru les
Test pattern generation
testable faults in the combinational logic Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test
Scan design rules
Use only clocked D-type of flip-flops for all state variables eas one p n mus e ava a e or es ; more pins, if available, can be used
Clocks must not feed data inputs of flip-flops
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Jin-Fu Li, EE, NCU
10
Correcting a R ule Vio lation
All clocks must be controlled from PIs Comb. l o g i c D1
Q .
D2
logic
CK
Comb. logic D1 FF
D2 CK Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
Comb. logic
11
Correcting a R ule Vio lation
Adding a scan FF and a mux allows a feedback loop to be opened for testing A 1
FF
T
Test
CK
CK
B
0
0
1
Testing derived clocks requires the use of a mux to b ass the division sta es Fre . Divider
FF
CK
Freq. Divider
FF
Test
FF
Advanced Reliable Systems (ARES) Lab.
1
Jin-Fu Li, EE, NCU
FF
12
Correcting a R ule Vio lation
The AND gates keep the bus drivers from being activated by the normal logic during testing
FF
FF
Test
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Jin-Fu Li, EE, NCU
13
Scan Test P rocedure
Step 1: Switch to the shift-register mode and check the SR o eration b shiftin in an alternating sequence of 1s and 0s, e.g., 00110 (functional test) Step 2: Initialize the SR---load the first pattern Step 3: Return to the normal mode and apply the test pattern Step 4: Switch to the SR mode and shift out the final state while setting the starting state for the next test. Go to Step 3
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
14
Combining Test Vectors
I1
I2
SCAN-IN T
O1 Combinational
logic Next s a e
Presen t state
Advanced Reliable Systems (ARES) Lab.
O2
Jin-Fu Li, EE, NCU
15
Combining Test Vectors
SCAN-IN
I2
I1
PI
S1
S2
T
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
PO
O1
SCAN-OUT
Do n ’t c a r e or random bits
1 0 0 0 0 0 0 0
O2
N2
N1
Se q u e n c e l e n g t h = (n c o m b + 1 ) n s f f + n c o m b c l o c k p e ri o ds n c o m b = n u m b e r of c o m b i n a t i o n a l ve c t o r s n s f f = n u m e r o s c a n Advanced Reliable Systems (ARES) Lab.
p- ops
Jin-Fu Li, EE, NCU
16
Testing Scan Reg ister
Scan register must be tested prior to
A shift sequence 00110011 . . . of length = , s 11 and 10 transitions in all flip-flops and observes the result at SCAN-OUT out ut Total scan test length: n +2 n +n +4 clock eriods Example: 2,000 scan flip-flops, 500 comb. 6 ~ Multiple scan registers reduce test length
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
,
17
M ultiple Scan Registers
Scan flip-flops can be distributed among any number of shift registers, each having a separate SCAN-IN and SCAN-OUT pin Test sequence length is determined by the longest scan shift register Just one test control (TC) pin is essential T -
SCAN-IN1
SCAN-INK
can
eg s er
-
Scan Register 2
SCAN-OUT2
Scan Register 3
SCAN-OUTK
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
18
Hierarchical Scan
Scan flip-flops are chained within subnetworks before chaining subnetworks Advantages:
Automatic scan insertion in netlist Circuit hierarchy preserved – helps in debugging and design changes
Disadvantage: Non-optimum chip layout SFF4
SFF1
Scanin
SFF1
SFF3
Scanout SFF2
SFF3
SFF4
SFF2
a Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
ayou 19
Optimum Scan Layout X’
X
pad
SFF cell SCANIN
pflop cell Y’
T
SCAN OUT
Routing channels Interconnects Active areas: XY and X’Y’ Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
20
Au tomated Scan Design Behav ior, RTL, and lo gic De s i g n a n d ve r i f i c a t i o n
Rule v o a ons Sc a n d e s i g n r u l e a u di t s
netlist Co m b i n at i o n a l
Sc a n h a r d w a r e
Combinational vectors c a n s eq u e nc e and t est program generation
Te s t p r o g r a m
Advanced Reliable Systems (ARES) Lab.
Scan netlist Sc a n c h a i n o r d e r
es gn an es data for manufacturing
Jin-Fu Li, EE, NCU
p a yo u : c a nc h a i n o p t i m i za t i o n , t i m i n g ve r i f i c a t i o n
M a sk d at a
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An Example of DFT Compiler Flow compile -scan
check _test
ScanReady Synthesis
Constraints: Scan style, s eed area
Pre-Scan DRC
insert_scan
check _test
Insert Scan
Post-Scan DRC
Technology Library: Gates, flip-flops, scan equivalents
Preview Covera e
Constraint-Based Scan Synthesis: Routing, balancing, gate-level optimization
Source: H.-J. Huang, CIC Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
22
Shift Registers Scan added: SHFT_IN SI
SHFT_OUT/ SO
DFF
DFF
DFF
CLK SE
Revised:
SHIFT_OUT
SHIFT_IN
DFF
SI SE
DFF
DFF
CLK
Source: H.-J. Huang, CIC Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
23
Lockup Latch I nsertion
F1
F2
CLK_RTZ_1
F3
latch
CLK_RTZ_2
tINV
clk1
clk1
clk2
clk2
OK!
Rearrange clock domain or insert lockup latch Source: H.-J. Huang, CIC
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
24
Rand om A ccess Scan
Uses addressable latches multiplexing—address selection
C SI L
L
L
L
SO
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
25
Rand om A ccess Scan
Random access scan cell DI
C=CK1&CK2
SI
+L
CK2 SO
Advantages
as ; m n ma mpac on norma pa Fast for testing—random access ‘
’
Disadvantages ar ware cos
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s arge; more p ns a Jin-Fu Li, EE, NCU
e 26
Random Access Architecture Combinational/Logic
clocks and controls y-address
Y decode r
Si Addressable storage .. . elements
Sin Sout
... X decoder x-address
During normal operation the storage cells operate in their arallel-load mode To scan in a bit, the appropriate cell is addressed,
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
27
Test P rocedure 1. Set test input to all test points . elements . , clock . in . 6.Check states of the output points 7.Read the scan-out states of all memory elements by applying appropriate X-Y signals Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
28
Scan-Hold FFs (SHFFs)
HOLD=0Q & Q’ are fixed SO D Q
SI TC
SFF Q
HOLD
The control input HOLD keeps the output steady at previous state of flip-flop Applications
Reduce power dissipation during scan, etc.
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
29
Scan Enters the N anom eter Era Trend
in flip flop count with design size
[Source: EE Times]
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
30
Scan Enters the N anom eter Era Adaptive
scan architecture
ource: Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
mes 31
Syndrome-Testable Desig n
Definition
function f
S ( f ) ≡
k ( f )
The syndrome of a Boolean is , n where k is the number of 1s (minterms) in and n is the number of independent input variables (Counter) ompara or
register
Exhaustive patterns
Go/No-go Reference
0 ≤ S ( f ) ≤ 1
A circuit is s ndrome testable iff ∀ fault α S ( f ) ≠ S ( f ) Syndromes of logic gates α
Gate
ANDn
S
1 / 2 n
Advanced Reliable Systems (ARES) Lab.
ORn 1 − (1 / 2 n ) Jin-Fu Li, EE, NCU
XORn 1 / 2
NOT
1 / 2 32
Syndrome Computation
Consider a circuit having 2 blocks, f and g, with unshared in uts OR
O/P Gate
AND
S + Sg − S Sg
S Sg
XOR
NAND
S + S g − 2 S S g 1 − S Sg
NOR
1− S − Sg + S Sg
Example
S1 S2
S S4
S3 Advanced Reliable Systems (ARES) Lab.
= = S2 = 1-1/4 = 3/4 S3 = 1/8 S4 = 1- S2 - S3 + S2S3 = 7/32 S = S1S4 = 21/128 1
Jin-Fu Li, EE, NCU
33
Syndr yndrom omee-Testable Testable Desig n
Consider the function f = xz + y z . The circuit is
S f = 1 / 2 If the circuit has a fault α ≡ z / 0 then the corresponding syndrome of the faulty circuit is S f ' =1 / 2 Thus the circuit is syndrome untestable
A realization C of a function f is f is said to be syndrome-testable syndrome-testable if no single stuck-at fault causes the circuit to have the same syndrome as the fault-free circuit Syndrome is a property of f u n c t i o n , not of implementation
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
34
Syndr yndrom omee-Testable Testable Desig n
Definition
A lo ic function is u n a t e in a v var aria iabl ble e x if it ca can n be be represented as an SOP or POS expression in which the variable xi appears either only in an form
f ( x1 , x 2 ) = x1 x 2 + x1 x 2 no unate f ( x1, x2 , x3 ) = x1 x2 + x2 x3 + x1x3 unate in x2 , x3 , not unate in x1
Theorem
A 2-level irredundant circuit realizing a unate function in all its variables is syndrome testable
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
35
Syndr yndrom omee-Testable Testable Desig n
Theorem
An 2-le 2-leve vell irre irredu dund ndan antt circu circuit it can can be be made made syndrome-testable by adding control inputs to the AND gates
For example The function f = xz + y z is syndrome untestable Now add a control input c ∋ f = cxz + y z , where 1 when in normal operation mode C ≡ norma p w en n es mo e S ′ = 3 / 8, f ′ = y , and S ′ = 1 / 2 ≠ S ′ Syndrome testable
α
α
r w
Only for combinational logic
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36
Easily Testable Circuits
Regularly structured circuits consists of an array of identical cells
They may be arranged in one-, two- or threedimensional arrays
(i, j ) i −1
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37
I terative Logic Ar rays
Combinational regular structures are usually referred to as iterative logic arrays (ILAs) For example
N-bit comparators are often organized in a onedimension array and each compares the corresponding bit from two numbers realized with a two-input XOR
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
38
C-Testability
Definition
A C - t e s t a b l e array is an array testable with cons an num er o es pa erns n epen en o size of the array ,
=
,
O
,
,
where f : Σ → Δ is the cell function and
e
I
Σ = {0,1}
,
Definition ,
1
1
2
,
2
,
,
1
1
2
,
2
If a function is injective and Σ= Δ , then the function is b i j e c t i v e .
Theorem
A k -dimensional ILA with a bijective cell function is C-testable
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
39
.
Design for C-Testability
A 2’complement array multiplier a
c b
s
sˆ aˆ
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Jin-Fu Li, EE, NCU
cˆ
40
Design for C-Testability
Modified the multiplier such that the inputs of the AND ate can be full controlled z
a
c
b
w
b
sˆ aˆ
s
cˆ
Advanced Reliable Systems (ARES) Lab.
sˆ aˆ
Jin-Fu Li, EE, NCU
bˆ cˆ 41
Design for C-Testability Truth table of the multiplier cell
Truth table of the modified multiplier cell
aˆ b sˆ cˆ
a
z
s c
aˆ b sˆ cˆ
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 0 0 1 1
0 1 0 1 0 1
0 0 0 0 0 0
0 0 1 1 1 1
1 0 0 1 1 0
0 1 0 0 0 1
0 0 0 0 0 0
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
0 0 0 0 0 0
0 0 1 1 1 1
1 0 0 1 1 0
0 1 0 1 0 1
0 1 1 0 0 1
1 0 1 0 1 0
1 1 1 1 1 1
0 0 0 1 1 1
1 1 0 1 0 0
0 0 1 0 1 1
1 1 1 1 1 1
0 0 0 1 1 1
0 1 1 0 0 1
1 0 1 0 1 0
1 1 1 1 1 1
0 0 0 1 1 1
1 1 0 1 0 0
1 0 1 0 1 0
s c
a
z
0
0
0
0 0 0 0 0 0
0 0 1 1 1 1
1 1 1 1 1 1
0 0 0 1 1 1
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
42
Test P attern App lication Test
application
I J are all ossible combinations Thus we only need apply (I i,Ji), the array can be tested regardless of the array size
J 3
J 2
J 1 I 2
I
1
J 3
J 2
I
I 3
Advanced Reliable Systems (ARES) Lab.
I 3
,
J 4
I 4
J 3
J 4
J 4
J 5
I 4
I
I 5
Jin-Fu Li, EE, NCU
I 5
J 5
I 6
J 6
43
I ntrodu ction to Built-I n Self-Test
Built-in self-test (BIST):
The capability of a circuit (chip/board/system) to test itself
Advantages of BIST r
r
-
r
y
increased Com ressed res onse evaluated on-chi observability increased Test can be on-line (concurrent) or off-line shorter test time; easier delay testing External test e ui ment reatl sim lified or even totally eliminated Easily adopting to engineering changes
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
44
I ntrodu ction to Built-I n Self-Test
On-line BIST
Concurrent EDAC NMR totall self-checkin checkers, etc.):
Coding or modular redundancy techniques (fault Module 1 Module 2
Module N
Voter
Output
N-Modular Redundancy (NMR)
Instantaneous correction of errors caused by
Nonconcurrent (diagnostic routines):
Carried out while a s stem is in an idle state
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
45
I ntrodu ction to Built-I n Self-Test
Off-line BIST
A typical BIST architecture Function al Circuit rcu n er es
-
BIST
Prestored TPG, e.g., ROM or shift register Exhaustive TPG, e.g., binary counter Pseudo-exhaustive TPG, e.g., constant-weight counter, combined LFSR and SR seu o-ran om pa ern genera or, e.g.,
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
46
I ntrodu ction to Built-I n Self-Test
Response analysis
Check-sum Ones counting Transition counting ar y c ec ng Syndrome analysis .
Linear feedback shift register (LFSR) can be
We need a gold unit to generate the good
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Jin-Fu Li, EE, NCU
47
Signature An alysis
A compression technique based on the concept of cyclic redundancy checking (CRC) and rea ze n ar ware us ng near ee ac shift registers De inition
A function f(x1,x2,…,xn) is said to be linear if it can
f = a 0 ⊕ a1 x1 ⊕ a 2 x 2 ⊕ ⊕ a n x n a ∈ 0 1 ∀i = 0 1 n
There are 2n+1 linear functions of n variables Linear operations: modulo addition, module scalar multiplication, & delay Nonlinear operations: AND, OR, NAND, NOR, etc.
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
48
Linear F eedback Shift R egister
Definition
A linear feedback shift register is a shift register with feedback paths which consist only of unit delays and XOR operators
Let M=fault-free circuit response, B=faulty circuit response, and E=error syndrome amm ng , w ere = ⊕ us = ⊕ and B=M ⊕ E
e nee a c rcu o a e as npu an compact it but still be able to tell if M!=B
s cons ere as a popu ar approac test response compaction Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
or
49
Structures of LFSR
Two types of generic standard LFSRs
C1
D FF
C2
CN-1
D FF
D FF
Y1
Y2
C1
D FF
C2
YN-1
Advanced Reliable Systems (ARES) Lab.
YN
CN-1
D FF Y1
CN
CN
D FF Y2 Jin-Fu Li, EE, NCU
YN-1
YN 50
M athematical Foun dation of LFSR
As a function of time, Y j can be expressed as Y j ( t ) = Y j −1 ( t − 1) for j ≠ 0 ence
=
0
−
If we denote the translation operator as Xk, w ere s e me rans a on un
Y j ( t ) = Y 0 ( t ) X j
n
j
an ,
0
can
e expresse
as
Y 0 (t ) = ∑ C jY j (t )
T en
e o N er =
N
Y 0 (t ) = ∑ C jY 0 (t ) X j for 1 ≤ j ≤ N =
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
51
M athematical Foun dation of LFSR
We can rewrite the Y0(t) as N
Y 0 (t ) = Y 0 (t )
C j X j =1 N
,
=
j
0 j = 1
0
N
=
For nontrivial solution, Y 0 (t ) ≠ 0, we must have N
= N
where P N ( X ) = 1 + ∑ C j X j =
P N ( X )
is called the characteristic polynomial of
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
52
LFSR for Signature A nalysis
A serial input stream mn, mn-1,…, m1, m0 entering the LFSR can be considered as the coe c en s o a po ynom a
n
m ( X ) = mn X + mn −1 X
C0
C1
D FF
n −1
+ + m1 X + m0
C2
Cr-1
D FF s1
Cr
D FF s2
sr-1
X sr
defined as follows r r −1 c ( X ) = cr X + cr −1 X + + c1 X + c0 Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
53
LFSR for Signature A nalysis
Assume that the initial state of the LFSR is Di=0, i=0,…,r-1, then the LFSR effectively v es any m yc , .e.,
m ( X ) = q ( X ) • C ( X ) + s ( X )
T e quotient q X appears seria y at t e output of the SR. The remainder s(X) is in the r :
r
s ( X ) = sr X + sr −1 X
Advanced Reliable Systems (ARES) Lab.
r −1
+ + s1 X + s0
Jin-Fu Li, EE, NCU
54
An Example
m(X)
The following LFSR divides any m(X) by c(X)=X5+X4+X2+1
1
0
3
2
= q(X)=X2+1, and s(X)=X4+X2 0
10101111 101 10 1 Advanced Reliable Systems (ARES) Lab.
0 0 0 0 0
1
0 1 0 0 0
2
0 1 0 0 1
3
0 1 1 0 0
Jin-Fu Li, EE, NCU
3
q(X)
,
4
0 1 0 1 1
1 01 101 55
Signature An alysis
Let m(X) be the input polynomial of degree k-1, q(X) the quotient, and s(X) the signature (remainder).
m(X)=q(X)c(X)+s(X)
polynomial e(X) 3 = 4 input b(X)=X3+X+1(01011), then the error syndrome is 11001 ⊕ 01011=10010, and is represen e ye = In general, an erroneous input polynomial can be
B(X)=m(X)+e(X)
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
56
Signature An alysis
Theorem1: Input streams m(X) and b(X) have the same signature iff e(X) is a multiple of c(X) the same signature, i.e., b(x)=q’(X)c(X)+s(X). Since m(X)=q(X)c(X)+s(X), we obtain e =m + =c q -q
Theorem2: Undetected errors correspond to error
Theorem3: If c(X) has 2 or more nonzero coefficients— i.e. at least 1 feedback term— then it can detect all single-bit errors
Proof: all nonzero multiples of c(X) must have at least 2 nonzero coe c en s. ere ore, any error w on y nonzero coefficient cannot be a multiple of c(X) and must be detectable.
Advanced Reliable Systems (ARES) Lab.
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57
Aliasing P robability
Theorem4: for a k-bit response sequence, if all possible error patterns are equally likely, then the r y rr r . ., aliasing probability) by the LFSR of length r is k − r
Pal =
2 k − 1 Proof: For a k-bit res onse de m X =k-1 and deg(e(X))>rP ~1 2r
Advanced Reliable Systems (ARES) Lab.
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58
M ultiple-I npu t Signature Register
The structure of multiple-input signature register (MISR)
D FF
Cr
Dr-2
D1
D0
Dr-1
D FF
Cr-1
D FF
C2
C1
The mathematical theory is a direct extension of the results shown above For equally likely error patterns and long data streams, the aliasing probability for an MISR of r P ≈ 1 / 2r . al
Advanced Reliable Systems (ARES) Lab.
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59
Response Compaction
Usually, we think of data compression as a process that preserves data integrity. This is why we given more attention here to data compaction, which may result in some losses
Parity testing
Transition counting
Signature analysis
Advanced Reliable Systems (ARES) Lab.
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60
P arity Testing
This is the simplest of all techniques but also the most lossy The parity of responses to the test patterns is calculated as i = L , i i =1 i the response for the ith test pattern pattern i and the partial product Pi-1 is illustrated as below
Test Patterns Advanced Reliable Systems (ARES) Lab.
CUT
r i
Pi −1
Jin-Fu Li, EE, NCU
D FF 61
One Counting
The number of 1’s in the response stream is calculated and compared to the number of 1’s in the u -r r Consider the circuit shown below a b
11110000
11000000 11101010
c
f
10101010
is m, the possibility of aliasing is [C(L,m)-1] patterns out of a total number of ossible strin s of len th L, (2L-1)
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
62
Transition Coun ting
In transition counting compaction, it is only the number of transition 01 and 10 that are counted. u ur v y i = L−1 ∑i =1 r i ⊕ r i +1 , where the summation is ordinary
The compaction scheme is shown below
r i Test Patterns
Advanced Reliable Systems (ARES) Lab.
CUT
D FF
Jin-Fu Li, EE, NCU
r i −1
63
P seudorandom P attern Generator
Logic BIST uses mostly pseudorandom (PR) tests. They are usually much longer than deterministic , u r y y r PR tests are generated using a LFSR or cellular By means of a simple circuit called an autonomous linear feedback shift re ister ALFSR Definition: an ALFSR is a LFSR with no external inputs Faults that are hard to detect with PR tests are called random pattern resistant faults
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
64
P seudorandom P attern Generator (P RP G)
Example: the following ALFSR generates the pseudorandom sequence shown in the table below
Q1
Q2
Q3
output
Q4
State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15=0
Q1
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
1
Q2
0
1
1
1
1
0
1
0
1
1
0
0
1
0
0
0
Q3
0
0
1
1
1
1
0
1
0
1
1
0
0
1
0
0
Q4
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
0
The output sequence is 000111101011001, which repeats after 15(2n-1) clocks Max period for an n-stage ALFSR=2n-1 All-0 state of the register cannot occur in the max-length cycle
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
65
M athematical Foundation of P RP G
A generic structure of ALFSR
C1
a
Q1
a
C2
Q2 −
a
Cn-2
Cn-1
Qn-1 −
am−n
Cn
Qn
a
−
A sequence of bits {am}=a0,a1,…,am,… can be associated with a polynomial—its g e n e r a t i o n f u n ct i o n : ∞
G ( X ) ≡ a0 + a1 X + + am X m + = ∑m =0 am X m
n e a ove gure, assume a e curren s a e o am-i, i=1,2,…,n, and the initial state of Qi is a-i=0, n i=1,2,…,n, but a-n=1, then am = = ci am−i
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
i
66
s
M athematical Foundation of P RP G G ( X ) =
∑
∞
m
a m X m =0
∞
=
n
∑ (∑ m =0
c i a m − i ) X
∑
=
i =1
c i X
∑
a m − i X
m −i
m =0
∞
i
c i X [ a − i X
−i
+ + a − 1 X
−1
+
i =1
∑
a m − i X
m −i
]
m =i ∞
n
=
∑
i
i =1
n
=
∞
n
m
c i X [ a − i X
−
+ + a − 1 X
−
+
i =1
a m X
m
]
m =0
n −i
i
=
−1
−
−
i =1 n
n i
= i =1
∑
−i
+ + a − 1 X
−1
)
i c i X ( a − i X
−i
+ + a − 1 X
−1
)
i =1
n
⇒ 1+
c i X ( a − i X
i
c i X G ( X ) + n
i
c i X G ( X ) =
i =1
i =1 n
⇒ G ( X ) =
∑
∑i
i
c i X ( a − i X =1
−i
n i =1
Advanced Reliable Systems (ARES) Lab.
+ + a − 1 X
−1
)
i i
Jin-Fu Li, EE, NCU
67
M athematical Foundation of P RP G
n
Now c( X ) = 1 + ∑i =1 ci X i is the characteristic polynomial of the LFSR as defined above. Since a -1=0, i=1,2,…,n-1, , -n G ( X ) =
∞
1
c ( X )
=
∑
m
a m X
m =0
,
m
to be p 1 0
c ( X )
1
p − 1 p − 1
p
+ X ( a 0 + a 1 X + + a p −1 X + X
2 p
( a 0 + a 1 X + + a
p −1
)
X p −1 )
−1
+
= ( a 0 + a 1 X + + a p −1 X = ∴
1 − X p c ( X )
= a
0
1
)( 1 + X p + X 2 p + )
p − 1 p − 1
1 − X p
+ a X + + a p − X
Advanced Reliable Systems (ARES) Lab.
p − 1
p −1
. .,
Jin-Fu Li, EE, NCU
-
p
68
Theorems
Theorem: If the initial state of an n-stage LFSR is a-i=0, i=1,2,…,n-1, and a-n=1, then the LFSR sequence {am} s per o c w a per o a s e sma es n eger p for which c(X) divides 1-Xp
= nFor a given n, we want to find a c(X) that maximizes p
Definition: The sequences produced by max-length LFSRs are called pseudorandom sequences or msequences. The characteristic polynomial associated . An irreducible polynomial is one that cannot be factored
Pseudorandom sequences (or m-sequences) are not really random since they are produced by a fixed circuit.
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
69
Theorems
Theorem: An irreducible polynomial c(X) satisfies the following 2 conditions:
as an o num er o erms nc u ng e cons an term If its de ree n>3 then c X must divide 1+Xp where p=2n-1
Theorem: A primitive polynomial is irreducible if the v r w y to divide evenly into 1+Xp occurs for p=2n-1, where n is the de ree of the ol nomial
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
70
Built-I n-Logic-Block-Observer (BI LBO)
A BILBO is a multi-purpose test module which serves as a test generator or a signature analyzer. It is for shift and feedback operation
B1 B2 SI 0
D
1
D
D
B1 B2
Function
0 1 0 1
All FFs are reset Behaves as separate latches—normal mode A linear shift register—SR mode MISR/PRPG—test mode
1 1 0 0
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
D
71
STUM P S Architecture
Logic BIST with STUMPS architecture PRPG
PIs es control signal
CUT
B S R
POs
MISR
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
72
Summary
Design-for-testability techniques
Ad-hoc techni ues Scan LSSD Random access scan Syndrome-testable C-testability
Scan is a popular DFT technique in modern IC design DFT can increase the controllability and observability of the circuit under test
Advanced Reliable Systems (ARES) Lab.
Jin-Fu Li, EE, NCU
73
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