Berido Op Layout

Mindanao State University- Iligan Institute of Technology EE 270: VLSI Technology

Operational Amplifier (LAYOUT #2)

Rovil S. Berido MSEE-Microelectronics I ID #: 2014-7835 Submission Date: May 2016 Location: /home/rovil_berido/TSMC/TSMC018UM/ /home/rovil_berido/TSMC/TSMC018UM/OP_2016/Op_SPECI OP_2016/Op_SPECIAL_x  AL_x 

INTRODUCTION

In this project, a Miller transconductance operational amplifier (Miller OTA) was designed and implemented using TSMC 0.18um technology. The design and implementation was carried out with Synopsys tool. The Miller OTA was designed for a load capacitance of 10pF.Pre-simulation 10pF.Pre-simulation and post-simulation results for gain, gain bandwidth, phase margin, CMRR, PSRR and slew rate in TT, SS and FF corners is presented in this report. Also attached are the waveforms for each of the simulation results. Parameter Gain Load Capacitance Gain Bandwidth Phase Margin  Transistor Length Slew Rate

Value At least 10 pF At least At least 1 um At least

10,000 (equivalent to 80 dB) 15 MHz for the given load C 60 degrees for the given load C 10 V/us

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PROCEDURE

 Taking into consideration the parasitic capacitances capacitance s that may degrade the frequency response of the design, in the calculation, the following specifications were used.

Parameter

Value

Remarks

Gain

At least 15,000 (equivalent to 84 dB)

1.5 times the original

Load Capacitance

10 pF

---

Gain Bandwidth

At least 20 MHz for the given load C

1.3 times the original

Phase Margin

At least 65 degrees for the given given load C

1.1 times the original

1 um

---

At least 15 V/us

1.5 times the original

 Transistor Length Slew Rate

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PROCEDURE CONT CONT..

 Transistor sizes were determined using a combination of hand calculation and characterization using the Synopsys tool. All transistors except for transistors used in the current reference are uniformly sized with W/L (width to length ratio) of 2.5um/1um. Only the multiple values are varied. In the current reference, W/L used are: 2.5um/1um; 2.5um/6um and 2.5um/ 16um.

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SCHEMATIC

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SCHEMATIC , IREF

BERIDO, ROVIL S. | OP-AMP LAYOUT

FLOORPLAN

M6 Compensation

M3/m

Compensation

4

4

Capacitor

R

R

M3/m

Capacitor

M1/M2

Current Reference

M7

M5/M8

DUMMY 

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M7

IMPLEMENTATION

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IMPLEMENTATION

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Constant Gm Iref

TESTBENCH CMRR

Gain, Gain Bandwidth and Phase Margin

acm=0

SlewRate

acm=1

acm=1

PSRR

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acm=1

PRE-SIM RESUL RESULTS: TS: Gain, Gain Bandwidth and Phase Margin

P R E S I M R E S U L T S

Gain=84.6 dB Gain Bandwidth=21.5 MHz Phase Margin=67 degrees

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PRE-SIM RESUL RESULTS: TS: CMRR

P R E CMRR=90.4 dB

S I M PRE-SIM RESULTS: PSRR

R E S U L T S

PSRR=87.7 dB

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PRE-SIM RESUL RESULTS: TS: SLEW RATE

P R E S I M

SLEW RATE=15.4V/us

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R E S U L T S

POST-SIM RESULTS: Gain, Gain Bandwidth and Phase Margin

P O S T S I M R E S U L T S

Gain=84.7 dB Gain Bandwidth=14 MHz Phase Margin=70.1degrees

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POST-SIM RESULTS: CMRR RESULTS: CMRR

P O S T

CMRR=90.4 dB

S I M POST-SIM RESULTS: PSRR

R E S U L T S

PSRR=88.4 dB

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POST-SIM RESULTS: SLEW RATE

P O S T S I M

SLEW RATE=10.5V/us

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R E S U L T S

SUMMARY OF RESULTS RESULTS

TT Parameter Gain (dB) Gain Bandwidth (MHz) Phase Margin (Degrees)

CMRR (dB) PSRR (dB) Slew Rate (V/us)

 Target 80 15 60 ----10

Pre 84.6 21.5 67 90.4 87.7 15.4

Post 84.7 14 80 90.4 88.4 10.5

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SS Pre 84.9 19.6 68 90.5 88 11.9

FF Post 84.9 13.2 82 90.4 88.5 9.47

Pre 79.4 27 63 85.8 82.9 17.4

Post 79.7 16.7 76 86.1 83.7 13.9