Bao Cao Lab1

Lab 1 – Cấu trúc máy tính

MIPS_Register File

LAB 1 : MIPS 32 by 32 REGISTER FILE 1. Yêu cầu thiết kế: - Thiết kế 1 bộ MIPS 32 by 32 Register dùng Verilog HDL. - Yêu cầu: + Dùng cấu trúc lệnh structural + Các cổng logic không được quá 4 ngõ vào + Delay 50ps 2. Giới thiệu file thanh ghi: Cấu tạo 1 file thanh ghi bao gồm: + 32 thanh ghi 32 bit, riêng thanh ghi đầu tiên( Reg0) thì luôn mang giá trị 0. + Có 2 ngõ vào chọn thanh ghi đọc (Read Register 1 và Read Register 2) và 2 ngõ ra dữ liệu (Read Data 1 và Dead Data 2) khi đọc file thanh ghi + Có 1 ngõ vào chọn thanh ghi để ghi dữ liệu (Write register) , 1 ngõ vào cho phép ghi (RegWrite) và1 ngõ vào dữ liệu (Write Data) khi ghi vào file thanh ghi.

Sơ đồ khối:

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

Sơ đồ chi tiết:

3. Nội dung thiết kế: - Từ sơ đồ chi tiết cho thấy, thiết kế 1 file thanh ghi yêu cầu: + 32 thanh ghi được cấu tạo từ các DFF + 1 bộ giải mã 5:12 điều khiển ghi dữ liệu + 2 bộ multiplexor 32x32 to 32

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MIPS_Register File

3.1 Thiết kế bộ giải mã 5:12 - Yêu cầu của khối mạch cần thiết kế là xuất ra tín hiệu điều khiển ghi dữ liệu vào các thanh ghi, với đầu vào là 5 bits để chọn thanh ghi, và tín hiệu điều khiển ghi RegWrite. - Để thiết kế bộ giải mã 5:12, ta xây dựng từ các bộ giãi mã 2:4 và 3:8 a) Mạch giải mã 2:4:

Code Verilog: /*bo giai ma 2:4 */ module decoder2to4(out,in,en); output [3:0]out; input [1:0]in; input en; wire [1:0]outnot;//ngo ra cong not not #50 not1(outnot[0],in[0]); not #50 not2(outnot[1],in[1]); and #50 and1(out[0],en,outnot[0],outnot[1]); and #50 and2(out[1],en,in[0],outnot[1]); and #50 and3(out[2],en,outnot[0],in[1]); and #50 and4(out[3],en,in[0],in[1]); endmodule

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Lab 1 – Cấu trúc máy tính -

MIPS_Register File

Kết quả mô phỏng trên Quartus:

b) Mạch giải mã 3:8

Code Verilog /* bo giai ma 3:8 */ module decoder3to8(out,in,en); output [7:0]out; input [2:0]in; input en; wire [2:0]outnot;

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MIPS_Register File

not #50 not1(outnot[0],in[0]); not #50 not2(outnot[1],in[1]); not #50 not3(outnot[2],in[2]); and #50 and1(out[0],en,outnot[0],outnot[1],outnot[2]); and #50 and2(out[1],en,in[0],outnot[1],outnot[2]); and #50 and3(out[2],en,outnot[0],in[1],outnot[2]); and #50 and4(out[3],en,in[0],in[1],outnot[2]); and #50 and5(out[4],en,outnot[0],outnot[1],in[2]); and #50 and6(out[5],en,in[0],outnot[1],in[2]); and #50 and7(out[6],en,outnot[0],in[1],in[2]); and #50 and8(out[7],en,in[0],in[1],in[2]); endmodule

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Kết quả mô phỏng trên Quartus:

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

c) Mạch giải mã 5:32:

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Ghép các bộ giải mã 2:4 và 3:8

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Lab 1 – Cấu trúc máy tính

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Code Verilog: /* bo giai ma 5:32 */ module decoder5to32(out, writereg, regwrite); output [31:0]out;// 32 bit dau ra, 1 bit cao, cac bit con lai thap input [4:0]writereg;//5 bit ngo vao Write register, chon thanh ghi ghi du lieu input regwrite;// ngo vao cho phep ghi wire [3:0]todec3_8;//ngo ra bo giai ma 2:4, ngo vao enable cac bo giai ma 3:8 decoder2to4 decode1(todec3_8,writereg[4:3],regwrite);//dau vao la bit thu 1 va thu 2 decoder3to8 decode2(out[7:0],writereg[2:0],todec3_8[0]); decoder3to8 decode3(out[15:8],writereg[2:0],todec3_8[1]); decoder3to8 decode4(out[23:16],writereg[2:0],todec3_8[2]); decoder3to8 decode5(out[31:24],writereg[2:0],todec3_8[3]); endmodule

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Kết quả mô phỏng trên Quartus:

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

3.2 Thiết kế 1 thanh ghi 32 bit: - Theo cấu trúc của file thanh ghi ta thiết kế thì nó bao gồm 32 thanh ghi, mà mỗi thanh ghi là gồm 32 bit, mỗi bit lại được tạo bởi 1 DFF. Do đó ta phải trải qua các bước sau: + Xây dựng 1 bit từ DFF. + Xây dựng 1 thanh ghi 32 bit từ 32 DFF.

a) Xây dựng 1 bit từ DFF:

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Bảng trạng thái:

Dn

Qn+1

0 1

0 1

Phương trình logic của DFF : Qn+1 = Dn

Code Verilog thực hiện 1 DFF: module D_FF (q, d, reset, clk); output q; input d, reset, clk; reg q; // Indicate that q is stateholding always @(posedge clk or posedge reset) if (reset) q = 0; // On reset, set to 0 else q = d; // Otherwise out = d endmodule

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MIPS_Register File

Từ DFF, ta xây dựng 1 bit thanh ghi với 2 ngõ vào Enable và WriteData:

Code Verilog thực hiện 1 bit thanh ghi: /*Tao 1 bit thanh ghi tu 1 D_Flipflop*/ module Regbit(BitOut, DataIn,En, clk,reset); output BitOut; // 1 bit cua thanh ghi input DataIn, En; input clk,reset; wire d,f1, f2; // ngo vao D Flip-Flop // bo multiplexor 2to1 dieu khien ghi 1 bit and #50 and1(f1, BitOut, (~En)); and #50 and2(f2, DataIn, En); or #50 or1(d, f1, f2); D_FF DFF0(BitOut, d, reset, clk); endmodule

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Kết quả mô phỏng trên Quartus:

b) Xây dựng một thanh ghi 32 bit: - Ở trên ta đã thực hiện tạo 1 bit của thanh ghi, do đó chỉ cần dùng module trên tạo ra 32 đối tượng rồi ghép lại ta được 1 thanh ghi 32 bits: Nhóm 14A – 08DT1

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

Code Verilog: /************Thiet ke 1 thanh ghi 32 bit****************/ module Reg32(WriteEnable, WriteData,d_out0,d_out1,d_out2,d_out3,d_out4, d_out5,d_out6,d_out7,d_out8,d_out9, d_out10,d_out11,d_out12,d_out13,d_out14, d_out15,d_out16,d_out17,d_out18,d_out19, d_out20,d_out21,d_out22,d_out23,d_out24, d_out25,d_out26,d_out27,d_out28,d_out29,d_out30,d_out31,clk); input WriteEnable, clk; input [31:0] WriteData; output d_out0,d_out1,d_out2,d_out3,d_out4, d_out5,d_out6,d_out7,d_out8,d_out9, d_out10,d_out11,d_out12,d_out13,d_out14, d_out15,d_out16,d_out17,d_out18,d_out19, d_out20,d_out21,d_out22,d_out23,d_out24, d_out25,d_out26,d_out27,d_out28,d_out29,d_out30,d_out31; Regbit Bit0 (d_out0,WriteData[0],WriteEnable,clk);

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Lab 1 – Cấu trúc máy tính Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit Regbit

MIPS_Register File

Bit1 (d_out1,WriteData[1],WriteEnable,clk); Bit2 (d_out2,WriteData[2],WriteEnable,clk); Bit3 (d_out3,WriteData[3],WriteEnable,clk); Bit4 (d_out4,WriteData[4],WriteEnable,clk); Bit5 (d_out5,WriteData[5],WriteEnable,clk); Bit6 (d_out6,WriteData[6],WriteEnable,clk); Bit7 (d_out7,WriteData[7],WriteEnable,clk); Bit8 (d_out8,WriteData[8],WriteEnable,clk); Bit9 (d_out9,WriteData[9],WriteEnable,clk); Bit10 (d_out10,WriteData[10],WriteEnable,clk); Bit11 (d_out11,WriteData[11],WriteEnable,clk); Bit12 (d_out12,WriteData[12],WriteEnable,clk); Bit13 (d_out13,WriteData[13],WriteEnable,clk); Bit14 (d_out14,WriteData[14],WriteEnable,clk); Bit15 (d_out15,WriteData[15],WriteEnable,clk); Bit16 (d_out16,WriteData[16],WriteEnable,clk); Bit17 (d_out17,WriteData[17],WriteEnable,clk); Bit18 (d_out18,WriteData[18],WriteEnable,clk); Bit19 (d_out19,WriteData[19],WriteEnable,clk); Bit20 (d_out20,WriteData[20],WriteEnable,clk); Bit21 (d_out21,WriteData[21],WriteEnable,clk); Bit22 (d_out22,WriteData[22],WriteEnable,clk); Bit23 (d_out23,WriteData[23],WriteEnable,clk); Bit24 (d_out24,WriteData[24],WriteEnable,clk); Bit25 (d_out25,WriteData[25],WriteEnable,clk); Bit26 (d_out26,WriteData[26],WriteEnable,clk); Bit27 (d_out27,WriteData[27],WriteEnable,clk); Bit28 (d_out28,WriteData[28],WriteEnable,clk); Bit29 (d_out29,WriteData[29],WriteEnable,clk); Bit30 (d_out30,WriteData[30],WriteEnable,clk); Bit31 (d_out31,WriteData[31],WriteEnable,clk);

endmodule

Kết quả mô phỏng trên Quartus

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Lab 1 – Cấu trúc máy tính

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MIPS_Register File

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

3.3 Thiết kế bộ multiplexor 32x32 to 32: - Bộ Multiplexor 32x32 to 32 có 32 ngõ dữ liệu đầu vào, mỗi ngõ dữ liệu có 32 bits. Dữ liệu ngõ ra ReadData có 32 bits bằng một trong số các ngõ vào. 5 bits của ReadRegister sẽ quyết định ngõ dữ liệu đầu vào nào sẽ được truyền đến đầu ra.

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Để thiết kế bộ Multiplexor 32x32 to 32, đầu tiên ta thiết kế bộ Multiplexor 32 to 1

a) Bộ multiplexor 32 to 1: - Bộ mux 32 to 1 được xây dựng từ các bộ mux 8 to 1, mà mỗi bộ mux 8 to 1 được xây dựng từ các bộ mux 2 to 1 và 4 to 1:

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MIPS_Register File

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

Code Verilog: //thiet ke bo mux2_1 module mux2_1(in,sel,out); input [1:0]in; input sel; output out; wire notsel; not#50 notsel0(notsel,sel); wire [1:0]f; and#50 and0(f[0],notsel,in[0]); and#50 and1(f[1],sel,in[1]); or#50 or0(out,f[0],f[1]); endmodule

//thiet ke bo mux4_1 module mux4_1(in,sel,out); input [3:0]in; input [1:0]sel; output out; wire [1:0]notsel; wire [3:0]f; not#50 notsel0(notsel[0],sel[0]); not#50 notsel1(notsel[1],sel[1]); and#50 and0(f[0],in[0],notsel[0],notsel[1]); and#50 and1(f[1],in[1],notsel[0],sel[1]); and#50 and2(f[2],in[2],sel[0],notsel[1]); and#50 and3(f[3],in[3],sel[0],sel[1]); or#50 or0(out,f[0],f[1],f[2],f[3]); endmodule

//thiet ke mux8_1 gom 2mux4_1 va 1mux2_1 module mux8_1(in,sel,out); input [7:0]in; input [2:0]sel; output out; wire [1:0]f; mux4_1 mux0(in[3:0],sel[1:0],f[0]); mux4_1 mux1(in[7:4],sel[1:0],f[1]); mux2_1 mux2(f[1:0],sel[2],out); endmodule //thiet ke mux32_1 gom 4mux8_1,1mux4_1 module mux32_1(in,sel,out); input [4:0]sel; input [31:0]in; output out;

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wire [3:0]f; mux8_1 mux0(in[7:0],sel[2:0],f[0]); mux8_1 mux1(in[15:8],sel[2:0],f[1]); mux8_1 mux2(in[23:16],sel[2:0],f[2]); mux8_1 mux3(in[31:24],sel[2:0],f[3]); mux4_1 mux4(f[3:0],sel[4:3],out); endmodule

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Mô phỏng trên Quartus:

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

b) Bộ multiplexor 32x32 to 32: - Sau khi thực hiện bộ Multiplexor 32 to 1 , ta dùng 32 bộ MUX (Multiplexor) 32 to 1 đó để thực hiện bộ MUX 32x32 to 32 . Cách thực hiện như sau: - Ta xem 32 thanh ghi 32 bit đó như một mảng 2 chiều 32x32 bit: A[0] A[1] …. A[30] A[31] Reg0 Reg1 … Reg30 Reg31 - Giả sử ta có tín hiệu điều khiển chọn thanh ghi ReadRegister = 5’b00001 , tức xuất dữ liệu ở thanh ghi số 1 ra ngõ ra. Ta muốn đưa 32 bits của Reg1 ra thì không thể cho chúng cùng vào 1 bộ MUX 32 to 1 , thay vào đó ta dùng 32 bộ MUX 32 to1 , đầu vào mỗi bộ MUX 32 to1 là 1 cột bit của bảng trên: A[0], A[1] …A[31], tín hiệu điều khiển vẫn dùng chung. Qua mỗi bộ MUX 32 to 1 sẽ thu được 1 bit của Reg1, có 32 bộ MUX như vậy thì sẽ đưa được toàn bộ Reg1 ra ngõ ra. Code Verilog: module mux32_32(reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8, reg9,reg10,reg11,reg12,reg13,reg14,reg15,reg16,reg17,reg18, reg19,reg20,reg21,reg22,reg23,reg24,reg25,reg26,reg27,reg28, reg29, reg30,reg31,sel,readata); input [31:0]reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8, reg9,reg10,reg11,reg12,reg13,reg14,reg15,reg16,reg17,reg18, reg19,reg20,reg21,reg22,reg23,reg24,reg25,reg26,reg27,reg28, reg29, reg30,reg31; input [4:0]sel; output [31:0]readata; mux32_1 r0(reg0,sel,readata[0]); mux32_1 r1(reg1,sel,readata[1]); mux32_1 r2(reg2,sel,readata[2]); mux32_1 r3(reg3,sel,readata[3]); mux32_1 r4(reg4,sel,readata[4]); mux32_1 r5(reg5,sel,readata[5]); mux32_1 r6(reg6,sel,readata[6]); mux32_1 r7(reg7,sel,readata[7]); mux32_1 r8(reg8,sel,readata[8]);

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MIPS_Register File

mux32_1 r9(reg9,sel,readata[9]); mux32_1 r10(reg10,sel,readata[10]); mux32_1 r11(reg11,sel,readata[11]); mux32_1 r12(reg12,sel,readata[12]); mux32_1 r13(reg13,sel,readata[13]); mux32_1 r14(reg14,sel,readata[14]); mux32_1 r15(reg15,sel,readata[15]); mux32_1 r16(reg16,sel,readata[16]); mux32_1 r17(reg17,sel,readata[17]); mux32_1 r18(reg18,sel,readata[18]); mux32_1 r19(reg19,sel,readata[19]); mux32_1 r20(reg20,sel,readata[20]); mux32_1 r21(reg21,sel,readata[21]); mux32_1 r22(reg22,sel,readata[22]); mux32_1 r23(reg23,sel,readata[23]); mux32_1 r24(reg24,sel,readata[24]); mux32_1 r25(reg25,sel,readata[25]); mux32_1 r26(reg26,sel,readata[26]); mux32_1 r27(reg27,sel,readata[27]); mux32_1 r28(reg28,sel,readata[28]); mux32_1 r29(reg29,sel,readata[29]); mux32_1 r30(reg30,sel,readata[30]); mux32_1 r31(reg31,sel,readata[31]); endmodule

-Kết quả mô phỏng trên Quartus:

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MIPS_Register File

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MIPS_Register File

3.4 Xây dựng bộ 32 thanh ghi 32 bit: - Kết hợp các module đã viết ở các phần trước lại, ta xây dựng được 1 bộ thanh ghi với cấu trúc, chức năng như đã giới thiệu Code Verilog: /*==========================FILE REGISTER==================*/ /*thiet ke 32 thanh ghi*/ module regfile(ReadData1,ReadData2,WriteData,ReadRegister1,ReadRegister2,Wr iteRegister,RegWrite,clk); output [31:0]ReadData1,ReadData2; input [31:0]WriteData; input [4:0]WriteRegister,ReadRegister1,ReadRegister2; input RegWrite,clk; wire [31:0] W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14,W15,W16,W17,W18,W1 9,W20,W21,W22,W23,W24,W25,W26,W27,W28,W29,W30,W31; // Wn: tat ca bit thu n cua 32 thanh ghi wire [31:0] decode_out; wire [31:0] WREG0,WREG1,WREG2,WREG3,WREG4,WREG5,WREG6,WREG7,WREG8,WREG9,WREG10,W REG11,WREG12,WREG13,WREG14,WREG15,WREG16,WREG17,WREG18, WREG19,WREG20,WREG21,WREG22,WREG23,WREG24,WREG25,WREG26,WREG27 ,WREG28,WREG29,WREG30,WREG31; // WREG : thanh ghi assign WREG0={W31[0],W30[0],W29[0],W28[0],W27[0],W26[0],W25[0],W24[0],W23[0 ],W22[0],W21[0],W20[0],W19[0],W18[0],W17[0],W16[0],W15[0],W14[0], W13[0],W12[0],W11[0],W10[0],W9[0],W8[0],W7[0],W6[0],W5[0],W4[0 ],W3[0],W2[0],W1[0],W0[0]}; assign WREG1={W31[1],W30[1],W29[1],W28[1],W27[1],W26[1],W25[1],W24[1],W23[1 ],W22[1],W21[1],W20[1],W19[1],W18[1],W17[1],W16[1],W15[1],W14[1], W13[1],W12[1],W11[1],W10[1],W9[1],W8[1],W7[1],W6[1],W5[1],W4[1],W3[1 ],W2[1],W1[1],W0[1]}; assign WREG2={W31[2],W30[2],W29[2],W28[2],W27[2],W26[2],W25[2],W24[2],W23[2 ],W22[2],W21[2],W20[2],W19[2],W18[2],W17[2],W16[2],W15[2],W14[2],

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Lab 1 – Cấu trúc máy tính

MIPS_Register File

W13[2],W12[2],W11[2],W10[2],W9[2],W8[2],W7[2],W6[2],W5[2],W4[2 ],W3[2],W2[2],W1[2],W0[2]}; assign WREG3={W31[3],W30[3],W29[3],W28[3],W27[3],W26[3],W25[3],W24[3],W23[3 ],W22[3],W21[3],W20[3],W19[3],W18[3],W17[3],W16[3],W15[3],W14[3], W13[3],W12[3],W11[3],W10[3],W9[3],W8[3],W7[3],W6[3],W5[3],W4[3 ],W3[3],W2[3],W1[3],W0[3]}; assign WREG4={W31[4],W30[4],W29[4],W28[4],W27[4],W26[4],W25[4],W24[4],W23[4 ],W22[4],W21[4],W20[4],W19[4],W18[4],W17[4],W16[4],W15[4],W14[4], W13[4],W12[4],W11[4],W10[4],W9[4],W8[4],W7[4],W6[4],W5[4],W4[4 ],W3[4],W2[4],W1[4],W0[4]}; assign WREG5={W31[5],W30[5],W29[5],W28[5],W27[5],W26[5],W25[5],W24[5],W23[5 ],W22[5],W21[5],W20[5],W19[5],W18[5],W17[5],W16[5],W15[5],W14[5], W13[5],W12[5],W11[5],W10[5],W9[5],W8[5],W7[5],W6[5],W5[5],W4[5 ],W3[5],W2[5],W1[5],W0[5]}; assign WREG6={W31[6],W30[6],W29[6],W28[6],W27[6],W26[6],W25[6],W24[6],W23[6 ],W22[6],W21[6],W20[6],W19[6],W18[6],W17[6],W16[6],W15[6],W14[6], W13[6],W12[6],W11[6],W10[6],W9[6],W8[6],W7[6],W6[6],W5[6],W4[6 ],W3[6],W2[6],W1[6],W0[6]}; assign WREG7={W31[7],W30[7],W29[7],W28[7],W27[7],W26[7],W25[7],W24[7],W23[7 ],W22[7],W21[7],W20[7],W19[7],W18[7],W17[7],W16[7],W15[7],W14[7], W13[7],W12[7],W11[7],W10[7],W9[7],W8[7],W7[7],W6[7],W5[7],W4[7 ],W3[7],W2[7],W1[7],W0[7]}; assign WREG8={W31[8],W30[8],W29[8],W28[8],W27[8],W26[8],W25[8],W24[8],W23[8 ],W22[8],W21[8],W20[8],W19[8],W18[8],W17[8],W16[8],W15[8],W14[8], W13[8],W12[8],W11[8],W10[8],W9[8],W8[8],W7[8],W6[8],W5[8],W4[8 ],W3[8],W2[8],W1[8],W0[8]};

Nhóm 14A – 08DT1

21

Lab 1 – Cấu trúc máy tính

MIPS_Register File

assign WREG9={W31[9],W30[9],W29[9],W28[9],W27[9],W26[9],W25[9],W24[9],W23[9 ],W22[9],W21[9],W20[9],W19[9],W18[9],W17[9],W16[9],W15[9],W14[9], W13[9],W12[9],W11[9],W10[9],W9[9],W8[9],W7[9],W6[9],W5[9],W4[9 ],W3[9],W2[9],W1[9],W0[9]}; assign WREG10={W31[10],W30[10],W29[10],W28[10],W27[10],W26[10],W25[10],W24[ 10],W23[10],W22[10],W21[10],W20[10],W19[10],W18[10],W17[10],W16[10], W15[10],W14[10], W13[10],W12[10],W11[10],W10[10],W9[10],W8[10],W7[10],W6[10],W5 [10],W4[10],W3[10],W2[10],W1[10],W0[10]}; assign WREG11={W31[11],W30[11],W29[11],W28[11],W27[11],W26[11],W25[11],W24[ 11],W23[11],W22[11],W21[11],W20[11],W19[11],W18[11],W17[11],W16[11], W15[11],W14[11], W13[11],W12[11],W11[11],W10[11],W9[11],W8[11],W7[11],W6[11],W5 [11],W4[11],W3[11],W2[11],W1[11],W0[11]}; assign WREG12={W31[12],W30[12],W29[12],W28[12],W27[12],W26[12],W25[12],W24[ 12],W23[12],W22[12],W21[12],W20[12],W19[12],W18[12],W17[12],W16[12], W15[12],W14[12], W13[12],W12[12],W11[12],W10[12],W9[12],W8[12],W7[12],W6[12],W5 [12],W4[12],W3[12],W2[12],W1[12],W0[12]}; assign WREG13={W31[13],W30[13],W29[13],W28[13],W27[13],W26[13],W25[13],W24[ 13],W23[13],W22[13],W21[13],W20[13],W19[13],W18[13],W17[13],W16[13], W15[13],W14[13], W13[13],W12[13],W11[13],W10[13],W9[13],W8[13],W7[13],W6[13],W5 [13],W4[13],W3[13],W2[13],W1[13],W0[13]}; assign WREG14={W31[14],W30[14],W29[14],W28[14],W27[14],W26[14],W25[14],W24[ 14],W23[14],W22[14],W21[14],W20[14],W19[14],W18[14],W17[14],W16[14], W15[14],W14[14], W13[14],W12[14],W11[14],W10[14],W9[14],W8[14],W7[14],W6[14],W5 [14],W4[14],W3[14],W2[14],W1[14],W0[14]};

Nhóm 14A – 08DT1

22

Lab 1 – Cấu trúc máy tính

MIPS_Register File

assign WREG15={W31[15],W30[15],W29[15],W28[15],W27[15],W26[15],W25[15],W24[ 15],W23[15],W22[15],W21[15],W20[15],W19[15],W18[15],W17[15],W16[15], W15[15],W14[15], W13[15],W12[15],W11[15],W10[15],W9[15],W8[15],W7[15],W6[15],W5 [15],W4[15],W3[15],W2[15],W1[15],W0[15]}; assign WREG16={W31[16],W30[16],W29[16],W28[16],W27[16],W26[16],W25[16],W24[ 16],W23[16],W22[16],W21[16],W20[16],W19[16],W18[16],W17[16],W16[16], W15[16],W14[16], W13[16],W12[16],W11[16],W10[16],W9[16],W8[16],W7[16],W6[16],W5 [16],W4[16],W3[16],W2[16],W1[16],W0[16]}; assign WREG17={W31[17],W30[17],W29[17],W28[17],W27[17],W26[17],W25[17],W24[ 17],W23[17],W22[17],W21[17],W20[17],W19[17],W18[17],W17[17],W16[17], W15[17],W14[17], W13[17],W12[17],W11[17],W10[17],W9[17],W8[17],W7[17],W6[17],W5 [17],W4[17],W3[17],W2[17],W1[17],W0[17]}; assign WREG18={W31[18],W30[18],W29[18],W28[18],W27[18],W26[18],W25[18],W24[ 18],W23[18],W22[18],W21[18],W20[18],W19[18],W18[18],W17[18],W16[18], W15[18],W14[18], W13[18],W12[18],W11[18],W10[18],W9[18],W8[18],W7[18],W6[18],W5 [18],W4[18],W3[18],W2[18],W1[18],W0[18]}; assign WREG19={W31[19],W30[19],W29[19],W28[19],W27[19],W26[19],W25[19],W24[ 19],W23[19],W22[19],W21[19],W20[19],W19[19],W18[19],W17[19],W16[19], W15[19],W14[19], W13[19],W12[19],W11[19],W10[19],W9[19],W8[19],W7[19],W6[19],W5 [19],W4[19],W3[19],W2[19],W1[19],W0[19]}; assign WREG20={W31[20],W30[20],W29[20],W28[20],W27[20],W26[20],W25[20],W24[ 20],W23[20],W22[20],W21[20],W20[20],W19[20],W18[20],W17[20],W16[20], W15[20],W14[20],

Nhóm 14A – 08DT1

23

Lab 1 – Cấu trúc máy tính

MIPS_Register File

W13[20],W12[20],W11[20],W10[20],W9[20],W8[20],W7[20],W6[20],W5 [20],W4[20],W3[20],W2[20],W1[20],W0[20]}; assign WREG21={W31[21],W30[21],W29[21],W28[21],W27[21],W26[21],W25[21],W24[ 21],W23[21],W22[21],W21[21],W20[21],W19[21],W18[21],W17[21],W16[21], W15[21],W14[21], W13[21],W12[21],W11[21],W10[21],W9[21],W8[21],W7[21],W6[21],W5 [21],W4[21],W3[21],W2[21],W1[21],W0[21]}; assign WREG22={W31[22],W30[22],W29[22],W28[22],W27[22],W26[22],W25[22],W24[ 22],W23[22],W22[22],W21[22],W20[22],W19[22],W18[22],W17[22],W16[22], W15[22],W14[22], W13[22],W12[22],W11[22],W10[22],W9[22],W8[22],W7[22],W6[22],W5 [22],W4[22],W3[22],W2[22],W1[22],W0[22]}; assign WREG23={W31[23],W30[23],W29[23],W28[23],W27[23],W26[23],W25[23],W24[ 23],W23[23],W22[23],W21[23],W20[23],W19[23],W18[23],W17[23],W16[23], W15[23],W14[23], W13[23],W12[23],W11[23],W10[23],W9[23],W8[23],W7[23],W6[23],W5 [23],W4[23],W3[23],W2[23],W1[23],W0[23]}; assign WREG24={W31[24],W30[24],W29[24],W28[24],W27[24],W26[24],W25[24],W24[ 24],W23[24],W22[24],W21[24],W20[24],W19[24],W18[24],W17[24],W16[24], W15[24],W14[24], W13[24],W12[24],W11[24],W10[24],W9[24],W8[24],W7[24],W6[24],W5 [24],W4[24],W3[24],W2[24],W1[24],W0[24]}; assign WREG25={W31[25],W30[25],W29[25],W28[25],W27[25],W26[25],W25[25],W24[ 25],W23[25],W22[25],W21[25],W20[25],W19[25],W18[25],W17[25],W16[25], W15[25],W14[25], W13[25],W12[25],W11[25],W10[25],W9[25],W8[25],W7[25],W6[25],W5 [25],W4[25],W3[25],W2[25],W1[25],W0[25]}; assign WREG26={W31[26],W30[26],W29[26],W28[26],W27[26],W26[26],W25[26],W24[

Nhóm 14A – 08DT1

24

Lab 1 – Cấu trúc máy tính

MIPS_Register File

26],W23[26],W22[26],W21[26],W20[26],W19[26],W18[26],W17[26],W16[26], W15[26],W14[26], W13[26],W12[26],W11[26],W10[26],W9[26],W8[26],W7[26],W6[26],W5 [26],W4[26],W3[26],W2[26],W1[26],W0[26]}; assign WREG27={W31[27],W30[27],W29[27],W28[27],W27[27],W26[27],W25[27],W24[ 27],W23[27],W22[27],W21[27],W20[27],W19[27],W18[27],W17[27],W16[27], W15[27],W14[27], W13[27],W12[27],W11[27],W10[27],W9[27],W8[27],W7[27],W6[27],W5 [27],W4[27],W3[27],W2[27],W1[27],W0[27]}; assign WREG28={W31[28],W30[28],W29[28],W28[28],W27[28],W26[28],W25[28],W24[ 28],W23[28],W22[28],W21[28],W20[28],W19[28],W18[28],W17[28],W16[28], W15[28],W14[28], W13[28],W12[28],W11[28],W10[28],W9[28],W8[28],W7[28],W6[28],W5 [28],W4[28],W3[28],W2[28],W1[28],W0[28]}; assign WREG29={W31[29],W30[29],W29[29],W28[29],W27[29],W26[29],W25[29],W24[ 29],W23[29],W22[29],W21[29],W20[29],W19[29],W18[29],W17[29],W16[29], W15[29],W14[29], W13[29],W12[29],W11[29],W10[29],W9[29],W8[29],W7[29],W6[29],W5 [29],W4[29],W3[29],W2[29],W1[29],W0[29]}; assign WREG30={W31[30],W30[30],W29[30],W28[30],W27[30],W26[30],W25[30],W24[ 30],W23[30],W22[30],W21[30],W20[30],W19[30],W18[30],W17[30],W16[30], W15[30],W14[30], W13[30],W12[30],W11[30],W10[30],W9[30],W8[30],W7[30],W6[30],W5 [30],W4[30],W3[30],W2[30],W1[30],W0[30]}; assign WREG31={W31[31],W30[31],W29[31],W28[31],W27[31],W26[31],W25[31],W24[ 31],W23[31],W22[31],W21[31],W20[31],W19[31],W18[31],W17[31],W16[31], W15[31],W14[31], W13[31],W12[31],W11[31],W10[31],W9[31],W8[31],W7[31],W6[31],W5 [31],W4[31],W3[31],W2[31],W1[31],W0[31]}; decoder5to32 decode(decode_out,WriteRegister,RegWrite);

Nhóm 14A – 08DT1

25

Lab 1 – Cấu trúc máy tính

MIPS_Register File

Reg32 reg0(1'b1,32'd0,W0[0],W1[0],W2[0],W3[0],W4[0],W5[0],W6[0],W7[0],W8[0 ],W9[0],W10[0],W11[0],W12[0],W13[0],W14[0],W15[0],W16[0],W17[0], W18[0],W19[0],W20[0],W21[0],W22[0],W23[0],W24[0],W25[0],W26[0] ,W27[0],W28[0],W29[0],W30[0],W31[0],clk); Reg32 reg1(decode_out[1],WriteData,W0[1],W1[1],W2[1],W3[1],W4[1],W5[1],W6[ 1],W7[1],W8[1],W9[1],W10[1],W11[1],W12[1],W13[1],W14[1],W15[1],W16[1 ],W17[1], W18[1],W19[1],W20[1],W21[1],W22[1],W23[1],W24[1],W25[1],W26[1],W27[1 ],W28[1],W29[1],W30[1],W31[1],clk); Reg32 reg2(decode_out[2],WriteData,W0[2],W1[2],W2[2],W3[2],W4[2],W5[2],W6[ 2],W7[2],W8[2],W9[2],W10[2],W11[2],W12[2],W13[2],W14[2],W15[2],W16[2 ],W17[2], W18[2],W19[2],W20[2],W21[2],W22[2],W23[2],W24[2],W25[2],W26[2],W27[2 ],W28[2],W29[2],W30[2],W31[2],clk); Reg32 reg3(decode_out[3],WriteData,W0[3],W1[3],W2[3],W3[3],W4[3],W5[3],W6[ 3],W7[3],W8[3],W9[3],W10[3],W11[3],W12[3],W13[3],W14[3],W15[3],W16[3 ],W17[3], W18[3],W19[3],W20[3],W21[3],W22[3],W23[3],W24[3],W25[3],W26[3],W27[3 ],W28[3],W29[3],W30[3],W31[3],clk); Reg32 reg4(decode_out[4],WriteData,W0[4],W1[4],W2[4],W3[4],W4[4],W5[4],W6[ 4],W7[4],W8[4],W9[4],W10[4],W11[4],W12[4],W13[4],W14[4],W15[4],W16[4 ],W17[4], W18[4],W19[4],W20[4],W21[4],W22[4],W23[4],W24[4],W25[4],W26[4],W27[4 ],W28[4],W29[4],W30[4],W31[4],clk); Reg32 reg5(decode_out[5],WriteData,W0[5],W1[5],W2[5],W3[5],W4[5],W5[5],W6[ 5],W7[5],W8[5],W9[5],W10[5],W11[5],W12[5],W13[5],W14[5],W15[5],W16[5 ],W17[5], W18[5],W19[5],W20[5],W21[5],W22[5],W23[5],W24[5],W25[5],W26[5],W27[5 ],W28[5],W29[5],W30[5],W31[5],clk); Reg32 reg6(decode_out[6],WriteData,W0[6],W1[6],W2[6],W3[6],W4[6],W5[6],W6[

Nhóm 14A – 08DT1

26

Lab 1 – Cấu trúc máy tính

MIPS_Register File

6],W7[6],W8[6],W9[6],W10[6],W11[6],W12[6],W13[6],W14[6],W15[6],W16[6 ],W17[6], W18[6],W19[6],W20[6],W21[6],W22[6],W23[6],W24[6],W25[6],W26[6],W27[6 ],W28[6],W29[6],W30[6],W31[6],clk); Reg32 reg7(decode_out[7],WriteData,W0[7],W1[7],W2[7],W3[7],W4[7],W5[7],W6[ 7],W7[7],W8[7],W9[7],W10[7],W11[7],W12[7],W13[7],W14[7],W15[7],W16[7 ],W17[7], W18[7],W19[7],W20[7],W21[7],W22[7],W23[7],W24[7],W25[7],W26[7],W27[7 ],W28[7],W29[7],W30[7],W31[7],clk); Reg32 reg8(decode_out[8],WriteData,W0[8],W1[8],W2[8],W3[8],W4[8],W5[8],W6[ 8],W7[8],W8[8],W9[8],W10[8],W11[8],W12[8],W13[8],W14[8],W15[8],W16[8 ],W17[8], W18[8],W19[8],W20[8],W21[8],W22[8],W23[8],W24[8],W25[8],W26[8],W27[8 ],W28[8],W29[8],W30[8],W31[8],clk); Reg32 reg9(decode_out[9],WriteData,W0[9],W1[9],W2[9],W3[9],W4[9],W5[9],W6[ 9],W7[9],W8[9],W9[9],W10[9],W11[9],W12[9],W13[9],W14[9],W15[9],W16[9 ],W17[9], W18[9],W19[9],W20[9],W21[9],W22[9],W23[9],W24[9],W25[9],W26[9],W27[9 ],W28[9],W29[9],W30[9],W31[9],clk); Reg32 reg10(decode_out[10],WriteData,W0[10],W1[10],W2[10],W3[10],W4[10],W5 [10],W6[10],W7[10],W8[10],W9[10],W10[10],W11[10],W12[10],W13[10],W14 [10],W15[10],W16[10],W17[10], W18[10],W19[10],W20[10],W21[10],W22[10],W23[10],W24[10],W25[10],W26[ 10],W27[10],W28[10],W29[10],W30[10],W31[10],clk); Reg32 reg11(decode_out[11],WriteData,W0[11],W1[11],W2[11],W3[11],W4[11],W5 [11],W6[11],W7[11],W8[11],W9[11],W10[11],W11[11],W12[11],W13[11],W14 [11],W15[11],W16[11],W17[11], W18[11],W19[11],W20[11],W21[11],W22[11],W23[11],W24[11],W25[11],W26[ 11],W27[11],W28[11],W29[11],W30[11],W31[11],clk); Reg32 reg12(decode_out[12],WriteData,W0[12],W1[12],W2[12],W3[12],W4[12],W5 [12],W6[12],W7[12],W8[12],W9[12],W10[12],W11[12],W12[12],W13[12],W14 [12],W15[12],W16[12],W17[12], W18[12],W19[12],W20[12],W21[12],W22[12],W23[12],W24[12],W25[12],W26[ 12],W27[12],W28[12],W29[12],W30[12],W31[12],clk);

Nhóm 14A – 08DT1

27

Lab 1 – Cấu trúc máy tính

MIPS_Register File

Reg32 reg13(decode_out[13],WriteData,W0[13],W1[13],W2[13],W3[13],W4[13],W5 [13],W6[13],W7[13],W8[13],W9[13],W10[13],W11[13],W12[13],W13[13],W14 [13],W15[13], W16[13],W17[13],W18[13],W19[13],W20[13],W21[13],W22[13],W23[13],W24[ 13],W25[13],W26[13],W27[13],W28[13],W29[13],W30[13],W31[13],clk); Reg32 reg14(decode_out[14],WriteData,W0[14],W1[14],W2[14],W3[14],W4[14],W5 [14],W6[14],W7[14],W8[14],W9[14],W10[14],W11[14],W12[14],W13[14],W14 [14],W15[14], W16[14],W17[14],W18[14],W19[14],W20[14],W21[14],W22[14],W23[14],W24[ 14],W25[14],W26[14],W27[14],W28[14],W29[14],W30[14],W31[14],clk); Reg32 reg15(decode_out[15],WriteData,W0[15],W1[15],W2[15],W3[15],W4[15],W5 [15],W6[15],W7[15],W8[15],W9[15],W10[15],W11[15],W12[15],W13[15],W14 [15],W15[15], W16[15],W17[15],W18[15],W19[15],W20[15],W21[15],W22[15],W23[15],W24[ 15],W25[15],W26[15],W27[15],W28[15],W29[15],W30[15],W31[15],clk); Reg32 reg16(decode_out[16],WriteData,W0[16],W1[16],W2[16],W3[16],W4[16],W5 [16],W6[16],W7[16],W8[16],W9[16],W10[16],W11[16],W12[16],W13[16],W14 [16],W15[16], W16[16],W17[16],W18[16],W19[16],W20[16],W21[16],W22[16],W23[16],W24[ 16],W25[16],W26[16],W27[16],W28[16],W29[16],W30[16],W31[16],clk); Reg32 reg17(decode_out[17],WriteData,W0[17],W1[17],W2[17],W3[17],W4[17],W5 [17],W6[17],W7[17],W8[17],W9[17],W10[17],W11[17],W12[17],W13[17],W14 [17],W15[17], W16[17],W17[17],W18[17],W19[17],W20[17],W21[17],W22[17],W23[17],W24[ 17],W25[17],W26[17],W27[17],W28[17],W29[17],W30[17],W31[17],clk); Reg32 reg18(decode_out[18],WriteData,W0[18],W1[18],W2[18],W3[18],W4[18],W5 [18],W6[18],W7[18],W8[18],W9[18],W10[18],W11[18],W12[18],W13[18],W14 [18],W15[18],

Nhóm 14A – 08DT1

28

Lab 1 – Cấu trúc máy tính

MIPS_Register File

W16[18],W17[18],W18[18],W19[18],W20[18],W21[18],W22[18],W23[18],W24[ 18],W25[18],W26[18],W27[18],W28[18],W29[18],W30[18],W31[18],clk); Reg32 reg19(decode_out[19],WriteData,W0[19],W1[19],W2[19],W3[19],W4[19],W5 [19],W6[19],W7[19],W8[19],W9[19],W10[19],W11[19],W12[19],W13[19],W14 [19],W15[19], W16[19],W17[19],W18[19],W19[19],W20[19],W21[19],W22[19],W23[19],W24[ 19],W25[19],W26[19],W27[19],W28[19],W29[19],W30[19],W31[19],clk); Reg32 reg20(decode_out[20],WriteData,W0[20],W1[20],W2[20],W3[20],W4[20],W5 [20],W6[20],W7[20],W8[20],W9[20],W10[20],W11[20],W12[20],W13[20],W14 [20],W15[20], W16[20],W17[20],W18[20],W19[20],W20[20],W21[20],W22[20],W23[20],W24[ 20],W25[20],W26[20],W27[20],W28[20],W29[20],W30[20],W31[20],clk); Reg32 reg21(decode_out[21],WriteData,W0[21],W1[21],W2[21],W3[21],W4[21],W5 [21],W6[21],W7[21],W8[21],W9[21],W10[21],W11[21],W12[21],W13[21],W14 [21],W15[21], W16[21],W17[21],W18[21],W19[21],W20[21],W21[21],W22[21],W23[21],W24[ 21],W25[21],W26[21],W27[21],W28[21],W29[21],W30[21],W31[21],clk); Reg32 reg22(decode_out[22],WriteData,W0[22],W1[22],W2[22],W3[22],W4[22],W5 [22],W6[22],W7[22],W8[22],W9[22],W10[22],W11[22],W12[22],W13[22],W14 [22],W15[22], W16[22],W17[22],W18[22],W19[22],W20[22],W21[22],W22[22],W23[22],W24[ 22],W25[22],W26[22],W27[22],W28[22],W29[22],W30[22],W31[22],clk); Reg32 reg23(decode_out[23],WriteData,W0[23],W1[23],W2[23],W3[23],W4[23],W5 [23],W6[23],W7[23],W8[23],W9[23],W10[23],W11[23],W12[23],W13[23],W14 [23],W15[23], W16[23],W17[23],W18[23],W19[23],W20[23],W21[23],W22[23],W23[23],W24[ 23],W25[23],W26[23],W27[23],W28[23],W29[23],W30[23],W31[23],clk); Reg32 reg24(decode_out[24],WriteData,W0[24],W1[24],W2[24],W3[24],W4[24],W5

Nhóm 14A – 08DT1

29

Lab 1 – Cấu trúc máy tính

MIPS_Register File

[24],W6[24],W7[24],W8[24],W9[24],W10[24],W11[24],W12[24],W13[24],W14 [24],W15[24], W16[24],W17[24],W18[24],W19[24],W20[24],W21[24],W22[24],W23[24],W24[ 24],W25[24],W26[24],W27[24],W28[24],W29[24],W30[24],W31[24],clk); Reg32 reg25(decode_out[25],WriteData,W0[25],W1[25],W2[25],W3[25],W4[25],W5 [25],W6[25],W7[25],W8[25],W9[25],W10[25],W11[25],W12[25],W13[25],W14 [25],W15[25], W16[25],W17[25],W18[25],W19[25],W20[25],W21[25],W22[25],W23[25],W24[ 25],W25[25],W26[25],W27[25],W28[25],W29[25],W30[25],W31[25],clk); Reg32 reg26(decode_out[26],WriteData,W0[26],W1[26],W2[26],W3[26],W4[26],W5 [26],W6[26],W7[26],W8[26],W9[26],W10[26],W11[26],W12[26],W13[26],W14 [26],W15[26], W16[26],W17[26],W18[26],W19[26],W20[26],W21[26],W22[26],W23[26],W24[ 26],W25[26],W26[26],W27[26],W28[26],W29[26],W30[26],W31[26],clk); Reg32 reg27(decode_out[27],WriteData,W0[27],W1[27],W2[27],W3[27],W4[27],W5 [27],W6[27],W7[27],W8[27],W9[27],W10[27],W11[27],W12[27],W13[27],W14 [27],W15[27], W16[27],W17[27],W18[27],W19[27],W20[27],W21[27],W22[27],W23[27],W24[ 27],W25[27],W26[27],W27[27],W28[27],W29[27],W30[27],W31[27],clk); Reg32 reg28(decode_out[28],WriteData,W0[28],W1[28],W2[28],W3[28],W4[28],W5 [28],W6[28],W7[28],W8[28],W9[28],W10[28],W11[28],W12[28],W13[28],W14 [28],W15[28], W16[28],W17[28],W18[28],W19[28],W20[28],W21[28],W22[28],W23[28],W24[ 28],W25[28],W26[28],W27[28],W28[28],W29[28],W30[28],W31[28],clk); Reg32 reg29(decode_out[29],WriteData,W0[29],W1[29],W2[29],W3[29],W4[29],W5 [29],W6[29],W7[29],W8[29],W9[29],W10[29],W11[29],W12[29],W13[29],W14 [29],W15[29], W16[29],W17[29],W18[29],W19[29],W20[29],W21[29],W22[29],W23[29],W24[ 29],W25[29],W26[29],W27[29],W28[29],W29[29],W30[29],W31[29],clk);

Nhóm 14A – 08DT1

30

Lab 1 – Cấu trúc máy tính

MIPS_Register File

Reg32 reg30(decode_out[30],WriteData,W0[30],W1[30],W2[30],W3[30],W4[30],W5 [30],W6[30],W7[30],W8[30],W9[30],W10[30],W11[30],W12[30],W13[30],W14 [30],W15[30], W16[30],W17[30],W18[30],W19[30],W20[30],W21[30],W22[30],W23[30],W24[ 30],W25[30],W26[30],W27[30],W28[30],W29[30],W30[30],W31[30],clk); Reg32 reg31(decode_out[31],WriteData,W0[31],W1[31],W2[31],W3[31],W4[31],W5 [31],W6[31],W7[31],W8[31],W9[31],W10[31],W11[31],W12[31],W13[31],W14 [31],W15[31], W16[31],W17[31],W18[31],W19[31],W20[31],W21[31],W22[31],W23[31],W24[ 31],W25[31],W26[31],W27[31],W28[31],W29[31],W30[31],W31[31],clk);

mux32_32 mux1(W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14,W15,W16,W17,W 18,W19,W20,W21,W22,W23,W24,W25,W26,W27, W28,W29,W30,W31,ReadRegister1,ReadData1); mux32_32 mux2(W0,W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14,W15,W16,W17,W 18,W19,W20,W21,W22,W23,W24,W25,W26,W27, W28,W29,W30,W31,ReadRegister2,ReadData2); endmodule

3.5 Kết quả mô phỏng bằng ICARUS : Code Verilog: /*==============TESTBENCH====================*/ // The verilog file containing your register file must // be named "regfile.v". module regstim(); parameter ClockDelay = 5000; reg [4:0] ReadRegister1, ReadRegister2, WriteRegister; reg [31:0] WriteData; reg RegWrite, clk; wire [31:0] ReadData1, ReadData2;

Nhóm 14A – 08DT1

31

Lab 1 – Cấu trúc máy tính

MIPS_Register File

integer i; // Your register file MUST be named "regfile". // Also you must make sure that the port declarations // match up with the module instance in this stimulus file. regfile reg1(ReadData1,ReadData2,WriteData, ReadRegister1,ReadRegister2,WriteRegister,RegWrite,clk); initial begin $dumpfile("regstim.vcd"); $dumpvars(1,reg1); end initial clk = 0; always #(ClockDelay/2) clk = ~clk; initial begin $monitor($time, " ReadData1=%h, ReadData2=%h, WriteData=%h, WriteReg=%b, Reg1=%h, Reg2=%h, RegWrite=%b, clk=%b", ReadData1, ReadData2, WriteData, WriteRegister, ReadRegister1, ReadRegister2, RegWrite,clk); #(ClockDelay/4); // Make all changes away from the clock edges // Try to write the value 0xA0 into register 0. // Register 0 should begin and remain at the value of 0. RegWrite=0; ReadRegister1=0; ReadRegister2=0; WriteRegister=0; WriteData=32'hA0; #(ClockDelay); RegWrite=1; #(ClockDelay); // Write a value into each register. for (i=1; i