Artemis User Guide

 

User Guide Version 7.0

 

© 2008 Opal-RT Technologies Inc. All rights reserved for all countries. Information in this document is subject to change without w ithout notice, and does not represent a commitment commitmen t on the part of OPAL-RT TECHNOLOGIES. The software and associated files described in this document are furnished under a license agreement, and can only be used or copied in accordance with the terms of the agreement. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or information and retrieval systems, for any an y purpose other than the purchaser's personal use, without express written permission of OPAL-RT TECHNOLOGIES Incorporated. Documents and information relating to or associated with OPAL-RT products, business, or activities, including but not limited to financial information; information ; data or statements; trade secrets; product research and development; existing and future product designs and performance specifications; marketing plans or techniques, client lists, computer programs, processes, and know-how that have been clearly identified and properly marked by OPAL-RT as  “proprietary information,” trade secrets, or company confidential information. The information must mus t have been developed by OPAL-RT and is not made available to the public witho without ut the express consent of OPAL-RT or its legal counsel. ARTEMiS, RT-EVENTS, RT-LAB and DINAMO are trademarks of OPAL-RT TECHNOLOGIES, Inc. MATLAB, Simulink, Real-Time Workshop and SimPowerSystem are trademarks of The Mathworks, Inc. LabVIEW is a trademark of National Instruments, Inc. QNX is a trademark of QNX Software Sof tware Systems Ltd. All other brand and product names are trademarks or service marks of their respective holders and are hereby acknow acknowledged. ledged. We have done our best to ensure that the material found in this publication is both useful and accurate. However, please be aware that errors may exist in this publication, and that neither the authors nor OPAL-RT TECHNOLOGIES make any guarantees concerning the accuracy of the information found here or in the use to which it may be put. Reference Number: RT-LAB User’s Guide Published in Canada Contact Us For additional information you may contact the Customer Support team at OPAL-RT at the following coordinates:

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TABLE of CONTENTS

CHAPTER 1: INTRODUCTION

What to Expect from this Guide G uide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About ARTEMiS ARTEMiS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intended Audience and Required Skills and Knowledge . . . . . . . . . . . . . . . . . . . Organization of Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conventions Convent ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 5 6 6 6

CHAPTER 2: QUICK START

Getting Started (Off-line simulation). simulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Getting Started (RT-LAB real-time simulation) . . . . . . . . . . . . . . . . . . . . . . . . . 9 CHAPTER 3: USING ARTEMIS

Six Pulse Converter Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-Thyristor Frequency Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Medium Power Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARTEMiS modeling of transformer saturation . . . . . . . . . . . . . . . . . . . . . . . . .

16 16 17 18

CHAPTER 4: STATE-SPACE SPACE (SSN) SOLVER BASICS

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction The ssnSSN_lib.mdl library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usage of the SSN Nodal Interface Block in a model . . . . . . . . . . . . . . . . . . . . 1st Real-life Real-life case: 12-pulse 12-pulse HVDC HVDC system . . . . . . . . . . . . . . . . . . . . . . . . . . . 2nd case: 3-level NCP inverter and SSN Real-Time Impulse Events . . . . . . . . . 3rd case: Inlined Thyristor Valve Compensation in SSN . . . . . . . . . . . . . . . . . Static Var Var Compensator Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSN parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 25 27 28 32 34 38 40

CHAPTER 5: REFERENCE

ARTEMiS Guide 45 ARTEMiS Distributed Parameters Line 53 ARTEMiS-SSN Frequency Dependent Line 63 ARTEMiS-SSN WideBand Line 71 ARTEMiS Stubline 79 ARTEMiS Transformer with Switched Saturable Core 91 ARTEMiS-SSN Nodal interface Blocks 101 ARTEMiS Distributed Parameters Line with Variable Internal Fault distance 107 ARTEMiS MMC 1P Cell 113 ARTEMiS MMC 2P Cell 117 ARTEMiS TSB 2-Level 121 OpReplaceSpsBlocks 125

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TABLE of CONTENTS

CHAPTER 6: KNOWN LIMITATIONS (ARTEMIS V6.0 RELEASE)

PC Memory limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 ARTEMiS limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SimPowerSystems 4.6- 5.0 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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Introduction

1.1

 

1

What What to Ex Expe pect ct from rom tthi his s Guid Guide e

This guide explains the ARTEMiS add-on for SimPowerSystems blockset. 1.2

About ARTEMiS ARTEMiS stands for Avanced Real-Time ElectroMechanical Simulator. It is a plug-in to the SimPowerSystems blockset for Simulink that enables hard real-time simulation of SimPowerSystems models. The objective of ‘hard’ real-time simulation is that all iteration iterat ion of the model are completed in a prescribed amount of time at each time step. The ‘hard’ real-time simulation objective is different that the typical simulation objective. In a normal simulation, one wants the smaller total simulation time or said in another way, the smallest average simulation time step. The ‘hard’ real-time simulation objective is to have the smaller maximum time step. The second main objective of real-time simulation is to maintain the simulation accuracy to a certain level. This is a potential problem in real-time simulation because it is made with fixed-step solvers. Compared with typical variable-step solvers, the usage of fixed-step solver can lead to innacuracies because there are no built-in accuracy check within the solvers. A typical variable step solver will implicitly compare it results with a higher order algorithm to verify accuracy. With a fixed-step solver, there is no such verification and larger time step always degrade simulation accuracy in some way. ARTEMiS help reach real-time simulation objectives in several ways. By its characteristics, characterist ics, ARTEMiS can extend the range of time step to achieve both speed and precision for a specific real-time application. In applications where network switching causes numerical oscillations that cannot be damped at time step above minimum hardware limits, ARTEMiS solvers good damping properties successfully damp the spurious oscillations. Furthermore, in applications where some underdamped or high frequency components, relative to the fastest possible sampling time must be taken into account, ARTEMiS improves the precision of those components compared to the trapezoidal or Tustin methods. m ethods. Since version 6.0, ARTEMiS offers a new solver called State-Space Nodal which combines the accuracy potential of state-space methods with the natural ability of the nodal approach to handle circuit with a large number of switches. Consequently, ARTEMiS is no longer limited with regards to the number of coupled switches in a circuit.  which provides some edges in the modelisation of microgrids or distribution networks in which artificial decoupling methods like stublines cannot be used but also in more standard systems like HVDC or SVC. In switched power system, ARTEMiS now comes with automatically Inlined Interpolation methods for thyristors and 2-level voltage inverters. These very efficient solver methods detects and compensates for switching events that occur in the middle m iddle of time steps. The option works in conjunction wi with th the RTEVENTS blockset and uses real-time optimized interpolation techniques to improve accuracy. ARTEMiS provides special model options. It comes with a saturable transformer model based which use flux as state and that does cause algebraic loops. One can also use SimPowerSystems SimPow erSystems continuous time machine model in conjunction with Simulink higher order fixed-step solvers. In some case, the use of higher order solver can increase notably the precision.

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Intended Audience and Required Skills and Knowledge

Introduction

Finally, ARTEMiS comes with specialized models for real-time simulation such as ARTEMiS Distributed Parameter Line and ARTEMiS Stublines that enables distributed simulation simulatio n of power systems on several CPUs or cores of standard PCs using RT-LAB. The ARTEMiS plug-in is especially designed to work in the RT-LAB real-time environment and shall prove very effective in helping the typical user reach its realtime simulation objectives.

1. 1.3 3

Intend Intended ed Aud Audien ience ce and and Requir Required ed Ski Skills lls and Knowle Knowledge dge

The ARTEMiS User Guide is intended for ARTEMiS users. It is recommended that you be familiar with Simulink and SimPowerSystems before getting started. 1.4

Org Organi anizat zatio ion n of Gui uid de The followingl guides come with the ARTEMiS documentation: • Inst Install allat atio ion n Gu Guid idee • Use serr Gui uid de

1.5

Conventions Opal-RT guides use the following conventions:

Table 1: General and Typographical Conventions THIS CONVENTI ON Bold

Note: Warning: Recommendation: Code

Italics Blue Text

6

INDICATES

User interface elements or text that must be typed exactly as shown. Emphasizes or supplements parts of the text. You can disregard the information in a note and still complete a task. Describes an action that must be avoided or followed to prevent a loss of data. A suggestion that you may or may not follow and still complete a task. Sample code. Reference work titles. Cross-references (internal or external) or hypertext links.

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Quick Start

This chapter describes how to use the ARTEMiS Add-On to SPS in RT-LAB. For a quick start on how to use the new State-Space Nodal Solver of ARTEMiS, please p lease refer to the ’SSN basics’ chapter of this guide.

2. 2.1 1

Gett Gettin ing g Sta Start rted ed (Of (Offf-li line ne si simu mula latio tion) n) To use the ARTEMiS Add-On to SPS: 1.

Start MATLAB. Open a Simul Simulink ink model model that uses uses the blocks blocks from the SimPowerSystems blockset like SPS demo power_monophaseline .

Figure 1:Time Domain and Frequency Domain Testing of Single Phase Line 2.

ARTEMIS User’s Guide

From the MATLAB MATLAB co command mmand window window,, open the ART ARTEMiS EMiS llibrar ibraryy promp promptt by typing artemis .

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Getting Started (Off-line simulation)

Quick Start

Figure 2:MATLAB

The ARTEMiS library window is displayed.

Figure 3:Library ARTEMiS 3.

8

Click on th the ARTEMiS  block and drag the ARTEMiS Guide block into your model.

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Getting Started (RT-LAB real-time simulation)

Figure 4:Time Domain and Frequency Domain Testing of Single Phase Line 4.

2. 2.2 2

Run Run yyou ourr mo mode del. l. On Once ce the ARTEMiS Guide block is placed in a model, the linear part of power system is simulated using the fixed time step algorithms and options specified in the ARTEMiS Guide dialog box. If both the ARTEMiS Guide block and the Discrete System block from SimPowerSystems blockset are present in a model, the ARTEMiS Guide block has precedence.

Gettin Getting g St Start arted ed (RT-LA (RT-LAB B real-t real-time ime simula simulatio tion) n) After the model has run offline successfully, s uccessfully, the following step is to modify the model to run it in real-time within RT-LAB. The first step to convert this model to RT-LAB RT -LAB and to exploit the parallel simulation capability of RT-LAB is to convert the SPS Distributed Parameter Line to a ARTEMiS Distributed Parameter Line (DPL). Both DPL models have the same underlying equations but the latter is design to be used inside RT-LAB. The ARTEMiS DPL model can be found in the ARTEMiS library under the ARTEMiS group. When this DPL model is used, the resulting electric model is effectively decoupled into 2 different state-space  and BLUE BLUE groups  groups of the figure below). RT-LAB will systems containing topologically connected elements (RED ( RED and then compute these state-space systems in different cores/CPUs during real-time simulation.

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Getting Started (RT-LAB real-time simulation)

Quick Start

So, step by step: • Select all bloc blocks ks lo located cated in in the sub subnetwork network 1 in the ffigure igure aabove bove and press Ctrl-G to create a new subsystem. • Mov Movee the ARTE ARTEMiS MiS b block lock insid insidee the sub subsys system tem.. • Rename th this is su subsyst bsystem em to SM SM_Subnet _Subnetwork_1 work_1.. The following following figure displays the content of the SS_Subnetwork_1 subsystem.

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Getting Started (RT-LAB real-time simulation)

• Select all bloc blocks ks lo located cated in in the sub subnetwork network 2 and pre press ss Ctrl Ctrl-G -G to create a new subsystem. • Add a ARTEMiS ARTEMiS Gui Guide de bl block ock inside the subsyste subsystem. m. • Rename tthis his subsyste subsystem m to SS_Subnetw SS_Subnetwork_2. ork_2. The ffollowi ollowing ng figu figure re illustrates the content of the SS_Subnetwork_2 subsystem.

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Getting Started (RT-LAB real-time simulation)

Quick Start

• Select the 3 remai remaining ning blocks, blocks, normally the two scopes scopes block blockss and the Mux1 block and press Ctrl-G to create a new subsystem. • Ren Rename ame th this is sub subsy syste stem m to SC_ SC_Cons Console ole.. • Add th thee RT-LAB opcom opcomm m block block between between the inp inports orts b blocks locks aand nd the content of the subsystem. Don’t forget to set the number of inports of the opcomm blocks to 3. Refer to the t he RT-LAB user guide for more help. • The fol following lowing figure iillustra llustrates tes the content of th thee SC_Cons SC_Console ole subsystem after the modifications described above have been made.

• Modif Modifyy the solver solver para parameters meters of of the model; model; select select one of the fix fixededstep solver, like ode3 for example, and change the fixed-step size to 50e-6. • Organi Organize ze the top level level blo blocks cks according according tto o the following following fi figure. gure. IMPORTANT: the powerGUI block must be at the top level and each subsystem must contain an ARTEMiS block

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Getting Started (RT-LAB real-time simulation)

• Sa Save ve yo your ur mode model. l. • Your mo model del is n now ow ready to be compiled compiled with RTRT-LAB. LAB. Refer Refer to the the RT-LAB User Guide for more help. If your have set the sample times of your model with a variable set in the workspace(ex: Ts), you should set the model initialization function with in File->Model Properties->Callbacks->InitFcn • IMPOR IMPORTANT TANT NOTE: A singl singlee ARTEMiS block can also be put in the top-level of the RT-LAB ready model. At compilation time, RT-LAB will make a copy of this block with identical parameters in all separated subsystems.

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Getting Started (RT-LAB real-time simulation)

Quick Start

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Using ARTEMiS

3

ARTEMiS, the Advanced Real-Time Electro-Mechanical Simulator, is a simulation toolset that includes the ARTEMiS Plug-in to the SimPowerSystems blockset. The ARTEMiS Plug-in is a performanceenhancing add-on product for the SimPo werSystems blockset. It is easy to use: simply ad add d the ARTEMiS Plug-in block to any Simulink model containing SimPowerSystems blockset blocks and the model runs using the ARTEMiS improved algorithms. The ARTEMiS Plug-in offers the following advantages to the standard SimPowerSystems Blockset: • Real-time computational capability. More than simply providing faster simulations, ARTEMiS is designed to enable real-time computation of SimPowerSystems blockset circuits. The following considerations were taken into account for the design of ARTEMiS: •

Stat Statee-Spa -Space ce Noda Nodall ((SS SSN) N) solv solver er w whi hich ch p pro rovi vide dess all all the the advantages of nodal methods such as enabling the real-time simulation of circuit with hundred of switches s witches and node count approaching 1000.

•

Im Impr prov oved ed mode modeli ling ng of some some power ower syst system em elem elemen ents ts suc such h as: Saturable transformer model (which can be simulated at fixed time step in a non-iterative manner in ARTEMiS)

•

Di Dist stri ribut buted ed multi multi-p -proc roces esso sors rs sim simul ulat ation ion capab capabililit ityy of complex power systems with ARTEMiS Distributed Parameter Line and ARTEMiS stubline models .

•

Comp Compat atibi ibilit lityy wit with h OPA OPALL-RT RT's 's RT-L RT-LAB AB suit suitee of of prod produc ucts ts for for easy integrated parallel simulation design process.

• Higher precision for linear circuits with high frequency components: ARTEMiS improves the SimPowerSystems SimPowerSystem s blockset's precision of simulation compared with the standard fixed-step integration methods such as trapezoidal or Tustin, especially for circuits whose variables have high frequency components. • Less numerical oscillations without the need for artificial stabilizing snubbers: ARTEMiS uses L-stable integration methods that are free from the numerical oscillations that often affect the standard SimPowerSystems blockset fixed-step integration methods such as trapezoidal or Tustin. The effect of ARTEMiS on numerical oscillation can be seen even on simple cases such as SPS SP S demo power_monophaseline . The following section are examples of what can be acheived with the ARTEMiS plug-in to the SimPowerSystems blockset using the SSN solver. The Simulink demo section of ARTEMiS contains many more examples.

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Distribution Grid Example

Using ARTEMiS

3.1

Dist Distri ribu buti tion on Grid Grid Exa Example mple Figure 5 shows a a typical configuration of distribution grid in France and a nd such a model is used to study the impact of various load profiles and control strategies. This distribution system (F1a) with an on-load tap changer (OLTC) transformer at the feeder point, 120 3-phase time-variable loads (TVL), 3-phase fault and more than 650 equivalent EMTP nodes is simulated in real-time with the SSN solver. 15 SSN nodes were used in the separation of the F1a network (the 5 red dots in image).

Figure 5:F1a distribution grid 3. 3.1.1 1.1 Rea Reall-Tim Time e perf perfor orman mance ce The F1a model with OLTC and one 3-phase ffault ault can be simulated in real-time at a time-step of 70 µs   on an Intel-Xeon Processor-E5-2687W (Xeon V3), using only 4 cores out of the 20 available, without any delays or stublines. See [1] for more detail on this thi s model. This performance is currently out of reach for other real-time platform such as Hypersim or RTDS because of there are no long transmission lines in distribution systems.

3. 3.2 2

Bipola Bipolar r HVDC HVDC system system with with swit switche ched d filt filter er banks banks In this section, SSN is used to simulate in real a complete 12-pulse bipolar HVDC link with switched filter banks. This test model is a 2000 MW (500 kV, 2 kA at each pole) HVDC link used to transmit power from a 500 kV, 5000 MVA, 60 Hz network to a 345 kV, 10 000 MVA, 50 Hz network. The rectifier and the inverter are 12-pulse converters and the link is bipolar. The rectifier and the inverter are interconnected through two 300 km distributed parameter line using 0.5 H smoothing reactors. The transformer tap changers are not simulated and fixed taps are assumed. Reactive power required by the converters is provided by a set of capacitor banks plus 11th, 13th and high pass filters for a total of 600 MVAR on each side. These capacitors and filters can be switched; each station has 7 switched banks.

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Simulation Results

Line e( (300 0k km ) transfo

6-pulse thyristor  rectifier 

6-pulse thyristor  rectifier  500kV  60H 0H z

 ACfilt lters(600M V ars )

345kV  50H 0H z

 ACfiillte rs(600M Vars)

Line e( (300 0k km )

Figure 6:Bipolar 12-pulse HVDC link with switched filter banks In Fig. 6, the SSN state-space groups are indicated by the colors. Stations Stat ions (with 2 poles each) on both sides of the lines are simulated on two different cores of the RT-LAB simulator. The natural delay of transmission line enables this decoupling. Each station circuit, comprising the two 12-pulse rectifiers are each simulated with a single SSN solver instance,  without decoupling delays. See [2] for more details.

 

Figure 7:Bipolar DC-link filter bank switching test overall result (left) and a nd ITVC algorithm effect on the DC-current of the HVDC link (right) 3. 3.2.1 2.1 Sim Simula ulatio tion n Re Resul sults ts As a test case, we made the DC-link energization. Then, Then , when the DC-link reached its nominal current, we began to connect filter banks 1 to 6 at a t 0.4 sec. intervals, followed by simultan simultaneous eous disconnection off all banks at 5 sec. As expected and shows in Fig. 7, each time tim e a filter bank is put on-line, it provides the AC network reactive power, i.e. raising the AC voltage amplitude and DC-link controllers reacts by raising the firing angle to keep the DC-link current at nominal level. The SSN method implements 'Inlined Thyristor Valve Compensation' algorithm (ITVC). The ITVC method is used to maintain the simulation accuracy even when the thyristor switching occurs between time-steps. Fig. 7 shows the effect of the ITVC algorithm: it decreases by 50% the jitter caused by the sampling of thyristors gate signal by the fixed-time step simulation time frame. It must be understood that this simulation imprecision, with ITVC algorithm is turned off, is caused by fixed step sampling and would be similar in any fixed step software like EMTP, PLECS or PSCAD. The figure also shows a very regular current pattern with ITVC in action. ARTEMIS User’s Guide

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Real-time simulation speed

Using ARTEMiS

3. 3.2.2 2.2 Rea Reall-tim time e simulati simulation on speed The bipolar HVDC link with switched filters filt ers can be simulated at a time step of 49 µs µ s on 6 cores of a 3.3 GHz Xeon V2 (3 cores per station). Higher speed can be expected if Xeon V3 are used.

3. 3.3 3

ARTEMi ARTEMiS S modeli modeling ng of transf transform ormer er satura saturatio tion n

3.3.1 3.3. 1 SPS mo modelin deling g of transf transformer ormer satura saturation tion The native saturable transformer model of SPS has no linear part in its magnetization branch. The magnetization branch is instead modeled entirely by a current injection. The current injection is computed from a table of the phi=f(i), with the flux being computed from the integral integ ral of voltage across magnetization branch.

Figure 8:Saturable transformer model in SPS and ARTEMiS In the SPS model, the non-linear Lsat component of the transformer is completely modeled by a current injection computed from the phi=f(i) characteristics

Figure 9:piecewise segment flux-current characteristic of the magnetization branch of a saturable transformer In SPS in particular, one can specify a residual flux only when the segment 1-2 has infinite slope as mentioned in the SPS documentation. 3. 3.3.2 3.2 ART ARTEMi EMiS S transf transforme ormer r model In ARTEMiS, a slightly different approach is used that modify the current injection curves by including the linear part of the magnetization curve inside the state space equations describing the system. The modification are as follow:

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Advantages of the approach

1-The first segment of the phi=f(i) characteristic is included in the linear part of the state-space st ate-space system described by ABCD matrices. 2-This linear part is extract from the original phi=f(i) characteristic. 3-The flux across the branch is computed from its linear part phi_linear=L_linear*I_linear 4-A current injection in parallel to the linear inductive branch is used to model the saturation.

Figure 10:Modified injection characteristic in ARTEMiS caused by the inclusion of the first segment in the linear part of the state-space system The method can be viewed as follow: in normal mode (non-saturated), the magnetization branch is part of the ABCD state-space system and the branch flux phi is obviously equal to L*i. When saturation occurs, it is like connecting other inductance in parallel to the first one. The important thing thi ng to notice is that the voltage across these two inductance is the same, so is the total flux that would be obtain by integration of the voltage across the branch and therefore this flux can be derived from the linear branch and used for current injection. The differences with SPS native model are the following: 1-The ARTEMiS saturable transformer model requires a non-infinite 1 segment slope to so a state can exist in the ABCD matrices. If not, ARTEMiS will add a very large one. 2-Residual flux flux can will be specified even the first segment do not infinite The implication of this is that the move from theifstart of the simulation simul ation buthas in aanvery slowslope. manne manner r because of the very high inductance. The model is therefore adapted to transformer re-energization tests. 3.3.3 3.3. 3 Adv Advantag antages es of the approach approach The main advantage of the ARTEMiS model is that is can provided accurate fixed-step simulation results without algebraic loops. In SPS, this algebraic loop is caused by the usage of a discrete-integrator (trapezoidal method) in the transformer itself. In ARTEMiS, this flux is computed in the linear part of the state-space system. SPS provides ways to break this algebraic loop but this can degrade accuracy. See the demo section for more details.

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Demos

Using ARTEMiS

3.3.4 Demo emos ARTEMiS provides demos linked to the saturable transformer model. artemis_power_ctsat.mdl :

single phase transformer energization test.

The demo shows an increased accuracy ac curacy of ARTEMiS over SPS at a time step of 50µs. The flux response of SPS is wrong at 50µs. The ARTEMiS response at 50 µs matches correctly the SPS response at 1 µs.

Figure 11:SPS response for artemis_power_ctstat.mdl at 50µs

Figure 12:SPS response at 1 µs matching the ARTEMiS response at 50 µs

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Initial flux setting

3. 3.3.5 3.5 In Init itial ial flux flux se setti tting ng Since ARTEMiS 5.1.4, the initial flux of the transformer can be specified in the transformer mask. In difference with the SPS method, ARTEMiS magnetisation branch is part of the ABCD state-space equation of the simulated system and initial states are set by the state variables. However, some SPS transformer model don’t allow the initialisation of magnetization flux. The following table lists what type of transformer support initial flux setting thought the transformer mask. When not supported, the user must set manually the magnetization inductance initial current in the POWERGUI panel of SPS.

Table 2: List of SimPowerSystems transformer model (R2008 A-B) Model

Direct Mask initial flux setting support

Saturable transformer

no

Multi-winding transformer

no

Zigzag Phase-Shifting Transformer 

no

Three-Phase Transformer (Three Windings)

yes

Three-Phase Transformer (Two Windings)

yes

step simulation of 3 phase saturable The ARTEMiS demo untitled: Fixed-time transformer without algebraic loop explains how to compute and set manually the initial flux of a transformer through the Initial States panel of the SPS POWERGUI.

3.3.6 3.3. 6 Limi Limitati tations ons of the approach approach When testing case with inrush current caused by residual flux, the approch can cause a small flux decay du to the non-inifinite linear part of the transformer core inductance.

3.4

Reference s [1] C. Dufour, S. Alma, S. Cuni, G. Scrosati, G. Valvo, G. Sapienza, "Renewable integration integ ration and protection studies on a 750-node distribution grid using a real-time simulator and a delay-free parallel solver", CIRED-2015, Lyon, France, June 15-18, 2015 [2] C. Dufour, L.-A. Grégoire, J. Bélanger, "Solvers for Real-Time Simulation of Bipolar Thyristor-Based HVDC and 180-cell HVDC Modular Multilevel Converter for System Interconnection and Distributed Energy Integration", 2011, CIGRÉ conference proceedings, Recife, Brazil, April 3-8, 2011.

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References

Using ARTEMiS

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State-Space Space (SSN) solver tutorial

 

4

This section explains how to use the SSN solver of ARTEMiS in ty typical pical applications. Examples of SSN nodes selection are given and some advanced ussage question are answered at the end.

4.1

Introduction The State-Space Nodal (SSN) method can be considered as a nodal method. The main difference is how the nodal branch or groups are made. In SSN, the user selects the way the groups are made. These groups are computed by a state-space method meth od while the interface between the groups is solved by a nodal method. By making large groups for example, the number of equivalent nodes to be solved by the nodal method can be limited. At the same time, by choosing wisely the groups, the number of switches per groups can be limited and full-precalculation can be made. See [1] for a detailed explanation on the SSN theory. Within the Simulink/SimPowerSystems environment, the SSN presents some challenges for the normal user to achieve real-time simulation. The main challenge is to correctly designed the SSN model using SSN Nodal Interface Blocks to make groups of reasonable state and number of switches and to also limit the number of total nodal nodes connecting these groups. The SSN also includes powerful features like: 1- Inlined interpolation of thyristor firing 2- Inlined Interpolation of voltage inverter in a manner similar to the RTeDRIVE models (TSB). 3- Real-time Impulse event detection. 4- Iterative method for MOV and switches. These will be explained through a series of example.

4.2

The SSN library The ARTEMiS library contains the nodal interface blocks along with some other utility blocks used in the SSN algorithm.

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The SSN library

State-Space Space (SSN) solver tutorial

Figure 12:NIB is the SSN library The blocks seen in Figure 1 are called 'SSN nodal interface blocks' or simply NIB. They represent the nodes of the nodal SSN. These SSN nodes n odes connect state-space described groups that must respect some method causalityused laws.inFor example, in state-space approach, one cannot connect a current source in series with an inductance. Similarly, the SSN nodal interface blocks must respects the same laws. To achieve this, the block port has a type I (for ccurrent urrent source) and V (for voltage source) and this type must be chosen to respect causality laws. Taking the 1-phase SSN nodal interface block as an example: the block has an I-type I- type port and V-type port as selected on its dialog box below .

Fig 1a Dialog box of the 3-ph SSN nodal interface block

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Usage of the SSN Nodal Interface Block in a model

4. 4.3 3

Usage Usage of the SSN Nodal Nodal Inte Interf rface ace Block Block in a mode modell  Fig. 2 shows the usage u sage of SSN blocks in a SPS models. The model used for this test te st is named 'ArtemisSSN_simple_switched_case.mdl'.

Figure 13:Example of nodal interface blocks Some basic rules are to be followed when using the SSN blocks. 1-SSN-nodal interface block (NIB) connected to inductive groups must have V-type port (view it has a Voltage source connected to an inductive element. V-type NIB contains a virtual voltage source) 2-SSN-nodal interface block (NIB) connected to capacitive groups must have I-type I- type port (view it has a current source connected to an capacitive element, I-type NIB contains a virtual current source) 3-The Main ARTEMiS Guide must have 'Enabled State-Space Nodal (SSN) method' set. Note that the solver used for the SSN method is trapezoidal like in EMTP-type software. The ARTEMiS 'Discretization method' item only apply to part of the network that do not use the SSN solver, like the inverter side of the HVDC model of the next section.

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Disabling SSN (for validation purposes in ’pure’ SPS)

State-Space Space (SSN) solver tutorial

Figure 14:Fig. 3SSN and ARTEMiS block options. 4.3.1 Disablin Disabling g SSN (for validation validation purposes in ’pu ’pure’ re’ SPS SPS) ) For comparison purposes, if you disable the 'Enable State-Space Nodal method (SSN)' checkbox, the model will run using standard ARTEMiS method with the SNN nodal interface blocks still inside the model. This is because the SSN nodal interface blocks are simply null current/voltage sources that do not change the simulation when the SSN method is turned off.

4. 4.4 4

1st 1st Real Real-l -lif ife e case case:: 12-p 12-pul ulse se HVD HVDC C sys syste tem m The SSN method will now be shown on a 12-pulse HVDC system. The HVDC case is interesting because it offers many possibilities as how make the groups. The HVDC system is also interesting because it contains many switches: 2 6-pulse 6 -pulse valve groups and possibly 20 or more switched filter banks on ACbus and DC-bus. The SSN method was designed in mind to cope with this type of real-time simulation challenge.

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1st example of SSN groups

Figure 15:AD_GRID04 12-pulse HVDC model. 4. 4.4.1 4.1 1st exam exampl ple e of SSN group groups s The most basic SSN separation we can make to use the t he SSN method is to use the filter bank connection point a SSN Consequently, we need to understand the causal causality ity of the groups we are going to defineasfrom thisnode. (3-phase) node.

Figure 16:Interface type from the chosen SSN node One can make the following observations: the transformer has an inductive impedance as seen from the SSN node. The source also has an inductive type impedance. Finally, the filter group has a capacitive impedance as seen from the SSN node because one of its component is a simple capacitor. The SSN method was applied here only to the rectifier side of the HVDC system. The inverter side is still simulated by needless standard to state-space method of SPS/ARTEMiS. The SSN could be applied also to the inverter side say.

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Adding groups

State-Space Space (SSN) solver tutorial

Using the filter connection point as a node, we end up u p with 3 SSN groups, described on the figure below.

Figure 17:Resulting groups with 3 SSN nodes. 4. 4.4. 4.2 2 Addi Adding ng gro group ups s In this example, we increase the number of groups by separating the transformer from the thyristors valves, producing an additional group and 9 nodes in total. From a real-time simulation perspective, the addition of 6 nodes will slow down the simulation but separating the transformer from the valves will produce much smaller group equations. Especially, the states sta tes of the transformer will no longer have to be precomputed 2^12 times with the valves. Also, because the thyristors have RC snubber attached to them, they are better considered as a capacitive group requiring an I-type SSN interface.

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Separating the valves groups

Figure 18:HVDC system with 4 groups and 9 nodes 4.4.3 4.4. 3 Sepa Separat rating ing the valves valves group groups s Making the two 6-pulse valves groups as 2 SSN groups has the advantage that memory requirements are minimize because there are only 2^6=64 permutations per group instead of 2^12=4096 for one 12-valve group. It may even allow the simulation to run entirely inside the L1 or L2 cache of microprocessors, so it may speed up the simulation even if we now have 11 SSN nodes.

Figure 19:HVDC system with 6 groups and 11 nodes

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Adding switched filter banks

State-Space Space (SSN) solver tutorial

4.4.4 4.4. 4 Add Adding ing swit switched ched filt filter er banks banks

Figure 20:HVDC system with switched capacitor banks. This last example is interesting because we added two switched filter banks ba nks to the AC-bus of the model without adding any nodes! This is caused by the facts that all the filter SSN groups (including the breakers) are connected to existing SSN node in the circuit.

4. 4.5 5

2nd cas case: e: 3-lev 3-level el NCP NCP invert inverter er and and SSN SSN Real-T Real-Time ime Impu Impulse lse Even Events ts The SSN algorithm is able to detect Impulse Events during simulation. By Impulse Event, we mean the instantaneous  opening or closing of a switch (most often a diode) following the open or closing of another switch in the system. This happens for example in a buck converter in which the free-wheeling diode turn-on instantaneously when the forced switch (IGBT or MOSFET) opens. In real-time simulation it happens that this type of event is difficult to simulate accurately. The reason is that switch natural conduction conditions are usually evaluated at the beginning of a time step, so if a forced switch change state, its effect is can only be detected on the next time step. In ARTEMiS and ARTEMiS-SSN algorithm, we use the fact that the state of a system cannot change instantaneously when a switch changes of conduction state. We can therefore re-evaluate the switch voltage after any forced switching by simply re-evaluating the outputs of state equations. In the ARTEMiS-SSN algorithm, some caution is to be taken for the Impulse Event Detection to work correctly because this Impulse Event verification is made on a group basis.

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2nd case: 3-level NCP inverter and SSN Real-Time Impulse Events

Figure 21:Three-level NCP inverter system in SSN

The figure a 3-level Neutral clamped inverter drive system SSN.above Each arm is depicts c omposed composed of 4 IGBT/Diode pairs plus 2 clamping diodes. d iodes.in SimPowerSystems and The real-time simulation of this model is really challenging because it is composed of 30 coupled switches. In the solution above, since SPS has a switch model for the IGBT/Diode pairs, the internal number of switches reduce to 18, which make real-time simulation still impractical because of the high number of matrix permutation to compute (2^18). The solution in SSN is to put each arm in a separate group of 10 switches (6 internal SPS switches, considering the IGBT/Diode pairs as one device).

Figure 22:SSN group separation for real time simulation

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Impulse Events in SSN

State-Space Space (SSN) solver tutorial

The resulting model has 5 groups and 6 nodes. The inverter was separated at the arm level to obtain 6 SPS switches per group, which can be precomputed and run in real-time after. Note that the NIB blocks ARE the nodes in SSN.

Key aspect of the separation with Impulse Events: the NIB that connects to the output of the inverters (A connector) are of I-type to provide the t he group with an image of the ’continuity variable’ during impulse events, that are the transformer tr ansformer input currents. This so-called ’continuity variable’ is the model variable that will not force the instantaneous switching in the inverter. In the above example model, suppose that all IGBT are turned-off suddenly. The transformer input current will surely drop but without discontinuities. It’s this current that will force some anti-parallel diode in the inverter to turn-on momentarily. Such methods was actually used by ABB to simulate such 3-level NPC converters [2]. 4. 4.5.1 5.1 Imp Impuls ulse e Eve Events nts iin n SSN SSN This last point is important to understand. It is caused by the fact that the SSN algorithm does not make multiple iteration of equation to verify Impulse Events like instantaneous diode turn-on effects. It only re-evaluate the Outputs of a group for natural switch thr threshold eshold crossing each time a forced switch is activated. This can be done on the basis that the states sta tes of a systems cannot change instantaneously on a switching action. In general, a switched device using u sing diodes as free-wheeling diode (for example) will have a branch that force the continuity of the current at switching time. This element must either be grouped with the switching elements (best case) or the NIB must have a I-type interface to give an image of this element in the groups for the SSN Impulse Event Detection to work. wor k. In the example of the 3-level NCP inverter, this element is the transformer primary leakage inductance.

4. 4.6 6

3rd 3rd ca case: se: Inlin Inlined ed Thyr Thyrist istor or Valv Valve e Compen Compensat sation ion in in SSN SSN The Inlined Thyristor Valve Compensation (ITVC) method is a real-time method to compensate the sampling effect of thyristor by the fixed step time frame. Simply Sim ply explained, each time a thyristor firing pulse is generated, it must ’wait’ the next time step to be taken into account inside the simulation. If the pulse arrive just before the fixed step frame, the error is minimal but when iitt occurs just after, then the error is bigger because the wait last almost a full time step. Because the firing pulse are not synchronized on the simulation time step, it usually results in a low-frequency jitter on important system variable, often confused with controller instability. The ITVC methods is designed to compensate this effect, in off-line and HIL simulation. It is so efficient that it is always active in the ARTEMiS (State-Space and SSN). We will explain the ITVC method on the HVDC example with 6 groups, 11 nodes SSN separation.

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3rd case: Inlined Thyristor Valve Compensation in SSN

Figure 23:HVDC system with ITVC (RT-LAB top level separation in 3 CPUs) In the model, a Firing Pulse Unit was designed with RT-EVENTS, a replica of the Simulink FPU with RTE blocks.

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3rd case: Inlined Thyristor Valve Compensation in SSN

State-Space Space (SSN) solver tutorial

Figure 24:RT-EVENTS based Firing Pulse Unit The RT-EVENTS blockset enables to keep in memory the in-step events of this type of firing pulse unit with multiple comparators. Since release 6 of ARTEMiS, the way wa y RT-EVENTS connects to ARTEMiS solvers has been simplified. The ARTEMiS solver now requires only a double value between zero and 1 to activate and compensate thyristors switches. If the value equal only exactly 1 and 0 (as in regular SPS), the simulation is not compensated. But if the value is between 0 and 1, the value is taken as the time ratio of the gate event within the time step. Ex: a value of 0.6 would mean that the event occurred at 60% after the beginning of the time step. Now, in common model a simple ’RTE converter’ block will do this job as in the following figure. If and only if the RT-EVENTS compensation item of the block is set to ’Enabled’, the HVDC simulation will also be compensated.

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3rd case: Inlined Thyristor Valve Compensation in SSN

Figure 25:Interface of RT-EVENTS and ARTEMiS (V6 and later) The ITVC algorithm action is very impressive considering it overall negligible computational cost. The following figure shows the DC current of the HVDC during energization.

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Static Var Compensator

State-Space Space (SSN) solver tutorial

Figure 26:HVDC energization If we now look closer at the Idc current and rectifier firing angle, the effect of the compensation is quite obvious.

Figure 27:Zoom on DC-link current and firing angles at of the rectifier side On the above figure, we observe a very characteristic low-frequency jitter on both DC-link current and firing angle, quantities linked by the HVDC control. When the ITVC is OFF, there is a approximate 10 Hz jitter on both values that is not present with ITVC IT VC in function. This jitter is typical of o f fixed-step solvers and would be present in all fixed-step based simulation algorithms (EMTP, PLECS, SPS, PSIM, etc...).

4.7

Sta tattic Va Var Co Compe mpensat nsator or A 300-Mvar Static Var Compensator (SVC) regulates voltage on a 6000-MVA 735-kV system. The SVC consists of a 735kV/16-kV 333-MVA coupling transformer, one 109-Mvar thyristor-controlled reactor bank (TCR) and three 94-Mvar thyristor-switched capacitor banks (TSC1 TSC2 TSC3) connected on the secondary side of the transformer. Switching the TSCs in and out allows a discrete variation of the secondary reactive power from zero to 282 Mvar capacitive (at 16 kV) by steps of 94 Mvar, whereas phase control of the TCR allows a continuous variation from zero to 109 Mvar inductive. Taking into account the leakage reactance of the transformer (15%), the SVC equivalent susceptance seen from the primary side can be varied continuously from -1.04 pu/100 MVA (fully inductive) to +3.23 pu/100 Mvar (fully capacitive). The SVC controller monitors the primary voltage and sends appropriate pulses to the 24 thyristors thyris tors (6 thyristors per three-phase bank) in order to obtain the susceptance required by the voltage regulator [1]. Each three-phase bank is connected in delta so that, during normal balanced operation, the zero-sequence tripple harmonics (3rd, 9th...) remain trapped inside the delta, thus reducing harmonic injection into the power system. The power system is represented by an inductive equivalent (6000 MVA short circuit level) and a 200-MW load. The internal voltage of the equivalent can be varied by means of programmable source in order to observe the SVC dynamic response to system voltage sags.

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Static Var Compensator

Figure 28:SVC compensated electric network With the SSN solver, the natural way to decouple the system is to use the common connection point of the TCR and the 3 TSCs,terms. resulting 4 groups switches each nodal matrix size 3 only, thuswhile verythe efficient in computational The in TCS groups of are6 interfaced withand I-type SSN NodalofInterface Blocks TCR and network group is interfaced with a V-type V -type block (hint: it is clearly inductive so it must be driven by a Volta Voltage ge source for causality reasons ->V-type). With the ITVC compensation of thyristor firing, very accurate simulation s imulation ca be achieved. The above figure shows sh ows the simulation results for a slow scan of the TCR bank firing firin g angle. The figure below shows a typical effect of thyristor-based system in fixed step simulation. In that case, a kind of quantization qua ntization effect occurs on the system output reactive power, as it shows some discrete step effects. With the ITVC compensation of ARTEMiS and SSN, the reactive output of the systems is smooth s mooth with regards to the fir firing ing angle.

Figure 29:Effect of firing compensation in ARTEMiS

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Inlined Voltage Inverter Compensation (IVIC)

State-Space Space (SSN) solver tutorial

4. 4.8 8

Inlin Inlined ed Voltag Voltage e Inver Inverter ter Compen Compensa satio tion n (IVIC (IVIC) ) In ARTEMiS v7, 2-level inverter (2LI) can be compensated ’inline’ in SSN, which results in compensated simulation similar to the well-known TSB of OPAL-RT but without the internal delays associated with TSB. See the online demo ssn_itsb_2levelvsc_hvdclink.mdl  for more details. Note that IVIC does not work for 3-level NPC inverters (3LNPCI). However, there is a demo called ThreeLevelInverter_IVIC_RTE2.mdl  that use IVIC method in a surrogate circuit of the 3LNPCI.

4.9

SSN SSN par para allel llel (w (wit itho hout ut del dela ays) ys) Starting with version 6.3 of ARTEMiS, the SSN solver is now capable of being executed on multiple processors. In most cases, this will significantly improve the performance of the solver. Note that this mode requires RT-Lab 10.3 or later. The parallel mode is activated only if multiple cores are allocated for a specific subsystem. To allocate additional cores, use the advanced view of the assignation page:

Figure 30:Subsystem settings page Select the “...” in the “Cores” column to activate the core selection dialog. There, select the t he number of cores and optionally, select specific cores. Unspecified cores are allocated automatically automat ically by the system using the assignati assignation on rules described in the RT-Lab User Guide.

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Iterative methods in SSN

Figure 31:Subsystem Core Selection Dialog When multiple cores are allocated for a given subsystem, SSN SS N groups are automatically divided among available avail able cores so that the total computation time is minimized. Thus, the number of groups and their relative size will have a direct impact on the possible performance improvements for the parallel mode. In some rare cases, the situation could be worse or without significative gains. In any cases, some experimentation is often needed to find the optimal configuration.

4. 4.10 10 Itera Iterative tive method methods s in in SSN SSN This section explains the new iteration feature of ARTEMiS (available with version 7 and later). With this option, it is now possible to run real-time simulation of Surge Arresters (often called Metal Oxide Varistor or MOV) and common switches with iterations to ensure the global accuracy of the simulation. These iterations are different than the ones that SSN makes inside each group. The new iteration method m ethod are global, meaning that a change of segment or operating point in one SSN group will force the global check for ite iteration ration among all iterative groups. The use of this new iteration iterat ion feature is determined, for MOV, MO V, by the use of a specific MOV block b lock in the ARTEMiS Library and, for switches, of a specific NIB connection. We call these simulation methods iMOV and iSWITCH respectively. 4.10.1iMOV To use iMOV in SSN, the user must use the special iMOV block provided in the ARTEMiS->SSN->Iterative Models library. The on-line demo SSN_iMOV_power_surgnetwork.mdl is used next to illustrate this in more details.

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iSWITCH

State-Space Space (SSN) solver tutorial

Figure 32:iMOV online demo SSN_iMOV_power_surgnetwork Basically, the iMOV model must be connected directly to X-type NIB anywhere in the model. Provided that the Maximum number to iteration (iMOV and iSWITCH) parameter of the ARTEMiS GUIde is set high enough (typical value of 5 is ok for mots mot s cases), the iterative solution of SSN will be used to solve this network. netw ork. The MATLAB prompt should also highlight that iMOV are used in the simulation. Third-Party Rule block detected: SSN_iMOV_power_surgnetwork/ARTEMiS Guide1 ARTEMiS-SSN: approx. memory required: 0.017752 Mb (including nodal matrix) SSN group info Group 1 : 12 states, 9 inputs, 9 outputs, 2 switches. Group 2 : 0 states, 4 inputs, 2 outputs, 0 switches. (SSN Iterative MOV) Group 3 : 0 states, 3 inputs, 2 outputs, 0 switches. (SSN Iterative MOV)

4.10.2iSWITCH In the case of iSWITCH, the standard SPS switches are used. The connection method determines if the iSWITCH method is used by SSN. This is illustrated in the next figure with the online demo SSN_iSWITCH_6pulse_rectifier.mdl.

Figure 33:iSWITCH online demo SSN_iSWITCH_6pulse_rectifier For an iSWITCH model and method to be detected by SSN, the switch must be: 1- alone in its SSN group 2- interfaced with V-type NIB 3- have no internal snubber capacitor, nor inductance, i.e. the switch must not contain any L-C state. 42

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Miscellaneous solver options

This is the case for the SSN_iSWITCH_6pulse_rectifier.mdl demo as shown in the figure below.

Figure 34:iSWITCH connection and parameters requirements When an iSWITCH is detected by SSN, the MATLAB prompt should highlight it correspondingly like the following: SSN group info Group 1 : 2 states, 2 inputs, 4 outputs, 0 switches. Group 2 : 9 states, 6 inputs, 9 outputs, 0 switches. Group 3 : 0 states, 4 inputs, 3 outputs, 1 switches. (SSN Iterative switch group) Group 4 : 0 states, 4 inputs, 3 outputs, 1 switches. (SSN Iterative switch group) Group 5 : 0 states, 4 inputs, 3 outputs, 1 switches. (SSN Iterative switch group) Group 6 : 0 states, 4 inputs, 3 outputs, 1 switches. (SSN Iterative switch group) Group 7 : 0 states, 4 inputs, 3 outputs, 1 switches. (SSN Iterative switch group) Group 8 : 0 states, 4 inputs, 3 outputs, 1 switches. (SSN Iterative switch group)

4. 4.11 11 Miscel Miscellan laneou eous s solver solver option options s The SSN solver has been improved since ARTEMiS version 7.x with the advent of iterative models and methods. The modifications are related to the node order within the nodal matrix. Nodes connected to iterative models are ordered last, more to the bottom/right of the admittance matrix. This enables an efficient partial refactorization of the admittance matrix during iterations. Nodes connected to non-iterative switched SSN groups are ordered  just before these. At the top/left of the admittance admittance matrix are then the nodes of non-switched SSN groups. Since these groups have constant discrete admittance, admittan ce, some form of pre-factorization can be mad madee on these nodes of the admittance matrix.

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Explanation of the reason of improved speed with SSN

State-Space Space (SSN) solver tutorial

The previous SSN solver came with an optional routine r outine to re-order the nodes in a tri-diagonal way. This so solver lver is normally disabled in ARTEMiS v7+. In case that this old solver is needed, the following variable must be declared in the MATLAB workspace during simulation and compilation. op_ssn_use_lu_tridiagonal_method=1;

The value 1 is not important, only the existence of the variable is checked. Note that the variable is now in lowercase letter.

4.12 4.1 2 Explana Explanation tion of the reason reason of improv improved ed speed speed with with SSN This section objective is to explain the fundamental reasons behind SSN speed improvement over regular statespace methods, in both real-time and non-real-time applications. The reason is simple: SSN make less multiply-addition operation for the same network.

S tatesp ac em eth o dw ith x s tates 

B rk0

xn+1= A k

xn +

S S Nm e th o dw ith2 g ro u p so f  x /2 s tatesea ch



B rk0

B rk1

B k

m a tri ix xse ts un+1 k= 1.. .. .6 4

 A 1m

xn+1=

 A 2 n

         o         n _            U



B rk1

B 1m xn  +

I_n on+1= Y 3 ,3

B 2n

u n + 1

m atrixs ets m =1 ...8 m =1 ...8

 

u_ no n + 1

Figure 35:State-Space vs. SSN comparison In Fig. 35, we compare SSN and state-space (SS) for a system with x states and y inputs. In SS there is therefore: x*x+x*y mult-add operations (operations in SS method) to be done at each time step. In the SSN method, two SSN groups separated by 3 nodal connection points (separating the complete network in two equal part let say) are defined. In this case, the algorithm would imply 2 state-space system iterations with x/2 state variables each, plus a 3x3 nodal matrix inversion. This results in: (x*x+x*y)/2 mult-add operations (operations in SSN method) plus 3x3 matrix factorization. If the number of SSN nodes is small compared to x, then SSN cut approximately by half the total number of operations required by the state-space iterations. More generally, if the Q SSN groups are balanced balanc ed in size, the state-space part of SSN will be Q times time s faster than pure state-space. Then the challenge is to keep the admittance matrix small. Full LU factorization of an admittance matrix is O(r3) operation , where r is the rank or row size of the admittance matrix. Since ARTEMiS v7.0, the SSN SS N LU factorization routine is made according to the 1969 1 969 Dommel paper, in whi which ch only modified row/column of the admittance matrix are refactorized. Therefore, the real criteria in SSN is to keep the ’switched nodes’ of the admittance matrix small. For example, applications in voltage control with few switches and many controlled PQ injections can have large admittance matrix without noticeable impact of the real-time computational speed. This is because unswitched row/column of the admittance matrix are ar e pre-factorized before going into the real-time loop.

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SSN Switch management in Real-Time applications

4.12.1 4.12 .1 SSN Switch Switch mana managemen gementt in Real-T Real-Time ime app applica lication tions s Fig. 35 shows that the SSN method makes the complete state-space equations block-diagonal by virtue of the decoupling induced by the approach. The decoupling is partial, partial , however, as the nodal solution links all parts of the network equations. Using a single CPU approach, the computational gain can approach a factor of 2 if the statespace iteration becomes more important, in comparison to the same 3x3 matrix inversion. Furthermore, the problem of memory storage of switch permutations is solved here: each group contains contain s only the pre-calculated set of matrices for the switch contained within the groups. Taking again the specific example of Fig. 35, which is composed two three-phase full pre-calculation of circuit modes in the standard state-space approach wouldofrequire the storagebreakers, of  2^6=64 permutations of states-space equations of size x,u In the SSN approach, two sets of 2^3=8 system matrices need to be stored (one for each group),that is: 2*(2^3)=16 permutations of states-space equations of size x/2,u/2 plus 3x3 admittance matrix. thus drastically reducing memory requirements. As the SSN groups and switches are determined by the user, he therefore has full control on the memory requirements. Separation of switches is always possible because they t hey can be modeled as a separate group in the proposed method. In that case, only the D matrix subsystem is non-empty, and the group admittance admit tance is included directly in the global admittance matrix in way similar to standard nodal method.

4.13 4.1 3 Useful Useful tricks tricks and pract practical ical issues issues with with SSN SSN is build on top of SimPowerSystems, which is a closed code. Therefore, there ther e exists some limitations in using SSN that are explained here. Other limitations come from the fact that SSN is a nodal method. 4. 4.13. 13.1 1

Which Which SSN SSN solv solver er shoul should d I use? use?

On the SSN solver pane, many solvers are available. It may happen that one specific solver works better than others without clear reasons. (The same is true about regular Simulink solvers by the way).This is explained briefly in [4]. Trapezoidal is the same than EMTP but without Backward Euler steps at switch change. Beware of numerical oscillation! Backward Euler: Backward Euler is probably the most stable solver of all, actually an L-stable one. The Ba Backward ckward Euler method is known to damp dam p too much some components of simulation however. how ever. art5 is the order 5 L-stable Padé approximant to the matrix exponential. In this solver, the input term is considered to vary linearly between time steps. art5 with Backward Euler nodal interface: this is the same as art5 for the discrete A matrix. But the discrete B matrix is different because the input term is considered fully implicit (u[n+1] only, no u[n] term) during integration. This solution is often more stable numerically than art5. art5 with balanced zero hold nodal interface: his is the same as art5 for the discrete A matrix. But in this case the input term is considered as constant and taking 2 values during integration (half the step at u[n] and the next half v[n+1]). The art5 variations are provided in case the art5 method does not work well.

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Avoid extreme values of parameters

State-Space Space (SSN) solver tutorial

4.13.2 4.13 .2

Avoid Avoid extreme extreme values values of param parameters eters

Use realistic Ron breaker resistance of 1e-4 Ohms, not 1e-12. Extreme values may make the nodal admittance matrix badly conditioned. Also avoid unrealistically high transformer core values. 4. 4.13. 13.3 3 Curren Currentt sensor sensors s direct direction ion error error When using current measurements, it can happen that SPS tries to takes this measurement in a branch that is located in a different SSN group. The current implementation of SPS current measurements blocks ’looks’ for branches on the ’+’ side of the sensor. s ensor. When this happens, a clear error message will appear and will explain to you that you must invert the current measurement ports and add a Simulink gain of -1 to the output of the block, giving the exact same value of current reading. 4.13.4 4.13 .4 How to choose choose V-type, V-type, I I-typ -type e and X X-typ -type e of NI NIB? B? X-type is simple: it’s only used for custom SSN S SN groups and frequency dependant line m models odels [3]. V-type and I-type must be chosen to avoid a void illegal connection of current source and vvoltage oltage source in the determination of state-space equations. This is because of the underlying state-space formulation used to determine SSN groups equations. In many case, but V-type and I-type are valid (they are if they do not trigger SPS connectivity errors). But typically, V-type NIB, which contains a virtual voltage source, is better when connected to inductive inputs of SSN groups and I-Type NIB, which contains a virtual current source, is better when w hen connected to a capacitive input of groups, like a shunt capacitor. 4.13.5 4.13 .5 Why can’t can’t I us use e SPS Multi Multimeter meter blocks blocks in SSN SSN? ? The reason is that in the current implementations implementatio ns of SPS, the presence of SPS Multimeter block force the merging of all the circuits in the diagram even if they are independent. SSN cannot currently deal with this situation. 4.13.6 4.13 .6 ’Illegal ’Illegal current current sou source rce in series’ series’ erro error r message message when usi using ng I-type I-type NIB. The I-Type NIB block contains a virtual current source, which is there for SSN to determine SSN groups. This source is visible by SPS and it sometimes create connectivity error by which whic h this current source is put in series with another current source or an inductor. (Physically, current sources are not supposed to be connected in series with inductor, it’s like trying to force a system state to a known value) In ARTEMiS v7, I-type NIB comes with a shunt resistor of high value (default 1e9 Ohms), that do not interfere wit h the simulation accuracy and avoid this connectivity error. 4. 4.13. 13.7 7 PC Memor Memory y llimi imitat tatio ion n in SSN SSN When compiling an ARTEMiS model, lack of memory may occur, especially when the size of the SSN group matrices ABDC are big and the number of switches is high. ARTEMiS tried to calculate all matrix permutation in all SSN groups of the electrical network. For example, for a very small network (only 10 states, 12 inputs and 11 outputs), outp uts), the state-space matrices would be like: x' = Ax+Bu

(A is [10x10], B is [10x12], x is [10x1], x' is [10x1], u is [12,1])

Y = Cx+Du

(C is [11x10], D is [11x12])

And the number of switches is 15, the size of memory required is: 46

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Optimizing SSN groups for best real-time performance

( (10*10 + 10 + 10*12 + 12 + 10) + (11*10 + 10 + 11*12 + 12 + 11) ) * 2^15 * 8 = 138MB Now the same calculation for a network with 40 states, 40 inputs and 40 outputs is 1.76GB. In SSN, the number of switch per SSN group is limited to 15 but should ideally be less than 10. It is ALWAYS POSSIBLE in SSN to limit the number of switch per group to a certain number, just by putting switches in different groups. The MATLAB prompt gives an indication of the memory memor y used by the SSN matrices, including the nodal admittance matrix. As a general guideline, this memory m emory usage should be kept low whenever possible. Value under 100 Mb are generally ok on Xeon V2 or V3 computers. ..... Y has 318 zeros out of 676 elements

ARTEMiS-SSN: approx. memory required: 71.4192 Mb (including nodal matrix) SSN group info Group 1 : 10 states, 24 inputs, 24 outputs, 12 switches. Group 2 : 14 states, 21 inputs, 24 outputs, 9 switches. Group 3 : 3 states, 9 inputs, 10 outputs, 6 switches. Group 4 : 0 states, 18 inputs, 20 outputs, 10 switches. Group 5 : 0 states, 15 inputs, 15 outputs, 6 switches. Group 6 : 12 states, 28 inputs, 28 outputs, 10 switches. SSN nodal matrix is of rank 26 (47.0414 % of zeros) ARTEMiS network information: the network contains 127 general EMTP equivalent nodes (RLC branches, sources, etc..)

..... 4.13.8 4.13 .8 Optimizi Optimizing ng SSN groups groups for for best real-tim real-time e perfo performan rmance ce When looking at an electric network to be simulated with SSN, two main criteria should be followed: 1- Try using nodes that will provide the higher ’SSN group number’/’number of SSN nodes’ ratio. For example, choosing an SSN node at the feeder point of star-connected distribution grid (Figure 36) will create 5 SSN groups while using a single (3-phase)SSN node. This is an excellent choice. After this, the grey point are the next best location of SSN nodes because they split each existing SSN group into 2. The switched filter bank node of the bipolar b ipolar HVDC example is anot another her good example of excellent SSN n node ode location because it creates many SSN groups with a single SSN node. 2- Try to correctly balance the size siz e of the SSN group. This is better when using the parallel SSN option in real-time. To help localize a specific SSN group, one can attached an ’SSN Group tag’ to different groups in the model, like shown in Fig.37. The MATLAB prompt listing will then refer to the different tag used: ARTEMiS-SSN: approx. memory required: 0.59939 Mb (including nodal matrix) SSN group info Group 1 : 3 states, 7 inputs, 8 outputs, 2 switches. Group 2 : 21 states, 9 inputs, 6 outputs, outputs, 3 switches. TAG: capa Group 3 : 12 states, 16 inputs, 18 outputs, 6 switches. TAG: xfo Group 4 : 6 states, 7 inputs, 4 outputs, 1 switches. TAG: rect SSN nodal matrix is of rank 4 (0 % of zeros)

ARTEMiS network information: the network contains 43 general EMTP equivalent nodes (RLC branches, sources....

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State-Space Space (SSN) solver tutorial

Figure 36:Star-shaped distribution grid: best SSN node location

Figure 37:Online demo model: ssn_power_hvdc_itvc.mdl with ’SSN Group tag’ blocks 48

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References

4.1 .14 4 Ref Referen erenc ces [1] C. Dufour, J. Mahseredjian , J. Bélanger, "A Combined State-Space Nodal Method for the Simulation of Power System Transients", IEEE Transactions on Power Delivery, Vol. 26, no. 2, April 2011 (ISSN 0885-8977), pp. 928935 [2] W. Wang, J. Bélanger, C. Dufour, A. Douzdouzani, "A Novel and Flexible Test Stand for Medium Voltage Drives Using a Hardware-in-loop (HIL) Simulator", 2011 PCIM Europe Proceeding, Nuremburg, Germany, May 8-10, 2011 [3] Ramos-Leanos, O.; Naredo, J. L.; Mahseredjian, J.; Dufour, C.; Gutierrez-Robles, J. A.; Ko Kocar, car, I.; "A Wideband Line/Cable Model for Real-Time Simulations of Power System Transients," Power Delivery, IEEE Transactions on , vol.27, no.4, pp.2211-2218, Oct. 2012 [4] C. Dufour, J. Mahseredjian, J. Bélanger, J. L. Naredo, "An Ad Advanced vanced Real-Time Electro-Magnetic Simulator for Power Systems with a Simultaneous Simultaneous State-Space Nodal Solver", IEEE/PES T&D 2010 - Latin Ame America, rica, São Paulo, Brazil, Nov. 8-10, 2010

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References

State-Space Space (SSN) solver tutorial

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Reference

 

This section describes the various blocks and functions provided with ARTEMiS.

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ARTEMiS Guide Library ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator) Block The ARTEMiS is the main discrete simulation ARTEMiS fromGuide whichblock the different ARTEMiS solvers can beparameter selected. control block of

Figure 32:ARTEMiS Guide Block Mask

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Figure 33:Mask of the ARTEMiS Guide Block Description The ARTEMiS Guide block is used to discretize discreti ze the linear part of the state-space system generated by the SimPowerSystem blockset (SPS). It implements strictly fixed time step simulation of SPS schematics and offers alternative to the Tustin discretization method of the SPS to increase numerical stability and an d precision. In contrast to the simulation technique of the SPS, the 'ARTEMiS Guide' block precomputes and discretizes all state-space matrices for all combinations of the switch topologies thus permitting hard real-time simulation. Since v6, ARTEMiS offers a new simulation algorithm called State-Space Nodal (SSN), (SSN ), which combines the accuracy advantages of state-space methods together with the advantages of nodal methods with regards to switch management. Basically, there is no switch count limit with the SSN solver. Since v6 also, the interpolation method have been changed to ’Inlined’ methods which are more efficient in terms of calculation and more easy to use. The interpolation methods are now active by default because of their th eir simplicity. Parameters

General tab Sets the sample time for the fixed time step simulation of the electrical part of the SPS model.This sample time should be the same as the one entered in the SPS PowerGUI block.

Sample Time (s):

Enable State-Space Nodal method:

When checked, activates the use of SSN methods in SPS subsystems where nodal nodes have been defined using SSN Nodal Interface Blocks.

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NOTE: the option Dynamic calculation of switch pattern matrix permutations  is now obsolete ARTEMiS. This option was provided in case of large switch count within a state-space method. With SSN, this limitation does not exist anymore. NOTE: the option RLC load substitution by Dynamic Load model is now obsolete. The option was provided to deal with some flaws in the SPS load flow routines. Since R2011B, SPS comes with a new load flow routine corrected these issues.

State-Space State-S pace Solver Options tab This option apply only to the parts pa rts of the model that don’t use the SSN solver. Sets the discretization method used by the ARTEMiS algorithm for the normal state-space system, not t he one using SSN method . Four different methods are available:art5 (default), art3, art3hd and trapezoidal . The art5 and art3  discretization methods are highly stable and very-accurate integration methods. Both are immune to numerical oscillations caused by switch operations in power networks. The art5  method is theoretically more accurate than art3, as it approximates the matrix exponential Taylor expansion to the 5th term, while art3 and trapezoidal  approximate to the 3rd and 2nd terms, respectively. The art3hd discretization methods a highly-stable method with good precision, especially in highly non-linear networks like the demo example provides with SPS called power_surgnetwork. mdl. The  art3hd method is the only integration method capable of simulating the power_surgnetwork.mdl model with a time step greater than 90us. 90 us. State-Space discretization method:

SSN tab These options apply only when the SSN solver is being used in a model. SSN solver:

type of solver used for the SSN method. The SSN algorithm solve a model as two parts: state-space groups connected in a nodal method. The state-space groups can be solved by state-space discretisation similar to standard ARTEMiS (art5 solver, an order 5 matrix exponential approximant) while the nodal part can be solved by Trapezoidal, Backward Euler or Balanced-zero-hold, a mix of Backward and Forward Euler. The default method is Trapezoidal.  Other methods are provided for help only. In case of numerical oscillations at nodal connection points, the Art5 or Backward Euler method can provide a solution. Disable SSN group iterations: SSN

iterates the solution within each group normally. For example, if 2 IGBTs are in the same sam e SSN groups, iterations are made to find the correct and coherent switch pattern at all time steps. This does not apply if the switch are in different SSN groups. This option disable the internal group iteration process. This can accelerate simulations in rare cases. SSN Groups maximum number of iterations :

This set a limit on the number num ber of iteration within each SSN groups. See Disable SSN group iterations option.

Maximum number of iterations (iMOV and iSWITCH): this

option controls the number of global SSN iteration when iMOV and iSWITCH models are detected inside an SSN model. This option only apply to iMOV and iSWITCH models. See Iterative Model in SSN  section for more details.

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Advanced tab Extinction angle computation (individual thyristor only) : this option makes ARTEMiS compute the extinction angle of the thyristors of the model. The computed extinction angle are outputted at the 1 output of individual SPS thyristors (see figure below).

This output angle is a number between 0 and 1 representing the time elaspsed between the previous time step hit and the actual zero-crossing of current that cuased the thyristor to open. The option is also available with the SSN algorithm. See demos artemis_ITVC_ExtinctionZeroCrossing.mdl and artemis_ITVC_ExtinctionZeroCrossingSSN.mdl for more explanations. this option will force SPS to use continuous-time machine models inside the fixed-step simulation scheme. The machine are modeled with Use continuous time machine models:

Laplace integrators and the main Simulink fixed-step solver (ode1 to ode5) will be used to iterate the machine models. this option allow to swap between ARTEMiS DPL model or SPS DPL model. Only the latter one can be used for load flow calculations. The ARTEMiS Distributed Parameter Line models are required to enable the parallel simulation simulat ion of subnetworks separated by them in the RT-LAB framework. Distributed Parameter Line model type:

Inputs None Outputs None Other notes

Number of switches in ARTEMiS state-space solvers and SSN The SSN method main purpose is to uplift the limitation on the number of switches that a model can contain in state-space approach. There is always a SSN group separation method that will allow full pre-calculation of all matrices and real-time simulation. Switches can even be alone in a group by themselves like in EMTP. With the ARTEMiS-SSN solver, the switch limitation of old ARTEMiS state-space solvers is waived but the user must create groups with a limited number of switches to limit memory usage by the stored matrix permutation inside the groups.  Consequently, switch number should be limited to reasonable number in each group(12 and lower for example per SSN group).

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At the limit of SSN, one can mimic classic EMTP approach and use only one switch and nothing else in a SSN group. This is perfectly valid in SSN but would produce huge nodal admittance matrix and may be not efficient in real-time when there are many switches.

Interpolation methods ARTEMiS v6 and later automatically incorporates many interpolation methods that were previously manually enabled. There are 3 types of interpolation implemented in ARTEMiS: Impulse Event Detection:

This type of interpolation occurs when a forced switch action instantaneously induce a limit condition on another natural switch like a diode. A good example of this is in buck converter where the opening of a IGBT instantaneously put the free wheeling diode in conduction. This type of event is now supported by default in ARTEMiS v6 and later. Inlined Thyristor Valves Compensation (ITVC, ITVC-SSN) :

this algorithm corrects the firing jitter of thyristor valves caused by fixed step sampling of the gate signals. It automatically activates if the gate signal is a double number ranging continuously from 0 to 1. The number (ex: 0.458) indicates the in-step delay since the last sample time. The method deactivates if the number is the usual binary number used to control switches. The method is implemented in both state-space and SSN algorithms. Inlined Voltage Inverter Compensation (IVIC-SSN) :

available in SSN only, the IVICSSN method will compensate the simulation of voltage inverter modeled with SPS Universal Bridge blocks in a matter equivalent to RTeDrive TSB blocks. It automatically activates if the gate signal is a double number ranging continuously from 0 to 1. The number indicates the in-step delay since the last sample time. The method naturally account for all working modes of the inverter, including high impedance case. It must be used in conjunction with a SSN-defined load (motor, filter, etc....) to work correctly. Other types of interpolation: custom interpolation methods are proposed in some SSN demos. See the demo ThreeLevelInverter_IVIC_RTE2.mdl fr example.

Direct Feedthrough Discrete sample time RT-LAB XHP suppo rt

N/A Yes Yes

Work offline

Yes

MATLAB version compatibility Although RT-LAB is compatible with many MATLAB versions, the ARTEMiS plug-in for SimPowerSystems is more limited due to fine variations in the SPS code.

ARTEMiS version 7.0.x

MATLAB Compatibility R2011B

Related Items ARTEMIS Distributed Parameters Line, ARTEMiS Stubline, ARTEMiS-SSN Nodal interface Blocks.

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ARTEMiS Distributed Parameters Line Library ARTEMiS Block The ARTEMiStransmission distributed parameters line block for implements N-phases distributed parameters line model optimized real-time an simulation.

Figure 34:ARTEMiS distributed parameters line block Mask

Figure 35:Mask of the ARTEMiS distributed parameters line block Description The ARTEMiS Distributed Parameters Line block implements an N-phases distributed parameters line model with lumped losses. The model is based on the Bergeron's travelling wave method used by the Electromagnetic Transient Program (EMTP) [1]. This block is similar to the SPS distributed parameters line block but is optimized for discrete real-time

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simulation and allows network decoupling. It also allows multi-CPU simulation on an RT-LAB simulator. Refer to the SPS Distributed Parameter Line block Reference page for more details on the mathematical model of the distributed parameters line. ARTEMiS provides an m-script that converts the SPS distributed parameters line block to an ARTEMiS distributed parameters line block. See the ARTEMIS Distributed Parameters Line

reference page for more details on this script. s cript.

Network decoupling

One of the main advantage of the ARTEMiS line blocks (Distributed parameters lines and Stublines), by opposition to the SPS lines, is the decoupling of the electric circuit into smaller subnetworks. This important property allows ARTEMiS to simulate, in real-time, circuit with more switching elements. SPS and ARTEMiS solve electric circuits using the common state-space method. One of the main limitation of this method is related to the switch elements. When an event occurs that changes the topology of the circuit (or change the state s tate of a switch), SPS and ARTEMiS need to compute a new state-space matrix. This calculation causes a non acceptable overhead when simulating a circuit in real-time. To solve this problem, ARTEMiS stores the state-space matrices matric es of a given set of topologies, normally the steady-state topologies, in cached memory and uses them when necessary without having to recalcule the matrices. However, the number of matrices matr ices required to cover all topologies of the system depends on the number of switch elements. When a circuit contains a lot of switch elements, the number of required topologies is high and it is not possible to store all matrices in cached memory because of the size of th thee matrices. The decoupling property of the line allows ARTEMiS to divide the state-space system in two different state-space systems and reduce the total s ize of the state-space matrices in memory. It also reduces the maximum number of topologies by an important factor. RT-LAB simulation using a cluster of PCs

The distributed configuration of RT-LAB allows all ows for complex models to be distributed over a cluster of PCs running in parallel. The target nodes in the cluster communicate between each other with low latency protocols such as shared memory, FireWire, SignalWire or InfiniBand, fast enough to provide reliable communication for real-time applications. However, electrical circuit cannot be easily distributed over a cluster of PCs without changing chan ging the dynamic behaviors of the system. The communication delays degrade the computation. ARTEMiS lines (Distributed Parameters Lines and Stublines) can be used to distribute a circuit over a cluster of PCs. ARTEMiS used the intrinsic delay of the line to split the circuit without affecting the dynamic property of the system. Moreover, SPS and ARTEMiS use physical modelling lines and connectors to model the circuit. This type of signals cannot be used by RT-LAB to communicate signals between subsystems, because the RT-LAB opcomm block only supports basic Simulink signals. The only exception to this rule are the ARTEMiS Distributed Parameters Line block and the ARTEMiS Stubline block. RT-LAB allows the insertion of a line block at the root level of the block diagram and the connection of the physical modelling ports of the block to the real-time subsystems. Also note that the physical modelling signals and ports do not have to pass through the opcomm block. The Example in Example in the Characteristics and Limitations  section illustrates how to use the block with RT-LAB.

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Parameters Defines the mathematical models of the distributed parameters line used by ARTEMiS and SPS. Here are the available options: Simulation mode:

• SimPower SimPowerSystem Systems: s: When tthis his option option is sselected elected the bloc blockk uses tthe he SPS mathematical model that is not optimized for real-time simulation. • ARTEM ARTEMiS iS model: model: When this this option option is se selected lected the blo block ck use usess the ARTEMiS mathematical model that allows fast real-time simulation and that allows network decoupling. Specifies the number of phases, N, of the model. The block dynamically changes according to the number of phases that you specify. When you aapply pply the parameters or close the dialog box, the number of inputs and outputs is updated.

Number of phases N:

Specifies the frequency used to compute the resistance R, inductance L, and capacitance C matrices of the line model. Frequency used for RLC specifications:

Resistance per unit length:

The resistance R per unit length, as an N-by-N matrix in ohms/km. For a symmetrical line, you can either specify the N-by-N matrix or the sequence

parameters. For a two-phase or three-phase continuously transposed line, you can enter the positive and zero-sequence resistances [R1 R0]. For a symmetrical six-phase line you can set the sequence parameters plus the zero-sequence mutual resistance [R1 R0 R0m]. For asymmetrical lines, you must specify the complete N-by-N resistance matrix. Inductance per unit length: The inductance L per unit length, as an N-by-N matrix in henries/km (H/km). For a symmetrical line, you can ca n either specify the N-by-N matrix or the sequence parameters. For a two-phase or three-phase continuously con tinuously transposed line, you can enter the positive and zero-sequence inductances [L1 L0]. For a symmetrical six-phase line, you can enter the sequence parameters plus the zero-sequence mutual inductance [L1 L0 L0m]. For asymmetrical lines, you must specify the complete N-by-N inductance matrix.

The capacitance C per unit length, as an N-by-N matrix in farads/km (F/km). For a symmetrical line, you can either specify the N-by-N matr matrix ix or the sequence parameters. For a two-phase or three-phase continuously con tinuously transposed line, you can enter the positive and zero-sequence capacitances [C1 C0]. For a symmetrical six-phase line you can enter the sequence parameters plus the zero-sequence mutual capacitance [C1 C0 C0m]. For asymmetrical lines, you must specify the complete N-by-N capacitance matrix. Capacitance per unit length:

Line length:

The line length, in km.

Measurements:

Line current and voltage measurement are not working.

Inputs N-Phases voltage-current signals Outputs N-Phases delayed voltage-current signals.

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Characteristics and Limitations The ARTEMiS distributed parameters line block does not initialize in steady-state so unexpected transients at the beginning of the simulation may occur. The use of the ARTEMiS Distributed Parameter Line disable the ‘Measurements’ option of the regular Distributed Parameter Line. Usage of regular voltage measurement blocks is a good alternative.

Direct Feedthrough Discrete sample time XHP support Work offline

No Yes, defined in the ARTEMiS guide block. Yes Yes

Example The example shows how to use the ARTEMiS distributed parameters line to decouple an electrical network into two distinct subnetworks and consenquently to optimize the time to simulate the system in real-time. This property also allows ARTEMiS to simulate systems that contains more switching elements and consequently more complex systems. Note that the procedure shown below can also be apply to ARTEMiS Stubline block to decouple subnetworks and optimize real-time simulation. • Open the SPS demo p power_mo ower_monophas nophaseline eline m model odel by by typi typing ng the following command in the command prompt of Matlab: power_monophaseline; • To beco become me familiar familiar with the example, example, consult consult the the help an and d per perform form simulation and check the results. The next steps will modify the demo to use the ARTEMiS solver instead of the normal SPS solver. • Drag an ARTEMiS Guide block block from from the ARTEMiS ARTEMiS librar libraryy into th thee model and set it sample time to 50e-6 seconds. • Set the S SPS PS PowerGUI PowerGUI blo block ck to mode mode with a ssample ample time equal to ARTEMiS • Change tthe he Distr Distributed ibuted Parameter Line line block of SPS to the ARTEMiS block and copy the original line parameters in the ARTEMiS Line model. Optionally, one can use the opReplaceSpsBlocks function. At the MATLAB prompt type: opReplaceSpsBlocks('power_monophaseline', 'ReplaceSpsBlocks'); • The mod model el must be be simi similar lar to tthe he foll following owing figure. figure. Save the model under the following name : power_monophaseline_artemis.mdl.

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• Simulat Simulatee the model model and ana analyse lyse the result results. s. You w will ill see tthat hat the results are similar to the original model.

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• The next steps will will sh show ow you how how to run run the mod model el on a cluster cluster o off PCs running RT-LAB. The general idea is to benefit from the intrinsic delay of the transmission line to split the model into subnetworks. The mathematical model of the distributed parameters line of ARTEMiS, contrary to the SPS model, allows distribution of the line onto two different CPUs. This property also allows ARTEMiS to simulate systems that contains more switching elements and consequently more complex systems. • Select all bloc blocks ks lo located cated in in the sub subnetwork network 1 in the ffigure igure aabove bove and press Ctrl-G to create a new subsystem. • Mov Movee the ARTE ARTEMiS MiS b block lock insid insidee the sub subsys system tem.. • Rename th this is su subsyst bsystem em to SM SM_Subnet _Subnetwork_1 work_1.. The following following figure displays the content of the SS_Subnetwork_1 subsystem.

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• Select all bloc blocks ks lo located cated in in the sub subnetwork network 2 and pre press ss Ctrl Ctrl-G -G to create a new subsystem. • Add a ARTEMiS ARTEMiS Gui Guide de bl block ock inside the subsyste subsystem. m. • Rename tthis his subsyste subsystem m to SS_Subnetw SS_Subnetwork_2. ork_2. The ffollowi ollowing ng figu figure re illustrates the content of the SS_Subnetwork_2 subsystem.

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• Select the 3 remai remaining ning blocks, blocks, normally the two scopes scopes block blockss and the Mux1 block and press Ctrl-G to create a new subsystem. • Ren Rename ame th this is sub subsy syste stem m to SC_ SC_Cons Console ole.. • Add th thee RT-LAB opcom opcomm m block block between between the inp inports orts b blocks locks aand nd the content of the subsystem. Don’t forget to set the number of inports of the opcomm blocks to 3. Refer to the t he RT-LAB user guide for more help. • The fol following lowing figure iillustra llustrates tes the content of th thee SC_Cons SC_Console ole subsystem after the modifications described above have been made.

• Modif Modifyy the solver solver para parameters meters of of the model; model; select select one of the fix fixededstep solver, like ode3 for example, and change the fixed-step size to 50e-6. • Organi Organize ze the top level level blo blocks cks according according tto o the following following fi figure. gure. IMPORTANT: the powerGUI block must be at the top level.

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• Sa Save ve yo your ur mode model. l. • Your mo model del is n now ow ready to be compiled compiled with RTRT-LAB. LAB. Refer Refer to the the RT-LAB User Guide for more help. If your have set the sample times of your model with a variable set in the workspace(ex: Ts), you should set the model initialization function with in File->Model Properties->Callbacks->InitFcn Limitations Usage in RT-LAB as task decoupling elements

When used in RT-LAB to decouple and separate computational tasks on different cores/CPUs, the following connection restriction are applicable to the ARTEMiS distributed parameters line model: 1- The ARTEMiS distributed parameters line must be located on the top-level of the RT-LAB compatible Simulink model 2- Each ARTEMiS distributed parameters line outports can be connected only to SimPowerSystems component located inside RT-LAB top-level subsystem (names beginning with ’SS’ or ’SM’ prefixes) 3- No connection between ARTEMiS distributed parameters lines is allowed on the top-level. If such a connection is required, the ARTEMiS distributed parameters block connection lines must be first routed inside the subsystems individually and the connection between the ARTEMiS distributed parameters line ports can be made inside the subsystem. Related Items OpReplaceSpsBlocks , ARTEMiS Guide, ARTEMiS Stubline

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References [1] Dommel, Dommel, H., “Digital Computer Computer Solution Solution of Electromagnetic Electromagnetic Transient Transientss in Single and Multiple Multiple Networks”. IEEE Transactions on Power Apparatus and Systems, Vol. PAS-88, No. 4, April, 1969.

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ARTEMiS-SSN Frequency Dependent Line Library ARTEMiS Block The ARTEMiS-SSN Frequency Dependent Line block implements an N-phases distributed parameters transmission line model with frequency dependence of line parameters.

Figure 36:ARTEMiS-SSN Frequency-dependent Line block Mask

Figure 37:Mask of the ARTEMiS-SSN Frequency-dependent Line block

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ARTEMiS-SSN Frequency Dependent Line

Figure 38:Mask of the ARTEMiS-SSN Frequency-dependent Line Block: Measurements Parameters Description The ARTEMiS-SSN Frequency Dependent Line block implements an N-phases distributed parameters line model with frequency dependence of line parameters. The model is based on the Marti’s model used by the Electromagnetic Transient Program (EMTP-RV) [1][2]. This model is optimized for discrete real-time simulation and allows network decoupling. It also allows multi-CPU simulation on an RT-LAB simulator. Parameters Number of phases: the

number of phase of the model (1-2-3-6)

the name of a MATLAB workspace variable containing the FD_line parameter. The variable is a structure containing the various parameter of the model. Line data variable:

>>fdfit = Nph: [1x1 struct] ......................................................number of phase NpolY: [1x1 struct] .......... ...................... .............. .. number of poles for Yc(s) (Yc=1/Zc) (Yc=1/Zc) Ypol: [1x1 struct] .......... .................... ....................... ....................... ...................... ............... ... poles of Yc(s) Yres: [1x1 struct] ......................................................residues of Yc(s) YDmat: [1x1 struct] .......... ...................... ...................... ................ ...... constant constant residues residues of Yc(s) NpolH: [1x1 struct] .......... ...................... ...................... .................... .......... number of poles of H(s) Hpol: [1x1 struct]...................................poles of H(s) (propagation function) Hres: [1x1 struct] ................... ............................ ................... ..................... ..................... .................residue .......residue of H(s) HDmat: [1x1 struct] .......... ...................... ...................... ................. ....... constant constant residues residues of H(s) taumin: [1x1 struct] ..................................minimum propagation delays Ti: [1x1 struct] ........... .......................... ............................. .............. current transformation matrix Tv: [1x1 struct] .......................................voltage transformation matrix

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 And each component being itsefl a structure with Data and Name parts. For example: >> fdfit.NpolY   Data: [3x1 double]   Name: 'Number o off po poles les for each mode in in Ycm'

The document untitled 'Obtaining FD-line model parameters from EMTP-RV' explains how to get these parameters from the fitting routines of EMTP-RV. It can be found in the installation repository of ARTEMiS:  pathtorepository   /ARTEMiS/ artemis_version artemis_version /art_r201 XY   /auxiliary_routines/marti   _fd_line/line_param/Obtaining_FDline_model_parameters_from_EMTP_RV  _fd_line/line_param/Obtaining _FDline_model_parameters_from_EMTP_RV .pdf 

a user set string that must be unique for each instance of this block inside a Simulink model. (Note: in future releases, this parameters will be set automatically and will not be visible from the user)

Unique Tag Identifier:

: User decide if we want to measure others parameters of the line like phase voltage or phase current. (Note : the voltage is a phase-to-ground measurement)

Voltage measurement and Current Measurement choice

Voltage and Current Label:

User can specify a label for its current or voltage values. In

caseuser the previous havecurrent. been setted up to current using and voltage labels provided by the are used choices to retrieve This can beyes, performed ‘label_’s for the sending side of the line ( the one connected to the source) and ‘label_r’ for the receiving side of the line. Inputs N-Phases voltage-current signals Outputs N-Phases delayed voltage-current signals. Example

Offline usage example The FD-line model interface with and a nd only with the SSN method. The reason for this is that the FD-line model is internal coded with the nodal approach. To make this interface, the FD-line FD-l ine model must be used in conjunction with SSN Nodal Interface Blocks (NIB) with the X-type interface chosen in the direction of the FD-line. The NIB can connect to other SSN groups of either V- I- or X-type. The curve below shows the source energization current while phase C is connected to the 1-1mH single phase load.

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ARTEMiS-SSN Frequency Dependent Line

Real-time example The distributed configuration of RT-LAB allows for complex models to be distributed over a cluster of PCs running in of parallel. However, electrical circuit cannot be easily distributed and/or cluster PCs without changing the dynamic behaviors of the system. over a multiple cores ARTEMiS lines (FD-line, Distributed Parameters Lines and Stublines) can be used to make the parallel

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simulation of an electric circuit. ARTEMiS used the intrinsic delay of the line to split the circuit without affecting the dynamic property of the system. See the ARTEMiS Distributed Parameter Line  documentation for a complete example of the usage of ARTEMiS line models in the RT-LAB framework. For real-time simulation the model had to be prepare according to RT-LAB conventions (SM_ SS_ toplevel Simulink groups for example). The model below contains 2 FD-line models connecting some source and loads.

The top-level separated model for RT-LAB will have the ARTEMiS-SSN Frequency Dependent Line model stay at the top-level of the diagram as shown below

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ARTEMiS-SSN Frequency Dependent Line

And with the NIB block inside the SM_Master and SS_Slave subsystems like depicted below:

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Compilation of this model in RT-LAB will results in two independent tasks (SM_Master and SS_Slave) interconnected by the 2 FD-line which will wi ll transmit their propagation voltage and currents between the two subsystems. Characteristics and Limitations Usage of the FD-line model in RT-LAB as task decoupling elements

When used in RT-LAB to decouple and separate computational tasks on different cores/CPUs, the following connection restriction are applicable to the ARTEMiS distributed parameters line model: 1- The ARTEMiS-SSN Frequency Dependent Line must be located on the top-level of the RTLAB compatible Simulink model 2- Each ARTEMiS-SSN Frequency Dependent Line outports can be connected only to SimPowerSystems component located inside RT-LAB top-level subsystem (names beginning with ’SS’ or ’SM’ prefixes) 3- No connection between ARTEMiS-SSN Frequency Dependent Lines is allowed on the toplevel. If such a connection is required, the ARTEMiS-SSN Frequency Dependent Line block connection lines must be first routed inside the subsystems individually and the connection between the ARTEMiS-SSN Frequency Dependent Line ports can be made inside the subsystem.

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SSN solver in the ARTEMiS GUIde block 

The SSN solver of the ARTEMiS GUIde block must be ’Trapezoidal’ when using a ARTEMiSSSN Frequency Dependent Line block. This is because the Trapezoidal solver is used internally by the ARTEMiS-SSN Frequency Dependent Line block.  Initialisation

The ARTEMiS-SSN Frequency Dependent Line block does not initialize in steady-state so unexpected transients at the beginning of the simulation may occur.

Direct Feedthrough Discrete sample time XHP support Work offline

No Yes, defined in the ARTEMiS guide block. Yes Yes

Related Items OpReplaceSpsBlocks, ARTEMiS Guide, ARTEMiS Stubline, ARTEMIS Distributed Parameters Line, ARTEMiS-SSN Nodal interface Blocks. Blocks .

References [2] J.R. Marti, “Accurate Modelling of Frequency-Dependent Transmission Lines in Electromagnetic Transient Simulations”, IEEE Trans. on Power App. and Systems, Vol. PAS101, No. 1,January 1982, pp. 147-155.

[3] C. Dufour, H. Le-Huy, Le-Huy, J.J.-C. C. Soumagne, A. El Hakimi, Hakimi, “Real“Real-Time Time Simulation Simulation of Power Power Transmission Lines using Marti Model with Optimal Fitting on Dual-DSP Du al-DSP Card”, IEEE Trans. on Power Delivery, Vol.11, No.1, Jan. 1996, pp. 412-419.

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ARTEMiS-SSN WideBand Line Library ARTEMiS Block The ARTEMiS-SSN WideBand Line block implements an N-phases distributed parameters transmission line model with frequency dependence of line parameters using full-phase domain modelisation.

Figure 39:ARTEMiS-SSN WideBand Line block Mask

Figure 40:Mask of the ARTEMiS-SSN WideBand Line block

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ARTEMiS-SSN WideBand Line

Figure 41:Mask of ARTEMiS-SSN Wideband Line block, Measurements tab

Description The ARTEMiS-SSN WideBand Line block implements an N-phases distributed parameters line model with frequency dependence of line parameters. In difference to the ARTEMiS-SSN FD line model which uses a modal transformation to compute the frequency dependant parameters, the WideBand model directly models all its frequency dependant parameter in the phase domain, avoiding the error caused by the use of a constant modal transformation matrix in FD line model. Cables in particular typically exhibit a strong frequency dependant of the modal transformation matrix, making the FD line model inaccurate in this case. The WideBand model is much more accurate with cables in this regards [1]. This model is optimized for discrete real-time simulation and allows the decoupling of network connected on each side of it. It also allows multi-CPU simulation on an RT-LAB simulator. Parameters Number of phases: the

number of phase of the model (1-2-3-4-6-8-10-12)

Line data variable: the name of a MATLAB workspace variable containing the WB line parameter. The variable is a structure containing the various parameter of the model.

>>wbfit =

Nph:........ ................... .................................... ................. ................. ................ ............................. ............. number ofgroups phase Ng: .................. ................. ................. .. Number of propagation tau: ................................................................................Propagation delays NYc: ........... ..................... ................... ................... ..................... ..................... ..................... .................... ............. .... Yc fittin fitting g order YcNpR: . .................. ................. ................. ............ Number of real Yc poles

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YcNpC: .............. ................. ................. .......... Number of complex Yc poles YcR: ........... ..................... ................... ................... ..................... ..................... ..................... .................... .............. ..... Real Yc poles YcCR: ........... ......................... ............................... ................. ................ Real part of complex Yc poles YcCI: ....................... ..... ............................... ............................ ............... Imaginary part of complex Yc poles YcstD: ...................................... ..................... ................. ................. ................. Yc constant residues YcRres: ...............................................................Residues of real Yc poles YcCRres: ............ ............................ .................... .... Real Part o off Residues of complex Yc poles YcCIres: .................. ... ....................... ........ Imaginary part of R Residues esidues of complex Yc poles NH: ............... .............. ............................... ................. ................. ................. ........ H fitting order HNpR: .....................................................................Number of real H poles HNpC: ................................. ................ ................. ................. ........... Number of complex H poles HR: ............... .............. ............................... ................. ................. ................. ......... Real H poles HCR: ......................... ......... ............................... ............................ ..................... ........ Real part of complex H poles HCI: .............. .............. ............................... ................. ......... Imaginary part of complex H poles HRres: ............... ................................ ................. ................. ................ Residues of real H poles HCRres: ........ .............. ............................ .............. Real part part of R Residues esidues of complex H poles HCIres: ............... ............................. .............. Imaginary part of Residues of complex H poles

The document untitled 'Obtaining WideBand line model parameters from EMTPRV' explains how to get these parameters from the fitting routines of EMTP-RV. It can be found in the installation repository of ARTEMiS:  pathtorepository   /ARTEMiS/ artemis_version artemis_version /art_r201 XY   /auxiliary_routines/wideb and/line_param/Obtaining_WideBand_ine_model_parameters_from_EMTP_RV.pdf 

a user set string that must be unique for each instance of this block inside a Simulink model. (Note: in future releases, this parameters will be set automatically and will not be visible from the user) Unique Tag Identifier:

: User decide if we want to measure others parameters of the line like phase voltage or phase current. (Note : the voltage is a phase-to-ground measurement)

Voltage measurement and Current Measurement choice

Voltage and Current Label: User can specify a label for its current or voltage values. In case the previous choices have been setted up to yes, current and voltage labels provided by

the user are used to retrieve current. This can be performed using ‘label_’s for the sending side of the line ( the one connected to the source) and ‘label_r’ for the receiving side of the line. Inputs N-Phases voltage-current signals Outputs N-Phases delayed voltage-current signals. Example

3-phase cable energizati energization on In the demo, a 15 km 3-ph cable (equivalent to 6 phase line considering the sheath) is energized with an open end. The sheath is grounded with 10 Ohms resistors at both ends. See the ‘Demo Validation against EMTP-RV’ section at the end of this document for more info on this test case.

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ARTEMiS-SSN WideBand Line

The WD-line model was fitted with a total of 14 poles for the characteristic admittance Yc(w) and 36 for the 6 propagation functions H1(w) to H6(w).

To make this interface, the FD-line FD-l ine model must be used in conjunction with SSN Nodal Interface Blocks (NIB) with the X-type interface chosen in the direction of the FD-line. The NIB can connect to other SSN groups of either V- I- or X-type.

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Energization from balanced source results in receiving end cable core voltage in the figure below.

Going to real-time The distributed configuration of RT-LAB allows for complex models to be distributed over a cluster of PCs running in parallel. ARTEMiS WideBand lines (and also FD-line, Distributed Parameters Lines and Stublines) can be used to make the parallel simulation of an electric circuit. ARTEMiS used the intrinsic delay of the line to split

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ARTEMiS-SSN WideBand Line

the circuit without affecting the dynamic property of the system. See the ARTEMiS Distributed Parameter Line documentation for a complete example of the usage of ARTEMiS line models in the RT-LAB framework. For real-time simulation the model had h ad to be prepare according to RT-LAB conventions (SM_ SS_ prefix for top-level Simulink groups for example). This demo model is already like this, the user us er can optionally add a RT-LAB console with SC prefix. Compilation of this model in RT-LAB will results in two independent tasks (sm_master ss_slave) interconnected by the WideBand-line which will transmit their propagation voltage and and currents between the two subsystems. Characteristics and Limitations Usage of the WideBand line model in RT-LAB as task decoupling elements

When used in RT-LAB to decouple and separate computational tasks on different cores/CPUs, the following connection restriction are applicable to the ARTEMiS distributed parameters line model: 1- The ARTEMiS-SSN WideBand Line must be located on the top-level of the RT-LAB

compatible Simulink model 2- Each ARTEMiS-SSN WideBand Line outports can be connected only to SimPowerSystems component located inside RT-LAB top-level subsystem (names beginning with ’SS’ or ’SM’ prefixes) 3- No connection between ARTEMiS-SSN WideBand Lines is allowed on the top-level. If such a connection is required, the ARTEMiS-SSN WideBand Line block connection lines must be first routed inside the subsystems individually and the connection between the ARTEMiSSSN WideBand Line ports can be made inside the subsystem.

SSN solver in the ARTEMiS GUIde block 

The SSN solver of the ARTEMiS GUIde block should be ’Trapezoidal’ when using a ARTEMiSSSN WideBand Line block. This is because the Trapezoidal solver is used internally by the ARTEMiS-SSN WideBand Line block.

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 Initialisation

The ARTEMiS-SSN WideBand Line block does not initialize in steady-state so unexpected transients at the beginning of the simulation may occur.

Direct Feedthrough Discrete sample time XHP support Work offline

No Yes, defined in the ARTEMiS guide block. Yes Yes

Related Items OpReplaceSpsBlocks, ARTEMiS Guide, ARTEMiS Stubline, ARTEMIS Distributed Parameters Line, ARTEMiS-SSN Nodal interface Blocks. Blocks .

References [1] Atef Morched, Bjrn Gustavsen,, Manoocher. Tartibi, “A universal model for accurate calculation of electromagnetic transients on overhead lines and underground cables”, IEEE Trans. on Power Delivery, Vol. 14, No. 3, pp. 1032-1038, July 1999.

[2] C. Dufour, H. Le-Huy, J.-C. Soumagne, Soumagn e, A. El Hakimi, “Real-Time Simulatio Simulation n of Power Transmission Lines using Marti Model with Optimal Fitting on Dual-DSP Card”, IEEE Trans. on Power Delivery, Vol.11, No.1, Jan. 1996, pp. 412-419.

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ARTEMiS Stubline Library ARTEMiS Block The ARTEMiS Stubline block implements an N-phase distributed parameters transmission line model with exactly one time step propagation delay. It is optimized for real-time simulation. The ARTEMiS Stubline block permits the t he decoupling of state-space system equations of networks on both sides of the stubline.

Figure 42:ARTEMiS Stubline block Mask

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ARTEMiS Stubline

Figure 43:Mask of the ARTEMiS Stubline block Description The ARTEMiS Stubline block implements an N-phase distributed parameters transmission line model with exactly one time step propagation delay. The m model odel is based on the Bergeron's travelling wave method used by the Electromagnetic Transient Program (EMTP) [1]

. Thisreal-time block is similar to the distributed ine blockallows but ismulti-CPU optimized for discrete simulation andSPS allows networkparameters decoupling.lline It also simulation on an RT-LAB simulator. Refer to the SPS Distributed Parameter Line block Reference page for more details on the mathematical model of the distributed parameters line. Network decoupling

One of the main advantage of the ARTEMiS line blocks (Distributed parameters lines and Stublines), by opposition to the SPS lines, is the decoupling of the electric circuit into smaller subnetworks. This important property allows ARTEMiS to simulate, in real-time, circuit with more switching elements. SPS and ARTEMiS solve electric circuits using the common state-space method. One of the main limitation of this method is related to the switch elements. When an event occurs that changes the topology of the circuit (or change the state s tate of a switch), SPS and ARTEMiS need to compute a new state-space matrix. This calculation causes a non acceptable overhead when simulating a circuit in real-time. To solve this problem, ARTEMiS stores the state-space matrices matric es of a given set of topologies, normally the steady-state topologies, in cached memory and uses them when necessary without having to recalcule the matrices. However, the number of matrices matr ices required to cover all topologies of the system depends on the number of switch elements. When a circuit contains a lot of switch elements, the number of required topologies is high and it is not possible to store all matrices in cached memory because of the size of th thee matrices. The decoupling property of the line allows ARTEMiS to divide the state-space system in two different state-space systems and reduce the total s ize of the state-space matrices in memory. It also reduces the maximum number of topologies by an important factor. RT-LAB simulation using a cluster of PCs

The distributed configuration of RT-LAB allows all ows for complex models to be distributed over a cluster of PCs running in parallel. The target nodes in the cluster communicate between each other with low latency protocols such as shared memory, FireWire, SignalWire or InfiniBand, fast enough to provide reliable communication for real-time applications. However, electrical circuit cannot be easily distributed over a cluster of PCs without changing chan ging the dynamic behaviors of the system. The communication delays degrade the computation. ARTEMiS lines (Distributed Parameters Lines and Stublines) can be used to distribute a circuit over a cluster of PCs. ARTEMiS used the intrinsic delay of the line to split the circuit without affecting the dynamic property of the system. Moreover, SPS and ARTEMiS use physical modelling lines and connectors to model the circuit. This type of signals cannot be used by RT-LAB to communicate signals between subsystems, because the RT-LAB opcomm block only supports basic Simulink signals. The only exception to this rule are the ARTEMiS Distributed Parameters Line block and the ARTEMiS Stubline block. RT-LAB allows the insertion of a line block at the root level of the block diagram and the connection of the

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physical modelling ports of the block to the real-time real-ti me subsystems. Also note that the physical modelling signals and ports do not have hav e to pass through the opcomm block.

Parameters Specifies the number of phases, N, of the model. The block

Number of phases N:

dynamically changes according to the number of phases that you you aapply pply the parameters or close the dialog box, the number of inputs and specify. outputs When is updated. Available number are 1 to 6 and ’2 (differential input)’. This last option is useful when us using ing ARTEMiS Stubline in case where it do not have to be refered to ground like in stubline transformer applications. Per-Unit value specification:

Specify if the resistance and inductance value are specified

in per-unit or not. Resistance per unit length:

The resistance R per unit length, in ohms or pu..

Inductance per unit length:

The inductance L per unit length, in henries (H) or pu.

Nominal power (VA): Nominal voltage(V):

Nominal power base (for per-unit values only).

Nominal voltage base (for per-unit values only).

Nominal frequency (Hz): Sample Time :

Nominal frequency base (for per-unit values value s only).

The block sample time, in second s econd (s).

Inputs N-Phases voltage-current physical domain connection. Outputs N-Phases delayed voltage-current physical domain connection. Characteristics and Limitations The ARTEMiS Stubline block does not initialize in steady-state so unexpected transients at the beginning of the simulation may occur.

Direct Feedthrough Discrete sample time XHP support Work offline

No Yes, defined in the ARTEMiS guide block. Yes Yes

Example This section provides an example on how to build a 3-phase stubline transformer. The stubline transformer will exhibit a decoupling delay between the primary and secondary sides suitable for distributed simulation real-time simulation of large systems. Such a transformer could be used to decouple HVDC system equations at the rectifier/inverter

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ARTEMiS Stubline

station transformers and compute each equations in parallel on different CPUs or cores. The model is part of the ARTEMiS demos and is named artemis_Transfo_Stubline (.mdl). In the example, we construct a stubline-based 3-phase transformer from an original SimPowerSystems transformer and compare the no-load and short-circuit responses. The principle used to build the stubline transformer is to ’move’ the secondary windings leakage inductance and resistance in stublines put in series with the windings themself. This is done using single-phase transformers first, then adjusting the per-unit stubline parameters and finally to make the Y ou Delta connections after the stubline.

Figure 3: Model of a stubline transformer The example uses a SPS 3-phase transformer with the following parameters:

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Figure 4: Three-phase transformer parameters We willSince buildwe thewill stubline 3-phase transformer using single-phase transformer using ground pu units. also use pu-based differential stubline (a stubline with no built-in referentials), appropriate single-phase per-unit bases have to be found. First, the total 3phase nominal power has to be divided by 3 when configuring single-phase transformer inside. Secondly, the 3-phase winding voltage takes into account the connection type (Y or Delta) in the voltage specification while single-phase transformer has no such thing. Third, the R-L pu specification of a 3-phase transformer are specified as ’Y-connection equivalent values’. In the final, the resulting single phase transformer therefore has the following parameters:

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ARTEMiS Stubline

Figure 5: Single phase transformer parameters (with null secondary R-L parameters) Note that the single-phase transformer winding that are Y connected have their voltage volt age ratio cut by a sqrt(3) factor. Also note the nominal power that is cut by a factor 3. The ARTEMiS Stubline put in the Y connection has the following parameters:

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Figure 6: ARTEMiS Stubline parameters (Y-connected windings) while the ARTEMiS Stubline put in the Delta connection has the following parameters:

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ARTEMiS Stubline

Figure 7: ARTEMiS Stubline parameters (Delta-connected windings) Note that the bases used are consequent with the parameters of the single-pase transformer. The R-L per-unit values are the same than in the 3-phase transformer transformer.. Only the base voltage values differ depending on the connection type. The design of such transformers is often tricky t ricky because of the possible errors in the base conversion. It is always advisable to compare the stubline model with a rererence for noload and short-circuit cases to verify the correctness of the design. This is what is done in the example where we superpose the voltages and currents of the stubline transformer with a standard SPS model.

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Figure 8: Comparison of stubline- and SPS- transformers values for no-load (before 0.25 sec.) and short-circuit (after 0.25 sec.) Finally, this model can be simulated in several CPU if the model is separated in accordance to RT-LAB rules with the stublines used as inter-CPU decoupling elements placed on the toplevel of the Simulink model.

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ARTEMiS Stubline

Figure 9: Stublines usage in RT-LAB to decouple compuational task on several cores/CPUs See the artemis_Transfo_StublineRT.mdl demo for details on how to use the stublines to decouple and simulate such a model m odel on several cores/CPUs in RT-LAB. Limitations Usage in RT-LAB as task decoupling elements

When used in RT-LAB to decouple and separate computational tasks on different cores/CPUs, the following connection restriction are applicable to the ARTEMiS Stubline model: 1- The ARTEMiS Stubline must be located on the top-level of the RT-LAB compatible compati ble Simulink model (as in Figure 9 for example) 2- Each ARTEMiS Stubline outports can be connected only to SimPowerSystems component located inside RT-LAB top-level subsystem (names beginning with ’SS’ or ’SM’ prefixes) 3- No connection between stublines is allowed on the top-level. If such a connection is required (ex: star-connection neutral point), the ARTEMiS Stubline lines must be first routed

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inside the subsystems individually and the connection between the ARTEMiS Stubline ports can be made inside the subsystem. Related Items OpReplaceSpsBlocks , ARTEMiS Guide, ARTEMIS Distributed Parameters Line

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ARTEMiS Transformer with Switched Saturable Core Library ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator) Block The ARTEMiS-Transformer with Switched Saturable Core implements a 3-phase saturable transformer in SimPowerSystems model using a switched saturable core method instead of the current injection with delay of the native SPS transformer models. This type of model is use to solve instability problems of the current injection methods with delay. Available models are zigzag-Y , Y-Y, Y-D (±30 deg.), in PU and SI versions.

Figure 44:ARTEMiS Transformer with Switched saturable Core

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ARTEMiS Transformer with Switched Saturable Core

Mask

Figure 45:Mask of the ARTEMiS Transformer with Switched saturable Core (zigzag-Y) Description The ARTEMiS-Transformer with Switched Saturable Core implements a 3-phase saturable transformer in SimPowerSystems model using a switched saturable core method instead of the current injection with delay of the native SPS transformer models. The model is to be used in conjunction with the ARTEMiS GUIde block. The model is based on the SimPowerSystems transformer model for the linear part. The non-linear part, i.e. the saturation is modeled has a switched core inductance. In the linear

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region of operation, the first segment of the i=f(flux) characteristic is included in the ABCD state-space matrix and flux is monitored from there. Whenever the flux reach the 2nd (and last) segment of the i=f(flux) characteristic, a inductance is switched in parallel with the linear one and simulation continues with the new configuration of the circuit caused by this switching action. Parameters (zig-zag) Units: Specify

units or or PU)PUforunits. Zigzag Phase-Shifting Transformer block. Two different blocksthe must be used used (SI for SI

Nominal power and frequency: The nominal power rating, in volt-amperes (VA), and nominal frequency, in hertz (Hz), of the transformer.

The phase-to-phase nominal voltage in volts RMS, for the primary winding of the transformer. Primary (zigzag) nominal voltage Vp:

The phase-to-phase nominal voltage, in volts RMS, and the phase shift, in degrees, for the secondary winding of the transformer. Secondary nom. voltage phase shift:

The resistance and leakage inductance of the windings 1 of the single-phase transformers used to implement the primary winding of the Zigzag PhaseShifting Transformer. Winding 1 zig-zag [R1 L1]:

Winding 2 zig-zag [R2 L2]:The resistance and leakage inductance of the windings 2 of the single-phase transformers used to implement the primary winding of the Zigzag PhaseShifting Transformer. Winding 3 secondary [R3 L3]: The resistance and

leakage inductance inducta nce of the windings 3 of the single-phase transformers used to implement the secondary winding of the Zigzag Phase-Shifting Transformer. This parameter is accessible only if the Saturable core parameter on the Configuration tab is selected.

Magnetization resistance Rm:

The saturation characteristic for the saturable core. Specify a series of current/ flux pairs (in pu) starting s tarting with the pair (0,0). Saturation characteristic:

NOTE: the ARTEMiS-Transformer with Switched Saturable Core only allow a two-segment saturation characteristic so only 3 pairs of points can be entered (including the (0,0) point). Parameters (Y-D) Units: Specify

the units used (SI or PU) for Zigzag Phase-Shifting Transformer block. Two different blocks must be used for SI or PU units.

The nominal power rating, in volt-amperes (VA), and nominal frequency, in hertz (Hz), of the transformer. Nominal power and frequency:

Primary (Y) nominal voltage Vp: The phase-to-phase nominal voltage in volts RMS, for the primary winding of the transformer. This winding is always connected in Y.

Secondary nom. voltage: The phase-to-phase nominal voltage, in volts RMS, for the secondary winding of the transformer.

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the type of connection for the secondary windings. Available connection are: Y-Y, and Y-D (±30 deg.). Note that the winding neutral point connection is always available at both primary and secondary winding. Secondary winding (abc) connection:

The resistance and leakage inductance of the windings 1 of the single-phase transformers used to implement the primary winding of the Zigzag Phase-Shifting Transformer. Winding 1 impedance [R1 L1]:

Winding 2 impedance [R2 L2]: The resistance and

leakage inductance inductanc e of the windings 2 of the single-phase transformers used to implement the primary winding of the Zigzag PhaseShifting Transformer. This parameter is accessible only if the Saturable core parameter on the Configuration tab is selected. Magnetization resistance Rm:

The saturation characteristic for the saturable core. Specify a series of current/ flux pairs (in pu) starting s tarting with the pair (0,0). Saturation characteristic:

NOTE: the ARTEMiS-Transformer with Switched Saturable Core only allow a two-segment saturation characteristic so only 3 pairs of points can be entered (including the (0,0) point). Advanced Parameters Use SPS injection method: Disable

the Switching Core Saturation and use standard SPS injection method to simulate saturation Disable the Switched Core saturation (only if Use SPS injection method is not selected)

Disable saturation:

Unique tag within the COMPLETE model to route some internal flux signalsinside the transformer model. If two ARTEMiS Switched Core transformer t ransformer model with the same Unique Global Tag are in the same simulation model, an error will occur. Unique Global Tag:

Examples

Example 1: Energization of a zig-zag transformer with an floating source This example case makes the energization of a 3-phase zigzag-Y transformer tr ansformer on an inductive load. The load is has about 0.8 p.u. of active power 0.6 pu of reactive power. The

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transformer has an total impedance of 0.26 pu and is energized from rest with a balanced source of 1 pu of voltage.

Figure 46:Test model for the zigzag-Y transformer The saturation curve is depicted on the next figure.

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Figure 47:Saturation curve of the zigzag transformer of the test model The particularity of this model is that it simply cannot be simulated in real-time with SimPowerSystems only. If one try to simulate this model with the current injection with delay method of SPS, the model is unstable, event at 0.1 µs! With the ARTEMiS-Transformer with Switched Saturable Core, the model is stable and very accurate at time step of 30µs 30 µs and more. The following curves compare the simulation results of the model with ARTEMiS-Transformer with Switched Saturable Core at 30µs with one made with native SimPowerSystems at 1µs, with an algebraic loop. This means that the solver becomes iterative in this case and not suitable for real-time simulation anyway. It can however be taken for off-line simulation reference. The simulations are conducted with positive and negative angle phase shifts to verify the internal connection of the ARTEMiS models.

Figure 48:Zigzag transformer input current comparison (positive 15° phase shift)

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Figure 49:Zigzag transformer output voltage comparison (positive 15° phase shift)

Figure 50:Zigzag transformer input current comparison (negative 15° phase shift)

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ARTEMiS Transformer with Switched Saturable Core

Figure 51:Zigzag transformer output voltage comparison (negative 15° phase shift)

Input-Outputs A+, B+, C+ (PM-type connectors): 1st winding of zigzag. Positive polarity zigzag winding connection. A-, B-, C-: (PM-type connectors). 2nd winding of zigzag. Negative polarity zigzag winding connection. a3, b3, c3: (PM-type connectors). 3rd (or ( or secondary) winding connected in Y. flux: core flux signals (size 3) Characteristics and Limitations

1- The ARTEMiS-Transformer with Switched Saturable Satur able Core can only work with the ARTEMiS GUIde block present in the model. The first reason is that the ARTEMiS saturable transformer models are used to provide the core flux readings required by the model. The 2nd reason is that the damping properties of the ARTEMiS art5 solver are required to obtain

Direct Feedthrough Discrete sample time RT-LAB XHP support

N/A Yes Yes

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Related Items ARTEMIS Distributed Parameters Line, ARTEMiS Stubline, ARTEMiS-SSN Nodal interface Blocks, ARTEMiS-SSN Frequency Dependent Line.

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ARTEMiS-SSN Nodal interface Blocks Library ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator) Block The ARTEMiS-SSN Nodal interface Blocks B locks are used to define nodes and groups of th thee ARTEMiS-SSN solver. The SSN (State-Space Nodal) solver is a simulation solver that use nodal method to couple together, without delays, groups defined by their discretized SPS state-space equation or any model that has h as a discrete resistive companion model compatible with the nodal method of EMTP.

Figure 52:ARTEMiS-SSN Nodal interface Blocks

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ARTEMiS-SSN Nodal interface Blocks

Mask

Figure 53:Mask of the ARTEMiS-SSN Nodal Interface Blocks (3-phase case) Description The ARTEMiS-SSN Nodal Interface Blocks Bloc ks (NIB)is used to define nodal point and state-space groups in a SimPowerSystems schematic within the ARTEMiS-SSN solver. Each block instance defines a node by itself. The NIB also defines the perimeter of the SSN groups. Parameters

Number of phase:

Set the number of phase for the NIB.

Set the number of Ports of the block. All phase of a single port connects to a single SSN group. Number of Ports:

Port x  Port  x  type  type:

The Number of Ports parameter sets the number of Port x type (where x= 1 to 16) accesible by the user. For each Port x type parameter, 6 different options are possible. V-type(Left) : Voltage type interface to the state-space state -space groups, with ports on the lleft eft side V-type (Right): Voltage type interface to the state-space groups, with ports on the right side I-type(Left): Current type interface to the state-space sta te-space groups, with ports on the left sside ide

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I-type(Right): Current type interface to the state-space s tate-space groups, with ports on the right side X-type(Left): External SSN group type interface, with ports on the left side X-type(Right): External SSN group type interface, with ports on the right side These various options are used to connect conne ct different types of SSN groups: • •

Ind Inducti uctive ve type SSN gro groups ups requir requiree a V-type V-type interf interface ace Capa Capacit citive ive typ typee SSN SSN gr group oupss re requir quiree a I-ty I-type pe interfa interface ce

•

Exte External rnal S SSN SN mod model, el, ssuch uch as as the FD-li FD-line ne mod model, el, re requir quiree a X-type X-type iinte nterfa rface ce

Some example will be given to explain this Examples

Example 1: NIB with I-type and V-type V -type interface Take the following model, ArtemisSSN_simple_switched_case.mdl, which contains a switched inductive source connected to a filter filt er bank.

The model has been separated into 2 SSN groups, with the intersection being defined by the NIB. The NIB interface is I-type in the direction of the capacitor of the filter bank while it is V-type in the direction of the inductive source. The type of interface is displayed on the block. The NIB also defines the 3 node that will used internally in the nodal part of the SSN solution.

Example 2: NIB with X-type interface, for SSN external models The model below simulates a Frequency Dependent Parameter Transmission Line (FD-line) based on

the model originally developped by Marti. This FD-line model is internally coded using the nodal ARTEMIS User’s Guide

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approach and can only produce discrete resistive companion model data like the model discrete admittance and history current sources. The direct inclusion of the line characteristic impedance Zc( ) into a state-space method would have produce huge ABCD matrices becaue of the many states that compose Zc( ))..  

 

For this reason, the SSN approach is prefered when the interface of this type of model to the statespace method of SimPowerSystems. To make the interface, the NIB block must have ha ve the type-X chosen and connected toward the external SSN model, an FD-line model in this case. AS previously, the NIB also defines the nodal point of the SSN solution. In this case, 6 nodes will be used in the nodal solution part of SSN. Input-Outputs PM-type connectors Characteristics and Limitations V- and I-type NIB blocks are used to compute state-space equation equ ation of the SSN groups, and are internally composed of current or voltage sources. State-space equation causality restrictions apply to these blocks. This is why w hy V-type (internal voltage source) connects tto o inductive groups and I-type (internal current source) to capacitive type groups.

Direct Feedthrough

N/A

D RTis-cLrAeBteXsHaPmspulepptiomrte Work offline

Yeess Y Yes

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Related Items ARTEMIS Distributed Parameters Line, ARTEMiS Stubline, ARTEMiS-SSN Frequency Dependent Line.

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ARTEMiS Distributed Parameters Line with Variable Internal Fault distance Library ARTEMiS Block The ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance block implements an 3-phases distributed parameters transmission line model with an on-line modifiable internal fault capability

Figure 54:ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance block Mask

Figure 55:Mask of the ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance block Description The ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance (ADPLF) block is based on the Bergeron's travelling wave method used by the Electromagnetic

Transient Program (EMTP) [4]. The model implement two DPL lines in series with an internal mid-point to connect faults. The fault type is specified inside the model (see the example ex ample at ARTEMIS User’s Guide

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the end). The fault location is entered as a signal input and can be change during the simulation without recompiling the models. An error signal is set if the fault location is to short. Otherwise, the fault distance can be arbitrarily set to any value For the model to have a fault distance that is variable during real-time simulation, an approximation is made in the distribution of the line losses. This is explained next: A standard Bergeron-type line is a lossless line to which lumped resistances are added to represent the line losses. This is the case of the EMTP and SimPowerSystems DPL models. Normally, when using two lines in series, the losses should be distributed in proportion of the respective line lengths. However, if we do this, the total surge impedance of the line would vary with the line length (i.e. the t he fault location). This in return would force the recalculation of state-space matrices and it is not acceptable during real-time simulation. The ADPLF model therefore fixes the losses distribution without regards to the fault location. By default, the losses are split in half between the two lines. Refer to the SPS Distributed Parameter Line block Reference page for more details on the mathematical model of the distributed parameters line. This may induce some error when the fault distance is very short. The Maximum fault distance from ABC terminal (%) parameter can help to minimize this error if the maximum fault distance is known. For example, if theinfault location is located first half of thelosses complete line, theoflosses would be distributed a {25%, 75 %} 75%} way, sointothe obtain the exact reparation the average distance of the fault. Parameters Number of phases N:

Currently, only 3-phase line is supported

Specifies the frequency used to compute the resistance R, inductance L, and capacitance C matrices of the line model. Frequency used for RLC specifications:

Resistance per unit length:

The resistance R per unit length, as an N-by-N matrix in ohms/km. For a symmetrical line, you can either specify the N-by-N matrix or the sequence parameters. For a two-phase or three-phase continuously transposed line, you can enter the positive and zero-sequence resistances [R1 R0]. For a symmetrical six-phase line you can

set the sequence parameters plus the zero-sequence mutual resistance [R1 R0 R0m]. For asymmetrical lines, you must specify the complete N-by-N resistance matrix. The inductance L per unit length, as an N-by-N matrix in henries/km (H/km). For a symmetrical line, you can ca n either specify the N-by-N matrix or the sequence parameters. For a two-phase or three-phase continuously con tinuously transposed line, you can enter the positive and zero-sequence inductances [L1 L0]. For a symmetrical six-phase line, you can enter the sequence parameters plus the zero-sequence mutual inductance [L1 L0 L0m]. For asymmetrical lines, you must specify the complete N-by-N inductance matrix. Inductance per unit length:

The capacitance C per unit length, as an N-by-N matrix in farads/km (F/km). For a symmetrical line, you can either specify the N-by-N matr matrix ix or the sequence parameters. For a two-phase or three-phase continuously con tinuously transposed line, you can enter the positive and zero-sequence capacitances [C1 C0]. For a symmetrical six-phase line you can enter the sequence parameters plus the zero-sequence mutual capacitance [C1 C0 C0m]. For asymmetrical lines, you must specify the complete N-by-N capacitance matrix. Capacitance per unit length:

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Line length:

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Maximum fault distance from ABC terminal (%) :

This parameter is used to indicate the maximum fault distance from the ABC side of the line (the side with the fault distance inport). A 100% is the default value for which the losses are distributed evenly between the two line section (independently of each section line length). If the maximum fault distance is known, the losses are then distributed differently to better approximate the average fault distance.

Inputs Fault distance in pu: this signal value is the location of the fault in per unit of total line length with regards to the side of the input connector on the block.

N-Phases voltage-current signals (Physical Connection) Outputs Too_short: when equal to 1, this signal output indicates that t hat the fault distance is too short for the selected simulation sample time. The model requires that the line transmission delay be at least one sample time of the model. In that case, the user has the option of either lowering the simulation sample time or increasing the line length or fault distance.

N-Phases delayed voltage-current signals (Physical connection Characteristics and Limitations The ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance block does not initialize in steady-state so unexpected transients at the beginning of the simulation may occur. The use of the ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance disable the ‘Measurements’ option of the regular Distributed Parameter Line. Usage of regular voltage measurement blocks is a good alternative.

Direct Feedthrough Discrete sample time XHP support Work offline

No Yes, defined in the ARTEMiS guide block. Yes Yes

Example The following example compare the ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance with a line fault modeled with two distinct line section. The example helps to put in context the error introduced by the model with regards to the normal ARTEMiS line model, that implement the standard Bergeron line model with lumped loss.

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Figure 56:Demonstration model of the ARTEMiS Distributed Parameters Line with Variable Internal Fault Distance Inside the ADPLF, the user can implement its own fault scheme as seen in the following figure. In our case, a single-phase fault to ground is implemented.  

Figure 57:User fault implementation inside the ADPLF

The main error will arise for faults near the line terminal because a lumped loss of R/8 instead of R/4*fault_length/line_length. Remember that a normal Bergeron line with loss has R/4 loss at each end and R/2 in the middle with losses proportional to line length

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section. In the case of the ADPLF, A DPLF, this loss is fixed and no m more ore proportional to section length. 110

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The line used for the test is 100 km in length and has a 0.01273 (direct) and 0.3864 (homopolar) Ohms/km series losses. The line has a minimum transmission delay of approximately 333 µs and the minimum fault distance is approximately 15 km for a simulation time step of 50 µs (50/3.33 , see Limitations ). The user must use pi-line to simulate shorter faults. The test consists on a 4-cycle single-phase to ground fault on the line from steady-state. The line is completely opened at 0.11 seconds. Because the line is not loaded, the per-fault steady-state current is quite small. The next two figure shows the results for a very short and a mid-line fault. On the short fault, one can observe that the input current during the fault is smaller than the reference. This is caused by the lumped losses of the t he line end which is bigger than tha n normal.

Figure 58:Evaluation of the ADPLF model for a fault distance of 15 km.

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Figure 59:Evaluation of the ADPLF model for a fault distance of 50% (mid-line fault) If we now make a fault at mid-line point, the two results are exactly the same. This is normal because the ADPLF assume a fixed losses distribution corresponding to a mid-line separation. Fault current is lower in this case also as expected for a fault occurring farther from the power source. Limitations Usage in RT-LAB as task decoupling elements

The ADPLF model cannot be used as a separating element in RT-LAB. Short distance fault limit 

The ADPLF model can only implement fault occurring at a distance corresponding to one time step of propagation of the line (the fastest mode for the 3-phase line). If shorter fault distance needs to be implemented, a pi-line model is recommended. As a quick rule of the thumb, considering the speed of light of 300000km/s, a 3.33µs/km relation exists between the minimum time step and minimal fault distance of the model. Related Items OpReplaceSpsBlocks , ARTEMiS Guide, ARTEMiS Stubline, ARTEMiS Distributed Parameter Line

References [4] Dommel, Dommel, H., “Digital Computer Computer Solution Solution of Electromagnetic Electromagnetic Transient Transientss in Single and Multiple Multiple Networks”. IEEE Transactions on Power Apparatus and Systems, Vol. PAS-88, No. 4, April,

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ARTEMiS MMC 1P Cell Library ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator) Block

Mask

Figure 60:Mask of MMC 1P block

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ARTEMiS MMC 1P Cell

Description The MMC cell block implement a unipolar bridge with a capacitor. Series RC snubber circuits are connected in shunt with each switch device. Press Help for ssuggested uggested snubber values when the model is discretized. The gates are controlled by Double signals. The following figure presents the equivalent electrical circuit of the MMC cell block implement a unipolar bridge.

Figure 61:Equivalent Electrical Circuit of the MMC cell Block

When the upper switch anti-parallel diode conducts, voltage the Center and the Common equalsorVcupper (minus internal voltage drops). When the between lower switch or diode of the leg conducts, this voltage is equal equ al to 0 (plus internal volta voltage ge drops). The RC snubber in shunt with the switch are required to solve numerical oscillation. Using the time step and the equivalent inductance of the circuit the value of the Rsnubber and Csnubber are given by the following equation.



R S nubber  = -----------------  Le q Ts  5

1 C S nubber  = -------------------------------------2     2  e q ---------------L   T s  15

Where Leq is the equivalent inductance and Ts the simulation time step. The resistance in shunt with the capacitor will discharge it. If no discharge resistance is required, it should be set to inf. If the upper and lower switches are turn ON at the same time, the error output will output 1 when the error occur and 0 otherwise. Upon error the capacitor voltage will become 0 instantaneously and return to normal once the fault is cleared. If the “keep cell short-circuit upon error” is checked the capacitor voltage will always remains to 0. The error output will indicate the total number of short-circuit cell. Parameters Snubber resistance: Snubber

resistance value, only used in high impedance mode.

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Cell capacitor:

Value of the cell's capacitor .

Resistance in shunt with the cell capacitor:

Value of the discharge resistance for the

cell's capacitor . Initial voltage value of the cell capacitor. It can be b e a scalar if all the capacitors start at the same value. If a vector vecto r the same length then the total number num ber of cell is used, the voltage for each eac h cell’s capacitor can be set. Initial capacitor voltage:

Ron:

Internal resistance of the selected device, in ohms.

Number of cells:  This

determine how many cells are connected in series. A maximum of 50 cells can be connected in series. If more then 50 cells are required, a second se cond MMC_1P block need to be connected in series. Sample time:Time

at which the capacitor voltage will be computed.

Keep cell short-circuit upon error: Check

this box if the cell capacitor should

remain to 0 when an error occurs. Inputs Upper gate (double): double

signals that controlled the upper switch gates. This signal has to be a vector of same length then the number of cells. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. Lower gate (double):  double

signals that controlled the lower switch gates. This signal has to be a vector of same length then the number of cells. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. Center (SPS): Middle

point of the cell.

Common (SPS): Common

point of the cell.

Outputs Vc (double): The

voltage at the cell's capacitor, vector of same length then the number of

cells. Error (double): Ouput

0 in normal operation and output 1 if a short-circuit occurs. When the “keep cell short-circuit upon error” is checked ch ecked it will output the total number of shortcircuited cells.

Characteristics

Direct Feedthrough Sample time Work offline Dimensionalized

No Parameter Yes Yes

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ARTEMiS MMC 2P Cell Library ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator) Block

Mask

Figure 62:Mask of MMC 2P block

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ARTEMiS MMC 2P Cell

Description The MMC-2P cell block implement a bipolar bridge with a capacitor. S Series eries RC snubber circuits are connected in parallel with each switch device. Press P ress Help for suggested snubber values when the model is discretized. The gates are controlled by Double signals. The following figure presents the equivalent electrical circuit of the MMC cell block implement a unipolar bridge.

Figure 63:Equivalent Electrical Circuit of the MMC-2P cell Block

The voltage between A and B is determined by the switching applied to g1 to g4. g1 and g2 must be complementary and so does g3 and g4. The RC snubber in shunt with the switch are required to solve numerical oscillation. Using the time step and the equivalent inductance of the circuit the value of the Rsnubber and Csnubber are given by the following equation

 1 R S nubber  = -----------------  L eq  ------------------Ts  5 nbcells

1 C S nubber  = -----------------------------------------  n b c e l l s 2     2  L  ---------------eq







T s 15

Where nbcells is the number of cells in series and Leq is the equivalent inductance Parameters Snubber resistance: Snubber Snubber Capacitor: Cell capacitor: Ron:

resistance value, only used in high impedance mode.

Snubber capacitor value, only used in high impedance mode.

Value of the cell's capacitor .

Internal resistance of the selected device, in ohms.

Number of cells:  This

determine how many cells are connected in series. A maximum of 20

cells can be connected in series. If more then 20 cells are required, a second se cond MMC_2P block need to be connected in series.

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Inputs g1 (double): double signals that controlled the upper left switch gates. This signal has to be a vector of same length then the number of cells. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. g2 (double): double

signals that controlled the lower left switch gates. This signal has to be a vector of same length then the number of cells. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF.

g3 (double): double

signals that controlled the upper right switch gates. This signal has to be a vector of same length then the number of cells. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. g4 (double): double

signals that controlled the lower right switch gates. This signal has to be a vector of same length then the number of cells. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. A (SPS): Middle

left point of the cell.

B (SPS): Middle

right point of the cell.

Outputs Vc (double): The

voltage at the cell's capacitor, vector of same length then the number of

cells Characteristics

Direct Feedthrough Sample time Work offline Dimensionalized

No Parameter Yes Yes

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ARTEMiS TSB 2-Level Library ARTEMiS (Advanced Real-Time ElectroMagnetic Simulator) Block

Mask

Figure 64:Mask of TSB 2-Level block Description

The TSB 2-Level block implements a 2-level IGBT/GTO/MOSFET inverter with 2 active switches with anti-parallel diodes. The block model uses a switching function approach with ARTEMIS User’s Guide

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interpolation and is also capable of simulating cases where the inverter output is in a highimpedance state (ex: no gating or natural rectification). Deadtime and anti-parallel diode effects are fully taken into account by this model. The gates are controlled by Double signals. The following figure presents the equivalent electrical circuit of the TSB 2-Level block.

Figure 65:Equivalent Electrical Circuit of TSB Block A numerical RC snubber is required to implement high impedance states when no gating is present at both switches. Suggested values are given next:

R S nubber  = -------- --------- L Ts  5  e q

1 C S nubber  = --------------------------------------2 2      L  --------------- e q T s  15

Where Leq is the equivalent inductance ind uctance of the load (connected to ’A’ port) and Ts the simulation time step. The Input DC current is normally equal to the current goiing across the upper IGBT. An alternative method is also provided based on o n power balance (Idc*Vdc=Vabc*Iabc). A compensation factor is provided to adjust this power equation. equati on. This factor simply makes the interpolationwith across thelow twopower last values Iabcastoan compute Idc. This canwith be very required applications very factorsofsuch inductive machine low in mechanical load. Parameters Switch Conduction resistance [Ohms]:

Conduction resistance of all switches, including

anti-parallel diodes. Snubber resistance (in high impedance mode only) [Ohms]: Snubber

resistance

value, only used in high impedance mode. Snubber Capacitor(in high impedance mode only) [Farad]:

Snubber capacitor value,

only used in high impedance mode. Sample time [s]:Time

at which the capacitor voltage will be computed.

This is the equivalent resistance of the inverter at voltage reversal on the DC-bus. This resistance r esistance is different than

Anti voltage reversal equivalent diode resistance [Ohms]:

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the one of the two anti-parallel diodes (that would start to conduct in case of DC-bus DC -bus voltage reversal) because of the switching function method meth od of the model. Alternate Idc calculation method based on power balance:  With

this option selected, the DC bus input current is computed from the power balance equation (Vdc*Idc=Vabc*Iabc) Alternate Idc compensation factor (default=0) (0...1):  This

factor enables some

delay tuning in the power equation Vdc*Idc=Vabc*Iabc by interpolating on the 2 last time value of Iabc. It can be useful in somelow power factor applications.

Inputs Gate (double, interpolated): (vector

of size 2). Double signals that controlled the upper and lower switch gates. A signal value of 1 indicates the switch is conducting, while a value of zero indicates the switch is OFF. A values between 0 and 1 indicates that a switching action occured during the last time step. Dc+, Dc-(SPS): The A (SPS): The

positive and negative side of the DC bus.

inverter middle point.

Outputs none.

Characteristics

Direct Feedthrough Sample time Work offline Dimensionalized

No Parameter Yes Yes

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ARTEMIS User Guide

 

OpReplaceSpsBlocks

Description This function helps replacing SimPowerSystems electrical blocks by ARTEMiS electrical blocks or replacing ARTEMiS electrical blocks by SimPowerSystems electrical blocks. This function is useful ARTEMiS provides advanced for real-time simulation; these blocks contain anbecause optimized implementation of the SPSblocks mathematical model which make them better suited for real-time simulation. This function also provides an optional interface to help the user select sele ct the blocks to be replaced. The figure below shows the dialog that appear when the function is called with the default argument.

Note that ARTEMiS currently only supports the Distributed Parameters line block. Other decoupling blocks than the Distributed Parameters line will be supported in a future release. Usage

opReplaceSpsBlocks (modelName,

ARTEMIS User’s Guide

operation, searchDepth);

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OpReplaceSpsBlocks

Inputs modelName operation

Name of the model to modify. Optional argument that specified the type of operation to perform when replacing the blocks. 1- ReplaceBlocks: open a dialog that will wi ll help to switch between the real-time ARTEMiS blocks and the nonreal-time SPS blocks. 2- ReplaceSpsBlocks: automatically replace all SPS blocks by their real-time ARTEMiS equivalent, 3- ReplaceArtemisBlocks: automatically replace all ARTEMiS blocks by their non real-time SPS equivalent.

searchDepth

The default value is “ReplaceBlocks”. Optional integer that constrains the model search to a specific depth.

Outputs None

Example To open a dialog that will help to switch between the real-time real-tim e ARTEMiS blocks and the nonreal-time SPS blocks: opReplaceSpsBlocks (modelName); To automatically replace all SPS blocks by their real-time ARTEMiS equivalent: opReplaceSpsBlocks (modelName, 'ReplaceSpsBlocks'); To automatically replace all ARTEMiS blocks by their non real-time SPS equivalent: opReplaceSpsBlocks (modelName, 'ReplaceArtemisBlocks') Related Items ARTEMIS Distributed Parameters Line, ARTEMiS Guide

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Known limitations (ARTEMiS v6.0 release)

 

The following issues and limitations of ARTEMiS v6.0 are known to OPAL-RT.

PC Memory limitation When compiling an ARTEMiS model, lack of memory may occur, especially when the size of the matrices ABDC are big and the number of switches is high. It only happens during the compilation because during offline simulation, the permutation matrices are not all calculates. Note that the separation and generation process take a lot of memory. Even before the generation process starts, a big part of the memory is already in used by RT-LAB and by Matlab itself (0.8GB). ARTEMiS tried to calculate all matrix permutation of the electrical network. For example, for a very small network (only 10 states, 12 inputs and 11 outputs), the state-space matrices would be like: x' = Ax+Bu

(A is [10x10], B is [10x12], x is [10x1], x' is [10x1], u is [12,1])

Y = Cx+Du

(C is [11x10], D is [11x12])

And the number of switches is 15, the size of memory required is: ( (10*10 + 10 + 10*12 + 12 + 10) + (11*10 + 10 + 11*12 + 12 + 11) ) * 2^15 * 8 = 138MB Now the same calculation for a network with 40 states, 40 inputs and 40 outputs is 1.76GB.  

ARTEMiS limitations 1- 3-level bridge with ’ideal switch’ option not supported in ARTEMiS-DTCSE mode. 2- Maximum number of switch is 28 in a single topologicaly connected network for all mode even Dynamic calculation 3- Stubline usage causes instability when using ARTEMiS-DTCSE mode. 4- ARTEMiS distributed parameters line have no 'Measurements' options. SPS mesurement blocks are an alternative for line measurements. 5- ARTEMiS distributed parameters lines are not initialized in itialized with stady state currents and voltages. This can results in some transients at the beginning of the simulation. 6- The trapezoidal solver does not support RT-Events based switch gating signals 7- Circuit containing SPS Multimeter blocks are simulated into a single state-space system.

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Known limitations (ARTEMiS v6.0 release)

SimPowerSystems 4.6- 5.0 limitations

SimPowerSystems SimPowerSys tems 4.6- 5.0 limitations SPS Neutral blocks:  There

is a limitation in SimPowerSystems (v4.6 and v5.0) that prevent the effective separation (or decoupling) of independant systems of state-space equation if any SPS SP S Neutral block is present in the model. This does not affects the simulation accuracy of models but only slows them down because big matrix systems are formed. In RT applications, this will increased the required memory and probably increase the minimal sample time. The effect is similar to the Ground Connections  problem described next. Ground Connections: There

is currently a bug in SPS 4.6 (R2008a) with regards to separation/decou-

pling of state-space systems. If , for example, 3 components are wired together to a single SPS 'Ground', the 3 componants will be put in the same state-space system. If the same componants are connected to 3 distinct SPS 'Ground' blocks, then the 3 componants will w ill be put into 3 differents state-space systems s ystems (provided that there is no other connections between the components) Electrically speaking, the 2 cases are identical but it affect the capacity of separation. The user is advised to verify the effective subsystems separation separat ion as it appears at the MATLAB prompt at the beginning of the simulation with ARTEMiS. The following prompt output shows that the power_x model is separated into 2 subsystems: SimPowerSystems processing circuit #1 of power_x ... Computing state-space representation of linear electrical circuit ...  (13 states ; 9 inputs ; 8 outputs ; 3 switches) ... ARTEMiS: approx. memory required for full matrix precomputation: 0.037056 Mb Ready. Third-Party Rule block detected: power_transfosat/ARTEMiS Guide SimPowerSystems processing circuit #2 of power_x ... Computing state-space representation of linear electrical circuit ...  (13 states ; 9 inputs ; 8 outputs ; 3 switches) ... ARTEMiS: approx. memory required for full matrix precomputation: 0.037056 Mb Ready.