ARM Notes from NPTEL.docx

ARM: Introduced by ACORN computers.

ARM Architecture: -

Load – Store Architecture.

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Basically 32-bit but supports both 16-bit and 32-bit.

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Basically RISC architecture

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Has auto increment and auto decrement addressing modes

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Consists of Barrel shifter to increase throughput.

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ARM is designed to suit embedded devices.

ARM Versions: Version 1: 26 bit addressing mode Version 2: 32-bit addressing mode Version 3: Real 32-bit addressing mode Version 4: Enhanced instructions, Thumb introduced ( Version 4T) Version 5: Added instructions, Version 5E supports signal processing.

Basic Architecture: -

No data instructions which can modify the data in memory. Operands are stored in Registers. Barrel shifter (Combinational circuit) in data process path can shift data to right / left in the same instruction cycle. Auto increment / Decrement which is uncommon in RISC is included into ARM, this is common in CISC. ALU and barrel shift operations done in same cycle. Primarily concentrated on Data path. All registers are of 32 bit. In User mode, 16 Data registers (R0 to R15) and 2 status register. 3 special function registers out of 16 Data Registers, they are R13, R14, R15. R13 is Stack Register. R14 is the link Register. R15 is the Program Counter. R13 and R14 can also use as normal general purpose register. CPSR, SPSR are the two status registers, these are not Data registers. All instructions are 32 bit aligned, 32  –bit boundaries is a block of 4 bytes. Least significant bits bit 0 and bit 1 are don’t care while handling addr esses. PC value is store in [31:2] Sticky Overflow Flag?? Processor modes determine rights to CPSR register. Privileged mode gives write/read access to CPSR register. ARM has seven modes. Privileged mode: abort, Fast interrupt request, interrupt r equest, supervisor, system and undefined. Non Privlileged mode: User mode. Abort mode: Failed attempt to access memory. FIQ, IR modes: interrupt available on ARM

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Supervisor mode: state after reset, the mode in which OS kernel executes.

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System mode: special version of user mode, allows R/W CPSR register.

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Undefined mode: undefined instruction.

Banked Registers: -

Total 37 registers

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20 registers are hidden from program and are called banked registers.

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Banked registers are available in processor mode other than system mode.

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One to one mapping with the registers in user mode.

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Gets fresh copy of R8 to R14 in FIQ mode whereas only R13 and R14 gets fresh copy in IR mode.

Memory Organization -

Supports both Little and big endian.

Classes of Instructions: -

Data Processing

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Branch instructions

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Load store instructions

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Software interrupt instruction

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Program status register instructions

Features of Instructions set -

3 address data processing instructions, 2 operands and

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Conditional execution of every instruction

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Load and store multiple registers

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Shift (Barrel shifter) and ALU operation in single instruction.

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Open instruction set extension through the coprocessor instruction.

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BIC r0, r1, r2: every binary 1 in r2 clears a corresponding bit in r1 and the result is stored in r0.

Types of Load/Store Instructions They are three types - Single register transfer: Load & Stor e on a boundary alignment, Supports different addressing modes. -

Multiple register transfer

- Swap Addressing Modes in Load Instructions: Increment after, Increment before, Decrement after, Decrement before.

Modes of Stack Processing in Multiple register transfer: Full ascending, empty ascending, full descending and empty descending.

Software Interrupt Instruction: SWI n, allows shifting the processor mode to supervisor mode.

Setting CPSR Flags: To enable interrupt flag: MRS r1, CPSR BIC r1, r1, #80 MSR CPSR, r1 Thumb Instruction: Changing T bit in CPSR, changes to Thumb mode BX r0 OR BLX r0 can changes to and fro to Thumb mode. Bit 0 in address specified in r0 is 1 indicates shift to Thumb mode. ARM exceptions & Modes Exception FIQ IR SWI and Reset Undefined instruction Pre-fetch abort & Data abort

Mode FIQ mode IRQ mode SVC Undefined mode Abort

Exception Priorities Exceptions Reset Data Abort FIQ IRQ Pre-fetch Abort SWI Undefined Instructions

Priority 1 2 3 4 5 6 6

I-Bit 1 1 1 1 1 1 1

F-bit 1 1 -